TNT4882

TNT4882 PANJIT | Alldatasheet

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48 GND

49 DATA6

50 DATA7

Figure 3. TNT4882 Generic Pin Configuration

1 BBUS_OEN O Asserts when DATA7-0 (B bus) is enabled for output

14 ABUSN I Enables register accesses through the A bus (DATA15-8) – DATA15 is the most significant bit

20 ABUS_OEN O Asserts when DATA15-8 (A bus) is enabled for output

21 TADCS O Asserts when the TNT4882 is an active or addressed IEEE 488 Talker (TADS, TACS, or SPAS)

22 CPUACC O Asserts in two-chip mode during a NAT4882 register I/O access

23 TRIG O Asserts when in DTAS or when the auxiliary trigger software command is issued

26 PAGED I Asserting this pin pages in the page-in registers in the 7210 mode

28 REM O Asserts when the TNT4882 is in a remote state (REMS or RWLS)

29 SWAPN I Rearranges the order of the registers when asserted and in 9914 mode

30 FIFO_RDY O Asserts when the FIFO is ready for burst access

31 BURST_RDN I When asserted, places the TNT4882 in a burst read mode, in which the first word in the

32 DRQ O Asserts to request a DMA transfer cycle

33 DACKN I Enables FIFO accesses during a DMA transfer cycle

34 INTR O Asserts when one or more of the unmasked interrupt conditions becomes true

38 RDY1 O Asserts during an I/O access to indicate that the read data is available or that the write

resistor between 50 kΩ and 150 kΩ .

51 DCAS O Asserts when the device clear state machine is in DCAS

52 NC O Leave this pin unconnected

53 MODE I Determines whether the TNT4882 powers up in 7210 or 9914 emulation mode –

55 CSN I Chip Select enables I/O transfers between the CPU and the TNT4882

62 BBUSN I Enables register accesses through the B bus (DATA7-0)

63 RDN I Enables the contents of the registers selected by ADDR 4:0 and CSN or the FIFOs to

64 WRN I Latches data on the bus selected by ABUSN and BBUSN into an internal TNT4882 register

66 LADCS O Asserts when the TNT4882 is addressed as a Listener

67 RESETN I Holds the TNT4882 in its idle state

95 XTAL0 O Output of crystal circuit – use only for driving a quartz crystal

96 XTAL1 I Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal

98 KEYCLKN O Strobes data to or from a DS1204 electronic key

99 KEYDQ I/O Transmits serial data between the TNT4882 and a DS1204 key

100 KEYRSTN O Resets a DS1204 key

Figure 4. TNT4882 ISA Pin Configuration

Single-Chip IEEE 488.2 Talker/Listener ASIC National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com ISA Pin Description All input (I) and bidirectional (I/O) pins have an internal pull-up resistor between 50 kΩ and 150 kΩ . Pins with names that end in “N” are active low signals – all others are active high. Open-collector outputs are type “OC.” Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more information. Pin No.(s) Name(s) Type Description

1 D7_0_OEN O Asserts when DATA7-0 bus is enabled for output – may be left unconnected

2,3,5,6,7 ,9,10,11 DATA15-8 I/O Upper eight bits of bidirectional three-state data bus for transfer of commands, data, and status between TNT4882 and CPU – can connect directly to the AT bus – DATA15 is the most significant bit

14 BHEN_N I Enables access to upper eight bits of data bus when asserted

19-15 ADDR4-0 I Determines which register will be accessed during an I/O access 31,30,29,28,26 ADDR9-5 I Determines if an I/O address is within the range occupied by the TNT4882 – the chip is selected and an I/O access occurs when ADDR9-5 match SW9-5 and AEN_N is asserted

20 D15_8_OEN O Asserts when DATA15:8 bus is enabled for output – may be left unconnected

21,54 NC O Leave unconnected 52,51,23,22,55 SW9-5 I Determines the base address of the TNT4882

37 AEN_N I Enables I/O accesses to the TNT4882

38 IOCHRDY OC When the TNT4882 is not accessed, this open-collector signal is not driven, and a

pull-up resistor on the system board keeps it pulled high – at the start of some TNT4882 accesses, the TNT4882 may drive it low, then pull it high again during the cycle to indicate that the TNT4882 is ready for the CPU to end that cycle 50,49,47,46,44, DATA7-0 I/O Lower eight bits of bidirectional three-state data bus for transfer of commands, data, 43,42,39 and status between TNT4882 and CPU – can connect directly to the AT bus – DATA7 is the most significant bit

53 MODE I Forces the TNT4882 to 7210 (high) or 9914 (low) emulation mode on a hardware

reset – may be left unconnected

62 SENSE_8_16N I Pull this pin low to tell the TNT4882 that it is connected to a 16-bit bus – leave it

unconnected if the TNT4882 is connected to an 8-bit bus

63 IORN I Drives the contents of the register selected by ADDR4-0 on the data bus when the

64 IOWN I The value on the data bus is latched into the register selected by ADDR4-0 on the

rising edge of IOWN when you select the TNT4882

66 IOCS16N OC Driven low during an access to the upper data bus

67 RESET I Causes a hardware reset and holds the TNT4882 in its idle state while asserted

71,74,77,80,88, DIO8-1N I/O 8-bit bidirectional IEEE 488 data bus 89,91,92 70,73,76,79,81, RENN, ATNN, SRQN, I/O IEEE 488 control signals 82,84,85 IFCN, NDACN, NRFDN, DAVN, EOIN

98 KEYCLKN O Strobes data to or from the DS1204 electronic key

4,8,13,25,27 ,35,41, GND – Ground pins – 0 V 12,24,36,40,56,58, VDD – Power pins – +5 V (±5%) 59,60,69,87 ,94

Single-Chip IEEE 488.2 Talker/Listener ASIC National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com TNT4882 Register Map Notes on Register Map 1. For complete register descriptions, see the “TNT4882 Programmer Reference Manual” (320724-01) 2. Some of the 7210 mode registers, such as the ISR1, have the same names as some of the 9914 mode registers. The 7210 mode registers are NOT the same as their 9914 mode counterparts. Be sure to refer to the appropriate bit map for the chip emulation mode you are using when programming these registers. 3. The shaded registers are “paged-in registers.” Paged-in registers only exist in 9914 mode. Writing to the address of the 9914 mode ADSR normally does not access any registers. Writing one of four page-in commands to the AUXCR changes all subsequent writes to that address to that of the corresponding paged-in register. The two readable paged-in registers, the 9914 mode SPSR and ISR2, are both paged in whenever any one of the four writable paged-in registers is paged in. When you write the clear page-in command to the AUXCR, all paged-in registers are paged out again and are no longer accessible. 4. There are several unused bytes in the address space of the TNT4882. These addresses are reserved for adding new features to the chip. You should not map any external hardware into these addresses or access them at any time, as this may cause compatibility problems with future versions of the TNT4882. NAT4882 Registers

7210 Mode 9914 Mode 9914 Mode Swapped

ADDR4-0 Hex Offset Read Register Write Register Read Register Write Register Read Register Write Register 00000 0 DIR CDOR ISR0 IMR0 DIR CDOR 00010 2 ISR1 IMR1 ISR1 IMR1 CPTR PPR 00100 4 ISR2 IMR2 ADSR IMR2 SPSR SPMR ““ EOSR ““ BCR ““ ACCR 00110 6 SPSR SPMR BSR AUXCR ISR2 ADR 01000 8 ADSR ADMR ISR2 ADR ADSR IMR2 ““ EOSR ““ BCR ““ ACCR

01010 A CPTR AUXMR SPSR SPMR BSR AUXCR

01100 C ADR0 ADR CPTR PPR ISR0 IMR0

01110 E ADR1 EOSR DIR CDOR ISR1 IMR1

10001 11 DSR SH_CNT – – – – 10111 17 CSR KEYREG – – – – 11011 1B SASR DCR – – – – 11101 1D ISR0 IMR0 – – – – 11111 1F BSR BCR – – – – Turbo488 Registers (Same in All Modes) ADDR4-0 Hex Offset Read Register Write Register 01001 9 CNT2 CNT2

01011 B CNT3 CNT3

01101 D – HSSEL

Special Registers Only Accessible in ISA Pin Configuration ADDR4-0 Hex Offset Read Register Write Register 00101 5 – ACCWR 00111 7 – INTR

40 MHz CMOS

Figure 5. PC/XT and A T (ISA) Bus to ISA Mode TNT4882

Single-Chip IEEE 488.2 Talker/Listener ASIC National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com SENSE_8_16N BHEN_N ADDR4-0 IORN IOWN DATA15-8 DATA7-0 0 0 11000 0 1 FIFOA FIFOB 0 0 11000 1 0 FIFOA FIFOB 0 0 XXXX1 0 1 Read Not Driven 0 0 XXXX1 1 0 Written Ignored 0 1 XXXX0 0 1 Not Driven Read 0 1 XXXX0 1 0 Ignored Written 1 1 XXXX0 0 1 Not Driven Read 1 1 XXXX0 1 0 Ignored Written 1 1 XXXX1 0 1 Not Driven Read 1 1 XXXX1 1 0 Ignored Written ISA Pin Configuration Byte Lane Table This table shows which byte lane accesses the TNT4882 internal registers during an I/O access when you use the ISA pin configuration. All combinations of ADDR4-1, SENSE_8_16N, and BHEN_N not shown in this table are illegal. You should not apply these combinations to the TNT4882 while the chip is selected. The accessed register is determined only by ADDR4-0, not SENSE_8_16N or BHEN_N.

Figure 6. Intel CPU to Generic Mode TNT4882

Single-Chip IEEE 488.2 Talker/Listener ASIC National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com Generic Mode DC Characteristics Parameter Symbol Min Max Unit Notes Supply voltage VDD 4.75 5.25 V Voltage input low VIL -0.5 0.8 V Voltage input high VIH 2.0 VCC V Voltage output low VOL 0.0 0.4 V Voltage output high VOH 2.4 VDD V Supply current IDD 90 mA 50 mA, typical Output current low IOL 24 mA VOL = 0.4 V DATA15-0, LADCS, DRQ, INTR, RDY1 Output current low IOL 8m A VOL = 0.4 V BBUS_OEN, ABUS_OEN, TADCS, CPUACC, REM, TRIG, DCAS, CIC FIFO_RDY IOL 4m A VOL = 0.4 V Output current low IOL 2m A VOL= 0.4 V KEYDQ, KEYRSTN, KEYCLKN DIO8-1N, IFCN, SRQN, EOIN, ATNN, IOL 48 mA VOL= 0.4 V RENN, DAVN, NRFDN, NDACN Output current high IOH -12 mA VOH = VDD-0.5 V DATA15-0, LADCS, DRQ, INTR, RDY1 -24 mA VOH = 2.4 V Output current high IOH -4 mA VOH = VDD-0.5 V BBUS_OEN, ABUS_OEN, TADCS, CPUACC, REM, TRIG, DCAS -8 mA VOH = 2.4 V FIFO_RDY IOH -2 mA VOH = VDD-0.5 V -4 VOH = 2.4 V Output current high IOH -1 mA VOH = VDD-0.5 V KEYDQ, KEYRSTN, KEYCLKN -2 mA VOH = 2.4 V DIO8-1N, IFCN, SRQN, EOIN, ATNN, IOH 16 mA VOH = 2.4 V RENN, DAVN, NRFDN, NDACN Input leakage current – all pins IIH ±10 mA VDD = 5.5 V Output leakage current – all pins IOZ ±10 mA VDD = 5.5 V Generic Mode Capacitance Parameter Symbol Min Typ Max Unit Notes Pin capacitance C 50 pF DIO8-1N, RENN, ATNN, IFCN, SRQN, DAVN, EOIN, NDACN, NRFDN Pin capacitance all other pins C 3.6 pF Generic Mode AC Characteristics Commercial Industrial Parameter Symbol Min Max Min Max Unit Address setup to RDN = 0, WRN = 0 tAS 24 27 ns Data delay from RDN = 0, CSN = 0 (one-chip mode access) tRD 71 78 ns Data float from RDN = 1 tDF 40 44 ns RDN pulsewidth (I/0 access) tRW 71 78 ns RDN recovery width tRR 40 44 ns Address hold from RDN = 1, WRN = 1 tAH 00 n s DRQ unassertion tDU 78 86 ns Data delay from RDN = 0, DACKN = 0 tDR 40 44 ns Data setup to WRN = 1 tWS 14 16 ns Data hold from WRN = 1 tWH 00 n s CSN setup to RDN or WRN tCS 00 n s CSN hold from RDN or WRN tCH 00 n s DACKN setup to RDN or WRN tDS 00 n s DACKN hold from RDN or WRN tDH 00 n s RDN or WRN to CPUACC (two-chip mode NAT4882 access only) tCPU 26 29 ns RDN or WRN to RDY1 assert tARDY Two-chip mode NAT4882 access 10 10 clock periods Other accesses 25 28 ns RDN or WRN to RDY1 unassert tURDY 22 25 ns WRN pulse width (DMA access) tWP 40 44 ns RDN pulse width (DMA access) tRP 40 44 ns

Figure 10. DMA Write

Figure 11. I/O Read Access Waveforms continued on page 14

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Includes 2 TNT4882 ASICs, PC AT evaluation board, ESP-488TL source code software, and documentation. Part Number Legend ab c d e TNT 4882 B Q a. Family name TNT = Single-chip, high-speed, GPIB Talker/Listener interface b. Device-number 4882 = IEEE 488.2 compatible c. Reserved d. Revision e. Package type Q = Quad flat packU.S. Corporate Headquarters Fax (512) 683-9300 • info@natinst.com Branch Offices: Australia 03 9879 5166 • Austria 0662 45 79 90 0 • Belgium 02 757 00 20 • Brazil 000 811 781 0559 • Canada 905 785 0085 China 86 21 6555 7838 • Denmark 45 76 26 00 • Finland 09 725 725 11 • France 01 48 14 24 24 • Germany 089 741 31 30 • Hong Kong 2645 3186 India 91805275406 • Israel 03 6120092 • Italy 02 413091 • Japan 03 5472 2970 • Korea 02 596 7456 • Mexico 001 800 010 0793 Netherlands 0348 433466 • New Zealand 09 914 0488 • Norway 32 27 73 00 • Singapore 2265886 • Spain 91 640 0085 • Sweden 08 587 895 00 Switzerland 056 200 51 51 • Taiwan 02 2377 1200 • U.K. 01635 523545 © Copyright 1999 National Instruments Corporation. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies. 0305599 www.natinst.com (512) 794-0100 *000000A-01* 340570D-01