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Worldwide Corporate Headquarters 16 Malcolm Hoyt Drive . Newburyport, MA 01950 © Rochester Electronics, LLC - All Rights Reserved - 11162012 – NEW PRODUCT INTRODUCTION – TN87C196KC-20 Rochester Electronics has re-introduced and continues to manufacture critically needed semiconductors with the full authorization of the original manufacturer and an attention to quality that meets or exceeds the original component. TN87C196KC-20 Original Part Number: TN87C196KC-20 Description: 16-Bit Microcontroller Package: 68 pin LDCC Manufacturing Flow: Industrial Available in Pb-Free versions TN87C196KC AN87C196KC AN87C196KC-20 MG87C196KC MG87C196KC/B Related Devices [ by temperature / package type / speed / application ] Original Manufacturer: POWERFUL MICROCONTROLLER for use in the automotive market The 80C196KC 16-bit microcontroller is a high perfor- mance member of the MCS® 96 microcontroller family. The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an optional 16 Kbytes of ROM/OTPR OM. Four high- speed capture inputs are provided to record times when events occur. Six high-speed outputs are available for pulse or waveform genera - tion. The high-speed output can also generate four software timers or start an A/D conversion. Events can be based on the timer or up/down counter. Re-introduced by Rochester Electronics on May, 22, 2012 TN80C196KC TN80C196KC-20 N80C196KC N80C196KC-20 S80C196KC-20

*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. July 2004 COPYRIGHT © INTELCORPORATION,2004 Order Number:270942-006 8XC196KC/8XC196KC20 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 87C196KC-16 Kbytes of On-Chip OTPROM 83C196KC-16 Kbytes ROM 80C196KC-ROMless Y 16 and 20 MHz Available Y 488 Byte Register RAM Y Register-to-Register Architecture Y 28 Interrupt Sources/16 Vectors Y Peripheral Transaction Server Y 1.4 ms 16 x 16 Multiply (20 MHz) Y 2.4 ms 32/16 Divide (20 MHz) Y Powerdown and Idle Modes Y Five 8-Bit I/O Ports Y 16-Bit Watchdog Timer Y Extended Temperature Available Y Dynamically Configurable 8-Bit or 16-Bit Buswidth Y Full Duplex Serial Port Y High Speed I/O Subsystem Y 16-Bit Timer Y 16-Bit Up/Down Counter with Capture Y 3 Pulse-Width-Modulated Outputs Y Four 16-Bit Software Timers Y 8- or 10-Bit A/D Converter with Sample/Hold Y HOLD/HLDA Bus Protocol Y OTPROM One-Time Programmable Version The 80C196KC 16-bit microcontroller is a high performance member of the MCS É 96 microcontroller family. The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an optional 16 Kbytes of ROM/OTPR OM. Intel's CHMOS III process provides a high performance processor along with low power consumption. The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16 Kbytes factory programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise stated. Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are available for pulse or waveform generation. The high-speed output can also generate four software timers or start an A/D conversion. Events can be based on the timer or up/down counter. With the commercial (standard) temperature option, operational characteristics are guaranteed over the tem- perature range of 0 §Ct o a70§C. With the extended (Express) temperature range option, operational charac- teristics are guaranteed over the temperature range of b40§Ct o a85§C. Unless otherwise noted, the specifi- cations are the same for both options. See the Packaging information for extended temperature designators.

  1. EPROMs are available as One Time Programmable

Figure 3. The 8XC196KC Family Nomenclature Table 1. Thermal Characteristics description of Intel’s thermal impedance test methodology. Table 2. 8XC196KC Memory Map

488 Bytes Register RAM (Note 1) 01FFH

  1. Code executed in locations 0000H to 01FFH will be
  2. Reserved memory locations must contain 0FFH unless
  3. Reserved SFR bit locations must contain 0.
  4. Refer to 8XC196KC User’s manual for SFR descriptions.
  5. WARNING: Reserved memory locations must not be

cations may change with future revisions of the device. locations may not function properly.

270942–2 Figure 4.68-LeadPLCC Package

Figure 5. 8XC196KC 80-Pin QFP Package

Figure 6. 80-Pin SQFP Package

VCC Main supply voltage (5V). VSS Digital circuit ground (0V). There are multiple VSS pins, all of which must be connected. VREF Reference voltage for the A/D converter (5V). V REF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. VPP Timing pin for the return from powerdown circuit. This pin also supplies the programming voltage on the EPROM device. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator frequency. RESET Reset input and open drain output. BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0a n 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. NMI A positive transition causes a vector through 203EH. INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch. EA Input for memory select (External Access). EA equal high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip ROM/E PROM. EAequal to low causes accesses to those locations to be directed to off-chip memory. Also used to enter programming mode. ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a signal to demultiplex the address from the address/data bus. When the pin is ADV , it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. RD Read signal output to external memory. RDis activated only during external memory reads. WR/WRL Write and Write Low output to external memory, as selected by the CCR. WRwill go low for every external write, while WRLwill go low only for external writes where an even byte is being written. WR/WRL is activated only during external memory writes. BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHEwill go low for external writes to the high byte of the data bus. WRHwill go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. When the external memory is not being used, READY has no effect. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. Port 1 8-bit quasi-bidirectional I/O port. Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC. Pins 2.6 and 2.7 are quasi-bidirectional.

PIN DESCRIPTIONS (Continued) Symbol Name and Function Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. HOLD Bus Hold input requesting control of the bus. HLDA Bus Hold acknowledge output indicating release of the bus. BREQ Bus Request output activated when the bus controller has a pending external memory cycle. PMODE Determines the EPROM programming mode. PACT A low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete. CPVER Cummulative Program Output Verification. Pin is high if all locations have programmed correctly since entering a programming mode. PALE A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). PROG A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid programming data (input to slave). PVER A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. AINC Auto Increment. Active low input signal indicates that the auto increment mode is enabled. Auto Increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write.

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Voltage from EA or NOTE: 1. This includes VPP and EA on ROM or CPU only devices. 2. Power dissipation is based on package heat transfer lim- itations, not device power consumption. NOTICE: This is a production data sheet. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the \\Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the \\Operating Conditions'' is not recommended and ex- tended exposure beyond the \\Operating Conditions'' may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Under Bias Commercial Temp. 0 a70 §C TA Ambient Temperature Under Bias Extended Temp. b40 a85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V ANGND Analog Ground Voltage VSS b 0.4 V SS a 0.4 V (1) FOSC Oscillator Frequency (8XC196KC) 8 16 MHz FOSC Oscillator Frequency (8XC196KC20) 8 20 MHz NOTE: 1. ANGND and VSS should be nominally at the same potential. DC CHARACTERISTICS (Over Specified Operating Conditions) Symbol Description Min Typ Max Units TestConditions VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage (Note 1) 0.2 V CC a 1.0 V CC a 0.5 V VIH1 Input High Voltage on XTAL 1 0.7 V CC VCC a 0.5 V VIH2 Input High Voltage on RESET 2.2 VCC a 0.5 V VHYS Hysteresis on RESET 300 mV V CC e 5.0V VOL Output Low Voltage 0.3 V I OL e 200 mA 0.45 V I OL e 2.8 mA

1.5 V I OL e 7m A

VOL1 Output Low Voltage 0.8 V IOL ea 0.4 mA in RESET on P2.5 (Note 2) VOH Output High Voltage VCC b 0.3 V I OH eb 200 mA (Standard Outputs) VCC b 0.7 V I OH eb 3.2 mA VCC b 1.5 V I OH eb 7m A

DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Symbol Description Min Typ Max Units TestConditions VOH1 Output High Voltage VCC b 0.3 V I OH eb 10 mA (Quasi-bidirectional Outputs) V CC b 0.7 V I OH eb 30 mA VCC b 1.5 V I OH eb 60 mA IOH1 Logical 1 Output Current in Reset. b0.8 mA V IH e VCC b 1.5V on P2.0. Do not exceed this or device may enter test modes. IIL2 Logical 0 Input Current in Reset TBD mA V IN e 0.45V on P2.0. Maximum current that must be sunk by external device to ensure test mode entry. IIH1 Logical 1 Input Current. a200 mAV IN e VCC e 2.4V Maximum current that external device must source to initiate NMI. ILI Input Leakage Current (Std. Inputs) g10 mA0 k VIN k VCC b 0.3V ILI1 Input Leakage Current (Port 0) g3 mA0 k VIN k VREF ITL 1 to 0 Transition Current (QBD Pins) b650 mAV IN e 2.0V IIL Logical 0 Input Current (QBD Pins) b70 mAV IN e 0.45V IIL1 Ports 3 and 4 in Reset b70 mAV IN e 0.45V ICC Active Mode Current in Reset 65 75 mA XTAL1 e 16 MHz (8XC196KC) VCC e VPP e VREF e 5.5V ICC Active Mode Current in Reset 80 92 mA XTAL1 e 20 MHz (8XC196KC20) VCC e VPP e VREF e 5.5V IIDLE Idle Mode Current (8XC196KC) 17 25 mA XTAL1 e 16 MHz VCC e VPP e VREF e 5.5V IIDLE Idle Mode Current (8XC196KC20) 21 30 mA XTAL1 e 20 MHz VCC e VPP e VREF e 5.5V IPD Powerdown Mode Current 8 15 mAV CC e VPP e VREF e 5.5V IREF A/D Converter Reference Current 2 5 mA V CC e VPP e VREF e 5.5V RRST Reset Pullup Resistor 6K 65K X VCC e 5.5V, VIN e 4.0V CS Pin Capacitance (Any Pin to VSS)1 0 pF NOTES: 1. All pins except RESET and XTAL1. 2. Violating these specifications in Reset may cause the part to enter test modes. 3. Commercial specifications apply to express parts except where noted. 4. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7. 5. Standard Outputs include AD0±15, RD ,W R, ALE, BHE , INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4, TXD/P2.0 and RXD (in serial mode 0). The V OH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs. 7. Maximum current per pin must be externally limited to the following values if V OL is held above 0.45V or V OH is held below VCC b 0.7V: IOL on Output pins: 10 mA IOH on quasi-bidirectional pins: self limiting IOH on Standard Output pins: 10 mA 8. Maximum current per bus pin (data and control) during normal operation is g3.2 mA. 9. During normal (non-transient) conditions the following total current limits apply: Port 1, P2.6 IOL:2 9m A IOH is self limiting HSO, P2.0, RXD, RESET IOL:2 9m A IOH:2 6m A P2.5, P2.7, WR, BHE IOL:1 3m A IOH:1 1m A AD0±AD15 IOL:5 2m A IOH:5 2m A RD, ALE, INST±CLKOUT I OL:1 3m A IOH:1 3m A

Frequencies below 8 MHz are shown for reference only; no testing is performed. Figure 7. I CC and IIDLE vs Frequency For use over specified operating conditions.

  1. If max is exceeded, additional wait states will occur.
  2. If wait states are used, add 2 T

OSC * N, where N e number of wait states.

AC CHARACTERISTICS (Continued) For user over specified operating conditions. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz The 80C196KC will meet these specifications: Symbol Description Min Max Units Notes FXTAL Frequency on XTAL1 (8XC196KC) 8 16 MHz (Note 1) FXTAL Frequency on XTAL1 (8XC196KC20) 8 20 MHz (Note 1) TOSC I/F XTAL (8XC196KC) 62.5 125 ns TOSC I/F XTAL (8XC196KC20) 50 125 ns TXHCH XTAL1 High to CLKOUT High or Low a20 a110 ns TCLCL CLKOUT Cycle Time 2 TOSC ns TCHCL CLKOUT High Period TOSC b 10 T OSCa15 ns TCLLH CLKOUT Falling Edge to ALE Rising b5 a15 ns TLLCH ALE Falling Edge to CLKOUT Rising b20 a15 ns TLHLH ALE Cycle Time 4 TOSC ns (Note 4) TLHLL ALE High Period TOSC b 10 T OSCa10 ns TAVLL Address Setup to ALE Falling Edge T OSC b 15 TLLAX Address Hold after ALE Falling Edge T OSC b 35 ns TLLRL ALE Falling Edge to RDFalling Edge T OSC b 30 ns TRLCL RD Low to CLKOUT Falling Edge a4 a30 ns TRLRH RD Low Period TOSC b 5 ns (Note 4) TRHLH RD Rising Edge to ALE Rising Edge T OSC TOSC a 25 ns (Note 2) TRLAZ RD Low to Address Float a5n s TLLWL ALE Falling Edge to WRFalling Edge T OSC b 10 ns TCLWL CLKOUT Low to WR Falling Edge 0 a25 ns TQVWH Data Stable to WR Rising Edge T OSC b 23 (Note 4) TCHWH CLKOUT High to WRRising Edge b5 a15 ns TWLWH WR Low Period TOSC b 20 ns (Note 4) TWHQX Data Hold after WR Rising Edge T OSC b 25 ns TWHLH WR Rising Edge to ALE Rising Edge T OSC b 10 T OSC a 15 ns (Note 2) TWHBX BHE, INST after WR Rising Edge T OSC b 10 ns TWHAX AD8±15 HOLD after WR Rising T OSC b 30 ns (Note 3) TRHBX BHE, INST after RD Rising Edge T OSC b 10 ns TRHAX AD8±15 HOLD after RD Rising T OSC b 25 ns (Note 3) NOTES: 1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 2. Assuming back-to-back bus cycles. 3. 8-Bit bus only. 4. If wait states are used, add 2 T OSC * N, where N e number of wait states.

270942±18

READY Timings (One Wait State) 270942±20 Buswidth Timings 270942±35

Symbol Description Min Max Units Notes THVCH HOLD Setup a55 ns (Note 1) TCLHAL CLKOUT Low to HLDA Low b15 a15 ns TCLBRL CLKOUT Low to BREQ Low b15 a15 ns THALAZ HLDA Low to Address Float a15 ns THALBZ HLDA Low to BHE, INST, RD,W R Weakly Driven a20 ns TCLHAH CLKOUT Low to HLDA High b15 a15 ns TCLBRH CLKOUT Low to BREQ High b15 a15 ns THAHAX HLDA High to Address No Longer Float b15 ns THAHBV HLDA High to BHE, INST, RD,W R Valid b10 a15 ns TCLLH CLKOUT Low to ALE High b5 a15 ns NOTE: 1. To guarantee recognition at next clock. DC SPECIFICATIONS IN HOLD Description Min Max Units Weak Pullups on ADV, RD, 50K 250K VCC e 5.5V, VIN e 0.45V WR,W RL, BHE Weak Pulldowns on 10K 50K VCC e 5.5V, VIN e 2.4 ALE, INST

270942±36 Maximum Hold Latency Bus Cycle Type Internal Execution 1.5 States 16-Bit External Execution 2.5 States 8-Bit External Execution 4.5 States EXTERNAL CLOCK DRIVE (8XC196KC) Symbol Parameter Min Max Units 1/T XLXL Oscillator Frequency 8 16.0 MHz TXLXL Oscillator Period 62.5 125 ns TXHXX High Time 20 ns TXLXX Low Time 20 ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns

EXTERNAL CLOCK DRIVE (8XC196KC20) Symbol Parameter Min Max Units 1/T XLXL Oscillator Frequency 8 20.0 MHz TXLXL Oscillator Period 50 125 ns TXHXX High Time 17 ns TXLXX Low Time 17 ns TXLXH Rise Time 8 ns TXHXL Fall Time 8 ns EXTERNAL CLOCK DRIVE WAVEFORMS 270942±21 EXTERNAL CRYSTAL CONNECTIONS 270942±41 NOTE: Keep oscillator components close to chip and use short, direct traces to XTAL1, XTAL2 and V SS. When using crystals, C1 e C2 & 20 pF. When using ceramic resonators, consult manufacturer for recommended cir- cuitry. EXTERNAL CLOCK CONNECTIONS 270942±42 NOTE: *Required if TTL driver used. Not needed if CMOS driver is used. AC TESTING INPUT, OUTPUT WAVEFORMS 270942±22 AC Testing inputs are driven at 2.4V for a Logic \\1'' and 0.45V for a Logic \\0'' Timing measurements are made at 2.0V for a Logic \\1'' and 0.8V for a Logic \\0''. FLOAT WAVEFORMS 270942±23 For Timing Purposes a Port Pin is no Longer Floating when a 150 mV change from Load Voltage Occurs and Begins to Float when a 150 mV change from the Loaded V OH/V OL Level occurs; IOL/I OH e g15 mA.

Each symbol is two pairs of letters prefixed by \\T'' for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: H- High L- Low V- Valid X- No Longer Valid Z- Floating Signals: A- Address B- BHE C- CLKOUT D- DATA G- Buswidth H- HOLD HA- HLDA L- ALE/ADV BR- BREQ R- RD W- WR /WRH /WRL X- XTAL1 Y- READY Q- Data Out AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE SERIAL PORT TIMING-SHIFT REGISTER MODE (MODE 0) Symbol Parameter Min Max Units TXLXL Serial Port Clock Period (BRRt 8002H) 6 TOSC ns TXLXH Serial Port Clock Falling Edge 4 TOSC b50 4 T OSC a50 ns to Rising Edge (BRR t 8002H) TXLXL Serial Port Clock Period (BRR e 8001H) 4 TOSC ns TXLXH Serial Port Clock Falling Edge 2 TOSC b50 2 T OSC a50 ns to Rising Edge (BRR e 8001H) TQVXH Output Data Setup to Clock Rising Edge 2 TOSC b 50 ns TXHQX Output Data Hold after Clock Rising Edge 2 T OSC b 50 ns TXHQV Next Output Data Valid after Clock Rising Edge 2 TOSC a 50 ns TDVXH Input Data Setup to Clock Rising Edge TOSC a50 ns TXHDX Input Data Hold after Clock Rising Edge 0 ns TXHQZ Last Clock Rising to Output Float 1 TOSC ns WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE SERIAL PORT WAVEFORM-SHIFT REGISTER MODE (MODE 0) 270942±24

The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V REF. 10-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Commercial Temp. 0 a70 §C TA Ambient Temperature Extended Temp. b40 a85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V TSAM Sample Time 1.0 ms(1) TCONV Conversion Time 10 20 ms(1) FOSC Oscillator Frequency (8XC196KC) 8.0 16.0 MHz FOSC Oscillator Frequency (8XC196KC20) 8.0 20.0 MHz NOTE: ANGND and VSS should nominally be at the same potential, 0.00V. 1. The value of AD_TIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions) Parameter Typical (1) Minimum Maximum Units *Notes Resolution 1024 1024 Levels 10 10 Bits Absolute Error 0 g3 LSBs Full Scale Error 0.25 g 0.5 LSBs Zero Offset Error 0.25 g 0.5 LSBs Non-Linearity 1.0 g 2.0 0 g3 LSBs Differential Non-Linearity Error lb1 a2 LSBs Channel-to-Channel Matching g0.1 0 g1 LSBs Repeatability g0.25 LSBs Temperature Coefficients: Offset 0.009 LSB/ §C Full Scale 0.009 LSB/ §C Differential Non-Linearity 0.009 LSB/ §C Off Isolation b60 dB 1, 2 Feedthrough b60 dB 1 VCC Power Supply Rejection b60 dB 1 Input Series Resistance 750 1.2K X 4 Voltage on Analog Input Pin ANGND b 0.5 V REF a 0.5 V 5, 6 DC Input Leakage 0 g3.0 mA Sampling Capacitor 3 pF NOTES: *An \\LSB'' as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25 §C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted. 7. All conversions performed with processor in IDLE mode.

8-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Commercial Temp. 0 a70 §C TA Ambient Temperature Extended Temp. b40 a85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V TSAM Sample Time 1.0 ms(1) TCONV Conversion Time 7 20 ms(1) FOSC Oscillator Frequency (8XC196KC) 8.0 16.0 MHz FOSC Oscillator Frequency (8XC196KC20) 8.0 20.0 MHz NOTE: ANGND and VSS should nominally be at the same potential, 0.00V. 1. The value of AD_TIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions) Parameter Typical Minimum Maximum Units * Notes Resolution 256 256 Levels 8 8 Bits Absolute Error 0 g1 LSBs Full Scale Error g0.5 LSBs Zero Offset Error g0.5 LSBs Non-Linearity 0 g1 LSBs Differential Non-Linearity Error lb1 a1 LSBs Channel-to-Channel Matching g1 LSBs Repeatability g0.25 LSBs Temperature Coefficients: Offset 0.003 LSB/ §C Full Scale 0.003 LSB/ §C Differential Non-Linearity 0.003 LSB/ §C Off Isolation b60 dB 2, 3 Feedthrough b60 dB 2 VCC Power Supply Rejection b60 dB 2 Input Series Resistance 750 1.2K Xs4 Voltage on Analog Input Pin VSS b 0.5 V REF a 0.5 V 5, 6 DC Input Leakage 0 g3.0 mA Sampling Capacitor 3 pF NOTES: *An \\LSB'' as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25 §C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if pin current is limited to g2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted. 7. All conversions performed with processor in IDLE mode.

OPERATING CONDITIONS DURING PROGRAMMING Symbol Description Min Max Units TA Ambient Temperature During Programming 20 30 C VCC Supply Voltage During Programming 4.5 5.5 V (1) VREF Reference Supply Voltage During Programming 4.5 5.5 V (1) VPP Programming Voltage 12.25 12.75 V (2) VEA EA Pin Voltage 12.25 12.75 V (2) FOSC Oscillator Frequency During Auto and Slave 6.0 8.0 MHz Mode Programming FOSC Oscillator Frequency During 6.0 16.0 MHz Run-Time Programming(8XC196KC) FOSC Oscillator Frequency During 6.0 20.0 MHz Run-Time Programming(8XC196KC20) NOTES: 1. VCC and VREF should nominally be at the same voltage during programming. 2. VPP and VEA must never exceed the maximum specification, or the device may be damaged. 3. VSS and ANGND should nominally be at the same potential (0V). 4. Load capacitance during Auto and Slave Mode programming e 150 pF. AC EPROM PROGRAMMING CHARACTERISTICS Symbol Description Min Max Units TSHLL Reset High to First PALE Low 1100 TOSC TLLLH PALE Pulse Width 50 TOSC TAVLL Address Setup Time 0 TOSC TLLAX Address Hold Time 100 TOSC TPLDV PROG Low to Word Dump Valid 50 TOSC TPHDX Word Dump Data Hold 50 TOSC TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TPLPH(1) PROG Pulse Width 50 TOSC TPHLL PROG High to Next PALE Low 220 TOSC TLHPL PALE High to PROG Low 220 TOSC TPHPL PROG High to Next PROG Low 220 TOSC TPHIL PROG High to AINC Low 0 TOSC TILIH AINC Pulse Width 240 TOSC TILVH PVER Hold after AINCLow 50 TOSC TILPL AINC Low to PROG Low 170 TOSC TPHVL PROG High to PVER Valid 220 TOSC NOTE: 1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. See user's manual for further information.

DC EPROM PROGRAMMING CHARACTERISTICS Symbol Description Min Max Units IPP VPP Supply Current (When Programming) 100 mA NOTE: Do not apply V PP until VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 270942±27 NOTE: P3.0 must be high (\\1'') SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT 270942±28 NOTE: P3.0 must be low (\\0'')

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT 270942±29 8XC196KB TO 8XC196KC DESIGN CONSIDERATIONS 1. Memory Map. The 8XC196KC has 512 bytes of RAM/SFRs and an optional 16K of ROM/OTPR OM. The extra 256 bytes of RAM will reside in locations 100H±1FFH and the extra 8K of ROM/OTPR OM will reside in locations 4000H±5FFFH. These locations are external memory on the 8XC196KB. 2. The CDE pin on the KB has become a V SS pin on the KC to support 16/20 MHz operation. 3. EPROM programming. The 8XC196KC has a dif- ferent programming algorithm to support 16K of on-board memory. When performing Run-Time Programming, use the section of code in the 8XC196KC User's Guide. 4. ONCE Mode Entry. The ONCE mode is entered on the 8XC196KC by driving the TXD pin low on the rising edge of RESET. The TXD pin is held high by a pullup that is specified by I OH1. This Pullup must not be overridden or the 8XC196KC will enter the ONCE mode. 5. During the bus HOLD state, the 8XC196KC weakly holds RD ,W R , ALE, BHE and INST in their inactive states. The 8XC196KB only holds ALE in its inactive state. 6. A RESET pulse from the 8XC196KC is 16 states rather than 4 states as on the 8XC196KB (i.e., a watchdog timer overflow). This provides a longer RESET pulse for other devices in the system. 8XC196KC ERRATA 1. Missed EXTINT on P0.7. The 80C196KC20 could possibly miss an EXTINT on P0.7. See techbit MC0893. 2. HSI_MODEdivide-by-eight. See Faxback Ý2192. 3. IPD hump. See Faxback Ý2311.

DATA SHEET REVISION HISTORY This data sheet is valid for devices with a \\H'', \\L'' or \\M'' at the end of the topside tracking number. The topside tracking number consists of nine characters and is the second line on the top side of the device. Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. The following are differences between the 270942-006 datasheet and the 270942-005 datasheet: 1. Package prefix variables have changed. Variables are now indicated by an "x" The following are differences between the 270942-004 and 270942-005 datasheets: 1. Removed \\Word Addressable Only'' from Port 3 and 4 in Table 2. 2. Renamed PVAL to CPVER. 3. Removed T LLYV and TLLGV from the waveform diagrams. 4. Added HSI_MODE divide-by-eight and IPD hump to 8XC196KC errata. The following are important differences between the 270942-002 and 270942-004 data sheets: 1. NMI during PTS, QBD port glitch and Divide HOLD/READY erratas were fixed and have been removed from the data sheet. The HSI errata is also removed as this is now considered normal operation. 2. Combined 16 and 20 MHz data sheets. Data sheet 270924-001 (20 MHz) is now obsolete. 3. Added 80-lead SQFP package pinout. 4. Added documentation for CLKOUT disable bit. 5. i JA for QFP package was changed to 55§C/W from 42 §C/W. 6. iJC for QFP package was changed to 16§C/W from TBD §C/W. 7. T SAM (MIN) in 10-bit mode was changed to 1.0ms from 3.0 ms. 8. T SAM (MIN) in 8-bit mode was changed to 1.0ms from 2.0 ms. 9. I IL1 specification for port 2.0 was renamed IIL2. 10. I IL2 (MAX) is changed to TBD from b 6 mA. 11. I IH1 (MAX) is changed to a200 mA from a100 mA. 12. I IH1 test condition changes to VIN e 2.4V from VIN e 5.5V. 13. V HYS is changed to 300 mV from 150 mV. 14. I CC (TYP) at 16 MHz is changed to 65 mA from 50 mA. 15. I CC (MAX) at 16 MHz is changed to 75 mA from 70 mA. 16. I CC (TYP) at 20 MHz is changed to 80 mA from 60 mA. 17. I CC (MAX) at 20 MHz is changed to 92 mA from 86 mA. 18. I IDLE (TYP) at 16 MHz is changed to 17 mA from 15 mA. 19. I IDLE (MAX) at 16 MHz is changed to 25 mA from 30 mA. 20. I IDLE (TYP) at 20 MHz is changed to 21 mA from 15 mA. 21. I IDLE (MAX) at 20 MHz is changed to 30 mA from 35 mA. 22. I PD (TYP) at 16 MHz is changed to 8mA from 15 mA. 23. I PD (MAX) at 16 MHz is changed to 15mA from TBD. 24. I PD (TYP) at 20 MHz is changed to 8mA from 18 mA. 25. I PD (MAX) at 20 MHz is changed to 15mA from TBD. 26. T CLDV (MAX) is changed to TOSC b45 ns from TOSC b 50 ns. 27. T LLAX (MIN) is changed to TOSC b35 ns from TOSC b 40 ns. 28. T CHWH (MIN) is changed to b5 ns from b10 ns. 29. T RHAX (MIN) is changed to TOSC b 25 ns from TOSC b 30 ns. 30. T HALAZ (MAX) is changed to a15 ns from a10 ns. 31. T HALBZ (MAX) is changed to a20 ns from a15 ns.

  1. T HAHBV (MAX) is now specified at a15 ns, was formerly unspecified. 33. The T LLYV and TLLGV specifications were removed. These specifications are not required in high-speed systems designs. 34. Added EXTINT, P0.7 errata to Errata section. The following are the important differences between the -001 and -002 versions of data sheet 270942. 1. Express and Commercial devices are combined into one data sheet. The Express only data sheet 270794-001 is obsolete. 2. Removed KB/KC feature set differences, pin definition table, and SFR locations and bitmaps. 3. Added programming pin function to package drawings and pin descriptions. 4. Changed absolute maximum temperature under bias from 0 §Ct o a70§Ct o b55§Ct o a125§C. 5. Replaced V OH2 specification with IOH1 and IIL1 specifications. 6. Added I IH1 specification for NMI pulldown resistors. 7. Added maximum hold latency table. 8. Added external oscillator and external clock circuit drawings. 9. Changed Clock Drive T XHXX and TXLXX Min spec to 20 ns. 10. Fixed Serial Port T XLXH specification. 11. Added 8- and 10-bit mode A/D operating conditions tables. 12. Specified operating range for sample and convert times. 13. Added specification for voltage on analog input pin. 14. Put operating conditions for EPROM programming into tabular format.