TN2640

TN2640_V01 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 20

Technical content

Features

• 2V Maximum Low Threshold
• High Input Impedance
• Low Input Capacitance
• Fast Switching Speeds
• Low On-Resistance
• Free from Secondary Breakdown
• Low Input and Output Leakage

Applications

• Logic-Level Interfaces (Ideal for TTL and CMOS)
• Solid-State Relays
• Battery-Operated Systems
• Photovoltaic Drives
• Analog Switches
• General Purpose Line Drivers
• Telecommunication Switches General Description The TN2640 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positiv e temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Microchip’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Package Types 3-lead TO-252 (D-PAK) (Top view) See Table 3-1, Table 3-2, and Table 3-3 for pin information. 3-lead TO-92 (Top view) 8-lead SOIC (Top view) GATE SOURCE DRAIN GATE SOURCE N/C N/C DRAIN DRAIN DRAIN DRAIN GATE SOURCE DRAIN N-Channel Enhancement-Mode Vertical DMOS FET

DS20005795B-page 2  2021-2024 Microchip Technology Inc. and its subsidiaries

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings† † Notice: Stresses above those listed under “Absolute Maxi mum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless otherwise stated. (Pulse test: 300 µs pulse, 2% duty cycle) Parameter Sym. Min. Typ. Max. Unit Conditions Drain-to-Source Breakdown Voltage BV DSS 400 — — V V GS = 0V, ID = 1 mA Gate Threshold Voltage V GS(th) 0.8 — 2 V V GS = VDS, ID = 2 mA Change in VGS(th) with Temperature ΔVGS(th) —- 2 . 5 - 4 m V / ° C V GS = VDS, ID = 2 mA (Note 1) Gate Body Leakage Current I GSS —— 1 0 0 n A V GS = ±20V, VDS = 0V Zero-Gate Voltage Drain Current I DSS — — 10 µA VGS = 0V, VDS = Maximum rating ——1 m A VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 1) On-State Drain Current I D(ON) 1.5 3.5 — A V GS = 5V, VDS = 25V 24 — A V GS = 10V, VDS = 25V Static Drain-to-Source On-State Resistance RDS(ON) —3 . 25 Ω VGS = 4.5V, ID = 500 mA —35 Ω VGS = 10V, ID = 500 mA Change in RDS(ON) with Temperature ΔRDS(ON) —— 0 . 7 5 % / ° C VGS = 10V, ID = 500 mA (Note 1) Note 1: Specification is obtained by characterization and is not 100% tested. AC ELECTRICAL CHARACTERISTICS Electrical Specifications: TA = 25°C unless otherwise specified. All AC parameters are not 100% sample tested. Parameter Sym. Min. Typ. Max. Unit Conditions Forward Transconductance G FS 200 330 — mmho V DS = 25V, ID = 100 mA Input Capacitance C ISS — 210 225 pF VGS = 0V, VDS = 25V, f = 1 MHzCommon-Source Output Capacitance C OSS —3 0 5 0 p F Reverse Transfer Capacitance C RSS — 8 15 pF Turn-On Delay Time t d(ON) —4 1 5 n s VDD = 25V, ID = 2A, RGEN = 25ΩRise Time t r — 1 52 0n s Turn-Off Delay Time t d(OFF) — 2 02 5n s Fall Time t f — 2 22 7n s DIODE PARAMETER Diode Forward Voltage Drop V SD —— 0 . 9 V V GS = 0V, ISD = 200 mA (Note 1) Reverse Recovery Time t rr —3 0 0 —n s V GS = 0V, ISD = 1A Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. (Pulse test: 300 µs pulse, 2% duty cycle)

 2021-2024 Microchip Technology Inc. and its subsidiaries DS20005795B-page 3 TN2640 TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Unit Conditions TEMPERATURE RANGE Operating Ambient Temperature T A -55 — +150 °C Storage Temperature T S -55 — +150 °C PACKAGE THERMAL RESISTANCE 3-lead TO-252 (D-PAK) JA —8 1 — ° C / W 8-lead SOIC JA —1 0 1 — ° C / W 3-lead TO-92 JA —1 3 2 — ° C / W THERMAL CHARACTERISTICS Package ID (Note 1) (Continuous) (mA) ID (Pulsed) (A) Power Dissipation at TA = 25°C (W) IDR (Note 1) (mA) IDRM (A) 3-lead TO-252 (D-PAK) 500 3 2.5 ( Note 2)5 0 0 3 8-lead SOIC 260 2 1.3 ( Note 2)2 6 0 2 3-lead TO-92 220 2 0.74 220 2 Note 1: ID (continuous) is limited by maximum TJ. 2: Mounted on an FR4 board, 25 mm x 25 mm x 1.57 mm

DS20005795B-page 4  2021-2024 Microchip Technology Inc. and its subsidiaries

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: BVDSS Variation with Temperature. FIGURE 2-2: Transfer Characteristics. FIGURE 2-3: Capacitance vs. Drain-to-Source Voltage. FIGURE 2-4: On-Resistance vs. Drain Current. FIGURE 2-5: VGS(th) and RDS(ON) Variation with Temperature. FIGURE 2-6: VGS(th) and RDS(ON) Variation with Temperature. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tabl es, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore outside the warranted range. BVDSS (normalized) 1.15 1.10 1.05 1.00 0.95 0.90 -50 0 50 100 150 Tj (OC) 3.0 2.4 1.8 1.2 0.6 ID (amperes) 0 2 4 6 8 10 VGS (volts) VDS = -25V TA = -55OC 25OC 125OC C (picofarads) 400 300 200 100 VDS (volts) 0 10 20 30 40 f = 1MHz CISS COSS CRSS 1.4 1.2 1.0 0.8 0.6 0.4 VGS(th) (normalized) -50 0 50 100 150 Tj (OC) 2.2 1.8 1.4 -1.0 0.6 0.2 RDS(ON) (normalized) RDS(ON) @ 10V, 0.5A V(th) @ 2.0mA 253pF

0 VGS (volts)

QG (nanocoulombs) VDS = 10V VDS = 40V 653pF RDS(ON) (ohms) ID (amperes) VGS = 5.0V VGS = 10V

DS20005795B-page 6  2021-2024 Microchip Technology Inc. and its subsidiaries

3.0 PIN DESCRIPTION

Table 3-1, Table 3-2, and Table 3-3 show the description of pins in TN2640. Refer to Package Types for the location of the pins. TABLE 3-1: 3-LEAD TO-252 (DPAK) PIN FUNCTION TABLE Pin Number Pin Name Description

1 Gate Gate

3 Source Source

4 Drain Drain

TABLE 3-2: 8-LEAD SOIC PIN FUNCTION TABLE Pin Number Pin Name Description

1 N/C No connect

2 N/C No connect

4 Gate Gate

5 Drain Drain

6 Drain Drain

7 Drain Drain

8 Drain Drain

TABLE 3-3: 3-LEAD TO-92 PIN FUNCTION TABLE Pin Number Pin Name Description

1 Source Source

2 Gate Gate

3 Drain Drain

 2021-2024 Microchip Technology Inc. and its subsidiaries DS20005795B-page 7 TN2640

4.0 FUNCTIONAL DESCRIPTION

Figure 4-1 illustrates the switching waveforms and test circuit for TN2640. FIGURE 4-1: Switching Waveforms and Test Circuit. 90% 10% 90% 90% 10%10% Pulse Generator VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF)tr INPUT INPUT OUTPUT 10V VDD RGEN tf TABLE 4-1: PRODUCT SUMMARY BVDSS/BVDGS (V) RDS(ON) (Maximum) (Ω) ID(ON) (Minimum) (A) VGS(th) (Maximum) (V) 400 5 2 2

DS20005795B-page 8  2021-2024 Microchip Technology Inc. and its subsidiaries

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. TO-252 (D-PAK) Example YYWWNNN XX XXXXXe3 2112541 2640 TN 3-lead TO-92 YWWNNN XXXXXX XXe3 Example 12987 TN2640

 2021-2024 Microchip Technology Inc. and its subsidiaries DS20005795B-page 9 TN2640 CTOP VIEW SIDE VIEW BOTTOM VIEW Microchip Technology Drawing C04-189 Rev C Sheet 1 of 2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 3-Lead Deca-Watt Package, TO-252 (EA) - [DPAK]; Supertex Legacy Package Code K4 A SEE DETAIL A

0.010 C A B

12N = 3 A H E BOTTOM VIEW LARGE PADSTANDARD PAD 3X b2 e L4L3 3X b Ø D

DS20005795B-page 10  2021-2024 Microchip Technology Inc. and its subsidiaries For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Microchip Technology Drawing C04-189 Rev C Sheet 1 of 2 H DETAIL A ș c L (L1) SEATING PLANE C ROTATED 90° Units b A E e D N (Leads) .090 BSC .205 .170 .250 .086 .028 .240 INCHES MIN NOM .265 .094 .035 MAX H- .370 .410 c2 .018 - .035 .065 .035 .024 - .020 BSC .077 .050 .035 -1° 5° L .055 .060 .070 7° REF L1 .108 REF ș .030 .045 .235 .245 A1 .000 - .005 c .018 - .024 3-Lead Deca-Watt Package, TO-252 (EA) - [DPAK]; Supertex Legacy Package Code K4

 2021-2024 Microchip Technology Inc. and its subsidiaries DS20005795B-page 11 TN2640 RECOMMENDED LAND PATTERN Dimension Limits Units Center Pad Width Contact Pad Spacing Center Pad Length Contact Pitch .244 .219 INCHES .090 BSC MIN E MAX .096 Contact Pad Length (Xnn) Contact Pad Width (Xnn) .112 .039 NOM C1Contact Pad Spacing .163 Contact Pad to Contact Pad (Xnn) G .412 Thermal Via Diameter V Thermal Via Pitch EV .013 .047 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing C04-2189 Rev C EV EV ØV E SILK SCREENG 3-Lead Deca-Watt Package, TO-252 (EA) - [DPAK]; Supertex Legacy Package Code K4

DS20005795B-page 12  2021-2024 Microchip Technology Inc. and its subsidiaries

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-C2X Rev K Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (C2X) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N ș c 4X ș1 4X ș1 (L1) L h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

H R VIEW C SEE VIEW C NOTE 1 D Atmel Legacy Global Package Code SWB

 2021-2024 Microchip Technology Inc. and its subsidiaries DS20005795B-page 13 TN2640 Microchip Technology Drawing No. C04-057-C2X Rev K Sheet 2 of 2 8-Lead Plastic Small Outline (C2X) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: 5. Datums A & B to be determined at Datum H. Atmel Legacy Global Package Code SWB Foot Angle 0° – 8° ––0°Lead Angle 0.51–0.31bLead Width 0.25–0.17cLead Thickness 1.27–0.40LFoot Length 0.50–0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25–0.10A1Standoff -–1.25A2Molded Package Thickness 1.75––AOverall Height

1.27 BSCePitch

Footprint L1 1.04 REF Mold Draft Angle 5° – 15° ș ––0.07R1Lead Bend Radius ––0.07RLead Bend Radius

DS20005795B-page 14  2021-2024 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-C2X Rev K BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (C2X) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

 2021-2024 Microchip Technology Inc. and its subsidiaries DS20005795B-page 15 TN2640 Microchip Technology Drawing C04-101-TO Rev D Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 3-Lead Plastic Transistor Outline (TO) [TO-92] (DATUM B) (DATUM A) VIEW A-A TOP VIEW E AL 3X b e D c N A A SIDE VIEW R

0.006 B A

DS20005795B-page 16  2021-2024 Microchip Technology Inc. and its subsidiaries Microchip Technology Drawing C04-101-TO Rev D Sheet 2 of 2 3-Lead Plastic Transistor Outline (TO) [TO-92] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 2. Dimensioning and tolerancing per ASME Y14.5M 1. Dimensions D and E do not include mold flash or protrusions. Mold flash or BSC: Basic Dimension. Theoretically exact value shown without tolerances. protrusions shall not exceed .005" per side. Notes: .022.014bLead Width .021.014cLead Thickness .105.080RMolded Package Radius .210.170AOverall Length .205.175EOverall Width .165.125DBottom to Package Flat .050 BSCePitch 3NNumber of Pins MAXMINDimension Limits INCHESUnits Tip to Seating Plane L .500 - NOM

 2021-2024 Microchip Technology Inc. and its subsidiaries DS20005795B-page 17 TN2640 APPENDIX A: REVISION HISTORY Revision B (February 2024)

• Updated Figure 2-9 in Section 2.0 “Typical Performance Curves”.
• Updated package drawings in Section 5.0 “Packaging Information”. Revision A (February 2021)
• Converted Supertex Doc# DSFP-TN2640 to Microchip DS20005795A.
• Changed the package marking format.
• Updated the quantity of the 8-lead SOIC from 2500/Reel to 3300/Reel to align it with the actual BQM.
• Removed the TO-92 N3 P002, P003, P005, P013, and P015 media types to align package specifications with the actual BQM.
• Made minor text changes throughout the document.

DS20005795B-page 18  2021-2024 Microchip Technology Inc. and its subsidiaries PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: a) TN2640K4-G : N-Channel Enhancement-Mode Vertical DMOS FET, 3-lead TO-252 (D-PAK), 2000/Reel b) TN2640LG-G: N-Channel Enhancement-Mode Vertical DMOS FET, 8-lead SOIC, 3300/Reel c) TN2640N3-G: N-Channel Enhancement-Mode Vertical DMOS FET, 3-lead TO-92, 1000/Bag PART NO. Device Device: TN2640 = N-Channel Enhancement-Mode Vertical DMOS FET Packages: K4 = 3-lead TO-252 (D-PAK) LG = 8-lead SOIC N3 = 3-lead TO-92 Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Types: (blank) = 2000/Reel for a K4 Package = 3300/Reel for an LG Package = 1000/Bag for an N3 Package XX Package - X - X Environmental Media Type Options

 2021-2024 Microchip Technology Inc. and its subsidiaries DS20005795B-page 19 This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this informa- tion in any other manner violates these terms. Information regarding device applications is provided only for your conve- nience and may be superseded by updates. It is your responsi- bility to ensure t hat your applicatio n meets with your specifications. Contact your lo cal Microchip sales office for additional support or, obtai n additional support at https:// www.microchip.com/en-us/support/design-help/client-support- services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE , INCIDENTAL, OR CONSE- QUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applica- tions is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses ar e conveyed, implicitly or otherwise, under any Microchip intellectual pr operty rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter- Chip Connectivity, JitterBlocker, Knob-on-Display, MarginLink, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART- I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY , ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2024, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. ISBN: 978-1-6683-4038-7 Note the following details of the code protection feature on Microchip products:

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