TN1200 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

information on 400 µm Flip Chips, see Application note AN2348. developed packages with reduced size, thickness and weight in the form of the Flip Chip. connections than the ones in standard plastic packages (such as TSSOP, SSOP or BGA). Figure 1. Micro-bumped flip-chip packages are available in mass production.

  • Product description
  • Mechanical description
  • Packing specifications and labeling description
  • Recommended storage and shipping instructions
  • Soldering assembly recommendations
  • User responsibility and returns
  • Changes
  • Delivery quantity
  • Quality 0DWUL[ 3HULSKHUDO 3HULSKHUDO ZLWKRXWFRUQHU

Product description TN1200

1 Product description

Flip Chips are manufactured with a wafer level process that STMicroelectronics has developed by attaching solder bumps on I/O pads of the active wafer side, thus allowing bumped dice to be produced. The I/O contact layout can be either matrix shape or set in periphery. No redistribution layer is used. This allows parasitic inductances coming from the redistribution metal tracks to be minimized. Paste composition is 96.5% Sn, 3% Ag, 0.5% Cu, SAC305. This is fully compatible with standard lead-free reflow processes. The bump dimension allows the pick and place process to be compatible with existing equipment (in particular with equipment used for ball grid array - BGA packages) and makes it also compatible with the PCB design rules used for standard ICs. These components are delivered in tape and reel packing with the bumps turned down (placed on the bottom of the carrier tape cavity). The other face of the component is flat and allows picking as in the standard SMD packages. Devices are 100% electrically tested before packing. The product references are marked on the flat side of the device.

2 Mechanical description

Mechanical dimensions of Flip Chips are provided through a product example in Figure 2. Figure 2. Mechanical dimensions of a 4 x 2 bump matrix array (sample). Note: The package height of 290 µm is valid for a die thickness of 200 µm. through vertical focuses show a bump plus die coplanarity below 50 µm. detected by standard vision systems. Marking dimensions are linked to the die size.

Figure 3. Flip Chip marking example (only for Si and HRSi)

  • “Dot” used for die thickness > 200 µm
  • “LL” used for die thickness < 200 µm

3 Packing specifications and labeling description

section are in accordance with EIA-481-D, IEC 60286-3 and EIA 763 (783) standards.

3.1 Carrier tape

Figure 4. Standard tape width is 8 mm for die sizes smaller than 3 mm (dimension B0). Figure 4. Carrier tape example

components. Specific hole is present to improve device stability during sealing and pick up.

3.2 Cover tape

tensile strength is higher than 10 N. between 165 and 180 degrees and the test is done at a speed of 120 ±10% mm/minute.

3.3 Reels

compliance with the IEC 60286-3, each reel contains a maximum of 0.1% empty cavities. from 2 different wafer lots. the end of the reel and consists of empty, sealed cavities (see Figure 6). Table 1. Tape cavity sizing component rotation cannot exceed 10° max.

3.4 Final packing

polyethylene bag (minimum of 4 mils material thickness). Reels are then packed in cardboard boxes. The complete description for packing is shown on Figure 7. Figure 7. Packing flow chart

3.5 Labeling

shipped quantity and traceability references ( Figure 8). history from the wafer fab to the customer’s location. Figure 8. Example of a reel label

Table 2. Parameter reel label

TN1200 Recommended storage, shipping instructions and descriptions

4 Recommended storage, shipping instructions and

Flip-Chip reels are packed under inert N 2 atmosphere in a sealed bag. For shipment and handling, reels are packed in a cardboard box. STMicroelectronics thus recommends the following shipping and storage conditions:

  • Relative humidity between 15% and 70%
  • Temperature range from -55 °C to +150 °C Components in a non opened sealed bag can be stored 6 months after shipment. Components in tape and reel must be protected from exposure to direct sunlight. Moisture sensitivity level (MSL as per JEDEC J-STD-020C) is not applicable to Flip-Chip devices since there is no plastic encapsulation and so no risk of moisture absorption and related possible package cracks.

5 Soldering assembly recommendations

5.1 PCB design recommendations for multi-pads Flip Chips

recommends the PCB design guidelines for each bumps configuration. Note: A too thick gold layer finishing on the PCB pad is not recommended (low joint reliability). size have to be properly designed (see Figure 9). Figure 9. Footprint the pads are connected to the lower layers using micro vias. Table 3. PCB design recommendations example.

5.2 PCB assembly guidelines

Figure 10. ST ECOPACK reflow, specially above 150 °C. prevent any bump cracks, ultrasonic cleaning methods are not recommended. Table 4. ST ECOPACK

Soldering assembly recommendations TN1200

5.3 Underfilling

Underfilling is not essential for Flip Chips. These devices can do without an underfill if the process temperature does not exceed 175 °C and if the process time is short (typically 5 minutes).

5.4 Manual rework

Flip Chips are able to tolerate one repair in addition to the two reflow mentioned in Section 5.2. As for other BGA type packages the use of laser systems is the most suitable form for Flip Chip repair. Manual hot gas soldering is acceptable but iron soldering is not recommended. For leaded Flip Chip manual rework the maximum temperature allowed is 260 °C (lead-free compatibility) and dwell time must not exceed 30 seconds. For lead-free Flip Chip manual rework, the maximum temperature allowed is 260 °C. The typical soldering profile of Figure 10 can be used.

5.4.1 Rework procedure

Rework process start with the removal of the device. To remove the device, heat must be applied to melt the solder joints so that the component can be lifted from the board. Large area bottom side preheater may be used to raise the temperature of the board. This may help to minimize warping of the board, and minimize the amount of heat that must be applied on the component. Top heating may be applied to the component by using a laser or a convective hot gas nozzle. Nozzle size must be selected to match the component footprint appropriately. After top heating has melted the solder, vacuum is applied through the pick-up nozzle, and the component is lifted from the board. The heat should be carefully directed at the component to be removed to avoid adjacent components solder joints being reflowed. Shielding, control of gas flow from the nozzle, and accurate temperature control are the key parameters. Removing solder Next step is cleaning the solder from the work site. Due to space constraints and the need for accurate temperature control, automatic tools are recommended. Typically, site cleaners consist of controlled non-contact gas heating and vacuuming tools. The objective is to remove the residual solder from the site without damaging the pads, solder masks or adjacent com ponents, and to prepare the site for application of new component.

  • Fully automated X,Y, Z and theta control
  • Fully automated alignment using digital feature separation (DFS) technology
  • Precision force sensor and mass flow controller
  • Four zone bottom preheater
  • Flux dipping station
  • Fire-wire (IEEE 1394) controls
  • Visual machines software
  • Machine table including power supply cabinet ONYX32 Options
  • Dispensing head for solder paste, flux, underfill or adhesives
  • Non-contact temperature sensor
  • Site solder removal system

6 Changes

STMicroelectronics reserves the right to implement minor changes of geometry and manufacturing processes without prior notice. Such changes will not affect electrical characteristics of the die, the pad layout or the maximum die size. However for confirmed orders, no variation will be made without cu stomer’s approval.

7 Quality

7.1 Electrical inspection

Products in Flip Chip are 100% electrically probed according to the critical parameters of the ST product specification. The last operation before packing is 100% electrical testing. The other parameters are guaranteed by technology, design rules and by continuous monitoring systems.

7.2 Visual inspection

A visual control is performed on all manufacturing lots according to the MIL-STD-883 method 2010.

8 Conclusion

applications where integration and performan ce are the main concerns of designers.

  • Remarkable board space saving (package size equal to die size and total height less than 380 µm)
  • Enhanced electrical performance (minimized parasitic inductance due to very short electrical paths and absence of redistribution layer)
  • High reliability due to integration of a whole function traditionally based on discrete interconnected components. Flip Chips are delivered in tape and reel and are fully compatible with other high volume SMD components (standard plastic packages or CSP/BGA packages) regarding existing pick and place equipment, standard solder reflow assembly equipment and standard PCB techniques.

9 Revision history

Table 5. Document revision history 10-Dec-2014 1 Initial release.