TN0436 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Introduction
  • 2 Differences cut1 and cut2
  • 2.1 Errata fixes
  • 2.2 Feature enhancements
  • 2.2.1 Nexus - NXSS
  • 2.2.2 Nexus - RDY PIN
  • 2.2.3 Nexus - DDR mode – I/O timing
  • 2.2.4 DSPI - enhanced version
  • 2.2.5 CRC Unit - support for additional polynominal
  • 2.2.6 AIPS MPROT - enhanced protection features
  • 2.2.7 MC_RGM - destructive reset can be triggered by software
  • 2.2.8 SSCM - easier access to NVM calibration data
  • 2.3 Device ID codes
  • 2.4 Pin muxing

1 Introduction

Table 1. Order codes

2 Differences cut1 and cut2

  • Errata fixes
  • Feature enhancements
  • ID codes
  • Pin muxing

2.1 Errata fixes

Table 2 shows the currently known errata for cut1 and the planned fixes for cut2. Table 2. Errata for cut1 and the fixes for cut2 e5299PS NEXUS Critical signals of Nexus debugger not monitored by FCCU. e5302PS JTAG Critical signals of JTAG not monitored by FCCU. e5681PS NEXUS Nexus interface availability is indicated too early. when device configured in DPM. e7292PS XOSC External oscillator is not controllable. e7811PS ADC1 Enabling of conversions of shared channels using ADC1. conversion mode on shared ADC channels. mode to safe/halt/stop mode. e5932PS FLASH RWW errors not correctly flagged at high system frequencies. e10483IPG DSPI DSPI: PCS Continuous Selection Format limitation. e18427IPG DSPI DSPI: DSPI Microsecond Bus Limitations. e8814PS ADC ADC parameters on negative current injection out of specification. e7764PS NEXUS Nexus stall feature not supported in lockstep mode. e5455PS BAM BAM: BookE mode not supported for serial downloads. e6020PS BAM BAM: autobaud feature is not available. respective peripheral is disabled at MC_ME.

condition causing the SAFE mode request has not been cleared. e6041PS ME MC_ME: peripherals in unknown state after SAFE mode exit. e6440PS MC SWT interrupt does not cause STOP0 mode exit. e6699PS CGM MC_CGM: short glitch may occur on output clock. frequency too high or too low event". possible incorrect counting of 1 tick. e9414PS eTimer Possible false DMA requests from eTimer. e6886PS NPC MCKO clock gating not implemented. low and then high in the same cycle the output signals are low. e6500PS ADC VREFP and VDD_HV_ADC power up sequencing constraint. e5485PS ADC ADC: ADC_DMAE[DCLR] should not be used. register of next channel conversion. e1685PS FMPLL FMPLL: FMPLL_CR[UNLOCK_ONCE] wrongly set. e7220PS SWG SWG: SGEN_CTRL.NRO bit is reserved *). e8099 PS DMA Limiations for DMA access to LINFlex. e7752PS Platform ICache commands ICBTLS and ICBLC do not work as specified. Table 2. Errata for cut1 and the fixes for cut2 (continued)

TN0436 Differences cut1 and cut2 Doc ID 18327 Rev 2 6/10

2.2 Feature enhancements

The list below shows feature enhancements for cut2.

  • Nexus - NXSS
  • Nexus - RDY PIN
  • Nexus – DDR mode – I/O timing
  • DSPI enhanced version
  • CRC Unit - support for additional polynominal
  • AIPS MPROT - enhanced protection features
  • MC_RGM - destructive reset can be triggered by software
  • SSCM - easier access to NVM calibration data
  • Selftest - reduction of execution time

2.2.1 Nexus - NXSS

The Nexus Crossbar Slave Port Data Trace Module for System SRAM allows to trace all DMA/SRAM accesses.

2.2.2 Nexus - RDY PIN

To increase the transfer rate of the IEEE 1149.1 port, an additional pin has been implemented to signal when data are ready to be transferred to and from NRRs. This may eliminate the need to poll NRRs for status information for synchronization purposes. This capability becomes especially important when performing read/write access transfers to different speed target memories. This functionality is only available on BGA257 package (ball K3). RDY is muxed with GPIO (GPIO is default out of reset).

2.2.3 Nexus - DDR mode – I/O timing

The I/O timing has been changed so that the MDO / MSEO outputs are valid during the MCKO rising and falling edges.

2.2.4 DSPI - enhanced version

Support higher net through put in slave mode by reducing required dead cycles in back to back operation.

2.2.5 CRC Unit - support for additional polynominal

An additional 8-bit CRC polynomial has been implemented. The bit field 28:29 of the register CRC_CFG for each context selects the polynomial preserving compatibility with previous versions of this IP used on cut1.

2.2.6 AIPS MPROT - enhanced protection features

The default reset MPROT (Master Protection) configuration for each AIPS bridge is determined via the aips_rstcfg vector which has been changed.

TN0436 Differences cut1 and cut2 Doc ID 18327 Rev 2 7/10 In general in both modes of operation only the two cores (Instruction Port, Load/Store Port and the Nexus subsystem) have access rights to the IPS peripherals per default configuration.

2.2.7 MC_RGM - destructive reset can be triggered by software

Additional support for software triggerable destructive reset event (D[14]) has been implemented.

2.2.8 SSCM - easier access to NVM calibration data

The selftest execution time has been reduced compared to cut1 by appr. 13 ms. The information is documented in the SPC56EL60L3, SPC56EL60L5 datasheet (see Appendix A: Reference document) as part of the reset sequence specification.

2.3 Device ID codes

SPC56EL60xx contains ID codes which identify the device.

  • JTAG ID Cut1: 0000_1010_1110_1010__0010_0000_0100_0001 Cut2: 0000_1010_1110_1010__0011_0000_0100_0001
  • MCU ID Register 1 (MIDR1)
  • MCU ID Register 2 (MIDR2) The values of these ID codes differ between cut1 and cut2.

2.4 Pin muxing

SPC56EL60xx cut2 is pin-compatible with cut1. Cut2 specifies an additional RDY pin for the BGA257 package (ball K3). On cut1 this ball is not connected to any function. The RDY pin on cut2 is muxed with GPIO (GPIO is default out of reset).

Appendix A Reference document 1. 32-bit Power Architecture ™ microcontroller for automotive SIL3/ASILD chassis and safety applications (SPC56EL60L5 - SPC56EL60C3 errata sheet - Doc ID 16945). 2. 32-bit Power Architecture ® microcontroller for automotive SIL3/ASILD chassis and safety applications (SPC56EL60L5 - SPC56EL60C3 datasheet - Doc ID 15457).

Revision history

Table 3. Document revision history 03-Jan-2011 1 Initial release. 18-Sep-2013 2 Updated Disclaimer.