TN0108 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Summary of differences
- 2 Memory and memory control
- 2.1 SRAM size
- 3 Pin configuration
- 3.1 Additional GPIO on JTAG pins
- 3.2 Medium speed pad allocation
- 3.3 Input/output state during and after reset
- 3.4 GPIO pin configuration in standby mode
- 4 Debug
- 4.1 Debug through LPM
- 4.2 JTAG operation in safe mode
- 4.3 Nexus configuration
- 5 Peripherals
- 5.1 Peripheral clock prescalers
- 5.2 ADC register map change
- 5.3 ADC additional external result registers
- 5.4 ADC multiplex control
- 5.5 ADC clock prescaler divider
- 5.6 ADC abort modification
- 5.7 ADC offset calculation
- 5.8 LINFlex slave configuration change
- 5.9 LINFlex slave filters
- 6 Reset and BAM
- 6.1 Reset Configuration Halfword (RCHW)
- 6.2 Correct reset event-disable feature
- 6.3 Write once protection of reset configurati on registers
devices targeted at automotive body applications. Cut 1.1 silicon and will require to migrate to the Cut 2 device. sections in the latest reference manual and errata document. The Table 1 shows the full part numbers and device identification. differences between the B and C variants, please consult the reference manual. Table 1. Device identification
1 Summary of differences
Table 2. Summary of differences
Table 2. Summary of differences (continued)
2 Memory and memory control
2.1 SRAM size
to create a contiguous 48 KB block on Cut 2. as a 32-bit read modify write in order to update the ECC. Table 3. SRAM size differences
3 Pin configuration
3.1 Additional GPIO on JTAG pins
been created for this purpose.
- The functionality of PH[9] and PH[10] cannot be debugged using a JTAG debug interface.
- If external application hardware is connected to PH[9] or PH[10], this may interfere with JTAG signals, making it impossible to enter debug mode without disconnecting the external hardware. This could be solved with an external multiplexer or jumpers.
- Setting the SIU to GPIO on PH[9] or PH[10] will prevent communication with the debugger, so debugging normal application code is impossible after the PCR of PH[9] or PH[10] has been modified to GPIO. These pins can only be set back to TCK/TMS via software (in other words, this cannot be done automatically by a JTAG debugger). Note: All references to JTAG are also applied to Nexus and these pins impact both JTAG and Nexus debug, as the signals are used in both interfaces.
3.2 Medium speed pad allocation
pads on Cut 1.1 to medium/slow pads on Cut 2. Table 4. JTAG pins Table 5. Additional medium speed pads
25 medium speed pads in the 100 QFP package. the maximum current, as defined in the device datasheet.
3.3 Input/output state during and after reset
On Cut 1 devices, the input/output pins are set to high impedance (tri stated) during reset. state, once the reset has been released.
- PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from Flash
- PA[8] (ABS) is pull-up
- RESET pad is driven low. This is pull-up only after PHASE2 reset completion
- JTAG pads (TCK, TMS, and TDI) are pull-up, whilst TDO remains tri state
- Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output
3.4 GPIO pin configuration in standby mode
on standby exit, until such a point as the pull-up is cleared by software. Table 6. I/O state during and after reset
4 Debug
4.1 Debug through LPM
mode, and that debug capability is re-initiated as soon as the MCU starts to wake up.
4.2 JTAG operation in safe mode
session is terminated as soon as the pins tri state. JTAG pins alive in safe mode, thus allowing debug through safe mode by default.
4.3 Nexus configuration
development tool vendors have already implemented this change for Cut 2.
- ACCESS_AUX_TAP_ONCE 10001 grants the platform ownership of the TAP
- ACCESS_AUX_TAP_NPC 10010 grants the Nexus Port Controller (NPC) ownership of the TAP . On Cut 2 Devices, these commands are modified to be in-line with previous eSYS devices with:
- ACCESS_AUX_TAP_ONCE 10001 grants the platform ownership of the TAP
- ACCESS_AUX_TAP_NPC 10000 grants the Nexus Port Controller (NPC) ownership of the TAP
Table 7. JTAG pins SMC control
5 Peripherals
5.1 Peripheral clock prescalers
peripheral clock prescalers. Table 8. System clock dividers
5.2 ADC register map change
format of other peripherals (for example including a Module Configuration Register). detailed in the next three sections.
5.3 ADC additional external result registers
multiplexers (controlled by the MA[0..2] bits) to provide up to 32 extended ADC channels. Cut 1.1 devices have a single result register for each of the four external ADC channels. channel in the same manner as an internal channel. Table 9. RGM_DERD and RGM_FERD write-once protection externally multiplexed channel.
5.4 ADC multiplex control
positions, as detailed in the table below. On Cut 2 devices, an additional pad multiplexing for MA[0] and MA[1] has been added.
5.5 ADC clock prescaler divider
stay operational, rather than in a LP mode, so increasing the average power consumption. the ADC clock to the system frequency. Table 10. MA[0..2] pad multiplexing locations Table 11. ADC clock prescaler
- The configuration of ADC clock = system clock is only valid for LPM wakeup when running on the 16 MHz
clock should be set to system clock/2.
5.6 ADC abort modification
before a new conversion chain can be issued. also cleared. For more details consult the device reference manual.
5.7 ADC offset calculation
The offset calculation mechanism has been removed for Cut 2 devices.
5.8 LINFlex slave configuration change
has eight identifiers filters). functionality. The remaining three LINFlex modules have been changed to master only. application code will need to be changed, if this was not using LINFlex channel zero. Table 12. ADC conversion chain abort Table 13. LINFlex configuration
5.9 LINFlex slave filters
channels supported slave mode). the number of ID filters increased from eight to 16. channel types (X, Y , and F). additional four modes, as detailed in the table below. Table 14. LINFlex slave filters Table 15. eMIOS modes
On Cut 2 devices, the new channel types are implemented as follows:
- eMIOS 0 ch1-7, channel type G
- eMIOS 0 ch9-15, channel type H
- eMIOS 1 ch9-15, channel type H For more details on the specifics of each mode and channel groupings, consult the device reference manual.
6 Reset and BAM
6.1 Reset Configuration Halfword (RCHW)
the upper 32-bits of the address space, as defined in the table below. found and the device will not successfully boot from Flash.
6.2 Correct reset event-disable feature
not desirable to be able to lock out all reset sources. only, so the reset sources within DERD cannot be disabled. Table 16. RCHW differences
For further details on the FERD and DERD registers, consult the device reference manual.
6.3 Write once protection of reset configuration registers
that any attempt to write to DERD will not impact the write-once mechanism for FERD. Table 17. Reset event disable via RGM_DERD and RGM_FERD
6.4 Unused BAM space abort
defined as an illegal instruction, which can be trapped. BAM location within the ROM block, an undefined operation would result. attempt to execute from within this area will result in an exception. Table 18. RGM_DERD and RGM_FERD write-once protection so with single 32-bit write.
7 Clocks (including RTC)
7.1 Invalid clock selection inhibit
peripheral clock disabled, the system hung with no response. determined by reading the ME_PSx registers.
7.2 RTC counter updates
stopped the counter, but also had the effect of resetting the counter. without halting the counter. get a timer compare almost immediately after modifying the RTVAL. Table 19. Unclocked peripheral behavior SPC560B Cut 1.1 Non-reco verable system hang. SPC560B Cut 2 System does not hang. Us er notified via IVOR2 exception. Table 20. Real-time counter
7.3 RTC operation throug h non-destructive reset
watchdog reset) is issued, the RTC (real-time clock) is reset. run and keep time through a non-destructive reset.
7.4 External 32 kHz oscillator
reference manual and datasheet. Table 21. RTC operation through non-destructive reset
8 CTU (Cross Triggering Unit)
8.1 CTU source update
which channel triggers the conversion. used in conjunction with the ADC for lighting applications. showing all of the CTU channel sources.
8.2 CTU PIT/eMIOS configuration change
On Cut 2 devices, PIT_3 has been moved to CTU channel 23. For the full CTU trigger source mapping, consult the device reference manual. Table 22. Additional CTU sources Table 23. CTU PIT trigger source
9 Power, low power, and wakeup
9.1 API/RTC wakeup source
On Cut 1 devices, the RTC and API shared the same wakeup source. On Cut 2 devices, the API is wakeup source zero and the RTC is wakeup source one.
9.2 Halt mode defect fixed
been fixed on Cut 2 devices.
9.3 Standby mode exit Flash control
DRUN_DFLA and DRUN_CFLA bits in the RGM_STDY register. the DFLAON and CFLAON bits in the ME_DRUN_MC register.
9.4 Voltage regulator power up current clamping
dipping with potential reset consequences. Table 24. Wakeup sources
- Note that the Cut 1.1 wakeup source one, PA0, has been replaced by the RTC on Cut 2 devices. PA0
Table 25. Standby mode exit Flash control
Power, low power, and wakeup TN0108 24/26 Doc ID 15874 Rev 2 On Cut 2 devices, the voltage regulator has been current-clamped to 200 mA, so the bulk- storage capacitors on the customer board can be smaller and more optimized. Note that hardware designed for Cut 1.1 will be fully functional with Cut 2 devices, but if the bulk capacitors have been reduced for Cut 2 hardware, this hardware will not support Cut 1.1.
Table 26. Document revision history 16-Jun-2009 1 Initial release. 18-Sep-2013 2 Updated Disclaimer.