Microcontroller

TMX5703137BPGEQQ1

Texas Instruments

TMS570LS3137 16/32-Bit RISC Flash Microcontroller

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 TMS570LS313716/32-BitRISCFlashMicrocontroller Check forSamples: TMS570LS3137

1 TMS570LS3137 16/32-BitRISC FlashMicrocontroller

1.1 Features

High-PerformanceAutomotive Grade • MultipleCommunication Interfaces MicrocontrollerforSafetyCriticalApplications – 10/100Mbps EthernetMAC (EMAC) – Dual CPU ’s runninginlockstep • IEEE 802.3compliant(3.3V-I/Oonly) – ECC on flashand RAM interfaces • Supports MIIand MDIO – Built-InSelfTestforCPU and on-chipRAMs – FlexRay Controllerwith2 channels – ErrorSignalingModule withErrorPin • 8KB message RAM withparityprotection – Voltageand Clock Monitoring • DedicatedTransferUnit(FTU)
ARM ® Cortex™ – R4F 32-bitRISC CPU – Three CAN Controllers(DCAN) – Efficient1.6DMIPS/MHz with8-stagepipeline • 64 mailboxes withparityprotectioneach – Floating-PointUnitwithSingle/Double • Compliant toCAN protocolversion2.0B Precision – Inter-IntegratedCircuit(I2C) – 12-RegionMemory ProtectionUnit – Three Multi-bufferedSerialPeripheral – Open Architecturewith3rd PartySupport Interfaces(MibSPI)
OperatingConditions • 128 Words withParityProtectioneach – Up to180MHz System Clock – Two Standard SerialPeripheralInterfaces – Core Supply Voltage(VCC):1.2Vnominal (SPI) – I/OSupply Voltage(VCCIO):3.3Vnominal – LocalInterconnectNetwork Interface(LIN) Controller• IntegratedMemory
Compliant toLIN protocolversion2.1– Up to3MB Program FlashwithECC – Standard SerialCommunication Interface– Up to256KB RAM withECC (SCI)– 64KB Flashforemulated EEPROM
Two High-End Timer Modules (N2HET)• 16-bitExternalMemory Interface – N2HET1: 32 programmable channels• Common PlatformArchitecture – N2HET2: 20 programmable channels– Consistentmemory map across family – 160 Word InstructionRAM withparity– Real-TimeInterruptTimer (RTI)OS Timer protectioneach– 96-channelVectoredInterruptModule (VIM) – Each includesHardware Angle Generator– 2-channelCyclicRedundancy Checker (CRC) – DedicatedTransferUnitforeach N2HET• DirectMemory Access (DMA) Controller (HTU)– 16 Channels and 32 ControlPackets • Two 10/12-bitMulti-BufferedADC Modules– ParityprotectionforcontrolpacketRAM – ADC1: 24 channels– DMA Accesses Protectedby DedicatedMPU – ADC2: 16 channels• Frequency-ModulatedPhase-Locked-Loop – 16 shared channels(FMPLL) withBuilt-InSlipDetector – 64 resultbufferswithparityprotectioneach• SeparateNon-ModulatingPLL forFlexRay • Packages• IEEE 1149.1JTAG, Boundary Scan and ARM – 144-pinQuad Flatpack(PGE) [Green]CoreSightComponents – 337-BallGridArray(ZWT) [Green]• JTAG SecurityModule
Trace and CalibrationCapabilities – Embedded Trace Macrocell(ETM-R4) – Data ModificationModule (DMM) – RAM Trace Port(RTP) – Parameter OverlayModule (POM) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCT PREVIEW informationconcernsproductsintheformative Copyright© 2011,Texas InstrumentsIncorporatedor design phase of development.Characteristicdata and other specificationsaredesigngoals.Texas Instrumentsreservestheright tochange ordiscontinuetheseproductswithoutnotice.

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

1.2 Applications

Brakingsystems (ABS and ESC)
Electricpower steering(EPS)
HEV/EV invertersystems
Batterymanagement systems
Activedriverassistancesystems
Aerospace and avionics
Railwaycommunications
Offroad vehicles

2 TMS570LS3137 16/32-BitRISC FlashMicrocontroller Copyright© 2011,Texas InstrumentsIncorporated

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

1.3 Description

The TMS570LS3137 isa highperformanceautomotivegrade microcontrollerfamilyforsafetysystems. The safetyarchitectureincludesDual CPUs inlockstep,CPU and Memory Built-InSelfTest(BIST)logic, ECC on boththeFlashand thedataSRAM, parityon peripheralmemories,and loopback capabilityon peripheralIOs. The TMS570LS3137 integratestheARM ® Cortex™-R4F FloatingPointCPU whichoffersan efficient1.6 DMIPS/MHz, and has configurationswhichcan runup to180MHz providingup to288 DMIPS. The device supportsthebig-endian[BE32]format. The TMS570LS3137 has up to 3MB integratedFlashand up to 256KB data RAM configurationswith singlebiterrorcorrectionand doublebiterrordetection.The flashmemory on thisdeviceisa nonvolatile, electricallyerasableand programmable memory implementedwitha 64-bit-widedatabus interface.The flashoperateson a 3.3V supplyinput(same levelas I/O supply)forallread,program and erase operations.When inpipelinemode, theflashoperateswitha system clockfrequencyofup to180MHz. The SRAM supportssingle-cycleread/writeaccessesinbyte,halfword,and word modes. The TMS570LS3137 devicefeaturesperipheralsforreal-timecontrol-basedapplications,includingtwo Next GenerationHigh End Timer (N2HET) timingcoprocessorswithup to 44 totalIO terminalsand a 12-bitAnalog-to-Digitalconvertersupportingup to24 inputs. The N2HET isan advanced intelligenttimerthatprovidessophisticatedtimingfunctionsforreal-time applications.The timerissoftware-controlled,usinga reduced instructionset,witha specializedtimer micromachineand an attachedI/O port.The N2HET can be used forpulsewidthmodulated outputs, captureor compare inputs,or general-purposeI/O.Itisespeciallywellsuitedforapplicationsrequiring multiplesensorinformationand driveactuatorswithcomplex and accuratetimepulses.A High End Timer TransferUnit(HET-TU) can performDMA type transactionsto transferN2HET data to or from main memory. A Memory ProtectionUnit(MPU) isbuiltintotheHET-TU. The devicehas two 12-bit-resolutionMibADCs with24 totalchannelsand 64 words of parityprotected bufferRAM each.The MibADC channelscan be convertedindividuallyorcan be groupedby softwarefor sequentialconversionsequences.Sixteenchannelsare shared between the two MibADCs. There are threeseparategroupings.Each sequence can be convertedonce when triggeredor configuredfor continuousconversionmode. The devicehas multiplecommunicationinterfaces:threeMibSPIs,up totwo SPIs,one LIN,one SCI,three DCANs, one I2C ,one Ethernet,and one FlexRay™ controller.The SPI providesa convenientmethod of serialinteractionforhigh-speedcommunicationsbetween similarshift-registertype devices.The LIN supportstheLocalInterconnectstandard2.0and can be used as a UART infull-duplexmode usingthe standardNon-Return-to-Zero(NRZ) format.The DCAN supportsthe CAN 2.0B protocolstandardand uses a serial,multimastercommunicationprotocolthatefficientlysupportsdistributedreal-timecontrolwith robustcommunicationratesof up to 1 megabitper second (Mbps).The DCAN isidealforapplications operatingin noisyand harsh environments(e.g.,automotiveand industrialfields)thatrequirereliable serialcommunicationor multiplexedwiring.The FlexRay uses a dual channelserial,fixedtime base multimastercommunicationprotocolwithcommunicationratesof 10 megabitsper second (Mbps) per channel.A FlexRayTransferUnit(FTU) enablesautonomous transfersofFlexRaydatatoand frommain CPU memory. Transfersare protectedby a dedicated,built-inMemory ProtectionUnit(MPU). The Ethernetmodule supportsMIIand MDIO interfaces. The I2C module is a multi-mastercommunication module providingan interfacebetween the microcontrollerand an I2C compatibledeviceviatheI2C serialbus.The I2C supportsboth100 Kbps and 400 Kbps speeds. The frequency-modulatedphase-lockedloop (FMPLL) clockmodule is used to multiplythe external frequencyreferencetoa higherfrequencyforinternaluse.The FMPLL providesone oftheseven possible clocksourceinputstotheglobalclockmodule (GCM). The GCM module manages themapping between theavailableclocksourcesand thedeviceclockdomains. Copyright© 2011,Texas InstrumentsIncorporated TMS570LS3137 16/32-BitRISC FlashMicrocontroller 3 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com The devicealsohas an externalclockprescaler(ECP) module thatwhen enabled,outputsa continuous externalclockon theECLK pin/ball.The ECLK frequencyisa user-programmableratiooftheperipheral interfaceclock(VCLK) frequency.Thislowfrequencyoutputcan be monitoredexternallyas an indicatorof thedeviceoperatingfrequency. The DirectMemory Access Controller(DMA) has 16 channels,32 controlpacketsand parityprotectionon itsmemory. A Memory ProtectionUnit(MPU) isbuiltintotheDMA toprotectmemory againsterroneous transfers. The ErrorSignalingModule (ESM) monitorsalldeviceerrorsand determineswhether an interruptor externalErrorpin/ballistriggeredwhen a faultisdetected.The nERROR can be monitoredexternallyas an indicatorofa faultconditioninthemicrocontroller. The ExternalMemory Interface(EMIF)providesa memory extensiontoasynchronousand synchronous memories orotherslavedevices. Severalinterfacesareimplementedtoenhance thedebuggingcapabilitiesofapplicationcode.Inaddition to the builtin ARM Cortex™-R4F CoreSight™ debug features.An ExternalTrace Macrocell(ETM) providesinstructionand datatraceofprogramexecution.Forinstrumentationpurposes,a RAM TracePort Module (RTP) isimplementedtosupporthigh-speedtracingofRAM and peripheralaccessesby theCPU or any othermaster.A Data ModificationModule (DMM) givestheabilitytowriteexternaldataintothe devicememory. Both theRTP and DMM have no oronlyminimum impacton theprogram executiontime of the applicationcode. A Parameter OverlayModule (POM) can re-routeFlash accesses to internal memory or to the EMIF, thus avoidingthe re-programmingstepsnecessaryforparameterupdates in Flash. With integratedsafetyfeaturesand a wide choice of communication and controlperipherals,the TMS570LS3137 isan idealsolutionforhighperformancerealtimecontrolapplicationswithsafetycritical requirements.

4 TMS570LS3137 16/32-BitRISC FlashMicrocontroller Copyright© 2011,Texas InstrumentsIncorporated

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PRODUCT□PREVIEW DMA POM DMM HTU1 FTU HTU2 EMAC Switched□Central□Resource Switched□Central□Resource Main□Cross□Bar: Arbitration□and□Prioritization□Control CRC Switched□Central□Resource Peripheral□Central□Resource□Bridge Dual□Cortex-R4F CPUs□in□Lockstep EMAC□Slaves Switched□Central□Resource MibADC1 DCAN1 MibADC2 DCAN2 DCAN3 LIN SCI I2CN2HET1 FlexRayGION2HET2 SPI4 64□KB□Flash for□EEPROM Emulation with□ECC MDIO MII MibSPI1 CAN1_RX CAN1_TX CAN2_RX CAN2_TX CAN3_RX CAN3_TX MIBSPI1_CLK MIBSPI1_SIMO[1:0] MIBSPI1_SOMI[1:0] MIBSPI1_nCS[5:0] MIBSPI1_nENA SPI2 SPI2_CLK SPI2_SIMO SPI2_SOMI SPI2_nCS[1:0] SPI2_nENA MibSPI3 MIBSPI3_CLK MIBSPI3_SIMO MIBSPI3_SOMI MIBSPI3_nCS[5:0] MIBSPI3_nENA SPI4_CLK SPI4_SIMO SPI4_SOMI SPI4_nCS0 SPI4_nENA MibSPI5 MIBSPI5_SIMO[3:0] MIBSPI5_SOMI[3:0] MIBSPI5_nCS[3:0] MIBSPI5_nENA LIN_RX LIN_TX SCI_RX SCI_TX IOMM PMM VIM RTI DCC1 DCC2 Flash with ECC ETM-R4RTP 64K 64K 64K 64K RTPCLKRTPnENARTPSYNCRTPDATA[15:0] TRACECLKINTRACECLKTRACECTLETMDATA[31:0]DMMCLKDMMnENADMMSYNCDMMDATA[15:0]256K RAM with ECC MDCLK MDIO MII_RXD[3:0] MII_RXER MII_TXD[3:0] MII_TXEN MII_TXCLK MII_RXCLK MII_CRS MII_RXDV MII_COL EMIF EMIF_CLK EMIF_CKE EMIF_nCS[4:2] EMIF_nCS[0] EMIF_ADDR[21:0] EMIF_BA[1:0] EMIF_DATA[15:0] EMIF_nDQM[1:0] EMIF_nOE EMIF_nWE EMIF_nRAS EMIF_nCAS EMIF_nRW EMIF_nWAIT VSSADVCCAD I2C_SCLI2C_SDA FRAY_RX1FRAY_TX1 FRAY_TXEN1 FRAY_RX2FRAY_TX2 FRAY_TXEN2 GIOB[7:0]GIOA[7:0] N2HET2[18,16]N2HET2[15:0]N2HET1[31:0] VCCADVSSAD ADREFHIADREFLO AD1EVT AD1IN[7:0]AD1IN[23:8]AD2IN[15:0] AD2EVTADREFHIADREFLO #□2 #□3 #□4 # 1 # 2 # 1always□on Core/RAM RAMCore # 5 # 3 Color□Legend□for□Power□Domains SYS nPORRST nRST ECLK ESM nERROR TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

1.4 FunctionalBlock Diagram

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

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1.1 Device Configuration

1.1.1 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall devicesand supporttools.Each commercialfamilymember has one ofthreeprefixes:TMX, TMP, orTMS (e.g.,TMS570LS3137U).Texas Instrumentsrecommends two of threepossibleprefixdesignatorsforits supporttools:TMDX and TMDS. These prefixesrepresentevolutionarystagesof productdevelopment fromengineeringprototypes(TMX/TMDX) throughfullyqualifiedproductiondevices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatis not necessarilyrepresentativeof the finaldevice'selectrical specifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthas notcompleted qualityand reliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproduct that has not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-supporttoolsare shipped againstthe following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devicesand TMDS development-supporttoolshave been characterizedfully,and the qualityand reliabilityofthedevicehave been demonstratedfully.TI'sstandardwarrantyapplies. Predictionsshow thatprototypedevices(TMX or TMP) have a greaterfailureratethan the standard productiondevices.Texas Instrumentsrecommends thatthesedevicesnot be used inany production systembecause theirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobe used. Copyright© 2011,Texas InstrumentsIncorporated Contents 7 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW Full□Part□# TMS 570 LS 31 3 7 A ZWT Q Q1 R Orderable□Part□# TMX 570 31 3 7 A ZWT Q Q1 R Prefix: TM TMS□=□Fully□Qualified TMP =□Prototype TMX□=□Samples Core Technology: 570□=□Cortex□R4F Architecture: (not□included□in□orderable□part□#) Flash□Memory□Size: 31□=□3MB RAM□MemorySize: 3□=□256kB Peripheral□Set: 7□=□FlexRay,□Ethernet Die□Revision: A =□1st□Die□Revision Package Type: ZWT =□337□BGA Package PGE□=□144□Pin□Package Temperature□Range: Q□=□-40...+125 C o Quality□Designator: Q1□= Automotive Shipping□Options: R□= Tape□and□Reel TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com The figurebelowillustratesthenumberingand symbolnomenclaturefortheTMS570LS3137 . Figure1-1.TMS570LS3137 Device Numbering Conventions

1.1.2 OrderablePartNumbers

Table1-1.OrderablePartNumbers OrderablePart# Part# Flash RAM EMAC FlexRay TMX5703137APGEQQ1 TMS570LS3137 3MB 256kB 10/100 2ch TMX5703137AZWTQQ1 TMS570LS3137 3MB 256kB 10/100 2ch

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1.1.3 Device Identification

1.1.3.1 Device IdentificationCode Register

The deviceidentificationcode registeridentifiesseveralaspectsofthedeviceincludingthesiliconversion. The detailsofthedeviceidentificationcode registerareshown inTable1-2.The deviceidentificationcode registervalueforthisdeviceis:

Rev 0 = 0x802AAD05 Figure1-2.Device ID BitAllocationRegister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CP-15 UNIQUE ID TECH R-1 R-00000000010101 R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TECH I/O PERIPH FLASH ECC RAM VERSION 1 0 1 VOLT PARITY ECC AGE R-101 R-0 R-1 R-10 R-1 R-00000 R-1 R-0 R-1 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Copyright© 2011,Texas InstrumentsIncorporated Contents 9 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table1-2.Device ID BitAllocationRegisterFieldDescriptions Bit Field Value Description

31 CP15 Indicatesthepresenceofcoprocessor15

1 CP15 present

30-17 UNIQUE ID 10101 Siliconversion(revision)bits. Thisbitfieldholdsa uniquenumber fora dedicateddeviceconfiguration(die). 16-13 TECH Processtechnologyon whichthedeviceismanufactured.

0101 F021

12 I/OVOLTAGE I/Ovoltageofthedevice. 0 I/Oare3.3v

11 PERIPHERAL PeripheralParity

1 Parityon peripheralmemories

10 Program memory withECC

8 RAM ECC IndicatesifRAM memory ECC ispresent.

1 ECC implemented

7-3 REVISION RevisionoftheDevice. 2-0 101 The platformfamilyID isalways0b101

1.1.3.2 Die IdentificationRegisters

The fourdieID registersataddresses0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a 128-bitdieidwiththeinformationas shown inTableTable1-3. Table1-3.Die-IDRegisters Item # ofBits BitLocation X Coord.on Wafer 8 7..0 Y Coord.on Wafer 8 15..8 Wafer # 6 21..16 Lot# 24 45..22 Reserved 82 127..46

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PRODUCT□PREVIEW 108 2 3 4 5 FRAYTXEN2 nTRST 109 144 110 111 112 113 114 115 116 117 118 119 120 121 AD1IN[10]□/ AD2IN[10] 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2323 24 25 26 2727 28 29 30 31 32 33 34 35 36 10710610510410310210110099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 FRAYTX2FRAYRX2 MIBSPI3NCS[3] MIBSPI3NCS[2] N2HET1[11] FLTP1FLTP2GIOA[2]VCCIO VSS CAN3RXCAN3TXGIOA[5] N2HET1[22] GIOA[6] VCC OSCIN Kelvin_GND OSCOUT VSS GIOA[7] N2HET1[01]N2HET1[03]N2HET1[0] VCCIO VSS VSSVCC N2HET1[02]N2HET1[05] MIBSPI5NCS[0] N2HET1[07] TEST N2HET1[09]N2HET1[4] MIBSPI3NCS[1] N2HET1[06] N2HET1[13] MIBSPI1NCS[2] N2HET1[15] VCCIO VSS VSS VCC nPORRST VSS VCC VCC VSS MIBSPI3SOMI MIBSPI3SIMO MIBSPI3CLK MIBSPI3NENA MIBSPI3NCS[0] VSS VCC AD1IN[16]□/ AD2IN[0] AD1IN[17]□/ AD2IN[01] AD1IN[0] AD1IN[07] AD1IN[18]□/ AD2IN[02] AD1IN[19]□/ AD2IN[03] AD1IN[20]□/ AD2IN[04] AD1IN[21]□/ AD2IN[05] ADREFHI ADREFLO VSSAD VCCAD AD1IN[09]□/ AD2IN[09] AD1IN[01] AD1IN[02]AD1IN[03]AD1IN[11]□/ AD2IN[11]AD1IN[04]AD1IN[12]□/ AD2IN[12]AD1IN[05]AD1IN[13]□/ AD2IN[13]AD1IN[06]AD1IN[22]□/ AD2IN[06]AD1IN[14]□/ AD2IN[14]AD1IN[08]□/ AD2IN[08]AD1IN[23]□/ AD2IN[07]AD1IN[15]□/ AD2IN[15]AD1EVTVCCVSSCAN1TXCAN1RXN2HET1[24]N2HET1[26]MIBSPI1SIMOMIBSPI1SOMIMIBSPI1CLKMIBSPI1NENAMIBSPI5NENAMIBSPI5SOMI[0]MIBSPI5SIMO[0]MIBSPI5CLKVCCVSSVSSVCCION2HET1[08]N2HET1[28]TMS TDI TDO TCK RTCK VCC VSS nRST nERROR N2HET1[10] ECLK VCCIO VSS VSS VCC N2HET1[12] N2HET1[14] FRAYRX1 N2HET1[30] CAN2TX CAN2RX MIBSPI1NCS[1] LINRX LINTX FRAYTX1 VCCP VSS VCCIO VCC VSS N2HET1[16] N2HET1[18] N2HET1[20] FRAYTXEN1 VCC VSS MIBSPI1NCS[0] TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

2 Device Package and TerminalFunctions

2.2 PGE QFP Package Pinout(144-Pin)

Figure2-3.PGE QFP Package Pinout(144-Pin) Note:Pinscan have multiplexedfunctions.Onlythedefaultfunctionisdepictedinabove diagram. Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 11 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW A B C D E F G H J K L M N P R T U V W

19 VSS VSS TMS N2HET1

[10] MIBSPI5 NCS[0] MIBSPI1 SIMO MIBSPI1 NENA MIBSPI5 CLK MIBSPI5 SIMO[0] N2HET1 [28] DMM_ DATA[0] CAN3RX AD1EVT AD1IN[15] AD2IN[15] AD1IN[22] AD2IN[06] AD1IN [06] AD1IN[11] AD2IN[11] VSSAD VSSAD 19

18 VSS TCK TDO nTRST N2HET1

[08] MIBSPI1 CLK MIBSPI1 SOMI MIBSPI5 NENA MIBSPI5 SOMI[0] N2HET1 [0] DMM_ DATA[1] CAN3TX NC AD1IN[08] AD2IN[08] AD1IN[14] AD2IN[14] AD1IN[13] AD2IN[13] AD1IN [04] AD1IN [02] VSSAD 18

17 TDI RST EMIF_

ADDR[21] EMIF_ nWE MIBSPI5 SOMI[1] DMM_ CLK MIBSPI5 SIMO[3] MIBSPI5 SIMO[2] N2HET1 [31] EMIF_ nCS[3] EMIF_ nCS[2] EMIF_ nCS[4] EMIF_ nCS[0] NC AD1IN [05] AD1IN [03] AD1IN[10] AD2IN[10] AD1IN [01] AD1IN[09] AD2IN[09]

16 RTCK FRAY

EMIF_ ADDR[20] EMIF_ BA[1] MIBSPI5 SIMO[1] DMM_ NENA MIBSPI5 SOMI[3] MIBSPI5 SOMI[2] DMM_ SYNC NC NC NC NC NC AD1IN[23] AD2IN[07] AD1IN[12] AD2IN[12] AD1IN[19] AD2IN[03] ADREFLO VSSAD 16

15 FRAY

EMIF_ ADDR[19] EMIF_ ADDR[18] ETM DATA[06] ETM DATA[05] ETM DATA[04] ETM DATA[03] ETM DATA[02] ETM DATA[16] / EMIF_ DATA[0] ETM DATA[17] / EMIF_ DATA[1] ETM DATA[18] / EMIF_ DATA[2] ETM DATA[19] / EMIF_ DATA[3] NC NC AD1IN[21] AD2IN[05] AD1IN[20] AD2IN[04] ADREFHI VCCAD 15

14 N2HET1

[26] nERROR EMIF_ ADDR[17] EMIF_ ADDR[16] ETM DATA[07] VCCIO VCCIO VCCIO VCC VCC VCCIO VCCIO VCCIO VCCIO NC NC AD1IN[18] AD2IN[02] AD1IN [07] AD1IN [0] 14

13 N2HET1

[17] N2HET1 [19] EMIF_ ADDR[15] NC ETM DATA[12] / EMIF_BA[0] VCCIO VCCIO ETM DATA[01] NC AD1IN[17] AD2IN[01] AD1IN[16] AD2IN[0] NC 13

12 ECLK N2HET1

[04] EMIF_ ADDR[14] NC ETM DATA[13] / EMIF_nOE VCCIO VSS VSS VCC VSS VSS VCCIO ETM DATA[0] MIBSPI5 NCS[3] NC NC NC 12

11 N2HET1

[14] N2HET1 [30] EMIF_ ADDR[13] NC ETM DATA[14] / EMIF_ nDQM[1] VCCIO VSS VSS VSS VSS VSS VCCPLL ETME TRACE CTL NC NC NC NC 11

10 CAN1TX CAN1RX EMIF_

ADDR[12] NC ETM DATA[15] / EMIF_ nDQM[0] VCC VCC VSS VSS VSS VCC VCC ETM TRACE CLKOUT NC NC MIBSPI3 NCS[0] GIOB[3] 10

9 N2HET1

[27] FRAY TXEN2 EMIF_ ADDR[11] NC ETM DATA[08] / EMIF_ ADDR[5] VCC VSS VSS VSS VSS VSS VCCIO ETM TRACE CLKIN NC NC MIBSPI3 CLK MIBSPI3 NENA 9

8 FRAY

EMIF_ ADDR[10] NC ETM DATA[09] / EMIF_ ADDR[4] VCCP VSS VSS VCC VSS VSS VCCIO ETM DATA[31] / EMIF_ DATA[15] NC NC MIBSPI3 SOMI MIBSPI3 SIMO 8

7 LINRX LINTX EMIF_

ADDR[9] NC ETM DATA[10] / EMIF_ ADDR[3] VCCIO VCCIO ETM DATA[30] / EMIF_ DATA[14] NC NC N2HET1 [09] nPORRST 7

6 GIOA[4] MIBSPI5

NCS[1] EMIF_ ADDR[8] NC ETM DATA[11] / EMIF_ ADDR[2] VCCIO VCCIO VCCIO VCCIO VCC VCC VCCIO VCCIO VCCIO ETM DATA[29] / EMIF_ DATA[13] NC NC N2HET1 [05] MIBSPI5 NCS[2] 6

5 GIOA[0] GIOA[5] EMIF_

ADDR[7] EMIF_ ADDR[1] ETM DATA[20] / EMIF_ DATA[4] ETM DATA[21] / EMIF_ DATA[5] ETM DATA[22] / EMIF_ DATA[6] FLTP2 FLTP1 ETM DATA[23] / EMIF_ DATA[7] ETM DATA[24] / EMIF_ DATA[8] ETM DATA[25] / EMIF_ DATA[9] ETM DATA[26] / EMIF_ DATA[10] ETM DATA[27] / EMIF_ DATA[11] ETM DATA[28] / EMIF_ DATA[12] NC NC MIBSPI3 NCS[1] N2HET1 [02] 5

4 N2HET1

[16] N2HET1 [12] EMIF_ ADDR[6] EMIF_ ADDR[0] NC NC NC N2HET1 [21] N2HET1 [23] NC NC NC NC NC EMIF_ nCAS NC NC NC NC 4

3 N2HET1

[29] N2HET1 [22] MIBSPI3 NCS[3] SPI2 NENA N2HET1 [11] MIBSPI1 NCS[1] MIBSPI1 NCS[2] GIOA[6] MIBSPI1 NCS[3] EMIF_ CLK EMIF_ CKE N2HET1 [25] SPI2 NCS[0] EMIF_ nWAIT EMIF_ nRAS NC NC NC N2HET1 [06] 3

2 VSS MIBSPI3

NCS[2] GIOA[1] SPI2 SOMI SPI2 CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1] KELVIN_ GND GIOB[0] N2HET1 [13] N2HET1 [20] MIBSPI1 NCS[0] NC TEST N2HET1 [01] VSS 2

1 VSS VSS GIOA[2] SPI2

SIMO GIOA[3] GIOB[7] GIOB[4] CAN2RX N2HET1 [18] OSCIN OSCOUT GIOA[7] N2HET1 [15] N2HET1 [24] NC N2HET1 [07] N2HET1 [03] VSS VSS 1 A B C D E F G H J K L M N P R T U V W TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

2.3 ZWT BGA Package Ball-Map(337BallGridArray)

Figure2-4.ZWT Package Pinout.Top View Note:Ballscan have multiplexedfunctions.Only thedefaultfunctionisdepictedinabove diagram,except fortheEMIF signalsthataremultiplexedwithETM signals.

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2.4 TerminalFunctions

Section2.4.1and Section2.4.2identifytheexternalsignalnames, theassociatedpin/ballnumbers along withthemechanicalpackage designator,thepin/balltype(Input,Output,IO,Power or Ground),whether the pin/ballhas any internalpullup/pulldown,whether the pin/ballcan be configuredas a GIO, and a functionalpin/balldescription.The firstsignalname listedisthe primaryfunctionforthatterminal.The signalname inBold isthe functionbeingdescribed.Referto the I/OMultiplexingModule (IOMM) User Guide forinformationon how toselectbetween differentmultiplexedfunctions. NOTE AllI/OsignalsexceptnRST areconfiguredas inputswhilenPORRST islowand immediately afternPORRST goes High. Alloutput-onlysignalsare configuredas inputswhilenPORRST islow,and are configured as outputsimmediatelyafternPORRST goes High. WhilenPORRST islow,theinputbuffersaredisabled,and theoutputbuffersaretri-stated.

2.4.1 PGE Package

2.4.1.1 Multi-BufferedAnalog-to-DigitalConverters(MibADC)

Table2-4.PGE Multi-BufferedAnalog-to-DigitalConverters(MibADC1, MibADC2) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE ADREFHI (1) 66 Input - - ADC highreference supply ADREFLO (1) 67 Input ADC lowreferencesupply VCCAD (1) 69 Power OperatingsupplyforADC VSSAD (1) 68 Ground AD1EVT /MII_RX_ER 86 Input PullDown Programmable, ADC1 eventtriggerinput, 20uA orGIO MIBSPI3NCS[0]/AD2EVT 55 I/O PullUp Programmable, ADC2 eventtriggerinput, 20uA orGIO AD1IN[0] 60 Input - - ADC1 analoginput AD1IN[01] 71 AD1IN[02] 73 AD1IN[03] 74 AD1IN[04] 76 AD1IN[05] 78 AD1IN[06] 80 AD1IN[07] 61 (1) The ADREFHI, ADREFLO, VCCAD and VSSAD connectionsarecommon forbothADC cores. Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 13 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table2-4.PGE Multi-BufferedAnalog-to-DigitalConverters(MibADC1, MibADC2) (continued) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE AD1IN[08]/AD2IN[08] 83 Input - - ADC1/ADC2 shared analoginputsAD1IN[09]/AD2IN[09] 70 AD1IN[10]/AD2IN[10] 72 AD1IN[11]/AD2IN[11] 75 AD1IN[12]/AD2IN[12] 77 AD1IN[13]/AD2IN[13] 79 AD1IN[14]/AD2IN[14] 82 AD1IN[15]/AD2IN[15] 85 AD1IN[16]/AD2IN[0] 58 AD1IN[17]/AD2IN[01] 59 AD1IN[18]/AD2IN[02] 62 AD1IN[19]/AD2IN[03] 63 AD1IN[20]/AD2IN[04] 64 AD1IN[21]/AD2IN[05] 65 AD1IN[22]/AD2IN[06] 81 AD1IN[23]/AD2IN[07] 84

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2.4.1.2 Enhanced High-End Timer Modules (N2HET)

Table2-5.PGE Enhanced High-End Timer Modules (N2HET) Terminal Signal DefaultPull PullType Description Type StateSignalName 144 PGE N2HET1[0]/SPI4CLK 25 I/O PullDown Programmable, N2HET1 time input20uAN2HET1[01]/SPI4NENA/N2HET2[8] 23 capture or output compare,orGIO.N2HET1[02]/SPI4SIMO 30 Each terminal has aN2HET1[03]/SPI4NCS[0]/N2HET2[10] 24 suppression filterthatN2HET1[04] 36 ignores input pulses N2HET1[05]/SPI4SOMI/N2HET2[12] 31 smaller than a programmableduration.N2HET1[06]/SCIRX 38 N2HET1[07]/N2HET2[14] 33 N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ 106 N2HET1[09]/N2HET2[16] 35 N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 118 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 N2HET1[12]/MII_CRS 124 N2HET1[13]/SCITX 39 N2HET1[14] 125 N2HET1[15]/MIBSPI1NCS[4] 41 N2HET1[16] 139 MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 N2HET1[18] 140 MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 N2HET1[20] 141 N2HET1[22] 15 MIBSPI1NENA/ N2HET1[23]/MII_RXD[2] 96 N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0] 91 MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 N2HET1[26]/MII_RXD[1] 92 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 N2HET1[28]/MII_RXCLK/MII_RX_AVCLK4 107 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 N2HET1[30]/MII_RX_DV 127 MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 GIOA[2]/N2HET2[0] 9 I/O PullDown Programmable, N2HET2 time input20uAGIOA[6]/N2HET2[4] 16 capture or output compare,orGIOGIOA[7]/N2HET2[6] 22 Each terminal has aN2HET1[01]/SPI4NENA/N2HET2[8] 23 suppression filterthatN2HET1[03]/SPI4NCS[0]/N2HET2[10] 24 ignores input pulses N2HET1[05]/SPI4SOMI/N2HET2[12] 31 smaller than a programmableduration.N2HET1[07]/N2HET2[14] 33 N2HET1[09]/N2HET2[16] 35 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 15 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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2.4.1.3 General-PurposeInput/Output (GIO)

Table2-6.PGE General-PurposeInput/Output (GIO) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE GIOA[2]/N2HET2[0] 9 I/O PullDown Programmable, General-purposeI/O. 20uA AllGIO terminalsareGIOA[5]/EXTCLKIN 14 capableofgenerating GIOA[6]/N2HET2[4] 16 interruptstotheCPU on rising/falling/bothGIOA[7]/N2HET2[6] 22 edges.

2.4.1.4 FlexRay InterfaceController(FlexRay)

Table2-7.FlexRay InterfaceController(FlexRay) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE FRAYRX1 126 Input PullDown Fixed,100uA FlexRaydatareceive (channel1) FRAYTX1 133 Output - - FlexRaydatatransmit (channel1) FRAYTXEN1 142 Output FlexRaytransmitenable (channel1) FRAYRX2 2 Input PullDown Fixed,100uA FlexRaydatareceive (channel2) FRAYTX2 1 Output - - FlexRaydatatransmit (channel2) FRAYTXEN2 5 Output FlexRaytransmitenable (channel2)

2.4.1.5 ControllerArea Network Controllers(DCAN)

Table2-8.PGE ControllerArea Network Controllers(DCAN) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE CAN1RX 90 I/O PullUp Programmable, CAN1 receive,orGIO 20uACAN1TX 89 CAN1 transmit,orGIO CAN2RX 129 CAN2 receive,orGIO CAN2TX 128 CAN2 transmit,orGIO CAN3RX 12 CAN3 receive,orGIO CAN3TX 13 CAN3 transmit,orGIO

2.4.1.6 LocalInterconnectNetwork InterfaceModule (LIN)

Table2-9.PGE LocalInterconnectNetwork InterfaceModule (LIN) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE LINRX 131 I/O PullUp Programmable, LIN receive,orGIO 20uALINTX 132 LIN transmit,orGIO

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2.4.1.7 Standard SerialCommunication Interface(SCI)

Table2-10.PGE Standard SerialCommunication Interface(SCI) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE N2HET1[06]/SCIRX 38 I/O PullDown Programmable, SCI receive,orGIO 20uAN2HET1[13]/SCITX 39 SCI transmit,orGIO

2.4.1.8 Inter-IntegratedCircuitInterfaceModule (I2C)

Table2-11.PGE Inter-IntegratedCircuitInterfaceModule (I2C) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI3NCS[2]/I2C_SDA /N2HET1[27] 4 I/O PullUp Programmable, I2C serialdata,orGIO 20uAMIBSPI3NCS[3]/I2C_SCL /N2HET1[29] 3 I2C serialclock,orGIO

2.4.1.9 Standard SerialPeripheralInterface(SPI)

Table2-12.PGE Standard SerialPeripheralInterface(SPI) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE N2HET1[0]/SPI4CLK 25 I/O PullDown Programmable, SPI4 clock,orGIO 20uAN2HET1[03]/SPI4NCS[0]/N2HET2[10] 24 SPI4 chipselect,orGIO N2HET1[01]/SPI4NENA /N2HET2[8] 23 SPI4 enable,orGIO N2HET1[02]/SPI4SIMO 30 SPI4 slave-input master-output,orGIO N2HET1[05]/SPI4SOMI /N2HET2[12] 31 SPI4 slave-output master-input,orGIO 2.4.1.10Multi-BufferedSerialPeripheralInterfaceModules (MibSPI) Table2-13.PGE Multi-BufferedSerialPeripheralInterfaceModules (MibSPI) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI1CLK 95 I/O PullUp Programmable, MibSPI1 clock,orGIO 20uAMIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 MibSPI1 chipselect,or GIOMIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 N2HET1[15]/MIBSPI1NCS[4] 41 PullDown Programmable, MibSPI1 chipselect,or 20uA GION2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0] 91 MIBSPI1NENA /N2HET1[23]/MII_RXD[2] 96 PullUp Programmable, MibSPI1 enable,orGIO 20uAMIBSPI1SIMO 93 MibSPI1 slave-in master-out,orGIO N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3] 106 PullDown Programmable, MibSPI1 slave-in 20uA master-out,orGIO MIBSPI1SOMI 94 PullUp Programmable, MibSPI1 slave-out 20uA master-in,orGIOMIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 17 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table2-13.PGE Multi-BufferedSerialPeripheralInterfaceModules (MibSPI)(continued) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI3CLK 53 I/O PullUp Programmable, MibSPI3 clock,orGIO 20uAMIBSPI3NCS[0]/AD2EVT/GIOB[2] 55 MibSPI3 chipselect,or GIOMIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 PullUp Programmable, MibSPI3 chipselect,or 20uA GIO MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31] 54 PullUp Programmable, MibSPI3 chipselect,or 20uA GIO MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3 enable,orGIO MIBSPI3SIMO 52 MibSPI3 slave-in master-out,orGIO MIBSPI3SOMI 51 MibSPI3 slave-out master-in,orGIO MIBSPI5CLK /MII_TXEN 100 I/O PullUp Programmable, MibSPI5 clock,orGIO 20uAMIBSPI5NCS[0] 32 MibSPI5 chipselect,or GIO MIBSPI5NENA /MII_RXD[3] 97 MibSPI5 enable,orGIO MIBSPI5SIMO[0]/MII_TXD[1] 99 MibSPI5 slave-in master-out,orGIO MIBSPI5SOMI[0]/MII_TXD[0] 98 MibSPI5 slave-out master-in,orGIO 2.4.1.11EthernetController Table2-14.PGE EthernetController:MDIO Interface Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Output PullUp - Serialclockoutput MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O PullUp Fixed,20uA Serialdatainput/output Table2-15.PGE EthernetController:Media IndependentInterface(MII) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 Input PullUp - Collisiondetect N2HET1[12]/MII_CRS 124 PullDown Fixed,20uA Carriersense and receive valid N2HET1[28]/MII_RXCLK/MII_RX_AVCLK4 107 I/O PullDown - MIIoutputreceiveclock N2HET1[30]/MII_RX_DV 127 Input PullDown Fixed,20uA Receiveddatavalid AD1EVT/ MII_RX_ER 86 Receiveerror N2HET1[28]/MII_RX_CLK /MII_RX_AVCLK4 107 I/O Receiveclock N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0] 92 Input Receivedata N2HET1[26]/MII_RXD[1] 92 MIBSPI1NENA/N2HET1[23]/MII_RXD[2] 96 PullUp Fixed,20uA MIBSPI5NENA/ MII_RXD[3] 97

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table2-15.PGE EthernetController:Media IndependentInterface(MII)(continued) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 118 I/O PullDown - MIIoutputtransmitclock N2HET1[10]/MII_TX_CLK /MII_TX_AVCLK4 118 Transmitclock MIBSPI5SOMI[0]/MII_TXD[0] 98 Output PullUp - Transmitdata MIBSPI5SIMO[0]/MII_TXD[1] 99 MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3] 106 PullDown - MIBSPI5CLK/MII_TXEN 100 PullUp - Transmitenable 2.4.1.12System Module Interface Table2-16.PGE System Module Interface Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE nPORRST 46 Input PullDown 100uA Power-onreset,coldreset Externalpower supply monitorcircuitrymust drivenPORRST lowwhen any ofthesuppliestothe microcontrollerfalloutof thespecifiedrange.This terminalhas a glitchfilter. See Section4.8. nRST 116 I/O PullUp 100uA System reset,warm reset, bidirectional. The internalcircuitry indicatesany reset conditionby drivingnRST low. The externalcircuitrycan asserta systemresetby drivingnRST low.To ensurethatan external resetisnotarbitrarily generated,TI recommends thatan externalpull-upresistoris connectedtothisterminal. Thisterminalhas a glitch filter.See Section4.8. nERROR 117 I/O PullDown 20uA ESM ErrorSignal Indicateserrorofhigh severity.See Section4.18. Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 19 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com 2.4.1.13Clock Inputsand Outputs Table2-17.PGE Clock Inputsand Outputs Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE OSCIN 18 Input - - From external crystal/resonator,or externalclockinput KELVIN_GND 19 Input Kelvingroundforoscillator OSCOUT 20 Output To external crystal/resonator ECLK 119 I/O PullDown Programmable, Externalprescaledclock 20uA output,orGIO. GIOA[5]/EXTCLKIN 14 Input PullDown 20uA Externalclockinput#1 2.4.1.14Testand Debug Modules Interface Table2-18.PGE Testand Debug Modules Interface Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE TEST 34 I/O PullDown Fixed,100uA Testenable nTRST 109 Input JTAG testhardwarereset RTCK 113 Output - - JTAG returntestclock TCK 112 Input PullDown Fixed,100uA JTAG testclock TDI 110 I/O PullUp JTAG testdatain TDO 111 I/O PullDown JTAG testdataout TMS 108 I/O PullUp JTAG testselect 2.4.1.15FlashSupply and TestPads Table2-19.PGE FlashSupply and TestPads Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE VCCP 134 Input - - Flashpump supply FLTP1 7 Flashtestpads.These terminalsarereservedforFLTP2 8 TIuse only.Forproper operationtheseterminals must connectonlytoa testpad ornotbe connectedatall[no connect(NC)].

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 2.4.1.16Supply forCore Logic:1.2Vnominal Table2-20.PGE Supply forCore Logic:1.2Vnominal Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE VCC 17 - - - Core supply VCC 29 VCC 45 VCC 48 VCC 49 VCC 57 VCC 87 VCC 101 VCC 114 VCC 123 VCC 137 VCC 143 2.4.1.17Supply forI/OCells:3.3Vnominal Table2-21.PGE Supply forI/OCells:3.3Vnominal Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE VCCIO 10 Input - - OperatingsupplyforI/Os VCCIO 26 VCCIO 42 VCCIO 104 VCCIO 120 VCCIO 136 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 21 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com 2.4.1.18Ground ReferenceforAllSuppliesExcept VCCAD Table2-22.PGE Ground ReferenceforAllSuppliesExcept VCCAD Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE VSS 11 Input - - Ground reference VSS 21 VSS 27 VSS 28 VSS 43 VSS 44 VSS 47 VSS 50 VSS 56 VSS 88 VSS 102 VSS 103 VSS 115 VSS 121 VSS 122 VSS 135 VSS 138

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2.4.2 ZWT Package

2.4.2.1 Multi-BufferedAnalog-to-DigitalConverters(MibADC)

Table2-23.ZWT Multi-BufferedAnalog-to-DigitalConverters(MibADC1, MibADC2) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT ADREFHI (1) V15 Input - - ADC highreference supply ADREFLO (1) V16 Input ADC lowreferencesupply VCCAD (1) W15 Power OperatingsupplyforADC VSSAD V19 Ground - - ADC supplypower W16 W18 W19 AD1EVT /MII_RX_ER N19 Input PullDown Programmable, ADC1 eventtriggerinput, 20uA orGIO MIBSPI3NCS[0]/AD2EVT /GIOB[2] V10 I/O PullUp Programmable, ADC2 eventtriggerinput, 20uA orGIO AD1IN[0] W14 Input - - ADC1 analoginput AD1IN[01] V17 AD1IN[02] V18 AD1IN[03] T17 AD1IN[04] U18 AD1IN[05] R17 AD1IN[06] T19 AD1IN[07] V14 AD1IN[08]/AD2IN[08] P18 Input - - ADC1/ADC2 shared analoginputsAD1IN[09]/AD2IN[09] W17 AD1IN[10]/AD2IN[10] U17 AD1IN[11]/AD2IN[11] U19 AD1IN[12]/AD2IN[12] T16 AD1IN[13]/AD2IN[13] T18 AD1IN[14]/AD2IN[14] R18 AD1IN[15]/AD2IN[15] P19 AD1IN[16]/AD2IN[0] V13 AD1IN[17]/AD2IN[01] U13 AD1IN[18]/AD2IN[02] U14 AD1IN[19]/AD2IN[03] U16 AD1IN[20]/AD2IN[04] U15 AD1IN[21]/AD2IN[05] T15 AD1IN[22]/AD2IN[06] R19 AD1IN[23]/AD2IN[07] R16 (1) The ADREFHI, ADREFLO, VCCAD and VSSAD connectionsarecommon forbothADC cores. Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 23 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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2.4.2.2 Enhanced High-End Timer Modules (N2HET)

Table2-24.ZWT Enhanced High-End Timer Modules (N2HET) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT N2HET1[0]/SPI4CLK K18 I/O PullDown Programmable, N2HET1 time input20uAN2HET1[01]/SPI4NENA/N2HET2[8] V2 capture or output compare,orGIO.N2HET1[02]/SPI4SIMO W5 Each terminal has aN2HET1[03]/SPI4NCS[0]/N2HET2[10] U1 suppression filterthatN2HET1[04] B12 ignores input pulses N2HET1[05]/SPI4SOMI/N2HET2[12] V6 smaller than a programmableduration.N2HET1[06]/SCIRX W3 N2HET1[07]/N2HET2[14] T1 N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3] E18 N2HET1[09]/N2HET2[16] V7 N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 D19 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3 N2HET1[12]/MII_CRS B4 N2HET1[13]/SCITX N2 N2HET1[14] A11 N2HET1[15]/MIBSPI1NCS[4] N1 N2HET1[16] A4 N2HET1[17] A13 N2HET1[18] J1 N2HET1[19] B13 N2HET1[20] P2 N2HET1[21] H4 N2HET1[22] B3 N2HET1[23] J4 N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0] P1 N2HET1[25] M3 N2HET1[26]/MII_RXD[1] A14 N2HET1[27] A9 N2HET1[28]/MII_RX_CLK/MII_RX_AVCLK4 K19 N2HET1[29] A3 N2HET1[30]/MII_RX_DV B11 N2HET1[31] J17

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table2-24.ZWT Enhanced High-End Timer Modules (N2HET) (continued) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT GIOA[2]/N2HET2[0] C1 I/O PullDown Programmable, N2HET2 time input20uAEMIF_ADDR[0]/N2HET2[1] D4 capture or output compare,orGIO.GIOA[3]/N2HET2[2] E1 Each terminal has aEMIF_ADDR[1]/N2HET2[3] D5 suppression filterthatGIOA[6]/N2HET2[4] H3 ignores input pulses EMIF_BA[1]/N2HET2[5] D16 smaller than a programmableduration.GIOA[7]/N2HET2[6] M1 EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 N2HET1[01]/SPI4NENA/N2HET2[8] V2 EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 N2HET1[03]/SPI4NCS[0]/N2HET2[10] U1 EMIF_ADDR[6]/RTP_DATA[13]/NHET2[11] C4 N2HET1[05]/SPI4SOMI/N2HET2[12] V6 EMIF_ADDR[7]/RTP_DATA[12]/NHET2[13] C5 N2HET1[07]/N2HET2[14] T1 EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 N2HET1[09]/N2HET2[16] V7 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 25 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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2.4.2.3 General-PurposeInput/Output (GIO)

Table2-25.ZWT General-PurposeInput/Output (GIO) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT GIOA[0] A5 I/O PullDown Programmable, General-purposeI/O. 20uA AllGIO terminalsareGIOA[1] C2 capableofgenerating GIOA[2]/N2HET2[0] C1 interruptstotheCPU on rising/falling/bothGIOA[3]/N2HET2[2] E1 edges. GIOA[4] A6 GIOA[5]/EXTCLKIN B5 GIOA[6]/N2HET2[4] H3 GIOA[7]/N2HET2[6] M1 GIOB[0] M2 GIOB[1] K2 GIOB[2] F2 GIOB[3] W10 GIOB[4] G1 GIOB[5] G2 GIOB[6] J2 GIOB[7] F1

2.4.2.4 FlexRay InterfaceController(FlexRay)

Table2-26.FlexRay InterfaceController(FlexRay) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT FRAYRX1 A15 Input PullDown Fixed,100uA FlexRaydatareceive (channel1) FRAYTX1 B15 Output - - FlexRaydatatransmit (channel1) FRAYTXEN1 B16 Output FlexRaytransmitenable (channel1) FRAYRX2 A8 Input PullDown Fixed,100uA FlexRaydatareceive (channel2) FRAYTX2 B8 Output - - FlexRaydatatransmit (channel2) FRAYTXEN2 B9 Output FlexRaytransmitenable (channel2)

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2.4.2.5 ControllerArea Network Controllers(DCAN)

Table2-27.ZWT ControllerArea Network Controllers(DCAN) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT CAN1RX B10 I/O PullUp Programmable, CAN1 receive,orGIO 20uACAN1TX A10 CAN1 transmit,orGIO CAN2RX H1 CAN2 receive,orGIO CAN2TX H2 CAN2 transmit,orGIO CAN3RX M19 CAN3 receive,orGIO CAN3TX M18 CAN3 transmit,orGIO

2.4.2.6 LocalInterconnectNetwork InterfaceModule (LIN)

Table2-28.ZWT LocalInterconnectNetwork InterfaceModule (LIN) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT LINRX A7 I/O PullUp Programmable, LIN receive,orGIO 20uALINTX B7 LIN transmit,orGIO

2.4.2.7 Standard SerialCommunication Interface(SCI)

Table2-29.ZWT Standard SerialCommunication Interface(SCI) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT N2HET1[06]/SCIRX W3 I/O PullDown Programmable, SCI receive,orGIO 20uAN2HET1[13]/SCITX N2 SCI transmit,orGIO Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 27 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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2.4.2.8 Inter-IntegratedCircuitInterfaceModule (I2C)

Table2-30.ZWT Inter-IntegratedCircuitInterfaceModule (I2C) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI3NCS[2]/I2C_SDA /N2HET1[27] B2 I/O PullUp Programmable, I2C serialdata,orGIO 20uAMIBSPI3NCS[3]/I2C_SCL /N2HET1[29] C3 I2C serialclock,orGIO

2.4.2.9 Standard SerialPeripheralInterface(SPI)

Table2-31.ZWT Standard SerialPeripheralInterface(SPI) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT SPI2CLK E2 I/O PullUp Programmable, SPI2 clock,orGIO 20uASPI2NCS[0] N3 SPI2 chipselect,orGIO SPI2NENA/ SPI2NCS[1] D3 SPI2 chipselect,orGIO SPI2NENA /SPI2NCS[1] D3 SPI2 enable,orGIO SPI2SIMO D1 SPI2 slave-input master-output,orGIO SPI2SOMI D2 SPI2 slave-output master-input,orGIO N2HET1[0]/SPI4CLK K18 I/O PullDown Programmable, SPI4 clock,orGIO 20uAN2HET1[03]/SPI4NCS[0]/N2HET2[10] U1 SPI4 chipselect,orGIO N2HET1[01]/SPI4NENA /N2HET2[8] V2 SPI4 enable,orGIO N2HET1[02]/SPI4SIMO W5 SPI4 slave-input master-output,orGIO N2HET1[05]/SPI4SOMI /N2HET2[12] V6 SPI4 slave-output master-input,orGIO

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 2.4.2.10Multi-BufferedSerialPeripheralInterfaceModules (MibSPI) Table2-32.ZWT Multi-BufferedSerialPeripheralInterfaceModules (MibSPI) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI1CLK F18 I/O PullUp Programmable, MibSPI1 clock,orGIO 20uAMIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] R2 MibSPI1 chipselect,or GIOMIBSPI1NCS[1]/N2HET1[17]/MII_COL F3 MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 MIBSPI1NCS[3]/N2HET1[21] J3 N2HET1[15]/MIBSPI1NCS[4] N1 PullDown Programmable, MibSPI1 chipselect,or 20uA GION2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0] P1 MIBSPI1NENA /N2HET1[23]/MII_RXD[2] G19 PullUp Programmable, MibSPI1 enable,orGIO 20uAMIBSPI1SIMO F19 MibSPI1 slave-in master-out,orGIO N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3] E18 PullDown Programmable, MibSPI1 slave-in 20uA master-out,orGIO MIBSPI1SOMI G18 PullUp Programmable, MibSPI1 slave-out 20uA master-in,orGIOMIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] R2 MIBSPI3CLK V9 I/O PullUp Programmable, MibSPI3 clock,orGIO 20uAMIBSPI3NCS[0]/AD2EVT/GIOB[2] V10 MibSPI3 chipselect,or GIOMIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3 PullUp Programmable, MibSPI3 chipselect,or 20uA GIO MIBSPI3NENA/ MIBSPI3NCS[5]/N2HET1[31] W9 PullUp Programmable, MibSPI3 chipselect,or 20uA GIO MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31] W9 MibSPI3 enable,orGIO MIBSPI3SIMO W8 MibSPI3 slave-in master-out,orGIO MIBSPI3SOMI V8 MibSPI3 slave-out master-in,orGIO MIBSPI5CLK /DMM_DATA[4] /MII_TXEN H19 I/O PullUp Programmable, MibSPI5 clock,orGIO 20uAMIBSPI5NCS[0]/DMM_DATA[5] E19 MibSPI5 chipselect,or GIOMIBSPI5NCS[1]/DMM_DATA[6] B6 MIBSPI5NCS[2]/DMM_DATA[2] W6 MIBSPI5NCS[3]/DMM_DATA[3] T12 MIBSPI5NENA /DMM_DATA[7]/MII_RXD[3] H18 MibSPI5 enable,orGIO MIBSPI5SIMO[0]/DMM_DATA[8] /MII_TXD[1] J19 MibSPI5 slave-in master-out,orGIOMIBSPI5SIMO[1]/DMM_DATA[9] E16 MIBSPI5SIMO[2]/DMM_DATA[10] H17 MIBSPI5SIMO[3]/DMM_DATA[11] G17 MIBSPI5SOMI[0]/DMM_DATA[12] /MII_TXD[0] J18 MIBSPI5SOMI[1]/DMM_DATA[13] E17 MIBSPI5SOMI[2]/DMM_DATA[14] H16 MIBSPI5SOMI[3]/DMM_DATA[15] G16 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 29 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com 2.4.2.11EthernetController Table2-33.ZWT EthernetController:MDIO Interface Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 Output PullUp - Serialclockoutput MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 I/O PullUp Fixed,20uA Serialdatainput/output

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 2.4.2.12ExternalMemory Interface(EMIF) Table2-34.ExternalMemory Interface(EMIF) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT EMIF_CKE L3 Output PullDown - EMIF ClockEnablen EMIF_CLK K3 I/O EMIF clock.Thisisan outputsignalinfunctional mode. Itisgatedoffby default,so thatthesignal istri-stated.PINMUX29[8] must be clearedtoenable thisoutput. EMIF_nWE/ EMIF_RNW D17 Output PullUp - EMIF Read-Not-Write ETMDATA[13]/EMIF_nOE E12 PullDown - EMIF Read Enable EMIF_nWAIT P3 I/O PullUp Fixed,20uA EMIF ExtendedWait Signal EMIF_nWE /EMIF_RNW D17 Output PullUp - EMIF WriteEnable. EMIF_nCAS R4 Output EMIF column address strobe EMIF_nRAS R3 Output EMIF row addressstrobe EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 Output EMIF chipselect, synchronous EMIF_nCS[2] L17 Output EMIF chipselects, asynchronousEMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 Output Thisappliestochip EMIF_nCS[4]/RTP_DATA[07] M17 Output selects2,3 and 4 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 31 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table2-34.ExternalMemory Interface(EMIF)(continued) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT ETMDATA[15]/EMIF_nDQM[0] E10 Output PullDown - EMIF Data Mask orWrite Strobe.ETMDATA[14]/EMIF_nDQM[1] E11 Output Data mask forSDRAM devices,writestrobefor connectedasynchronous devices. ETMDATA[12]/EMIF_BA[0] E13 Output EMIF bank addressor addressline EMIF_BA[1]/N2HET2[5] D16 Output EMIF bank addressor addressline EMIF_ADDR[0] /N2HET2[1] D4 Output EMIF address EMIF_ADDR[1] /N2HET2[3] D5 Output ETMDATA[11]/EMIF_ADDR[2] E6 Output ETMDATA[10]/EMIF_ADDR[3] E7 Output ETMDATA[09]/EMIF_ADDR[4 E8 Output ETMDATA[08]/EMIF_ADDR[5] E9 Output EMIF_ADDR[6] /RTP_DATA[13] C4 Output EMIF_ADDR[7] /RTP_DATA[12] C5 Output EMIF_ADDR[8] /RTP_DATA[11] C6 Output EMIF_ADDR[9] /RTP_DATA[10] C7 Output EMIF_ADDR[10] /RTP_DATA[09] C8 Output EMIF_ADDR[11] /RTP_DATA[08] C9 Output EMIF_ADDR[12] /RTP_DATA[06] C10 Output EMIF_ADDR[13] /RTP_DATA[05] C11 Output EMIF_ADDR[14] /RTP_DATA[04] C12 Output EMIF_ADDR[15] /RTP_DATA[03] C13 Output EMIF_ADDR[16] /RTP_DATA[02] D14 Output EMIF_ADDR[17] /RTP_DATA[01] C14 Output PullDown - EMIF_ADDR[18] /RTP_DATA[0] D15 Output EMIF_ADDR[19] /RTP_nENA C15 Output EMIF_ADDR[20] /RTP_nSYNC C16 Output EMIF_ADDR[21] /RTP_CLK C17 Output ETMDATA[16]/EMIF_DATA[0] K15 I/O PullDown Fixed,20uA EMIF Data ETMDATA[17]/EMIF_DATA[1] L15 I/O ETMDATA[18]/EMIF_DATA[2] M15 I/O ETMDATA[19]/EMIF_DATA[3] N15 I/O ETMDATA[20]/EMIF_DATA[4] E5 I/O ETMDATA[21]/EMIF_DATA[5] F5 I/O ETMDATA[22]/EMIF_DATA[6] G5 I/O ETMDATA[23]/EMIF_DATA[7] K5 I/O ETMDATA[24]/EMIF_DATA[8] L5 I/O ETMDATA[25]/EMIF_DATA[9] M5 I/O ETMDATA[26]/EMIF_DATA[10] N5 I/O ETMDATA[27]/EMIF_DATA[11] P5 I/O ETMDATA[28]/EMIF_DATA[12] R5 I/O ETMDATA[29]/EMIF_DATA[13] R6 I/O ETMDATA[30]/EMIF_DATA[14] R7 I/O ETMDATA[31]/EMIF_DATA[15] R8 I/O

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 2.4.2.13Embedded Trace MacrocellforCortex-R4FCPU (ETM-R4F) Table2-35.Embedded Trace MacrocellforCortex-R4FCPU (ETM-R4F) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT ETMTRACECLKIN /EXTCLKIN2 R9 Input PullDown Fixed,20uA ETM TraceClockInput ETMTRACECLKOUT R10 Output PullDown - ETM TraceClockOutput ETMTRACECTL R11 Output PullDown - ETM tracecontrol ETMDATA[0] R12 ETM data ETMDATA[01] R13 ETMDATA[02] J15 ETMDATA[03] H15 ETMDATA[04] G15 ETMDATA[05] F15 ETMDATA[06] E15 ETMDATA[07] E14 ETMDATA[08] /EMIF_ADDR[5] E9 ETMDATA[09] /EMIF_ADDR[4] E8 ETMDATA[10] /EMIF_ADDR[3] E7 ETMDATA[11] /EMIF_ADDR[2] E6 ETMDATA[12] /EMIF_BA[0] E13 ETMDATA[13] /EMIF_nOE E12 ETMDATA[14] /EMIF_nDQM[1] E11 ETMDATA[15] /EMIF_nDQM[0] E10 ETMDATA[16] /EMIF_DATA[0] K15 ETMDATA[17] /EMIF_DATA[1] L15 ETMDATA[18] /EMIF_DATA[2] M15 ETMDATA[19] /EMIF_DATA[3] N15 ETMDATA[20] /EMIF_DATA[4] E5 ETMDATA[21] /EMIF_DATA[5] F5 ETMDATA[22] /EMIF_DATA[6] G5 ETMDATA[23] /EMIF_DATA[7] K5 ETMDATA[24] /EMIF_DATA[8] L5 ETMDATA[25] /EMIF_DATA[9] M5 ETMDATA[26] /EMIF_DATA[10] N5 ETMDATA[27] /EMIF_DATA[11] P5 ETMDATA[28] /EMIF_DATA[12] R5 ETMDATA[29] /EMIF_DATA[13] R6 ETMDATA[30] /EMIF_DATA[14] R7 ETMDATA[31] /EMIF_DATA[15] R8 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 33 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com 2.4.2.14RAM Trace Port(RTP) Table2-36.RAM Trace Port(RTP) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT EMIF_ADDR[21]/RTP_CLK C17 I/O PullDown Programmable, RTP packetclock,orGIO 20uAEMIF_ADDR[19]/RTP_nENA C15 I/O RTP packethandshake, orGIO EMIF_ADDR[20]/RTP_nSYNC C16 I/O RTP synchronization,or GIO EMIF_ADDR[18]/RTP_DATA[0] D15 I/O RTP packetdata,orGIO EMIF_ADDR[17]/RTP_DATA[01] C14 EMIF_ADDR[16]/RTP_DATA[02] D14 EMIF_ADDR[15]/RTP_DATA[03] C13 EMIF_ADDR[14]/RTP_DATA[04] C12 EMIF_ADDR[13]/RTP_DATA[05] C11 EMIF_ADDR[12]/RTP_DATA[06] C10 EMIF_nCS[4]/RTP_DATA[07] M17 PullUp Programmable, 20uA EMIF_ADDR[11]/RTP_DATA[08] C9 PullDown Programmable, 20uAEMIF_ADDR[10]/RTP_DATA[09] C8 EMIF_ADDR[9]/RTP_DATA[10] C7 EMIF_ADDR[8]/RTP_DATA[11] C6 EMIF_ADDR[7]/RTP_DATA[12] C5 EMIF_ADDR[6]/RTP_DATA[13] C4 EMIF_nCS[0]/RTP_DATA[15] /N2HET2[7] N17 EMIF_nCS[3]/RTP_DATA[14] /N2HET2[9] K17 PullUp Programmable, 20uA

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 2.4.2.15Data ModificationModule (DMM) Table2-37.Data ModificationModule (DMM) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT DMM_CLK F17 I/O PullUp Programmable, DMM clock,orGIO 20uADMM_nENA F16 DMM handshake,orGIO DMM_SYNC J16 DMM synchronization,or GIO DMM_DATA[0] L19 DMM data,orGIO DMM_DATA[1] L18 MIBSPI5NCS[2]/DMM_DATA[2] W6 MIBSPI5NCS[3]/DMM_DATA[3] T12 MIBSPI5CLK/DMM_DATA[4] /MII_TXEN H19 MIBSPI5NCS[0]/DMM_DATA[5] E19 MIBSPI5NCS[1]/DMM_DATA[6] B6 MIBSPI5NENA/ DMM_DATA[7] /MII_RXD[3] H18 MIBSPI5SIMO[0]/DMM_DATA[8] /MII_TXD[1] J19 MIBSPI5SIMO[1]/DMM_DATA[9] E16 MIBSPI5SIMO[2]/DMM_DATA[10] H17 MIBSPI5SIMO[3]/DMM_DATA[11] G17 MIBSPI5SOMI[0]/DMM_DATA[12] /MII_TXD[0] J18 MIBSPI5SOMI[1]/DMM_DATA[13] E17 MIBSPI5SOMI[2]/DMM_DATA[14] H16 MIBSPI5SOMI[3]/DMM_DATA[15] G16 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 35 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com 2.4.2.16System Module Interface Table2-38.ZWT System Module Interface Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT nPORRST W7 Input PullDown 100uA Power-onreset,coldreset Externalpower supply monitorcircuitrymust drivenPORRST lowwhen any ofthesuppliestothe microcontrollerfalloutof thespecifiedrange.This terminalhas a glitchfilter. See Section4.8. nRST B17 I/O PullUp 100uA System reset,warm reset, bidirectional. The internalcircuitry indicatesany reset conditionby drivingnRST low. The externalcircuitrycan asserta systemresetby drivingnRST low.To ensurethatan external resetisnotarbitrarily generated,TI recommends thatan externalpull-upresistoris connectedtothisterminal. Thisterminalhas a glitch filter.See Section4.8. nERROR B14 I/O PullDown 20uA ESM ErrorSignal Indicateserrorofhigh severity.See Section4.18. 2.4.2.17Clock Inputsand Outputs Table2-39.ZWT Clock Inputsand Outputs Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT OSCIN K1 Input - - From external crystal/resonator,or externalclockinput KELVIN_GND L2 Input Kelvingroundforoscillator OSCOUT L1 Output To external crystal/resonator ECLK A12 I/O PullDown Programmable, Externalprescaledclock 20uA output,orGIO. GIOA[5]/EXTCLKIN B5 Input PullDown 20uA Externalclockinput#1 ETMTRACECLKIN/ EXTCLKIN2 R9 Input Externalclockinput#2 VCCPLL P11 Input - Dedicatedcoresupplyfor PLL's

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 2.4.2.18Testand Debug Modules Interface Table2-40.ZWT Testand Debug Modules Interface Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT TEST U2 I/O PullDown Fixed,100uA Testenable nTRST D18 Input JTAG testhardwarereset RTCK A16 Output - - JTAG returntestclock TCK B18 Input PullDown Fixed,100uA JTAG testclock TDI A17 I/O PullUp JTAG testdatain TDO C18 I/O PullDown JTAG testdataout TMS C19 I/O PullUp JTAG testselect 2.4.2.19FlashSupply and TestPads Table2-41.ZWT FlashSupply and TestPads Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT VCCP F8 Input - - Flashpump supply FLTP1 J5 Flashtestpads.These terminalsarereservedforFLTP2 H5 TIuse only.Forproper operationtheseterminals must connectonlytoa testpad ornotbe connectedatall[no connect(NC)]. Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 37 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com 2.4.2.20No Connects Table2-42.No Connects Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT NC D6 - - - No Connects.These balls arenotconnectedtoanyNC D7 - - - internallogicand can be NC D8 - - - connectedtothePCB groundwithoutaffectingNC D9 - - - thefunctionalityofthe NC D10 - - - device. Any otherballmarked asNC D11 - - - "NC" may be internally NC D12 - - - connectedtosome functionality.ItisNC E4 - - - recommended forsuch NC F4 - - - ballstobe left unconnected.NC G4 - - - NC K4 - - - NC L4 - - - NC M4 - - - NC N4 - - - NC N18 - - - NC P4 - NC P15 - - - NC P16 - - - NC P17 - - - NC R1 - - - NC R14 - - - NC R15 - - - NC T5 - - - NC T6 - - - NC T7 - - - NC T8 - - - NC T13 - - - NC T14 - - - NC V4 - - - NC W4 - - -

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 2.4.2.21Supply forCore Logic:1.2Vnominal Table2-43.ZWT Supply forCore Logic:1.2Vnominal Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT VCC F9 - - - Core supply VCC F10 VCC H10 VCC J14 VCC K6 VCC - VCC K8 VCC K12 VCC K14 VCC L6 VCC M10 VCC P10 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 39 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com 2.4.2.22Supply forI/OCells:3.3Vnominal Table2-44.ZWT Supply forI/OCells:3.3Vnominal Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT VCCIO F6 Input - - OperatingsupplyforI/Os VCCIO F7 VCCIO F11 VCCIO F12 VCCIO F13 VCCIO F14 VCCIO G6 VCCIO G14 VCCIO H6 VCCIO H14 VCCIO J6 VCCIO L14 VCCIO M6 VCCIO M14 VCCIO N6 VCCIO N14 VCCIO P6 VCCIO P7 VCCIO P8 VCCIO P9 VCCIO P12 VCCIO P13 VCCIO P14

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 2.4.2.23Ground ReferenceforAllSuppliesExcept VCCAD Table2-45.ZWT Ground ReferenceforAllSuppliesExcept VCCAD Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT VSS A1 Input - - Ground reference VSS A2 VSS A18 VSS A19 VSS B1 VSS B19 VSS H8 VSS H9 VSS H11 VSS H12 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VSS K9 VSS K10 VSS K11 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VSS M8 VSS M9 VSS M11 VSS M12 VSS V1 VSS W1 VSS W2 Copyright© 2011,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 41 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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3 Device OperatingConditions

3.1 AbsoluteMaximum RatingsOver OperatingFree-AirTemperature Range, (1)

VCC (2) -0.3V to1.43V Supplyvoltagerange: VCCIO ,VCCP (2) -0.3V to4.1V VCCAD -0.3V to5.5V Inputvoltagerange: Allinputpins -0.3V to4.1V IIK (VI< 0 orVI> VCCIO ) ±20 mA Allpins,exceptAD1IN[23:0]and AD2IN[15:0] Inputclamp current: IIK (VI< 0 orVI> VCCAD ) ±10 mA AD1IN[23:0]and AD2IN[15:0] Total ±40 mA Operatingfree-airtemperaturerange,TA: -40°C to105°C Operatingjunctiontemperaturerange,TJ: -40°C to125°C Storagetemperaturerange,Tstg -65°C to150°C (1) Stressesbeyond thoselistedunder“absolutemaximum ratings” may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder“recommended operating conditions” isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.Allvoltagevaluesarewithrespecttotheirassociated grounds.

3.2 Device Recommended OperatingConditions(1)

VCC Digitallogicsupplyvoltage(Core) 1.14 1.2 1.32 V VCCPLL PLL SupplyVoltage 1.14 1.2 1.32 V VCCIO Digitallogicsupplyvoltage(I/O) 3 3.3 3.6 V VCCAD MibADC supplyvoltage 3 3.3 3.6 V 4.5 5.0 5.25 VCCP Flashpump supplyvoltage 3 3.3 3.6 V VSS Digitallogicsupplyground 0 V VSSAD MibADC supplyground -0.1 0.1 V VADREFHI A-to-Dhigh-voltagereferencesource VSSAD VCCAD V VADREFLO A-to-Dlow-voltagereferencesource VSSAD VCCAD V TA Operatingfree-airtemperature -40 105 °C TJ Operatingjunctiontemperature -40 150 °C (1) AllvoltagesarewithrespecttoVSS ,exceptVCCAD ,whichiswithrespecttoVSSAD

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PRODUCT□PREVIEW Address□Waitstates Data□Waitstates RAM Address□Waitstates Data□Waitstates Flash 0MHz 0MHz 0MHz 0MHz 90MHz45MHz 0 1 3 135MHz 120MHz fHCLK(max) fHCLK(max) fHCLK(max) fHCLK(max) TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

3.3 SwitchingCharacteristicsover Recommended OperatingConditionsforClock Domains

Table3-1.Clock Domain Timing Specifications Parameter Description Conditions Min Max Unit fHCLK HCLK -System clockfrequency PGE Pipelinemode 160 MHz enabled Pipelinemode 45 MHz disabled ZWT Pipelinemode 180 MHz enabled Pipelinemode 45 MHz disabled fGCLK GCLK -CPU clockfrequency fHCLK MHz fVCLK VCLK -Primaryperipheralclock 100 MHz frequency fVCLK2 VCLK2 -Secondaryperipheralclock 100 MHz frequency fVCLK3 VCLK3 -Secondaryperipheralclock 100 MHz frequency fVCLKA1 VCLKA1 -Primaryasynchronous 100 MHz peripheralclockfrequency fVCLKA2 VCLKA2 -Secondaryasynchronous 100 MHz peripheralclockfrequency fVCLKA4 VCLKA4 -Secondaryasynchronous 50 MHz peripheralclockfrequency fRTICLK RTICLK -clockfrequency fVCLK MHz

3.4 Wait StatesRequired

Figure3-1.ZWT Wait StatesScheme As shown inthefigureabove,theTCM RAM can supportprogram and datafetchesatfullCPU speed without any addressordatawaitstatesrequired. The TCM flashcan supportzeroaddressand datawaitstatesup toa CPU speed of45MHz innon-pipelined mode. The flashsupportsa maximum CPU clockspeed of160MHz inpipelinedmode forthePGE Package and 180MHz fortheZWT package,withone addresswaitstateand threedatawaitstates. The flashwrapperdefaultstonon-pipelinedmode withzeroaddresswaitstateand one random-readdatawait state. Copyright© 2011,Texas InstrumentsIncorporated DeviceOperatingConditions 43 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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3.5 Power Consumption Over Recommended OperatingConditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fHCLK = 160MHz for 350 forPGEfHCLK = 180MHz for PackageVCC digitalsupplycurrent(operatingmode) ZWT Package mA 375 forZWT PackagefVCLK = 90MHz, Flash in pipelinedICC mode, VCCmax LBIST clock rate =VCC Digitalsupplycurrent(LBISTmode) mA40090MHz Peak PBIST ROM clock TBDVCC Digitalsupplycurrent frequency= 90MHz mA(PBIST mode) RMS 405 ICCPLL VCCPLL digitalsupplycurrent(operatingmode) VCCPLL = VCCPLLmax 10 mA ICCIO VCCIO Digitalsupplycurrent(operatingmode. No DC load,VCCmax 15 mA SingleADC 15 operational, VCCADmax ICCAD VCCAD supplycurrent(operatingmode) mA BothADCs 30 operational, VCCADmax SingleADC 5 operational, AD REFHImax ICCREFHI AD REFHI supplycurrent(operatingmode) mA BothADCs 10 operational, AD REFHImax readoperation 34 VCCPmax program,VCCPmax 37 readfrom1 bank 55ICCP VCCP pump supplycurrent mA and program anotherbank, VCCPmax erase,VCCPmax 27

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3.6 Input/OutputElectricalCharacteristicsOver Recommended OperatingConditions(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Inputhysteresis Allinputs(except 180 FRAYRX1, mV Vhys FRAYRX2) FRAYRX1, FRAYRX2 100 mV Allinputs(2)(except -0.3 0.8 FRAYRX1, V VIL Low-levelinputvoltage FRAYRX2) FRAYRX1, FRAYRX2 0.4VCCIO V Allinputs(2)(except 2 VCCIO + 0.3 FRAYRX1, V VIH High-levelinputvoltage FRAYRX2) FRAYRX1, FRAYRX2 0.6VCCIO V IOL = IOLmax 0.2VCCIO IOL = 50 µA,standard 0.2 outputmodeVOL Low-leveloutputvoltage V IOL = 50 µA,low-EMI 0.2VCCIO outputmode (see Section3.10) IOH = IOHmax 0.8VCCIO IOH = 50 µA,standard VCCIO -0.2 outputmodeVOH High-leveloutputvoltage V IOH = 50 µA,low-EMI 0.8VCCIO outputmode (see Section3.10) VI< VSSIO -0.3orVI -2 2IIC Inputclamp current(I/Opins) mA> VCCIO + 0.3 IIH Pulldown20µA VI= VCCIO 5 40 IIH Pulldown100µA VI= VCCIO 40 195 II Inputcurrent(I/Opins) IILPullup20µA VI= VSS -40 -5 µA IILPullup100µA VI= VSS -195 -40 Allotherpins No pulluporpulldown -1 1 C I Inputcapacitance 2 pF C O Outputcapacitance 3 pF (1) Sourcecurrents(outofthedevice)arenegativewhilesinkcurrents(intothedevice)arepositive. (2) Thisdoes notapplytothenPORRST pin.

3.7 Output BufferDriveStrengths

Table3-2.Output BufferDriveStrengths Low-levelOutput Current, IOL forVI=VOLmax or Signals High-levelOutput Current, IOH forVI=VOHmin FRAYTX2, FRAYTX1, FRAYTXEN1, FRAYTXEN2, MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0],MIBSPI5SIMO[1],MIBSPI5SIMO[2],MIBSPI5SIMO[3], 8mA TMS, TDI,TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR, N2HET2[1],N2HET2[3], AllEMIF Outputsand I/Os,AllETM Outputs Copyright© 2011,Texas InstrumentsIncorporated DeviceOperatingConditions 45 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW VCCIO V IH VIH VIL Input tpw V IL TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table3-2.Output BufferDriveStrengths (continued) Low-levelOutput Current, IOL forVI=VOLmax or Signals High-levelOutput Current, IOH forVI=VOHmin TEST, 4mA MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, nRST AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, DMM_CLK, DMM_DATA[0], DMM_DATA[1], DMM_nENA, DMM_SYNC, GIOA[0-7],GIOB[0-7], LINRX, LINTX,2mA zero-dominant MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA, MIBSPI5NCS[0-3],MIBSPI5NENA, N2HET1[0-31],N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7], N2HET2[8],N2HET2[9],N2HET2[10],N2HET2[11],N2HET2[12],N2HET2[13],N2HET2[14], N2HET2[15],N2HET2[16],N2HET2[18], SPI2NCS[0],SPI2NENA, SPI4NCS[0],SPI4NENA ECLK, selectable8mA /2mA SPI2CLK, SPI2SIMO, SPI2SOMI The defaultoutputbufferdrivestrengthis8mA forthesesignals.

3.8 InputTimings

Figure3-2.TTL-LevelInputs Table3-3.Timing Requirements forInputs(1) Parameter MIN MAX Unit tpw Inputminimum pulsewidth tc(VCLK) + 10(2) ns (1) tc(VCLK) = peripheralVBUS clockcycletime= 1 /f(VCLK) (2) The timingshown above isonlyvalidforpinused inGIO mode.

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3.9 Output Timings

Table3-4.SwitchingCharacteristicsforOutput Timings versus Load Capacitance(CL) Parameter MIN MAX Unit Risetime,tr 8mA lowEMI pins CL = 15 pF 2.5 ns (seeTable3-2) CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Falltime,tf CL = 15 pF 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Risetime,tr 4mA lowEMI pins CL = 15 pF 5.6 ns (seeTable3-2) CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Falltime,tf CL = 15 pF 5.6 ns CL= 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Risetime,tr 2mA-z lowEMI pins CL = 15 pF 8 ns (seeTable3-2) CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Falltime,tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Risetime,tr Selectable8mA /2mA-z 8mA mode CL = 15 pF 2 ns pins CL = 50 pF 4(seeTable3-2) CL = 100 pF 8 CL = 150 pF 11 Falltime,tf CL = 15 pF 2 ns CL = 50 pF 4 CL = 100 pF 8 CL = 150 pF 11 Risetime,tr 2mA-z mode CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Falltime,tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Copyright© 2011,Texas InstrumentsIncorporated DeviceOperatingConditions 47 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW tftr VCCIO V OH VOH VOL VOL Output TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Figure3-3.CMOS-Level Outputs Table3-5.Timing Requirements forOutputs(1) Parameter MIN MAX UNIT td(parallel_out) Delaybetween lowtohigh,orhightolowtransitionofgeneral-purposeoutputsignals 5 ns thatcan be configuredby an applicationinparallel,e.g.allsignalsina GIOA port,or allN2HET1 signals,etc. (1) Thisspecificationdoes notaccountforany outputbufferdrivestrengthdifferencesorany externalcapacitiveloadingdifferences.Check Table3-2foroutputbufferdrivestrengthinformationon each signal.

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3.10 Low-EMI Output Buffers

The low-EMI outputbufferhas been designedexplicitlyto addressthe issueof decouplingsourcesof emissionsfromthepinswhichtheydrive.Thisisaccomplishedby adaptivelycontrollingtheimpedance of theoutputbuffer,and isparticularlyeffectivewithcapacitiveloads. Thisisnotthedefaultmode ofoperationofthelow-EMIoutputbuffersand must be enabledby settingthe system module GPCR1 registerforthe desiredmodule or signal,as shown inTable 3-6. The adaptive impedance controlcircuitmonitorstheDC biaspointoftheoutputsignal.The bufferinternallygenerates two referencelevels,VREFLOW and VREFHIGH, which are set to approximately10% and 90% of VCCIO, respectively. Once theoutputbufferhas driventheoutputtoa low level,iftheoutputvoltageisbelow VREFLOW, then the outputbuffer’s impedance willincreaseto hi-Z.A high degree of decouplingbetween the internal groundbus and theoutputpinwilloccurwithcapacitiveloads,orany loadinwhichno currentisflowing, e.g.thebufferisdrivinglowon a resistivepathtoground.Currentloadson thebufferwhichattempttopull theoutputvoltageabove VREFLOW willbe opposed by thebuffer’s outputimpedance so as tomaintain theoutputvoltageatorbelowVREFLOW. Conversely,once the outputbufferhas driventhe outputto a highlevel,ifthe outputvoltageisabove VREFHIGH thentheoutputbuffer’s impedance willagainincreasetohi-Z.A highdegree ofdecoupling between internalpower bus ad outputpinwilloccurwithcapacitiveloadsorany loadsinwhichno current isflowing,e.g.bufferisdrivinghighon a resistivepath to VCCIO. Currentloadson the bufferwhich attempttopulltheoutputvoltagebelow VREFHIGH willbe opposed by thebuffer’s outputimpedance so as tomaintaintheoutputvoltageatorabove VREFHIGH. The bandwidthof the controlcircuitryisrelativelylow,so thatthe outputbufferinadaptiveimpedance controlmode cannot respond to high-frequencynoisecouplingintothe buffer’s power buses.In this manner,internalbus noiseapproaching20% peak-to-peakofVCCIO can be rejected. Unlikestandardoutputbufferswhich clamp totherails,an outputbufferinimpedance controlmode will allowa positivecurrentloadto pullthe outputvoltageup to VCCIO + 0.6V withoutopposition.Also,a negativecurrentloadwillpulltheoutputvoltagedown toVSSIO – 0.6V withoutopposition.Thisisnotan issuesincetheactualclamp currentcapabilityisalwaysgreaterthantheIOH /IOL specifications. The low-EMI outputbuffersare automaticallyconfiguredto be in the standardbuffermode when the deviceentersa low-powermode. Table3-6.Low-EMI Output BufferHookup Module or SignalName ControlRegistertoEnable Low-EMI Mode Module:MibSPI1 GPREG1.0 Module:SPI2 GPREG1.1 Module:MibSPI3 GPREG1.2 Reserved GPREG1.3 Module:MibSPI5 GPREG1.4 Module:FlexRay GPREG1.5 Module:SPI2 GPREG1.6 Module:SPI2 GPREG1.7 Signal:TMS GPREG1.8 Signal:TDI GPREG1.9 Signal:TDO GPREG1.10 Signal:RTCK GPREG1.11 Signal:TEST GPREG1.12 Signal:nERROR GPREG1.13 Reserved GPREG1.14 Module:RTP GPREG1.15 Copyright© 2011,Texas InstrumentsIncorporated DeviceOperatingConditions 49 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4 System Informationand ElectricalSpecifications

4.1 Device Power Domains

The devicecorelogicissplitup intomultiplepower domains inordertooptimizethepower fora given applicationuse case.There are 8 corepower domains intotal:PD1, PD2, PD3, PD4, PD5, RAM_PD1, RAM_PD2 and RAM_PD3. The actualcontentsofthesepower domains areindicatedin. PD1 isan "always-ON"power domain,whichcannotbe turnedoff.Each oftheothercorepower domains can be turnedON/OFF one timeduringdeviceinitializationas per theapplicationrequirement.Referto thePower Management Module (PMM) chapterofthedevicetechnicalreferencemanual formore details. NOTE The clocksto a module must be turnedoffbeforepoweringdown the core domain that containsthemodule. NOTE The logicinthemodules thatare powered down losesitspower completely.Any access to modules thatare powered down resultsin an abortbeing generated.When power is restored,themodules power-uptotheirdefaultstates(afternormalpower-up).No registeror memory contentsarepreservedinthecoredomains thatareturnedoff. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 51 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.2 VoltageMonitorCharacteristics

A voltagemonitorisimplementedon thisdevice.The purposeofthisvoltagemonitoristoeliminatethe requirementfora specificsequence when poweringup thecoreand I/Ovoltagesupplies.

4.2.1 ImportantConsiderations

The voltagemonitordoes noteliminatetheneed ofa voltagesupervisorcircuittoguaranteethatthe deviceisheldinresetwhen thevoltagesuppliesareoutofrange.
The voltagemonitoronlymonitorsthe core supply(VCC) and the I/O supply(VCCIO). The other suppliesare notmonitoredby theVMON. For example,iftheVCCAD or VCCP are suppliedfrom a sourcedifferentfrom thatforVCCIO, then thereisno internalvoltagemonitorforthe VCCAD and VCCP supplies.

4.2.2 VoltageMonitorOperation

The voltagemonitorgeneratesthePower Good MCU signal(PGMCU) as wellas theI/OsPower Good IO signal(PGIO)on thedevice.Duringpower-uporpower-down,thePGMCU and PGIO aredrivenlowwhen the core or I/O suppliesare lowerthan the specifiedminimum monitoringthresholds.The PGIO and PGMCU beinglow isolatesthecorelogicas wellas theI/Ocontrolsduringthepower-uporpower-down ofthesupplies.Thisallowsthecoreand I/Osuppliestobe powered up ordown inany order. When thevoltagemonitordetectsa low voltageon theI/Osupply,itwillasserta power-onreset.When thevoltagemonitordetectsan out-of-rangevoltageon thecoresupply,itasynchronouslymakes alloutput pinshighimpedance,and assertsa power-on reset.The voltagemonitorisdisabledwhen the device entersa lowpower mode. The VMON alsoincorporatesa glitchfilterforthenPORRST input.RefertoSection4.3.3.1forthetiming informationon thisglitchfilter. Table4-1.VoltageMonitoringSpecifications PARAMETER MIN TYP MAX UNIT VCC low-VCC levelbelowthis 0.8 0.9 1.0 V thresholdisdetectedas toolow. Voltagemonitoring VCC high-VCC levelabove this 1.40 1.7 2.1VMON thresholds thresholdisdetectedas toohigh. VCCIO low-VCCIO levelbelowthis 1.9 2.4 2.9 thresholdisdetectedas toolow.

4.2.3 Supply Filtering

The VMON has thecapabilitytofilterglitcheson theVCC and VCCIO supplies. The followingtableshows thecharacteristicsofthesupplyfiltering.Glitchesinthesupplylargerthanthe maximum specificationcannotbe filtered. Table4-2.VMON Supply GlitchFilteringCapability Parameter MIN MAX Widthofglitchon VCC thatcan be filtered 250ns 1us Widthofglitchon VCCIO thatcan be filtered 250ns 1us

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4.3 Power Sequencing and Power On Reset

4.3.1 Power-Up Sequence

There is no timingdependency between the ramp of the VCCIO and the VCC supplyvoltage.The power-up sequence startswiththe I/O voltagerisingabove the minimum I/O supplythreshold,(see Table4-4formore details),corevoltagerisingabove theminimum coresupplythresholdand therelease of power-on reset.The high frequencyoscillatorwillstartup firstand itsamplitudewillgrow to an acceptablelevel.The oscillatorstartup timeisdependenton thetypeofoscillatorand isprovidedby the oscillatorvendor.The differentsuppliestothedevicecan be powered up inany order. The devicegoes throughthefollowingsequentialphases duringpower up. Table4-3.Power-Up Phases Oscillatorstart-upand validitycheck 1032 oscillatorcycles eFuse autoload 1180 oscillatorcycles Flashpump power-up 688 oscillatorcycles Flashbank power-up 617 oscillatorcycles Total 3517 oscillatorcycles The CPU resetisreleasedattheend oftheabove sequence and fetchesthefirstinstructionfromaddress 0x00000000. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 53 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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3.3 V VCCIOPORH

1.2 V VCCPORH VCCIOPORL V (1.2 V) V / V (3.3 V) CC CCIO CCP nPORRST 6 6 VCCPORL VIL(PORRST) V / VCCIO CCP VCC VCCPORL VIL(PORRST)VIL VIL VIL VCCIOPORH VCCPORH VCCIOPORL NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

4.3.2 Power-Down Sequence

The differentsuppliestothedevicecan be powered down inany order.

4.3.3 Power-On Reset:nPORRST

Thisisthepower-onreset.Thisresetmust be assertedby an externalcircuitrywhenever theI/Oorcore suppliesareoutsidethespecifiedrecommended range.Thissignalhas a glitchfilteron it.Italsohas an internalpulldown. 4.3.3.1 nPORRST Electricaland Timing Requirements Table4-4.ElectricalRequirements fornPORRST NO Parameter MIN MAX Unit VCCPORL VCC lowsupplylevelwhen nPORRST must be activeduring 0.5 V power-up VCCPORH VCC highsupplylevelwhen nPORRST must remainactiveduring 1.14 V power-upand become activeduringpower down VCCIOPORL VCCIO /VCCP lowsupplylevelwhen nPORRST must be activeduring 1.1 V power-up VCCIOPORH VCCIO /VCCP highsupplylevelwhen nPORRST must remainactive 3.0 V duringpower-upand become activeduringpower down VIL(PORRST) Low-levelinputvoltageofnPORRST VCCIO > 2.5V 0.2*VCCIO V Low-levelinputvoltageofnPORRST VCCIO < 2.5V 0.5 V 3 tsu(PORRST) Setuptime,nPORRST activebeforeVCCIO and VCCP > VCCIOPORL 0 ms duringpower-up 6 th(PORRST) Holdtime,nPORRST activeafterVCC > VCCPORH 1 ms 7 tsu(PORRST) Setuptime,nPORRST activebeforeVCC < VCCPORH duringpower 2 µs down 8 th(PORRST) Holdtime,nPORRST activeafterVCCIO and VCCP > VCCIOPORH 1 ms 9 th(PORRST) Holdtime,nPORRST activeafterVCC < VCCPORL 0 ms tf(nPORRST) 500 2000 nsFiltertimenPORRST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset. Figure4-1.nPORRST Timing Diagram

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4.4 Warm Reset (nRST)

Thisisa bidirectionalresetsignal.The internalcircuitrydrivesthesignallow on detectingany devicereset condition.An externalcircuitcan asserta deviceresetby forcingthe signallow.On thisterminal,the outputbufferisimplementedas an open drain(driveslow only).To ensure an externalresetisnot arbitrarilygenerated,TIrecommends thatan externalpullupresistorisconnectedtothisterminal. Thisterminalhas a glitchfilter.Italsohas an internalpullup

4.4.1 Causes ofWarm Reset

Table4-5.Causes ofWarm Reset DEVICE EVENT SYSTEM STATUS FLAG Power-Up Reset ExceptionStatusRegister,bit15 Oscillatorfail GlobalStatusRegister,bit0 PLL slip GlobalStatusRegister,bits8 and 9 Watchdog exception/Debugger reset ExceptionStatusRegister,bit13 CPU Reset(drivenby theCPU STC) ExceptionStatusRegister,bit5 SoftwareReset ExceptionStatusRegister,bit4 ExternalReset ExceptionStatusRegister,bit3 4.4.2 nRST Timing Requirements Table4-6.nRST Timing Requirements(1) PARAMETER MIN MAX UNIT tv(RST) Validtime,nRST activeafter 1180 tc(OSC) + 1048tc(OSC) ns nPORRST inactive Validtime,nRST active(allother 8tc(VCLK) System resetconditions) tf(nRST) 500 2000 nsFiltertimenRST pin; pulses less than MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset (1) Specifiedvaluesdo NOT includerise/falltimes.Forriseand falltimings,see theswitchingcharacteristicsforoutputtimingsversusload capacitancetable. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 55 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.5 ARM © Cortex-R4F™ CPU Information

4.5.1 Summary ofARM Cortex-R4F™ CPU Features

The featuresoftheARM Cortex-R4F™ CPU include:

An integerunitwithintegralEmbeddedICE-RT logic.
High-speedAdvanced MicroprocessorBus Architecture(AMBA) Advanced eXtensibleInterfaces(AXI) forLeveltwo (L2)masterand slaveinterfaces.
FloatingPointCoprocessor
Dynamic branchpredictionwitha globalhistorybuffer,and a 4-entryreturnstack
Low interruptlatency.
Non-maskableinterrupt.
A HarvardLevelone (L1)memory systemwith: – Tightly-CoupledMemory (TCM) interfaceswith supportforerrorcorrectionor paritychecking memories – ARMv7-R architectureMemory ProtectionUnit(MPU) with12 regions
Dualcorelogicforfaultdetectioninsafety-criticalapplications.
An L2 memory interface: – Single64-bitmasterAXI interface – 64-bitslaveAXI interfacetoTCM RAM blocks
A debug interfacetoa CoreSightDebug Access Port(DAP).
A traceinterfacetoa CoreSightETM-R4.
A PerformanceMonitoringUnit(PMU).
A VectoredInterruptController(VIC)port. Formore informationon theARM Cortex-R4F™ CPU pleasesee www.arm.com .

4.5.2 ARM Cortex-R4F™ CPU FeaturesEnabled by Software

The followingCPU featuresaredisabledon resetand must be enabledby theapplicationifrequired.

ECC On Tightly-CoupledMemory (TCM) Accesses
Harware VectoredInterrupt(VIC)Port
FloatingPointCoprocessor
Memory ProtectionUnit(MPU)

4.5.3 Dual Core Implementation

The devicehas two Cortex-R4Fcores,where the outputsignalsof both CPUs are compared in the CCM-R4 unit.To avoidcommon mode impactsthesignalsoftheCPUs tobe compared aredelayedby 2 clockcyclesas shown inFigure4-3. The CPUs have a diverseCPU placementgivenby followingrequirements:

differentorientation;e.g.CPU1 = "north"orientation,CPU2 = "flipwest"orientation
dedicatedguardringforeach CPU Figure4-2.Dual -CPU Orientation

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4.5.4 DuplicateclocktreeafterGCLK

The CPU clockdomain issplitintotwo clocktrees,one foreach CPU, withthe clockof the 2nd CPU runningatthesame frequencyand inphase totheclockofCPU1. See Figure4-3.

4.5.5 ARM Cortex-R4F™ CPU Compare Module (CCM) forSafety

Thisdevicehas two ARM Cortex-R4F™ CPU cores,where theoutputsignalsofbothCPUs arecompared intheCCM-R4 unit.To avoidcommon mode impactsthesignalsoftheCPUs tobe compared aredelayed ina differentway as shown inthefigurebelow. Figure4-3.Dual Core Implementation To avoidan erroneousCCM-R4 compare error,the applicationsoftwaremust initializethe registersof both CPUs beforethe registersare used,includingfunctioncallswhere the registervaluesare pushed ontothestack.

4.5.6 CPU Self-Test

The CPU STC (Self-TestController)is used to testthe two Cortex-R4F CPU Cores using the DeterministicLogicBIST Controlleras thetestengine. The main featuresoftheself-testcontrollerare:

Abilitytodividethecompletetestrunintoindependenttestintervals
Capableofrunningthecompletetestas wellas runningfew intervalsata time
Abilityto continuefrom the lastexecuted interval(testset)as wellas abilityto restartfrom the beginning(Firsttestset)
Completeisolationoftheself-testedCPU corefromrestofthesystemduringtheself-testrun
AbilitytocapturetheFailureintervalnumber
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4.5.6.1 ApplicationSequence forCPU Self-Test

Configureclockdomain frequencies. 2. Selectnumber oftestintervalstobe run. 3. Configurethetimeoutperiodfortheself-testrun. 4. Enableself-test. 5. WaitforCPU reset. 6. Intheresethandler,readCPU self-teststatustoidentifyany failures. 7. RetrieveCPU stateifrequired. Formore informationsee theTMS570LS31X/21X TechnicalReferenceManual (SPNU499).

4.5.6.2 CPU Self-TestClock Configuration

The maximum clockratefortheself-testis90MHz. The STCCLK isdivideddown from theCPU clock. Thisdividerisconfiguredby theSTCCLKDIV registerataddress0xFFFFE108. Formore informationsee theTMS570LS31X/21X TechnicalReferenceManual (SPNU499).

4.5.6.3 CPU Self-TestCoverage

Table4-7 shows CPU testcoverageachievedforeach self-testinterval.Italsoliststhecumulativetest cycles.The testtimecan be calculatedby multiplyingthenumber oftestcycleswiththeSTC clockperiod. Table4-7.CPU Self-TestCoverage INTERVALS TEST COVERAGE, % TEST CYCLES 0 0 0 1 62.13 1365 2 70.09 2730 3 74.49 4095 4 77.28 5460 5 79.28 6825 6 80.90 8190 7 82.02 9555 8 83.10 10920 9 84.08 12285 10 84.87 13650 11 85.59 15015 12 86.11 16380 13 86.67 17745 14 87.16 19110 15 87.61 20475 16 87.98 21840 17 88.38 23205 18 88.69 24570 19 88.98 25935 20 89.28 27300 21 89.50 28665 22 89.76 30030 23 90.01 31395 24 90.21 32760

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PRODUCT□PREVIEW OSCIN OSCOUT (see Note A) Crystal (a) OSCIN OSCOUT (b) External (toggling 0-3.3V) Clock Signal Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor. Kelvin_GND Note B: Kelvin_GND should not be connected to any other GND. (see Note B) TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.6 Clocks

4.6.1 Clock Sources

The tablebelow liststheavailableclocksourceson thedevice.Each oftheclocksourcescan be enabled or disabledusingthe CSDISx registersin the system module. The clocksource number in the table correspondstothecontrolbitintheCSDISx registerforthatclocksource. The tablealsoshows thedefaultstateofeach clocksource. Table4-8.AvailableClock Sources Clock Name Description DefaultStateSource #

0 OSCIN Main Oscillator Enabled

1 PLL1 OutputFrom PLL1 Disabled

2 Reserved Reserved Disabled

3 EXTCLKIN1 ExternalClockInput#1 Disabled

4 CLK80K Low FrequencyOutputofInternalReferenceOscillator Enabled

HighFrequencyOutputofInternalReference5 CLK10M EnabledOscillator

6 PLL2 OutputFrom PLL2 Disabled

7 EXTCLKIN2 ExternalClockInput#2 Disabled

4.6.1.1 Main Oscillator

The oscillatorisenabledby connectingtheappropriatefundamentalresonator/crystaland loadcapacitors acrossthe externalOSCIN and OSCOUT pinsas shown inFigure4-4. The oscillatorisa singlestage inverterheld in bias by an integratedbias resistor.This resistoris disabledduringleakage test measurement and lowpower modes. TI stronglyencourages each customer to submit samples of the device to the resonator/crystal vendors forvalidation.The vendors are equipped to determinewhat load capacitorswillbest tune theirresonator/crystalto the microcontrollerdevice for optimum start-upand operation over temperature/voltageextremes. An externaloscillatorsourcecan be used by connectinga 3.3V clocksignaltotheOSCIN pinand leaving theOSCOUT pinunconnected(open)as shown inthefigurebelow. Figure4-4.Recommended Crystal/ClockConnection Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 59 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com 4.6.1.1.1Timing Requirements forMain Oscillator Table4-9.Timing Requirements forMain Oscillator Parameter MIN Type MAX Unit tc(OSC) Cycletime,OSCIN (when usinga sine-waveinput) 50 200 ns tc(OSC_SQR) Cycletime,OSCIN, (when inputtotheOSCIN isa 12.5 200 ns squarewave ) tw(OSCIL) Pulseduration,OSCIN low(when inputtotheOSCIN 6 ns isa squarewave) tw(OSCIH) Pulseduration,OSCIN high(when inputtotheOSCIN 6 ns isa squarewave)

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PRODUCT□PREVIEW BIAS_EN Low Power Oscillator LFEN LF_TRIM HFEN HF_TRIM CLK80K CLK10M CLK10M_V ALID nPORRST TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.6.1.2 Low Power Oscillator

The Low Power Oscillator(LPO) iscomprisedof two oscillators— HF LPO and LF LPO, ina single macro. 4.6.1.2.1Features The main featuresoftheLPO are:

Suppliesa clockatextremelylow power forpower-savingmodes. Thisisconnectedas clocksource# 4 oftheGlobalClockModule.
Suppliesa high-frequencyclockfornon-timing-criticalsystems.Thisisconnectedas clocksource# 5 oftheGlobalClockModule.
Providesa comparisonclockforthecrystaloscillatorfailuredetectioncircuit. Figure4-5.LPO Block Diagram Figure4-5shows a blockdiagramoftheinternalreferenceoscillator.Thisisa low power oscillator(LPO) and providestwo clocksources:one nominally80KHz and one nominally10MHz. 4.6.1.2.2LPO Electricaland Timing Specifications Table4-10.LPO Specifications Parameter MIN Type MAX Unit LPO -HF oscillator untrimmedfrequency 5.5 9.6 19.5 MHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 10 µs atleast900µs) coldstartuptime 900 µs LPO -LF oscillator untrimmedfrequency 36 85 180 kHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 100 µs atleast900µs) coldstartuptime 2000 µs Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 61 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW /NR /1 to /64 OSCIN PLL INTCLK /OD /1 to /8 VCOCLK /R /1 to /32 post_ODCLK /NF /1 to /256 PLLCLK /NR2 /1 to /64 OSCIN PLL#2 INTCLK2 /OD2 /1 to /8 VCOCLK2 /R2 /1 to /32 post_ODCLK2 /NF2 /1 to /256 PLL2CLK fPLLCLK = (fOSCIN / NR) * NF / (OD * R) fPLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2) TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

4.6.1.3 Phase Locked Loop (PLL)Clock Modules

The PLL isused tomultiplytheinputfrequencytosome higherfrequency. The main featuresofthePLL are:

Frequency modulationcan be optionallysuperimposedon the synthesizedfrequencyof PLL1. The frequencymodulationcapabilityofPLL2 ispermanentlydisabled.
Configurablefrequencymultipliersand dividers.
Built-inPLL Slipmonitoringcircuit.
Optiontoresetthedeviceon a PLL slipdetection. 4.6.1.3.1Block Diagram Figure4-6shows a high-levelblockdiagramofthetwo PLL macros on thismicrocontroller.PLLCTL1 and PLLCTL2 areused toconfigurethemultiplierand dividersforthePLL1. PLLCTL3 isused toconfigurethe multiplierand dividersforPLL2. Figure4-6.ZWT PLLx Block Diagram 4.6.1.3.2PLL Timing Specifications Table4-11.PLL Timing Specifications PARAMETER MIN MAX UNIT fINTCLK PLL1 ReferenceClockfrequency 1 f(OSC_SQR) MHz fpost_ODCLK Post-ODCLK – PLL1 Post-dividerinput 400 MHz clockfrequency fVCOCLK VCOCLK – PLL1 OutputDivider(OD) input 550 MHz clockfrequency fINTCLK2 PLL2 ReferenceClockfrequency 1 f(OSC_SQR) MHz fpost_ODCLK2 Post-ODCLK – PLL2 Post-dividerinput 400 MHz clockfrequency fVCOCLK2 VCOCLK – PLL2 OutputDivider(OD) input 550 MHz clockfrequency

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4.6.1.4 ExternalClock Inputs

The devicesupportsup totwo externalclockinputs.Thisclockinputmust be a squarewave input.The electricaland timingrequirementsfortheseclockinputsarespecifiedbelow. Table4-12.ExternalClock Timing and ElectricalSpecifications Parameter Description Min Max Unit fEXTCLKx Externalclockinputfrequency 80 MHz tw(EXTCLKIN)H EXTCLK high-pulseduration 6 ns tw(EXTCLKIN)L EXTCLK low-pulseduration 6 ns viL(EXTCLKIN) Low-levelinputvoltage -0.3 0.8 V viH(EXTCLKIN) High-levelinputvoltage 2 VCCIO + 0.3 V

4.6.2 Clock Domains

4.6.2.1 Clock Domain Descriptions

The tablebelow liststhedeviceclockdomains and theirdefaultclocksources.The tablealsoshows the systemmodule controlregisterthatisused toselectan availableclocksourceforeach clockdomain. Table4-13.Clock Domain Descriptions Clock Domain Name DefaultClock Clock Source Description Source SelectionRegister HCLK OSCIN GHVSRC • IsdisabledviatheCDDISx registersbit1

Used forallsystemmodules includingDMA, ESM GCLK OSCIN GHVSRC • Alwaysthesame frequencyas HCLK
Inphase withHCLK
IsdisabledseparatelyfromHCLK viatheCDDISx registersbit0
Can be dividedby 1up to8 when runningCPU self-test(LBIST) usingtheCLKDIV fieldoftheSTCCLKDIV registerataddress 0xFFFFE108 GCLK2 OSCIN GHVSRC • Alwaysthesame frequencyas GCLK
2 cyclesdelayedfromGCLK
IsdisabledalongwithGCLK
Gets dividedby thesame dividersettingas thatforGCLK when runningCPU self-test(LBIST) VCLK OSCIN GHVSRC • Divideddown fromHCLK
Can be HCLK/1, HCLK/2, ...orHCLK/16
IsdisabledseparatelyfromHCLK viatheCDDISx registersbit2 VCLK2 OSCIN GHVSRC • Divideddown fromHCLK
Can be HCLK/1, HCLK/2, ...orHCLK/16
Frequencymust be an integermultipleofVCLK frequency
IsdisabledseparatelyfromHCLK viatheCDDISx registersbit3 VCLK3 OSCIN GHVSRC • Divideddown fromHCLK
Can be HCLK/1, HCLK/2, ...orHCLK/16
IsdisabledseparatelyfromHCLK viatheCDDISx registersbit8 VCLKA1 VCLK VCLKASRC • DefaultstoVCLK as thesource
IsdisabledviatheCDDISx registersbit4 VCLKA2 VCLK VCLKASRC • DefaultstoVCLK as thesource
IsdisabledviatheCDDISx registersbit5 VCLKA3_S VCLK VCLKACON • DefaultstoVCLK as thesource
Frequencycan be as fastas HCLK frequency.
IsdisabledviatheCDDISx registersbit10 Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 63 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table4-13.Clock Domain Descriptions(continued) Clock Domain Name DefaultClock Clock Source Description Source SelectionRegister VCLKA3_DIVR VCLK VCLKACON1 • Divideddown fromtheAVCLK3_S usingtheVCLKA3R fieldof theVCLKACON1 registerataddress0xFFFFE140

Frequencycan be VCLKA3_S/1, VCLKA3_S/2, ...,or VCLKA3_S/8
DefaultfrequencyisVCLKA3_S/2
IsdisabledseparatelyviatheVCLKACON1 register VCLKA3_DIV_CDDIS bitonlyiftheVCLKA3_S clockisnot disabled VCLKA4 VCLK VCLKACON1 • DefaultstoVCLK as thesource
IsdisabledviatheCDDISx registersbit11 RTICLK VCLK RCLKSRC • DefaultstoVCLK as thesource
Ifa clocksourceotherthanVCLK isselectedforRTICLK, then theRTICLK frequencymust be lessthanorequaltoVCLK/3 – Applicationcan ensurethisby programmingtheRTI1DIV fieldoftheRCLKSRC register,ifnecessary
IsdisabledviatheCDDISx registersbit6

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PRODUCT□PREVIEW HCLK (to□SYSTEM) GCLK,□GCLK2 (to□CPU) GCM VCLK_peri (VCLK to peripherals on□PCR1) VCLK2□(to□NHETx and□HTUx) VCLKA1□(to D CANx) /1..16 /1..16 RTICLK (to□RTI,□DWWD) /1,□2,□4,□or□8 VCLK OSCIN Low□Power Oscillator 10MHz 80kHz FMzPLL PLL #□2 VCLK /1,2,..1024 Phase_seg2 CAN□Baud□Rate Phase_seg1 VCLKA1 /1,2,..256 SPIx,MibSPIx /2,3..224 LIN,□SCI SPI LIN /□SCI /1,2..32 MibADCx ADCLK /1,2..65536 External□Clock ECLK VCLK2 NHETx HRP /1..64 LRP /20..25 Loop Resolution□Clock High Baud□Rate Baud□Rate NHETx VCLK2 TU Ethernet VCLKA4 (SSPLL) (SSPLL) VCLK VCLKA4□(to□Ethernet ,□as□alternate EXTCLKIN1 EXTCLKIN2 VCLK VCLK3 EMIF VCLK3□(to□EMIF,□and□Ethernet)/1..16 VCLK_sys (VCLK to system□modules) exceed□the□maximum□HCLK□specifiation. /1,2..256 I2C I2C□baud rate for MIITXCLK□and/or MIIRXCLK) VCLKA2□(to□FlexRa y) VCLK /1,2,..4 VCLKA 2 GTUC1,2 NTU[1] NTU[0] NTU[2] NTU[3] RTI Macro Tick Start of□cycle PLL#2□output EXTCLKIN1 VCLKA2 Prop_seg DCANx FlexRay Baud Rate FlexRay TU FlexRay TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.6.2.2 Mapping ofClock Domains toDevice Modules

Each clockdomain has a dedicatedfunctionalityas shown inthefiguresbelow. Figure4-7.Device Clock Domains Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 65 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.6.3 Clock TestMode

The TMS570 platformarchitecturedefinesa specialmode thatallowsvariousclocksignalstobe brought outon totheECLK pinand N2HET1[12] deviceoutputs.Thismode iscalledtheClockTestmode. Itis very usefulfordebugging purposes and can be configuredvia the CLKTEST registerin the system module. Table4-14.Clock TestMode Options SEL_ECP_PIN SEL_GIO_PIN = SIGNAL ON ECLK = SIGNAL ON N2HET1[12] CLKTEST[3-0] CLKTEST[11-8]

0000 Oscillator 0000 OscillatorValidStatus

0001 Main PLL free-runningclockoutput 0001 Main PLL Validstatus

0010 Reserved 0010 Reserved

0011 EXTCLKIN1 0011 Reserved

0100 CLK80K 0100 Reserved

0101 CLK10M 0101 CLK10M Validstatus

0110 SecondaryPLL free-runningclockoutput 0110 SecondaryPLL ValidStatus

0111 EXTCLKIN2 0111 Reserved

1000 GCLK 1000 CLK80K

1001 RTI Base 1001 Reserved

1010 Reserved 1010 Reserved

1011 VCLKA1 1011 Reserved

1100 VCLKA2 1100 Reserved

1101 Reserved 1101 Reserved

1110 VCLKA4 1110 Reserved

1111 Reserved 1111 Reserved

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PRODUCT□PREVIEW f[MHz]1.375 4.875 22 78 guaranteed fail lower threshold guaranteed pass upper threshold guaranteed fail TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.7 Clock Monitoring

The LPO ClockDetect(LPOCLKDET) module consistsofa clockmonitor(CLKDET) and an internallow power oscillator(LPO). The LPO providestwo differentclocksources – a low frequency(CLK80K) and a high frequency (CLK10M). The CLKDET isa supervisorcircuitforan externallysuppliedclocksignal(OSCIN).Incase theOSCIN frequencyfallsoutofa frequencywindow,theCLKDET flagsthisconditionintheglobalstatusregister (GLBSTAT bit0:OSC FAIL)and switchesallclockdomains sourcedby OSCIN totheCLK10M clock(limp mode clock). The validOSCIN frequencyrangeisdefinedas:fCLK10M /4 < fOSCIN < fCLK10M *4.

4.7.1 Clock MonitorTimings

Table4-15.LPO and Clock Detection Parameter MIN Type MAX Unit ClockDetection oscillatorfailfrequency-lowerthreshold,using 1.375 2.4 4.875 MHz untrimmedLPO output oscillatorfailfrequency-higherthreshold,using 22 38.4 78 MHz untrimmedLPO output LPO -HF oscillator untrimmedfrequency 5.5 9.6 19.5 MHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 10 µs atleast900ms) coldstartuptime 900 µs ICC,CLK10M and CLK80K active 150 µA LPO -LF oscillator untrimmedfrequency 36 85 180 kHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 100 µs atleast900ms) coldstartuptime 2000 µs ICC,onlyCLK80K active 27 µA LPO totalICC STANDBY current 20 µA Figure4-8.LPO and Clock Detection,Untrimmed CLK10M

4.7.2 ExternalClock (ECLK) Output Functionality

The ECLK pincan be configuredtooutputa pre-scaledclocksignalindicativeofan internaldeviceclock. Thisoutputcan be externallymonitoredas a safetydiagnostic.

4.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determinesthe accuracyof selectableclocksources by countingthe pulsesof two independentclocksources(counter0 and counter1).Ifone clockisout of spec,an errorsignalisgenerated.For example,the DCC1 can be configuredto use CLK10M as the referenceclock(forcounter0) and VCLK as the "clockunder test"(forcounter1).Thisconfiguration allowstheDCC1 tomonitorthePLL outputclockwhen VCLK isusingthePLL outputas itssource. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 67 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com An additionaluse ofthismodule istomeasure thefrequencyofa selectableclocksource,usingtheinput clockas a reference,by countingthe pulsesof two independentclocksources.Counter0 generatesa fixed-widthcountingwindow aftera preprogrammed number ofpulses.Counter1 generatesa fixed-width pulse(1 cycle)aftera pre-programmednumber ofpulses.Thispulsesetsas an errorsignalifcounter1 does notreach0 withinthecountingwindow generatedby counter0.

4.7.3.1 Features

Takes two differentclocksourcesas inputtotwo independentcounterblocks.
One oftheclocksourcesistheknown-good,orreferenceclock;thesecond clocksourceisthe"clock undertest."
Each counterblockisprogrammablewithinitial,orseed values.
The counterblocksstartcountingdown fromtheirseed valuesatthesame time;a mismatch fromthe expectedfrequencyforthe clockunder testgeneratesan errorsignalwhich isused to interruptthe CPU.

4.7.3.2 Mapping ofDCC Clock Source Inputs

Table4-16.DCC1 Counter 0 Clock Sources CLOCK SOURCE [3:0] CLOCK NAME others oscillator(OSCIN) 0x5 highfrequencyLPO 0xA testclock(TCK) Table4-17.DCC1 Counter 1 Clock Sources KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME others - N2HET1[31] 0x0 Main PLL free-runningclockoutput 0x1 PLL #2 free-runningclockoutput 0x2 lowfrequencyLPO 0xA 0x3 highfrequencyLPO 0x4 flashHD pump oscillator 0x5 EXTCLKIN1 0x6 EXTCLKIN2 0x7 ringoscillator 0x8 -0xF VCLK Table4-18.DCC2 Counter 0 Clock Sources CLOCK SOURCE [3:0] CLOCK NAME others oscillator(OSCIN) 0xA testclock(TCK) Table4-19.DCC2 Counter 1 Clock Sources KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME others - N2HET2[0] 0xA 00x0 -0x7 Reserved 0x8 -0xF VCLK

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4.8 GlitchFilters

A glitchfilterispresenton thefollowingsignals. Table4-20.GlitchFilterTiming Specifications Pin Parameter MIN MAX Unit nPORRST tf(nPORRST) 500 2000 nsFiltertimenPORRST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset(1) nRST tf(nRST) 500 2000 nsFiltertimenRST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset TEST tf(TEST) 500 2000 nsFiltertimeTEST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willpass through (1) The glitchfilterdesignon thenPORRST signalisdesignedsuch thatno sizepulsewillresetany partofthemicrocontroller(flashpump, I/Opins,etc.)withoutalsogeneratinga validresetsignaltotheCPU. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 69 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW Flash□(3MB) RAM□(256KB) 0x00000000 0x002FFFFF 0x08000000 0x0803FFFF CRC0xFE000000 Peripherals -□Frame□1 0xFF000000 SYSTEM□Modules0xFFFFFFFF 0xF07FFFFF RAM□-□ECC 0x08400000 0x0843FFFF RESERVED RESERVED RESERVED 0xF0000000 Flash□(3MB)□(Mirrored□Image) 0x20000000 0x202FFFFF RESERVED RESERVED Peripherals -□Frame□2 0xFC000000 0xFFF80000 RESERVED Flash□Module□Bus2□Interface (Flash□ECC,□OTP and□EEPROM□accesses) 0xFCFFFFFF TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

4.9 Device Memory Map

4.9.1 Memory Map Diagram

The figurebelowshows thedevicememory map. Figure4-9.Memory Map The Flash memory ismirroredto supportECC logictesting.The base address of the mirroredFlash image is0x2000 0000.

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4.9.2 Memory Map Table

Pleaserefertoand fora blockdiagramsshowingthedevicesinterconnect. Table4-21.Device Memory Map FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME Memories tightlycoupled totheARM Cortex-R4FCPU TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 3MB TCM RAM + RAM CSRAM0 0x0800_0000 0x0BFF_FFFF 64MB 256KBECC Abort FlashmirrorMirroredFlash 0x2000_0000 0x20FF_FFFF 16MB 3MBframe ExternalMemory Accesses EMIF ChipSelect EMIF select2 0x6000_0000 0x63FF_FFFF 64MB 16MB2 (asynchronous) EMIF ChipSelect EMIF select3 0x6400_0000 0x67FF_FFFF 64MB 16MB3 (asynchronous) Access to"Reserved"space will generateAbortEMIF ChipSelect EMIF select4 0x6800_0000 0x6BFF_FFFF 64MB 16MB4 (asynchronous) EMIF ChipSelect EMIF select0 0x8000_0000 0x87FF_FFFF 128MB 128MB0 (synchronous) FlashModule Bus2 Interface Customer OTP, 0xF000_0000 0xF000_FFFF 64KB 16KBTCM FlashBanks Customer OTP, 0xF000_E000 0xF000_FFFF 8KB 4KBEEPROM Bank Customer OTP –ECC, TCM 0xF004_0000 0xF004_1FFF 8KB 2KB FlashBanks Customer OTP –ECC, 0xF004_1C00 0xF004_1FFF 1KB 1KB EEPROM Bank TIOTP, TCM 0xF008_0000 0xF008_FFFF 64KB 16KBFlashBanks Abort TIOTP, EEPROM 0xF008_E000 0xF008_FFFF 8KB 4KBBank TIOTP –ECC, 0xF00C_0000 0xF00C_1FFF 8KB 2KBTCM FlashBanks TIOTP –ECC, 0xF00C_1C00 0xF00C_1FFF 1KB 1KBEEPROM Bank EEPROM 0xF010_0000 0xF013_FFFF 256KB 8KBBank–ECC EEPROM Bank 0xF020_0000 0xF03F_FFFF 2MB 64KB FlashData Space 0xF040_0000 0xF04F_FFFF 1MB 384KBECC Ethernetand EMIF slaveinterfaces CPPI Memory Slave(Ethernet 0xFC52_0000 0xFC52_1FFF 8KB 8KB Abort RAM) CPGMAC Slave 0xFCF7_8000 0xFCF7_87FF 2KB 2KB No error(EthernetSlave) CPGMACSS Wrapper 0xFCF7_8800 0xFCF7_88FF 256B 256B No error(Ethernet Wrapper) EMIF Registers 0xFCFF_E800 0xFCFF_E8FF 256B 256B Abort Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 71 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table4-21.Device Memory Map (continued) FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME CyclicRedundancy Checker (CRC) Module Registers CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accessesabove 0x200 generateabort. PeripheralMemories MIBSPI5 RAM PCS[5] 0xFF0A_0000 0xFF0B_FFFF 128KB 2KB Abortforaccessesabove 2KB MIBSPI3 RAM PCS[6] 0xFF0C_0000 0xFF0D_FFFF 128KB 2KB Abortforaccessesabove 2KB MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128KB 2KB Abortforaccessesabove 2KB Wrap aroundforaccessesto unimplementedaddressoffsetslowerDCAN3 RAM PCS[13] 0xFF1A_0000 0xFF1B_FFFF 128KB 2KB than0x7FF.Abortgeneratedfor accessesbeyond offset0x800. Wrap aroundforaccessesto unimplementedaddressoffsetslowerDCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128KB 2KB than0x7FF.Abortgeneratedfor accessesbeyond offset0x800. Wrap aroundforaccessesto unimplementedaddressoffsetslowerDCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128KB 2KB than0x7FF.Abortgeneratedfor accessesbeyond offset0x800. Wrap aroundforaccessesto unimplementedaddressoffsetslowerMIBADC2 RAM PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128KB 8KB than0x1FFF.Abortgeneratedfor accessesbeyond 0x1FFF. Wrap aroundforaccessesto unimplementedaddressoffsetslowerMIBADC1 RAM PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB 8KB than0x1FFF.Abortgeneratedfor accessesbeyond 0x1FFF. Wrap aroundforaccessesto unimplementedaddressoffsetslowerN2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128KB 16KB than0x3FFF.Abortgeneratedfor accessesbeyond 0x3FFF. Wrap aroundforaccessesto unimplementedaddressoffsetslowerN2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB than0x3FFF.Abortgeneratedfor accessesbeyond 0x3FFF. N2HET2 TU2 PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128KB 1KB AbortRAM N2HET1 TU1 PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB AbortRAM FlexRayTU RAM PCS[40] 0xFF50_0000 0xFF51_FFFF 128KB 1KB Abort Debug Components CoreSightDebug Reads returnzeros,writeshave noCSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KBROM effect Cortex-R4F Reads returnzeros,writeshave noCSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KBDebug effect Reads returnzeros,writeshave noETM-R4 CSCS2 0xFFA0_2000 0xFFA0_2FFF 4KB 4KB effect Reads returnzeros,writeshave noCoreSightTPIU CSCS3 0xFFA0_3000 0xFFA0_3FFF 4KB 4KB effect POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4KB 4KB Abort PeripheralControlRegisters Reads returnzeros,writeshave noFTU PS[23] 0xFFF7_A000 0xFFF7_A1FF 512B 512B effect Reads returnzeros,writeshave noHTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B effect

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table4-21.Device Memory Map (continued) FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME Reads returnzeros,writeshave noHTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B effect Reads returnzeros,writeshave noN2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B effect Reads returnzeros,writeshave noN2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B effect Reads returnzeros,writeshave noGIO PS[16] 0xFFF7_BC00 0xFFF7_BCFF 256B 256B effect Reads returnzeros,writeshave noMIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B effect Reads returnzeros,writeshave noMIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B effect Reads returnzeros,writeshave noFlexRay PS[12]+PS[13] 0xFFF7_C800 0xFFF7_CFFF 2KB 2KB effect Reads returnzeros,writeshave noI2C PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B effect Reads returnzeros,writeshave noDCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B effect Reads returnzeros,writeshave noDCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B effect Reads returnzeros,writeshave noDCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B effect Reads returnzeros,writeshave noLIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B effect Reads returnzeros,writeshave noSCI PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B effect Reads returnzeros,writeshave noMibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B effect Reads returnzeros,writeshave noSPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B effect Reads returnzeros,writeshave noMibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B effect Reads returnzeros,writeshave noSPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B effect Reads returnzeros,writeshave noMibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B effect System Modules ControlRegistersand Memories DMA RAM PPCS0 0xFFF8_0000 0xFFF8_0FFF 4KB 4KB Abort Wrap aroundforaccessesto unimplementedaddressoffsetslowerVIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4KB 1KB than0x3FF.Abortgeneratedfor accessesbeyond 0x3FF. RTP RAM PPCS3 0xFFF8_3000 0xFFF8_3FFF 4KB 4KB Abort FlashModule PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort eFuse Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort Power Management PPSE0 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort Module (PMM) TestController Reads returnzeros,writeshave noPPSE1 0xFFFF_0400 0xFFFF_07FF 1KB 1KB(FMTM) effect Reads returnzeros,writeshave noPCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B effect Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 73 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.9.3 Master/SlaveAccess Privileges

The tablebelowliststheaccesspermissionsforeach bus masteron thedevice.A bus masterisa module thatcan initiatea readora writetransactionon thedevice. Each slavemodule on themain interconnectislistedinthetable.A "Yes"indicatesthatthemodule listed inthe"MASTERS" column can accessthatslavemodule. Table4-22.Master /SlaveAccess Matrix MASTERS ACCESS MODE SLAVES ON MAIN SCR FlashModule Non-CPU CRC EMIF, Ethernet, Peripheral Bus2 Interface: Accesses to SlaveInterfaces Control OTP, ECC, Program Flash Registers,All EEPROM Bank and CPU Data Peripheral RAM Memories, And AllSystem Module Control RegistersAnd Memories CPU READ User/Privilege Yes Yes Yes Yes Yes CPU WRITE User/Privilege No Yes Yes Yes Yes DMA User Yes Yes Yes Yes Yes POM User Yes Yes Yes Yes Yes DMM User Yes Yes Yes Yes Yes DAP Privilege Yes Yes Yes Yes Yes HTU1 Privilege No Yes Yes Yes Yes HTU2 Privilege No Yes Yes Yes Yes FTU User No Yes Yes Yes Yes EMAC User No Yes No Yes No

4.9.3.1 SpecialNotes on Accesses toCertainSlaves

WriteaccessestothePower Domain Management Module (PMM) controlregistersarelimitedtotheCPU (masterid= 1).The othermasterscan onlyreadfromtheseregisters. A debuggercan alsowritetothePMM registers.The master-idcheckisdisabledindebug mode. The devicecontainsdedicatedlogictogeneratea bus errorresponseon any accesstoa module thatisin a power domain thathas been turnedOFF. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 75 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.9.4 POM OverlayConsiderations

The POM overlaycan map onto up to 8MB of the internalor externalmemory space.The starting addressand thesizeofthememory overlayare configurableviathePOM module controlregisters. Care must be takentoensurethattheoverlayismapped on toavailablememory.
ECC must be disabledby softwareviaCP15 incase POM overlayisenabled;otherwiseECC errors willbe generated.
POM overlaymust notbe enabledwhen theflashand internalRAM memories are swapped viathe MEM SWAP fieldoftheBus MatrixModule ControlRegister1 (BMMCR1).
When POM isused to overlaythe flashon to internalor externalRAM, thereisa bus contention possibilitywhen anothermasteraccessestheTCM flash.Thisresultsina systemhang. – The POM module implementsa timeoutfeaturetodetectthisexactscenario.The timeoutneeds to be enabledwhenever POM overlayisenabled. – The timeoutcan be enabledby writing1010 totheEnableTimeOut (ETO) fieldofthePOM Global Controlregister(POMGLBCTRL, address= 0xFFA04000). – Incase a readrequestby thePOM cannotbe completedwithin32 HCLK cycles,thetimeout(TO) flagis set in the POM Flag register(POMFLG, address = 0xFFA0400C). Also,an abortis generatedtotheCPU. Thiscan be a prefetchabortforan instructionfetchor a dataabortfora datafetch. – The prefetch-and data-aborthandlersmust be modifiedtocheck iftheTO flaginthePOM module isset.Ifso, then the applicationcan assume thatthe timeoutiscaused by a bus contention between thePOM transactionand anothermasteraccessingthesame memory region.The abort handlersneed tocleartheTO flag,so thatany furtherabortsarenotmisinterpretedas havingbeen caused due toa timeoutfromthePOM.

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4.10 FlashMemory

4.10.1 FlashMemory Configuration

Flash Bank: A separateblockof logicconsistingof 1 to 16 sectors.Each flashbank normallyhas a customer-OTP and a TI-OTP area.These flashsectorsshare input/outputbuffers,data paths,sense amplifiers,and controllogic. Flash Sector:A contiguousregionofflashmemory whichmust be erasedsimultaneouslydue tophysical constructionconstraints. Flash Pump: A charge pump which generatesallthe voltagesrequiredforreading,programming,or erasingtheflashbanks. FlashModule: Interfacecircuitryrequiredbetween thehostCPU and theflashbanks and pump module. Table4-23.FlashMemory Banks and Sectors Memory Arrays(orBanks)(1) Sector Segment Low Address High Address No. BANK0 (1.5MBytes) 0 32K Bytes 0x0000_0000 0x0000_7FFF 1 32K Bytes 0x0000_8000 0x0000_FFFF 2 32K Bytes 0x0001_0000 0x0001_7FFF 3 32K Bytes 0x0001_8000 0x0001_FFFF 4 128K Bytes 0x0002_0000 0x0003_FFFF 5 128K Bytes 0x0004_0000 0x0005_FFFF 6 128K Bytes 0x0006_0000 0x0007_FFFF 7 128K Bytes 0x0008_0000 0x0009_FFFF 8 128K Bytes 0x000A_0000 0x000B_FFFF 9 128K Bytes 0x000C_0000 0x000D_FFFF 10 128K Bytes 0x000E_0000 0x000F_FFFF 11 128K Bytes 0x0010_0000 0x0011_FFFF 12 128K Bytes 0x0012_0000 0x0013_FFFF 13 128K Bytes 0x0014_0000 0x0015_FFFF 14 128K Bytes 0x0016_0000 0x0017_FFFF BANK1 (1.5MBytes) 0 128K Bytes 0x0018_0000 0x0019_FFFF 1 128K Bytes 0x001A_0000 0x001B_FFFF 2 128K Bytes 0x001C_0000 0x001D_FFFF 3 128K Bytes 0x001E_0000 0x001F_FFFF 4 128K Bytes 0x0020_0000 0x0021_FFFF 5 128K Bytes 0x0022_0000 0x0023_FFFF 6 128K Bytes 0x0024_0000 0x0025_FFFF 7 128K Bytes 0x0026_0000 0x0027_FFFF 8 128K Bytes 0x0028_0000 0x0029_FFFF 9 128K Bytes 0x002A_0000 0x002B_FFFF 10 128K Bytes 0x002C_0000 0x002D_FFFF 11 128K Bytes 0x002E_0000 0x002F_FFFF BANK7 (64kBytes)forEEPROM emulation(2)(3) 0 16K Bytes 0xF020_0000 0xF020_3FFF 1 16K Bytes 0xF020_4000 0xF020_7FFF 2 16K Bytes 0xF020_8000 0xF020_BFFF 3 16K Bytes 0xF020_C000 0xF020_FFFF (1) The Flashbanks are144-bitwidebank withECC support. (2) The flashbank7 can be programmed whileexecutingcode fromflashbank0 orbank1. (3) Code executionisnotallowedfromflashbank7. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 77 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.10.2 Main FeaturesofFlashModule

Supportformultipleflashbanks forprogramand/ordatastorage
Simultaneousreadaccesson a bank whileperformingprogramoreraseoperationon any otherbank
Integratedstatemachinestoautomateflasheraseand programoperations
Softwareinterfaceforflashprogramand eraseoperations
Pipelinedmode operationtoimproveinstructionaccessinterfacebandwidth
SupportforSingleErrorCorrectionDoubleErrorDetection(SECDED) blockinsideCortex-R4FCPU – Erroraddressiscapturedforhostsystemdebugging
Supportfora richsetofdiagnosticfeatures

4.10.3 ECC ProtectionforFlashAccesses

Allaccessestotheprogramflashmemory areprotectedby SingleErrorCorrectionDoubleErrorDetection (SECDED) logicembedded insidetheCPU. The flashmodule provides8 bitsofECC code for64 bitsof instructionsordatafetchedfromtheflashmemory. The CPU calculatestheexpectedECC code based on the64 bitsreceivedand compares itwiththeECC code returnedby theflashmodule.A signle-biterroris correctedand flaggedby theCPU, whilea multi-biterrorisonlyflagged.The CPU signalsan ECC error viaitsEventbus.Thissignalingmechanism isnotenabledby defaultand must be enabledby settingthe "X"bitofthePerformanceMonitorControlRegister,c9. MRCp15,#0,r1,c9,c12,#0;EnablingEventmonitorstates ORRr1,r1,#0x00000010 MCRp15,#0,r1,c9,c12,#0;Set4thbit(‘X’)ofPMNCregister MRCp15,#0,r1,c9,c12,#0 The applicationmust alsoexplicitlyenablethe CPU's ECC checkingforaccesses on the CPU's ATCM and BTCM interfaces.These are connected to the program flashand data RAM respectively.ECC checkingfortheseinterfacescan be done by settingtheB1TCMPCEN, B0TCMPCEN and ATCMPCEN bitsoftheSystem Controlcoprocessor'sAuxiliaryControlRegister,c1. MRCp15,#0,r1,c1,c0,#1 ORRr1,r1,#0x0e000000;EnableECCcheckingforATCMandBTCMs DMB MCRp15,#0,r1,c1,c0,#1

4.10.4 FlashAccess Speeds

Forinformationon flashmemory accessspeeds and therelevantwaitstatesrequired,refertoSection3.4.

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4.10.5 FlashProgram and Erase Timings

Table4-24.Timing SpecificationsforFlash Parameter MIN NOM MAX Unit tprog (144bit) Wide Word (144bit)programmingtime 40 tbd µs tprog (Total) 3MByte programmingtime(1) -40°C to125°C tbd s 0°C to60°C, forfirst 8 tbd s 25 cycles tprog (Total) EEPROM Emulation64kByteprogramming -40°C to12°5C tbd ms time(1) 0°C to60°C, forfirst 165 tbd ms 25 cycles terase(sector) Sectorerasetime -40°C to125°C tbd ms 0°C to60°C, forfirst 30 tbd ms 25 cycles terase(bank) Bank erasetime(2) FlashBank 0 300 tbd ms terase(bank) Bank erasetime(2) FlashBank 1 240 tbd ms terase(bank) EEPROM EmulationBank erasetime(2) FlashBank 7 80 tbd ms twec Write/erasecycles FlashBank 0 1000 cycles FlashBank 1 twec Write/erasecycles FlashBank 7 100000 cycles (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoes notincludedatatransfertime. (2) Nominalconditionsfortheabove specificationsmean thefirst25 program/erasecyclesatan ambienttemperaturebetween 0c to60c Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 79 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW EVEN Address TCM□BUS ODD Address TCM□BUS 64□Bit□data□bus 64□Bit□data□bus Upper□32□bits data□& 4□ECC□bits Lower32□bits data□& 4□ECC□bits 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM Upper□32□bits data□& 4□ECC□bits Lower32□bits data□& 4□ECC□bits 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM TCRAM Interface□1 PMT I/FVBUSP I/F Cortex□R4F™ TCM TCM A TCM TCRAM Interface□2 PMT I/FVBUSP I/F TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

4.11 Tightly-CoupledRAM InterfaceModule

Figure4-10illustratestheconnectionoftheTightlyCoupledRAM (TCRAM) totheCortex-R4F™ CPU. Figure4-10.TCRAM Block Diagram

4.11.1 Features

The featuresoftheTightlyCoupledRAM (TCRAM) Module are:

Actsas slavetotheCortex-R4FCPU's BTCM interface
SupportsCPU's internalECC scheme by providing64-bitdataand 8-bitECC code
MonitorsCPU EventBus and generatessingleormulti-biterrorinterrupts
Storesaddressesforsingleand multi-biterrors
SupportsRAM tracemodule
ProvidesCPU addressbus integritycheckingby supportingparitycheckingon theaddressbus
PerformsredundantaddressdecodingfortheRAM bank chipselectand ECC selectgenerationlogic
Providesenhanced safetyforthe RAM addressingby implementingtwo 36-bitwide byte-interleaved RAM banks and generatingindependentRAM accesscontrolsignalstothetwo banks
Supportsauto-initializationoftheRAM banks alongwiththeECC bits
No supportforbit-wiseRAM accesses

4.11.2 TCRAMW ECC Support

The TCRAMW passes on theECC code foreach datareadby theCortex-R4FCPU fromtheRAM. Italso storesthe CPU's ECC portcontentsin the ECC RAM when the CPU does a writeto the RAM. The TCRAMW monitorsthe CPU's eventbus and providesregistersforindicatingsingle/multi-biterrorsand alsoforidentifyingtheaddressthatcaused thesingleormulti-biterror.The eventsignalingand theECC checkingfortheRAM accessesmust be enabledinsidetheCPU. Formore informationsee theTMS570LS31X/21X TechnicalReferenceManual (SPNU499).

4.12 ParityProtectionforAccesses toperipheralRAMs

Accesses to allperipheralRAMs are protectedby odd/evenparitychecking.Duringa read access the parityiscalculatedbased on thedataread from theperipheralRAM and compared withthegood parity valuestoredintheparityRAM forthatperipheral.Ifany word failstheparitycheck,themodule generates a parityerrorsignalthatis mapped to the ErrorSignalingModule. The module also capturesthe peripheralRAM addressthatcaused theparityerror.

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 The parityprotectionforperipheralRAMs is not enabled by defaultand must be enabled by the application.Each individualperipheralcontainscontrolregistersto enable the parityprotectionfor accessestoitsRAM. NOTE The CPU read access getstheactualdatafrom theperipheral.The applicationcan choose togeneratean interruptwhenever a peripheralRAM parityerrorisdetected. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 81 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.13 On-Chip SRAM Initializationand Testing

4.13.1 On-Chip SRAM Self-TestUsing PBIST

4.13.1.1Features

Extensiveinstructionsettosupportvariousmemory testalgorithms
ROM-based algorithmsallowapplicationtorunTIproduction-levelmemory tests
Independenttestingofallon-chipSRAM 4.13.1.2PBIST RAM Groups Table4-25.PBIST RAM Grouping TestPattern(Algorithm) March 13N (1) March 13N (1) tripleread tripleread two port singleportMemory RAM Group TestClock MEM Type slow read fastread (cycles) (cycles) ALGO MASK ALGO MASK ALGO MASK ALGO MASK 0x1 0x2 0x4 0x8 PBIST_ROM 1 ROM CLK ROM X X STC_ROM 2 ROM CLK ROM X X DCAN1 3 VCLK DualPort 25200 DCAN2 4 VCLK DualPort 25200 DCAN3 5 VCLK DualPort 25200 ESRAM1 6 HCLK SinglePort 266280 MIBSPI1 7 VCLK DualPort 33440 MIBSPI3 8 VCLK DualPort 33440 MIBSPI5 9 VCLK DualPort 33440 VIM 10 VCLK DualPort 12560 MIBADC1 11 VCLK DualPort 4200 DMA 12 HCLK DualPort 18960 N2HET1 13 VCLK DualPort 31680 HET TU1 14 VCLK DualPort 6480 RTP 15 HCLK DualPort 37800

16 VCLK DualPort 75400

17 SinglePort 133160

MIBADC2 18 VCLK DualPort 4200 N2HET2 19 VCLK DualPort 31680 HET TU2 20 VCLK DualPort 6480 ESRAM5 21 HCLK SinglePort 266280 ESRAM6 22 HCLK SinglePort 266280 23 8700 DualPort ETHERNET 24 VCLK3 6360

25 SinglePort 133160

ESRAM8 28 HCLK SinglePort 266280 (1) Thereareseveralmemory testingalgorithmsstoredinthePBIST ROM. However,TIrecommends theMarch13N algorithmfor applicationtesting. The PBIST ROM clockfrequencyislimitedto90MHz, if90MHz < HCLK <= HCLKmax, orHCLK, ifHCLK <= 90MHz. The PBIST ROM clockisdivideddown fromHCLK. The dividerisselectedby programmingtheROM_DIV fieldoftheMemory Self-TestGlobalControlRegister(MSTGCR) ataddress0xFFFFFF58.

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4.13.2 On-Chip SRAM Auto Initialization

This microcontrollerallowssome of the on-chipmemories to be initializedviathe Memory Hardware Initializationmechanism in the System module. This hardware mechanism allowsan applicationto program thememory arrayswitherrordetectioncapabilitytoa known statebased on theirerrordetection scheme (odd/evenparityorECC). The MINITGCR registerenablesthe memory initializationsequence,and the MSINENA registerselects thememories thataretobe initialized. For more informationon these registerssee the TMS570LS31X/21X TechnicalReference Manual (SPNU499). The mapping ofthedifferenton-chipmemories tothespecificbitsoftheMSINENA registersisshown in Table4-26. Table4-26.Memory Initialization ADDRESS RANGE CONNECTING MODULE MSINENA REGISTER BIT # BASE ADDRESS ENDING ADDRESS RAM (PD#1) 0x08000000 0x0800FFFF 0(1) RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0(1) RAM (RAM_PD#2) 0x08020000 0x0802FFFF 0(1) RAM (RAM_PD#3) 0x08030000 0x0803FFFF 0(1) MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12(2) MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11(2) MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(2) DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 FlexRayRAM RAM isnotCPU-Addressable n/a(3) MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8 N2HET2 RAM 0xFF440000 0xFF57FFFF 15 N2HET1 RAM 0xFF460000 0xFF47FFFF 3 HET TU2 RAM 0xFF4C0000 0xFF4DFFFF 16 HET TU1 RAM 0xFF4E0000 0xFF4FFFFF 4 DMA RAM 0xFFF80000 0xFFF80FFF 1 VIM RAM 0xFFF82000 0xFFF82FFF 2 RTP RAM 0xFFF83000 0xFFF83FFF n/a FlexRayTU RAM 0xFF500000 0xFF51FFFF 13 EthernetRAM (CPPI Memory 0xFC520000 0xFC521FFF n/aSlave) (1) The TCM RAM wrapperhas separatecontrolbitstoselecttheRAM power domain thatistobe auto-initialized. (2) The MibSPIxmodules performan initializationofthetransmitand receiveRAMs as soon as themulti-bufferedmode isenabled.Thisis independentofwhethertheapplicationchoosestoinitializetheMibSPIxRAMs usingthesystemmodule auto-initializationmethod. (3) Reservedonly.The FlexRayRAM has itsown initializationmechanism. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 83 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_nOE EMIF_DA T A[15:0] EMIF_nWE EMIF_nDQM[1:0] 3029 TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

4.14 ExternalMemory Interface(EMIF)

4.14.1 Features

The EMIF includesmany featuresto enhance the ease and flexibilityof connectingto external asynchronousmemories orSDRAM devices.The EMIF featuresincludessupportfor:

3 addressablechipselectforasynchronousmemories ofup to16MB each
1 addressablechipselectspace forSDRAMs up to128MB
8 or16-bitdatabus width
Programmable cycletimingssuch as setup,strobe,and holdtimesas wellas turnaroundtime
Selectstrobemode
ExtendedWaitmode
Data bus parking

4.14.2 Electricaland Timing Specifications

4.14.2.1Read Timing (Asynchronous RAM) Figure4-11.Asynchronous Memory Read Timing

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PRODUCT□PREVIEW EMIF_nCS[3:2] 1 1 Asserted Deasserted EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_DA T A[15:0] EMIF_nOE EMIF_WAIT SETUP Extended Due to EMIF_WAIT STROBE HOLD STROBE EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_nWE EMIF_DAT A[15:0] EMIF_nOE EMIF_nDQM[1:0] TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Figure4-12.EMIFnWAIT Read Timing Requirements 4.14.2.2WriteTiming (Asynchronous RAM) Figure4-13.Asynchronous Memory WriteTiming Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 85 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW EMIF_nCS[3:2] Asserted EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_DA T A[15:0] EMIF_nWE EMIF_WAIT SETUP Extended Due to EMIF_WAIT Deasserted STROBE STROBE HOLD EMIF_CLK EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_DAT A[15:0] 2 2 1 1 17 18

2 EM_CLK Delay

EMIF_nCS[0] EMIF_nDQM[1:0] EMIF_nRAS EMIF_nCAS EMIF_nWE TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Figure4-14.EMIFnWAIT WriteTiming Requirements 4.14.2.3Read Timing (Synchronous RAM) Figure4-15.Basic SDRAM Read Operation

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PRODUCT□PREVIEW EMIF_CLK EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_DA T A[15:0] 2 2 1 1 BASIC SDRAM WRITE OPERA TION EMIF_CS[0] EMIF_DQM[1:0] EMIF_nRAS EMIF_nCAS EMIF_nWE TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 4.14.2.4WriteTiming (Synchronous RAM) Figure4-16.Basic SDRAM WriteOperation 4.14.2.5EMIF Asynchronous Memory Timing Table4-27.EMIF Asynchronous Memory Timing Requirements NO. Value Unit MIN NOM MAX Reads and Writes 2 tw(EM_WAIT) Pulseduration,EMIFnWAIT 2E ns assertionand deassertion Reads 12 tsu(EMDV-EMOEH) Setuptime,EMIFDATA[15:0] 3 ns validbeforeEMIFnOE high 13 th(EMOEH-EMDIV) Holdtime,EMIFDATA[15:0] 0.5 ns validafterEMIFnOE high 14 tsu(EMOEL-EMWAIT) SetupTime,EMIFnWAIT 4E+3 ns assertedbeforeend ofStrobe Phase (1) Writes 28 tsu(EMWEL-EMWAIT) SetupTime,EMIFnWAIT 4E+3 ns assertedbeforeend ofStrobe Phase(1) (1) Setupbeforeend ofSTROBE phase (ifno extendedwaitstatesareinserted)by whichEMIFnWAIT must be assertedtoadd extended waitstates.FigureFigure4-12and FigureFigure4-14describeEMIF transactionsthatincludeextendedwaitstatesinsertedduringthe STROBE phase.However,cyclesinsertedas partofthisextendedwaitperiodshouldnotbe counted;the4E requirementistothestart ofwhere theHOLD phase wouldbeginiftherewere no extendedwaitcycles. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 87 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table4-28.EMIF Asynchronous Memory SwitchingCharacteristics(1)(2)(3) NO Parameter Value Unit MIN NOM MAX Reads and Writes 1 td(TURNAROUND) Turnaroundtime (TA)*E-3 (TA)*E (TA)*E+ 3 ns Reads 3 tc(EMRCYCLE) EMIF readcycletime(EW = 0) (RS+RST+RH)* (RS+RST+RH)* (RS+RST+RH)* ns E -3 E E + 3 EMIF readcycletime(EW = 1) (RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+( ns EWC*16))*E -3 EWC*16))*E EWC*16))*E + 4 tsu(EMCEL-EMOEL) Outputsetuptime, (RS)*E-3 (RS)*E (RS)*E+3 ns EMIFnCS[4:2]lowtoEMIFnOE low(SS = 0) Outputsetuptime, -3 0 +3 ns EMIFnCS[4:2]lowtoEMIFnOE low(SS = 1) 5 th(EMOEH-EMCEH) Outputholdtime,EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+ 3 ns toEMIFnCS[4:2]high(SS = 0) Outputholdtime,EMIFnOE high -3 0 +3 ns toEMIFnCS[4:2]high(SS = 1) 6 tsu(EMBAV-EMOEL) Outputsetuptime,EMIFBA[1:0] (RS)*E-3 (RS)*E (RS)*E+3 ns validtoEMIFnOE low 7 th(EMOEH-EMBAIV) Outputholdtime,EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+3 ns toEMIFBA[1:0]invalid 8 tsu(EMBAV-EMOEL) Outputsetuptime, (RS)*E-3 (RS)*E (RS)*E+3 ns EMIFADDR[21:0] validto EMIFnOE low 9 th(EMOEH-EMAIV) Outputholdtime,EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+3 ns toEMIFADDR[21:0] invalid 10 tw(EMOEL) EMIFnOE activelowwidth(EW (RST)*E-3 (RST)*E (RST)*E+3 ns = 0) EMIFnOE activelowwidth(EW (RST+(EWC*16 (RST+(EWC*16 (RST+(EWC*16 ns 11 td(EMWAITH-EMOEH) DelaytimefromEMIFnWAIT 3E-3 4E 4E+3 ns deassertedtoEMIFnOE high Writes 15 tc(EMWCYCLE) EMIF writecycletime(EW = 0) (WS+WST+WH (WS+WST+WH (WS+WST+WH ns )*E-3 )*E )*E+3 EMIF writecycletime(EW = 1) (WS+WST+WH (WS+WST+WH (WS+WST+WH ns +(EWC*16))*E +(E WC*16))*E +(EWC*16))*E -3 + 3 16 tsu(EMCEL-EMWEL) Outputsetuptime, (WS)*E -3 (WS)*E (WS)*E + 3 ns EMIFnCS[4:2]lowtoEMIFnWE low(SS = 0) Outputsetuptime, -3 0 +3 ns EMIFnCS[4:2]lowtoEMIFnWE low(SS = 1) 17 th(EMWEH-EMCEH) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFnCS[4:2]high(SS = (1) TA = Turnaround,RS = Read setup,RST = Read strobe,RH = Read hold,WS = Writesetup,WST = Writestrobe,WH = Writehold, MEWC = Maximum externalwaitcycles.These parametersareprogrammed viatheAsynchronousBank and AsynchronousWaitCycle ConfigurationRegisters.These supportthefollowingrangesofvalues:TA[4–1],RS[16–1],RST[64–1],RH[8–1],WS[16 –1],WST[64 –1], WH[8 –1],and MEWC[1 –256].See theEMIF User’s guideformore information. (2) E = EMIF_CLK periodinns. (3) EWC = externalwaitcyclesdeterminedby EMIFnWAIT inputsignal.EWC supportsthefollowingrangeofvalues.EWC[256 –1].Note thatthemaximum waittimebeforetimeoutisspecifiedby bitfieldMEWC intheAsynchronousWaitCycleConfigurationRegister.See theEMIF User’s Guide formore information.

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table4-28.EMIF Asynchronous Memory SwitchingCharacteristics(1)(2)(3)(continued) NO Parameter Value Unit MIN NOM MAX Outputholdtime,EMIFnWE -3 0 +3 ns hightoEMIFCS[4:2]high(SS = 18 tsu(EMDQMV-EMWEL) Outputsetuptime,EMIFBA[1:0] (WS)*E-3 (WS)*E (WS)*E+3 ns validtoEMIFnWE low 19 th(EMWEH-EMDQMIV) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFBA[1:0]invalid 20 tsu(EMBAV-EMWEL) Outputsetuptime,EMIFBA[1:0] (WS)*E-3 (WS)*E (WS)*E+3 ns validtoEMIFnWE low 21 th(EMWEH-EMBAIV) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFBA[1:0]invalid 22 tsu(EMAV-EMWEL) Outputsetuptime, (WS)*E-3 (WS)*E (WS)*E+3 ns EMIFADDR[21:0] validto EMIFnWE low 23 th(EMWEH-EMAIV) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFADDR[21:0] invalid 24 tw(EMWEL) EMIFnWE activelowwidth(EW (WST)*E-3 (WST)*E (WST)*E+3 ns = 0) EMIFnWE activelowwidth(EW (WST+(EWC*1 (WST+(EWC*1 (WST+(EWC*1 ns 25 td(EMWAITH-EMWEH) DelaytimefromEMIFnWAIT 3E-3 4E 4E+3 ns deassertedtoEMIFnWE high 26 tsu(EMDV-EMWEL) Outputsetuptime, (WS)*E-3 (WS)*E (WS)*E+3 ns EMIFDATA[15:0]validto EMIFnWE low 27 th(EMWEH-EMDIV) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFDATA[15:0]invalid Table4-29.EMIF Synchronous Memory Timing Requirements NO. Parameter MIN MAX Unit 19 tsu(EMIFDV-EM_CLKH) Inputsetuptime,readdatavalidon 1 ns EMIFDATA[15:0]beforeEMIF_CLK rising 20 th(CLKH-DIV) Inputholdtime,readdatavalidon 1.5 ns EMIFDATA[15:0]afterEMIF_CLK rising Table4-30.EMIF Synchronous Memory SwitchingCharacteristics NO. Parameter MIN MAX Unit 1 tc(CLK) Cycletime,EMIF clockEMIF_CLK 15 ns 2 tw(CLK) Pulsewidth,EMIF clockEMIF_CLK 5 ns highorlow 3 td(CLKH-CSV) Delaytime,EMIF_CLK risingto 7 ns EMIFnCS[0] valid 4 toh(CLKH-CSIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnCS[0] invalid 5 td(CLKH-DQMV) Delaytime,EMIF_CLK risingto 7 ns EMIFnDQM[1:0] valid 6 toh(CLKH-DQMIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnDQM[1:0] invalid 7 td(CLKH-AV) Delaytime,EMIF_CLK risingto 7 ns EMIFADDR[21:0] and EMIFBA[1:0] valid Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 89 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table4-30.EMIF Synchronous Memory SwitchingCharacteristics(continued) NO. Parameter MIN MAX Unit 8 toh(CLKH-AIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFADDR[21:0] and EMIFBA[1:0] invalid 9 td(CLKH-DV) Delaytime,EMIF_CLK risingto 7 ns EMIFDATA[15:0]valid 10 toh(CLKH-DIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFDATA[15:0]invalid 11 td(CLKH-RASV) Delaytime,EMIF_CLK risingto 7 ns EMIFnRAS valid 12 toh(CLKH-RASIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnRAS invalid 13 td(CLKH-CASV) Delaytime,EMIF_CLK risingto 7 ns EMIFnCAS valid 14 toh(CLKH-CASIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnCAS invalid 15 td(CLKH-WEV) Delaytime,EMIF_CLK risingto 7 ns EMIFnWE valid 16 toh(CLKH-WEIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnWE invalid 17 tdis(CLKH-DHZ) Delaytime,EMIF_CLK risingto 7 ns EMIFDATA[15:0]tri-stated 18 tena(CLKH-DLZ) Outputholdtime,EMIF_CLK risingto 1 ns EMIFDATA[15:0]driving

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4.15 VectoredInterruptManager

The vectoredinterruptmanager (VIM) provideshardware assistanceforprioritizingand controllingthe many interruptsourcespresenton thisdevice.Interruptsarecaused by eventsoutsideofthenormalflow ofprogram execution.Normally,theseeventsrequirea timelyresponsefrom thecentralprocessingunit (CPU);therefore,when an interruptoccurs,theCPU switchesexecutionfromthenormalprogram flowto an interruptserviceroutine(ISR).

4.15.1 VIM Features

The VIM module has thefollowingfeatures:

Supports96 interruptchannels. – Providesprogrammablepriorityand enableforinterruptrequestlines.
Providesa directhardwaredispatchmechanism forfastestIRQ dispatch.
Providestwo softwaredispatchmechanisms when theCPU VIC portisnotused. – Indexinterrupt – Registervectoredinterrupt
Parityprotectedvectorinterrupttableagainstsofterrors.

4.15.2 InterruptRequest Assignments

Table4-31.InterruptRequest Assignments Modules InterruptSources DefaultVIM Interrupt Channel ESM ESM Highlevelinterrupt(NMI) 0 Reserved Reserved 1 RTI RTI compare interrupt0 2 RTI RTI compare interrupt1 3 RTI RTI compare interrupt2 4 RTI RTI compare interrupt3 5 RTI RTI overflowinterrupt0 6 RTI RTI overflowinterrupt1 7 RTI RTI timebaseinterrupt 8 GIO GIO interruptA 9 N2HET1 N2HET1 level0 interrupt 10 HET TU1 HET TU1 level0 interrupt 11 MIBSPI1 MIBSPI1 level0 interrupt 12 LIN LIN level0 interrupt 13 MIBADC1 MIBADC1 eventgroupinterrupt 14 MIBADC1 MIBADC1 sw group1 interrupt 15 DCAN1 DCAN1 level0 interrupt 16 SPI2 SPI2 level0 interrupt 17 FlexRay FlexRaylevel0 interrupt 18 CRC CRC Interrupt 19 ESM ESM Low levelinterrupt 20 SYSTEM Softwareinterrupt(SSI) 21 CPU PMU Interrupt 22 GIO GIO interruptB 23 N2HET1 N2HET1 level1 interrupt 24 HET TU1 HET TU1 level1 interrupt 25 MIBSPI1 MIBSPI1 level1 interrupt 26 Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 91 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table4-31.InterruptRequest Assignments (continued) Modules InterruptSources DefaultVIM Interrupt Channel LIN LIN level1 interrupt 27 MIBADC1 MIBADC1 sw group2 interrupt 28 DCAN1 DCAN1 level1 interrupt 29 SPI2 SPI2 level1 interrupt 30 MIBADC1 MIBADC1 magnitudecompare interrupt 31 FlexRay FlexRaylevel1 interrupt 32 DMA FTCA interrupt 33 DMA LFSA interrupt 34 DCAN2 DCAN2 level0 interrupt 35 DMM DMM level0 interrupt 36 MIBSPI3 MIBSPI3 level0 interrupt 37 MIBSPI3 MIBSPI3 level1 interrupt 38 DMA HBCA interrupt 39 DMA BTCA interrupt 40 EMIF AEMIFINT3 41 DCAN2 DCAN2 level1 interrupt 42 DMM DMM level1 interrupt 43 DCAN1 DCAN1 IF3interrupt 44 DCAN3 DCAN3 level0 interrupt 45 DCAN2 DCAN2 IF3interrupt 46 FPU FPU interrupt 47 FlexRayTU FlexRayTU TransferStatusinterrupt 48 SPI4 SPI4 level0 interrupt 49 MIBADC2 MibADC2 eventgroupinterrupt 50 MIBADC2 MibADC2 sw group1interrupt 51 FlexRay FlexRayT0C interrupt 52 MIBSPI5 MIBSPI5 level0 interrupt 53 SPI4 SPI4 level1 interrupt 54 DCAN3 DCAN3 level1 interrupt 55 MIBSPI5 MIBSPI5 level1 interrupt 56 MIBADC2 MibADC2 sw group2interrupt 57 FlexRayTU FlexRayTU Errorinterrupt 58 MIBADC2 MibADC2 magnitudecompare interrupt 59 DCAN3 DCAN3 IF3interrupt 60 FMC FSM_DONE interrupt 61 FlexRay FlexRayT1C interrupt 62 N2HET2 N2HET2 level0 interrupt 63 SCI SCI level0 interrupt 64 HET TU2 HET TU2 level0 interrupt 65 I2C I2C level0 interrupt 66 Reserved Reserved 67-72 N2HET2 N2HET2 level1 interrupt 73 SCI SCI level1 interrupt 74 HET TU2 HET TU2 level1 interrupt 75 Ethernet C0_MISC_PULSE 76 Ethernet C0_TX_PULSE 77 Ethernet C0_THRESH_PULSE 78

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table4-31.InterruptRequest Assignments (continued) Modules InterruptSources DefaultVIM Interrupt Channel Ethernet C0_RX_PULSE 79 HWAG1 HWA_INT_REQ_H 80 HWAG2 HWA_INT_REQ_H 81 DCC1 DCC done interrupt 82 DCC2 DCC2 done interrupt 83 Reserved Reserved 84-87 HWAG1 HWA_INT_REQ_L 88 HWAG2 HWA_INT_REQ_L 89 Reserved Reserved 90-95 NOTE Address location0x00000000 in the VIM RAM isreservedforthe phantom interruptISR entry;thereforeonlyrequestchannels0..94can be used and areoffsetby 1 addressinthe VIM RAM. NOTE The EMIF_nWAIT signalhas a pull-upon it.The EMIF module generatesa "WaitRise" interruptwhenever itdetectsa risingedge on the EMIF_nWAIT signal.This interrupt conditionisindicatedas soon as the deviceispowered up. This can be ignoredifthe EMIF_nWAIT signalisnotused intheapplication.IftheEMIF_nWAIT signalisactuallyused intheapplication,thentheexternalslavememory must alwaysdrivetheEMIF_nWAIT signal such thatan interruptisnotcaused due tothedefaultpull-upon thissignal. NOTE The lower-orderinterruptchannelsarehigherprioritychannelsthanthehigher-orderinterrupt channels. NOTE The applicationcan change themapping ofinterruptsourcestotheinterruptchannelsviathe interruptchannelcontrolregisters(CHANCTRLx) insidetheVIM module. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 93 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.16 DMA Controller

The DMA controllerisused totransferdatabetween two locationsinthememory map inthebackground ofCPU operations.Typically,theDMA isused to:

Transferblocksofdatabetween externaland internaldatamemories
Restructureportionsofinternaldatamemory
Continuallyservicea peripheral

4.16.1 DMA Features

CPU independentdatatransfer
One masterport-PortB(64bitswide)thatinterfacestotheTMS570 Memory System.
FIFO buffer(4entriesdeep and each 64bitwide)
ChannelcontrolinformationisstoredinRAM protectedby parity
16 channelswithindividualenable
Channelchainingcapability
32 peripheralDMA requests
Hardware and SoftwareDMA requests
8,16,32 or64-bittransactionssupported
Multipleaddressingmodes forsource/destination(fixed,increment,offset)
Auto-initiation
Power-management mode
Memory Protectionwithfourconfigurablememory regions

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4.16.2 DefaultDMA Request Map

The DMA module on thismicrocontrollerhas 16 channelsand up to 32 hardware DMA requests.The module containsDREQASIx registerswhichareused tomap theDMA requeststotheDMA channels.By default,channel0 ismapped torequest0,channel1 torequest1,and so on. Some DMA requestshave multiplesources,as shown inTable 4-32. The applicationmust ensure that onlyone oftheseDMA requestsourcesisenabledatany time. Table4-32.DMA Request LineConnection Modules DMA Request Sources DMA Request MIBSPI1 MIBSPI11 DMAREQ[0] MIBSPI1 MIBSPI10 DMAREQ[1] SPI2 SPI2 receive DMAREQ[2] SPI2 SPI2 transmit DMAREQ[3] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[2]/MIBSPI3[2]/DCAN2 IF3 DMAREQ[4] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[3]/MIBSPI3[3]/DCAN2 IF2 DMAREQ[5] DCAN1 /MIBSPI5 DCAN1 IF2/MIBSPI5[2] DMAREQ[6] MIBADC1 /MIBSPI5 MIBADC1 event/MIBSPI5[3] DMAREQ[7] MIBSPI1 /MIBSPI3 /DCAN1 MIBSPI1[4]/MIBSPI3[4]/DCAN1 IF1 DMAREQ[8] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[5]/MIBSPI3[5]/DCAN2 IF1 DMAREQ[9] MIBADC1 /I2C /MIBSPI5 MIBADC1 G1 /I2C receive/MIBSPI5[4] DMAREQ[10] MIBADC1 /I2C /MIBSPI5 MIBADC1 G2 /I2C transmit/MIBSPI5[5] DMAREQ[11] RTI /MIBSPI1 /MIBSPI3 RTI DMAREQ0 /MIBSPI1[6]/MIBSPI3[6] DMAREQ[12] RTI /MIBSPI1 /MIBSPI3 RTI DMAREQ1 /MIBSPI1[7]/MIBSPI3[7] DMAREQ[13] MIBSPI3 /MibADC2 /MIBSPI5 MIBSPI31/MibADC2 event/MIBSPI5[6] DMAREQ[14] MIBSPI3 /MIBSPI5 MIBSPI30/MIBSPI5[7] DMAREQ[15] MIBSPI1 /MIBSPI3 /DCAN1 /MibADC2 MIBSPI1[8]/MIBSPI3[8]/DCAN1 IF3/MibADC2 G1 DMAREQ[16] MIBSPI1 /MIBSPI3 /DCAN3 /MibADC2 MIBSPI1[9]/MIBSPI3[9]/DCAN3 IF1/MibADC2 G2 DMAREQ[17] RTI /MIBSPI5 RTI DMAREQ2 /MIBSPI5[8] DMAREQ[18] RTI /MIBSPI5 RTI DMAREQ3 /MIBSPI5[9] DMAREQ[19] N2HET1 /N2HET2 /DCAN3 N2HET1 DMAREQ[4] /N2HET2 DMAREQ[4] /DCAN3 DMAREQ[20] IF2 N2HET1 /N2HET2 /DCAN3 N2HET1 DMAREQ[5] /N2HET2 DMAREQ[5] /DCAN3 DMAREQ[21] IF3 MIBSPI1 /MIBSPI3 /MIBSPI5 MIBSPI1[10]/MIBSPI3[10]/MIBSPI5[10] DMAREQ[22] MIBSPI1 /MIBSPI3 /MIBSPI5 MIBSPI1[11]/MIBSPI3[11]/MIBSPI5[11] DMAREQ[23] N2HET1 /N2HET2 /SPI4 /MIBSPI5 N2HET1 DMAREQ[6] /N2HET2 DMAREQ[6] /SPI4 DMAREQ[24] receive/MIBSPI5[12] N2HET1 /N2HET2 /SPI4 /MIBSPI5 N2HET1 DMAREQ[7] /N2HET2 DMAREQ[7] /SPI4 DMAREQ[25] transmit/MIBSPI5[13] CRC /MIBSPI1 /MIBSPI3 CRC DMAREQ[0] /MIBSPI1[12]/MIBSPI3[12] DMAREQ[26] CRC /MIBSPI1 /MIBSPI3 CRC DMAREQ[1] /MIBSPI1[13]/MIBSPI3[13] DMAREQ[27] LIN /MIBSPI5 LIN receive/MIBSPI5[14] DMAREQ[28] LIN /MIBSPI5 LIN transmit/MIBSPI5[15] DMAREQ[29] MIBSPI1 /MIBSPI3 /SCI /MIBSPI5 MIBSPI1[14]/MIBSPI3[14]/SCI receive/ DMAREQ[30] MIBSPI51 MIBSPI1 /MIBSPI3 /SCI /MIBSPI5 MIBSPI1[15]/MIBSPI3[15]/SCI transmit/ DMAREQ[31] MIBSPI50 (1) SPI1,SPI3,SPI5 receiveinstandardSPI mode (2) SPI1,SPI3,SPI5 transmitinstandardSPI mode Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 95 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW RTICLK External control CAP event□source□0 CAP event□source□1 =Up□counter Capture up□counter Compare up□counter Free□running□counter Capture RTIFRCx free□running□counter RTICAFRCx OVLINTxRTICPUCx RTIUCx RTICAUCx To□Compare UnitNTU0 NTU1 NTU2 NTU3 TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

4.17 Real Time InterruptModule

The real-timeinterrupt(RTI) module providestimer functionalityfor operatingsystems and for benchmarkingcode.The RTI module can incorporateseveralcountersthatdefinethetimebasesneeded forschedulingan operatingsystem. The timersalsoallowyou tobenchmark certainareasofcode by readingthevaluesofthecountersatthe beginningand theend ofthedesiredcode rangeand calculatingthedifferencebetween thevalues. In additionthe RTI providesa mechanism to synchronizethe operatingsystem to the FlexRay communicationcycle.Clocksupervisioncan detectissueson theFlexRaybus withan automaticswitchto an internallygeneratedtimebase.

4.17.1 Features

The RTI module has thefollowingfeatures:

Two independent64 bitcounterblocks
Four configurablecompares forgeneratingoperatingsystem ticksor DMA requests.Each eventcan be drivenby eithercounterblock0 orcounterblock1.
One counter block usable for applicationsynchronizationto FlexRay network includingclock supervision
Fastenabling/disablingofevents
Two time-stamp(capture)functionsforsystemorperipheralinterrupts,one foreach counterblock

4.17.2 Block Diagrams

Figure4-17 shows a high-levelblockdiagram forone of the two 64-bitcounterblocksinsidethe RTI module. Both the counterblocksare identicalexceptthe Network Time Unit(NTUx) inputsare only availableas timebase inputsforthecounterblock0. Figure4-17.Counter Block Diagram

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PRODUCT□PREVIEW 31 0 Compare control INTy DMAREQyCompare Update compare From counter block 0 From counter block 1 RTIUDCPy RTICOMPy 31 0 TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Figure4-18.Compare Block Diagram

4.17.3 Clock Source Options

The RTI module uses theRTI1CLK clockdomain forgeneratingtheRTI timebases. The applicationcan selecttheclocksourcefortheRTI1CLK by configuringtheRCLKSRC registerinthe System module ataddress0xFFFFFF50. The defaultsourceforRTI1CLK isVCLK. Formore informationon clocksourcesrefertoTable4-8and Table4-13.

4.17.4 Network Time SynchronizationInputs

The RTI module supports4 NetworkTime Unit(NTU) inputsthatsignalinternalsystem events,and which can be used tosynchronizethetimebase used by theRTI module.On thisdevice,theseNTU inputsare connectedas shown below. Table4-33.Network Time SynchronizationInputs NTU Input Source

0 Macrotick

1 StartofCycle

2 PLL2 Clockoutput

3 EXTCLKIN1 clockinput

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4.18 ErrorSignalingModule

The ErrorSignalingModule (ESM) manages thevariouserrorconditionson theTMS570 microcontroller. The errorconditionishandledbased on a fixedseveritylevelassignedtoit.Any severeerrorcondition can be configuredtodrivea low levelon a dedicateddeviceterminalcallednERROR. Thiscan be used as an indicatortoan externalmonitorcircuittoputthesystemintoa safestate.

4.18.1 Features

The featuresoftheErrorSignalingModule are:

128 interrupt/errorchannelsaresupported,dividedinto3 differentgroups – 64 channelswithmaskableinterruptand configurableerrorpinbehavior – 32 errorchannelswithnon-maskableinterruptand predefinederrorpinbehavior – 32 channelswithpredefinederrorpinbehavioronly
Errorpintosignalseveredevicefailure
Configurabletimebaseforerrorsignal
Errorforcingcapability

4.18.2 ESM Channel Assignments

The ErrorSignalingModule (ESM) integratesallthedeviceerrorconditionsand groupsthem intheorder ofseverity.Group1 isused forerrorsofthelowestseveritywhileGroup3 isused forerrorsofthehighest severity.The deviceresponse to each erroris determinedby the severitygroup itis connected to. Table4-35shows thechannelassignmentforeach group. Table4-34.ESM Groups ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR PIN Group1 maskable,loworhighpriority configurable Group2 non-maskable,highpriority fixed Group3 no interruptgenerated fixed Table4-35.ESM Channel Assignments ERROR SOURCES GROUP CHANNELS Reserved Group1 0 MibADC2 -parity Group1 1 DMA -MPU Group1 2 DMA -parity Group1 3 Reserved Group1 4 DMA -imprecisereaderror Group1 5 FMC -correctableerror:bus1 and bus2 interfaces Group1 6(doesnotincludeaccessestoEEPROM bank) N2HET1/N2HET2 -parity Group1 7 HET TU1/HET TU2 -parity Group1 8 HET TU1/HET TU2 -MPU Group1 9 PLL -Slip Group1 10 ClockMonitor-interrupt Group1 11 FlexRay-parity Group1 12 DMA -imprecisewriteerror Group1 13 FlexRayTU -parity Group1 14 VIM RAM -parity Group1 15 FlexRayTU -MPU Group1 16 MibSPI1 -parity Group1 17

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table4-35.ESM Channel Assignments (continued) ERROR SOURCES GROUP CHANNELS MibSPI3 -parity Group1 18 MibADC1 -parity Group1 19 Reserved Group1 20 DCAN1 -parity Group1 21 DCAN3 -parity Group1 22 DCAN2 -parity Group1 23 MibSPI5 -parity Group1 24 Reserved Group1 25 RAM even bank (B0TCM) -correctableerror Group1 26 CPU -selftest Group1 27 RAM odd bank (B1TCM) -correctableerror Group1 28 Reserved Group1 29 DCC1 -error Group1 30 CCM-R4 -selftest Group1 31 Reserved Group1 32 Reserved Group1 33 Reserved Group1 34 FMC -correctableerror(EEPROM bank access) Group1 35 FMC -uncorrectableerror(EEPROM bank access) Group1 36 IOMM -Mux configurationerror Group1 37 Power domain controllercompare error Group1 38 Power domain controllerself-testerror Group1 39 eFuse ControllerError– thiserrorsignalisgeneratedwhen any bitintheeFuse controllererrorstatusregisterisset.The applicationcan choose togeneratean Group1 40 interruptwhenever thisbitissettoserviceany eFuse controllererrorconditions. eFuse Controller-SelfTestError.Thiserrorsignalisgeneratedonlywhen a self teston theeFuse controllergeneratesan errorcondition.When thiserrorsignalis Group1 41 set,group1 channel40 errorsignalwillalsobe set. PLL2 -Slip Group1 42 EthernetControllermasterinterface Group1 43 Reserved Group1 44 Reserved Group1 45 Reserved Group1 46 Reserved Group1 47 Reserved Group1 48 Reserved Group1 49 Reserved Group1 50 Reserved Group1 51 Reserved Group1 52 Reserved Group1 53 Reserved Group1 54 Reserved Group1 55 Reserved Group1 56 Reserved Group1 57 Reserved Group1 58 Reserved Group1 59 Reserved Group1 60 Reserved Group1 61 Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 99 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table4-35.ESM Channel Assignments (continued) ERROR SOURCES GROUP CHANNELS DCC2 -error Group1 62 Reserved Group1 63 Reserved Group2 0 Reserved Group2 1 CCMR4 -compare Group2 2 Reserved Group2 3 FMC -uncorrectableerror(addressparityon bus1 accesses) Group2 4 Reserved Group2 5 RAM even bank (B0TCM) -uncorrectableerror Group2 6 Reserved Group2 7 RAM odd bank (B1TCM) -uncorrectableerror Group2 8 Reserved Group2 9 RAM even bank (B0TCM) -addressbus parityerror Group2 10 Reserved Group2 11 RAM odd bank (B1TCM) -addressbus parityerror Group2 12 Reserved Group2 13 Reserved Group2 14 Reserved Group2 15 Flash(ATCM) -ECC livelockdetect Group2 16 Reserved Group2 17 Reserved Group2 18 Reserved Group2 19 Reserved Group2 20 Reserved Group2 21 Reserved Group2 22 Reserved Group2 23 RTI_WWD_NMI Group2 24 Reserved Group2 25 Reserved Group2 26 Reserved Group2 27 Reserved Group2 28 Reserved Group2 29 Reserved Group2 30 Reserved Group2 31 Reserved Group3 0 eFuse Controller-autoloaderror Group3 1 Reserved Group3 2 RAM even bank (B0TCM) -ECC uncorrectableerror Group3 3 Reserved Group3 4 RAM odd bank (B1TCM) -ECC uncorrectableerror Group3 5 Reserved Group3 6 FMC -uncorrectableerror:bus1 and bus2 interfaces Group3 7(doesnotincludeaddressparityerrorand errorson accessestoEEPROM bank) Reserved Group3 8 Reserved Group3 9 Reserved Group3 10 Reserved Group3 11

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table4-35.ESM Channel Assignments (continued) ERROR SOURCES GROUP CHANNELS Reserved Group3 12 Reserved Group3 13 Reserved Group3 14 Reserved Group3 15 Reserved Group3 16 Reserved Group3 17 Reserved Group3 18 Reserved Group3 19 Reserved Group3 20 Reserved Group3 21 Reserved Group3 22 Reserved Group3 23 Reserved Group3 24 Reserved Group3 25 Reserved Group3 26 Reserved Group3 27 Reserved Group3 28 Reserved Group3 29 Reserved Group3 30 Reserved Group3 31 Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 101 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.19 Reset /Abort /ErrorSources

Table4-36.Reset/Abort/ErrorSources ESM HOOKUPERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel CPU TRANSACTIONS Precisewriteerror(NCNB/StronglyOrdered) User/Privilege PreciseAbort(CPU) n/a Precisereaderror(NCB/DeviceorNormal) User/Privilege PreciseAbort(CPU) n/a Imprecisewriteerror(NCB/DeviceorNormal) User/Privilege ImpreciseAbort(CPU) n/a UndefinedInstructionTrapIllegalinstruction User/Privilege n/a(CPU)(1) MPU accessviolation User/Privilege Abort(CPU) n/a SRAM B0 TCM (even)ECC singleerror(correctable) User/Privilege ESM 1.26 Abort(CPU),ESM =>B0 TCM (even)ECC doubleerror(non-correctable) User/Privilege 3.3nERROR B0 TCM (even)uncorrectableerror(i.e.redundantaddress User/Privilege ESM => NMI 2.6decode) B0 TCM (even)addressbus parityerror User/Privilege ESM => NMI 2.10 B1 TCM (odd)ECC singleerror(correctable) User/Privilege ESM 1.28 Abort(CPU),ESM =>B1 TCM (odd)ECC doubleerror(non-correctable) User/Privilege 3.5nERROR B1 TCM (odd)uncorrectableerror(i.e.redundantaddress User/Privilege ESM => NMI 2.8decode) B1 TCM (odd)addressbus parityerror User/Privilege ESM => NMI 2.12 FLASH FMC correctableerror-Bus1 and Bus2 interfaces(doesnot User/Privilege ESM 1.6includeaccessestoEEPROM bank) FMC uncorrectableerror-Bus1 accesses Abort(CPU),ESM =>User/Privilege 3.7(doesnotincludeaddressparityerror) nERROR FMC uncorrectableerror-Bus2 accesses (doesnotincludeaddressparityerrorand EEPROM bank User/Privilege ESM => nERROR 3.7 accesses) FMC uncorrectableerror-addressparityerroron Bus1 User/Privilege ESM => NMI 2.4accesses FMC correctableerror-AccessestoEEPROM bank User/Privilege ESM 1.35 FMC uncorrectableerror-AccessestoEEPROM bank User/Privilege ESM 1.36 DMA TRANSACTIONS Externalimpreciseerroron read(Illegaltransactionwithok User/Privilege ESM 1.5response) Externalimpreciseerroron write(Illegaltransactionwithok User/Privilege ESM 1.13response) Memory accesspermissionviolation User/Privilege ESM 1.2 Memory parityerror User/Privilege ESM 1.3 DMM TRANSACTIONS Externalimpreciseerroron read(Illegaltransactionwithok User/Privilege ESM 1.5response) Externalimpreciseerroron write(Illegaltransactionwithok User/Privilege ESM 1.13response) HET TU 1 (HTU 1) NCNB (StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=> VIM n/a Externalimpreciseerror(Illegaltransactionwithok response) User/Privilege Interrupt=> VIM n/a Memory accesspermissionviolation User/Privilege ESM 1.9 (1) The UndefinedInstructionTRAP isNOT detectableoutsidetheCPU. The trapistakenonlyiftheinstructionreachestheexecutestage oftheCPU.

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table4-36.Reset/Abort/ErrorSources (continued) ESM HOOKUPERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel Memory parityerror User/Privilege ESM 1.8 HET TU2 (HTU2) NCNB (StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=> VIM n/a Externalimpreciseerror(Illegaltransactionwithok response) User/Privilege Interrupt=> VIM n/a Memory accesspermissionviolation User/Privilege ESM 1.9 Memory parityerror User/Privilege ESM 1.8 N2HET 1 Memory parityerror User/Privilege ESM 1.7 N2HET2 Memory parityerror User/Privilege ESM 1.7 FLEXRAY Memory parityerror User/Privilege ESM 1.12 FLEXRAY TU NCNB (StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=> VIM n/a Externalimpreciseerror(Illegaltransactionwithok response) User/Privilege Interrupt=> VIM n/a Memory accesspermissionviolation User/Privilege ESM 1.16 Memory parityerror User/Privilege ESM 1.14 ETHERNET MASTER INTERFACE Any errorreportedby slavebeingaccessed User/Privilege ESM 1.43 MIBSPI MibSPI1 memory parityerror User/Privilege ESM 1.17 MibSPI3 memory parityerror User/Privilege ESM 1.18 MibSPI5 memory parityerror User/Privilege ESM 1.24 MIBADC MibADC 1 Memory parityerror User/Privilege ESM 1.19 MibADC2 Memory parityerror User/Privilege ESM 1.1 DCAN DCAN1 memory parityerror User/Privilege ESM 1.21 DCAN2 memory parityerror User/Privilege ESM 1.23 DCAN3 memory parityerror User/Privilege ESM 1.22 PLL PLL sliperror User/Privilege ESM 1.10 PLL #2 sliperror User/Privilege ESM 1.42 CLOCK MONITOR Clockmonitorinterrupt User/Privilege ESM 1.11 DCC DCC1 error User/Privilege ESM 1.30 DCC2 error User/Privilege ESM 1.62 CCM-R4 Selftestfailure User/Privilege ESM 1.31 Compare failure User/Privilege ESM => NMI 2.2 VIM Memory parityerror User/Privilege ESM 1.15 VOLTAGE MONITOR VMON outofvoltagerange n/a Reset n/a CPU SELFTEST (LBIST) CPU Selftest(LBIST)error User/Privilege ESM 1.27 Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 103 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table4-36.Reset/Abort/ErrorSources (continued) ESM HOOKUPERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel PIN MULTIPLEXING CONTROL Mux configurationerror User/Privilege ESM 1.37 POWER DOMAIN CONTROL PSCON compare error User/Privilege ESM 1.38 PSCON self-testerror User/Privilege ESM 1.39 eFuse Controller eFuse Controllererror User/Privilege ESM 3.1 eFuse Controller-Any bitsetintheerrorstatusregister User/Privilege ESM 1.40 eFuse Controllerself-testerror User/Privilege ESM 1.41 WINDOWED WATCHDOG WWD Non-MaskableInterruptexception n/a ESM 2.24 ERRORS REFLECTED IN THE SYSESR REGISTER Power-Up Reset n/a Reset n/a Oscillatorfail/PLL slip(2) n/a Reset n/a Watchdog exception n/a Reset n/a CPU Reset(drivenby theCPU STC) n/a Reset n/a SoftwareReset n/a Reset n/a ExternalReset n/a Reset n/a (2) Oscillatorfail/PLLslipcan be configuredinthesystemregister(SYS.PLLCTL1) togeneratea reset.

4.20 DigitalWindowed Watchdog

Thisdeviceincludesa digitalwindowed watchdog (DWWD) module thatprotectsagainstrunaway code execution. The DWWD module allowstheapplicationtoconfigurethetimewindow withinwhichtheDWWD module expectstheapplicationtoservicethewatchdog.A watchdogviolationoccursiftheapplicationservicesthe watchdog outsideof thiswindow, or failsto servicethe watchdog at all.The applicationcan choose to generatea systemresetora non-maskableinterrupttotheCPU incase ofa watchdogviolation. The watchdog isdisabledby defaultand must be enabledby theapplication.Once enabled,thewatchdog can onlybe disabledupon a systemreset.

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PRODUCT□PREVIEW TRST TMS TCK TDI TDO RTCK ICEPICK_C Boundary□Scan BSR/BSDL Boundary□Scan□I/F Secondary□Tap□0 DAP Debug APB Debug ROM1 APB□slave Cortex R4F APB□Mux AHB-AP POM ETM TPIU to□SCR1□via A2A from PCR1/Bridge Secondary□Tap□1 DMM RTP TAP 0 TAP 1 Secondary□Tap□2 AJSM TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.21 Debug Subsystem

4.21.1 Block Diagram

The devicecontainsan ICEPICK module toallowJTAG accesstothescan chains. Figure4-19.ZWT Debug Subsystem Block Diagram

4.21.2 Debug Components Memory Map

Table4-37.Debug Components Memory Map FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME CoreSightDebug Reads returnzeros,writeshave noCSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KBROM effect Cortex-R4F Reads returnzeros,writeshave noCSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KBDebug effect Reads returnzeros,writeshave noETM-R4 CSCS2 0xFFA0_2000 0xFFA0_2FFF 4KB 4KB effect Reads returnzeros,writeshave noCoreSightTPIU CSCS3 0xFFA0_3000 0xFFA0_3FFF 4KB 4KB effect Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 105 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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4.21.3 JTAG IdentificationCode

The JTAG ID code forthisdeviceis0x0D8A002F. Thisisthesame as thedeviceICEPickIdentification Code.

4.21.4 Debug ROM

The Debug ROM storesthelocationofthecomponents on theDebug APB bus: Table4-38.Debug ROM table ADDRESS DESCRIPTION VALUE 0x000 pointertoCortex-R4F 0x0000 1003 0x001 ETM-R4 0x0000 2003 0x002 TPIU 0x0000 3003 0x003 POM 0x0000 4003 0x004 end oftable 0x0000 0000

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PRODUCT□PREVIEW 1 1 TMS TDI TDO RTCK TCK TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.21.5 JTAG Scan InterfaceTimings

Table4-39.JTAG Scan InterfaceTiming(1) No. Parameter Min MAX Unit fTCK TCK frequency(atHCLKmax) 12 MHz fRTCK RTCK frequency(atTCKmax and HCLKmax) 10 MHz 1 td(TCK-RTCK) Delaytime,TCK toRTCK 24 ns 2 tsu(TDI/TMS-RTCKr) Setuptime,TDI,TMS beforeRTCK rise(RTCKr) 15 ns 3 th(RTCKr-TDI/TMS) Holdtime,TDI,TMS afterRTCKr 0 ns 4 th(RTCKr-TDO) Holdtime,TDO afterRTCKf 0 ns 5 td(TCKf-TDO) Delaytime,TDO validafterRTCK fall(RTCKf) 10 ns (1) TimingsforTDO arespecifiedfora maximum of50pF loadon TDO Figure4-20.JTAG Timing Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 107 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW H L H L H L L H .□.□. .□.□. 128-bit□comparator H L L H H L L H UNLOCK Flash□Module□Output OTP Contents Unlock□By□Scan Register Internal□Tie-Offs (example□only) (example) L H H L LInternal□Tie-Offs (example□only) L H H TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

4.21.6 Advanced JTAG SecurityModule

Thisdeviceincludesa an Advanced JTAG SecurityModule (AJSM).whichprovidesmaximum securityto thedevice’s memory contentby allowinguserstosecurethedeviceafterprogramming. Figure4-21.AJSM Unlock The deviceisunsecure by defaultby virtueof a 128-bitvisibleunlockcode programmed in the OTP address0xF0000000.The OTP contentsare XOR-ed withthe "UnlockBy Scan" registercontents.The outputsoftheseXOR gatesare againcombined witha setofsecretinternaltie-offs.The outputofthis combinationallogicis compared againsta secrethard-wired128-bitvalue.A match resultsin the UNLOCK signalbeingasserted,so thatthedeviceisnow unsecure. A usercan securethedeviceby changingatleastone bitinthevisibleunlockcode from1 to0.Changing a 0 to1 isnotpossiblesincethevisibleunlockcode isstoredintheOne Time Programmable (OTP) flash region.Also,changingallthe128 bitstozerosisnota validconditionand willpermanentlysecurethe device. Once secured,a user can unsecurethe deviceby scanningan appropriatevalueintothe "UnlockBy Scan" registeroftheAJSM module.The valuetobe scanned issuch thattheXOR oftheOTP contents and theUnlock-By-Scanregistercontentsresultsintheoriginalvisibleunlockcode. The Unlock-By-Scanregisterisresetonlyupon assertingpower-onreset(nPORRST). A securedeviceonlypermitsJTAG accessestotheAJSM scan chainviatheSecondary Tap # 2 ofthe ICEPickmodule.Allothersecondarytaps,testtapsand theboundaryscan interfacearenotaccessiblein thisstate.

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PRODUCT□PREVIEW tr(ETM) th(ETM) tl(ETM) tf(ETM) tcyc(ETM) TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.21.7 Embedded Trace Macrocell(ETM-R4)

The devicecontainsa ETM-R4 module witha 32-bitinternaldataport.The ETM-R4 module isconnected toa TPIU witha 32-bitdatabus;theTPIU providesa 35-bit(32-bitdata,3-bitcontrol)externalinterface fortrace.The ETM-R4 isCoreSightcompliantand followstheETM v3 specification;formore detailssee ARM CoreSightETM-R4 TRM specification. 4.21.7.1ETM TRACECLKIN Selection The ETM clocksource can be selectedas eitherVCLK or the externalETMTRACECLKIN pin.The selectionisdone by theEXTCTRLOUT[1:0] controlbitsoftheTPIU;thedefaultis'00'.The addressofthis registerisTPIU base address+ 0x404. Beforeyou beginaccessingTPIU registers,TPIU shouldbe unlockedviacoresightkey and 1 or2 should be writtentothisregister. Table4-40.TPIU /TRACECLKIN Selection EXTCTRLOUT[1:0] TPIU/TRACECLKIN 00 tied-zero

01 VCLK

10 ETMTRACECLKIN

4.21.7.2Timing Specifications Figure4-22.ETMTRACECLKOUT Timing Table4-41.ETMTRACECLK Timing Parameter MIN Description tcyc(ETM) t(HCLK) *4 Clockperiod tl(ETM) 20ns Low pulsewidth th(ETM) 20ns Highpulsewidth tr(ETM) 3ns Clockand datarisetime tf(ETM) 3ns Clockand datafalltime Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 109 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW tsu(ETM) th(ETM) ETMTRACECLK ETMDA T A tsu(ETM) th(ETM) TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Figure4-23.ETMDATA Timing Table4-42.ETMDATA Timing Parameter MIN Description tsu(ETM) 2.5ns Data setuptime th(ETM) 1.5ns Data holdtime NOTE The ETMTRACECLK and ETMDATA timingis based on a 15pF load and forambient temperaturelowerthan85°C.

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PRODUCT□PREVIEW tcyc(RTP) tr tfth(RTP) tl(RTP) TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.21.8 RAM Trace Port(RTP)

The RTP providesthe abilityto datalogthe RAM contentsof the TMS570 devicesor accesses to peripheralswithoutprogram intrusion.Itcan tracealldata writeor read accesses to internalRAM. In addition,itprovidesthe capabilityto directlytransferdata to a FIFO to supporta CPU-controlled transmissionofthedata.The tracedataistransmittedovera dedicatedexternalinterface. 4.21.8.1Features The RTP offersthefollowingfeatures:

Two modes ofoperation-TraceMode and DirectData Mode – TraceMode
Non-intrusivedatatraceon writeorreadoperation
VisibilityofRAM contentatany timeon externalcapturehardware
Traceofperipheralaccesses
2 configurabletraceregionsforeach RAM module tolimitamount ofdatatobe traced
FIFO tostoredataand addressofdataofmultipleread/writeoperations
TraceofCPU and/orDMA accesseswithindicationofthemasterinthetransmitteddatapacket – DirectData Mode
DirectlywritedatawiththeCPU ortracereadoperationstoa FIFO,withouttransmittingheader and addressinformation
Dedicatedsynchronousinterfacetotransmitdatatoexternaldevices
Free-runningclockgenerationorclockstopmode between transmissions
Up to100 Mbitpersec/pintransferratefortransmittingdata
Pinsnotused infunctionalmode can be used as GIOs 4.21.8.2Timing Specifications Figure4-24.RTPCLK Timing Table4-43.RTPCLK Timing Parameter MIN Description tcyc(RTP) tc(HCLK) *2 Clockperiod,prescaledfromHCLK; must notbe faster thanHCLK /2 th(RTP) ((tcyc(RTP))/2)-((tr+tf)/2) Highpulsewidth tl(RTP) ((tcyc(RTP))/2)-((tr+tf)/2) Low pulsewidth Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 111 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW RTPSYNC RTPCLK RTPDA T A tssu(RTP) tsh(RTP) tdsu(RTP) tdh(RTP) HCLK RTPCLK RTPENA RTPSYNC RTPDATA HCLK RTPCLK RTPENA RTPSYNC RTPDATA tena(RTP)tdis(RTP) HCLK RTPCLK RTPnENA RTPSYNC RTPDA T A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d1 d2 d3 d4 d5 d6 d7 d8 Divide by 1 TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Figure4-25.RTPDATA Timing Table4-44.RTPDATA Timing Parameter MIN Description tdsu(RTP) 3ns Data setuptime tdh(RTP) 2ns Data holdtime tssu(RTP) 3ns SYNC setuptime tsh(RTP) 2ns SYNC holdtime Figure4-26.RTPnENA timing Table4-45.RTPnENA timing Parameter MIN MAX Description tdis(RTP) 3tc(HCLK) + timeRTPnENA must go highbeforewhat wouldbe thenextRTPSYNC, tr(RTPSYNC) + toguaranteedelayingthenextpacket 12ns tena(RTP) 4tc(HCLK) + 5tc(HCLK) + timeafterRTPnENA goes lowbeforea packetthathas been halted, tr(RTPSYNC) tr(RTPSYNC) + resumes 12ns

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PRODUCT□PREVIEW tcyc(DMM) tr tfth(DMM) tl(DMM) DMMSYNC DMMCLK DMMDA T A tssu(DMM) tsh(DMM) tdsu(DMM) tdh(DMM) TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.21.9 Data ModificationModule (DMM)

The Data ModificationModule (DMM) providesthecapabilitytomodifydataintheentire4 GB address space oftheTMS570 devicesfroman externalperipheral,withminimalinterruptionoftheapplication. 4.21.9.1Features The DMM module has thefollowingfeatures:

Actsas a bus master,thusenablingdirectwritestothe4GB addressspace withoutCPU intervention
Writestomemory locationsspecifiedinthereceivedpacket(leveragespacketsdefinedby tracemode oftheRAM traceport(RTP) module
Writesreceiveddata to consecutiveaddresses,which are specifiedby the DMM module (leverages packetsdefinedby directdatamode ofRTP module)
Configurableportwidth(1,2,4,8,16 pins)
Up to100 Mbit/spindatarate
Unused pinsconfigurableas GIO pins 4.21.9.2Timing Specifications Figure4-27.DMMCLK Timing Table4-46.DMMCLK Timing Parameter MIN Description tcyc(DMM) tc(HCLK) *2 Clockperiod th(DMM) ((tcyc(DMM))/2)-((tr+tf)/2) Highpulsewidth tl(DMM) ((tcyc(DMM))/2)-((tr+tf)/2) Low pulsewidth Figure4-28.DMMDATA Timing Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 113 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW HCLK DMMCLK DMMSYNC DMMDA T A DMMnENA D00 D01 D10 D1 1 D20 D21 D30 D31 D40 D41 D50 TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table4-47.DMMDATA Timing Parameter MIN Description tssu(DMM) 2ns SYNC activetoclkfallingedge setuptime tsh(DMM) 3ns clkfallingedge toSYNC deactiveholdtime tdsu(DMM) 2ns DATA toclkfallingedge setuptime tdh(DMM) 3ns clkfallingedge toDATA holdtime Figure4-29.DMMnENA Timing Figure4-29 shows a case with1 DMM packetper 2 DMMCLK cycles(Mode = DirectData Mode, data width= 8,portwidth= 4)where none ofthepacketsreceivedby theDMM aresentout,leadingtofillingup of the internalbuffers.The DMMnENA signalisshown asserted,afterthe firsttwo packetshave been receivedand synchronisedtotheHCLK domain.Here,theDMM has thecapacitytoacceptpacketsD4x, D5x, D6x, D7x. PacketD8 would resultinan overflow.Once DMMnENA isasserted,theDMM expectsto stop receivingpacketsafter4 HCLK cycles;once DMMnENA is de-asserted,the DMM can handle packetsimmediately(after0 HCLK cycles).

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PRODUCT□PREVIEW TRST TMS TCK TDI TDO RTCK IC EPICK Boundary BSDL Boundary Scan Interface Scan Device Pins (conceptual) TDI TDO TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

4.21.10 Boundary Scan Chain

The devicesupportsBSDL-compliantboundary scan fortestingpin-to-pincompatibility.The boundary scan chainisconnectedtotheBoundaryScan InterfaceoftheICEPICK module. Figure4-30.Boundary Scan Implementation(ConceptualDiagram) Data isseriallyshiftedintoallboundary-scanbuffersviaTDI,and outviaTDO. Copyright© 2011,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 115 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5 PeripheralInformationand ElectricalSpecifications

5.1 PeripheralLegend

Table5-1.PeripheralLegend Abbreviation FullName MibADC AnalogTo DigitalConverter CCM-R4F CPU Compare Module -CortexR4F CRC CyclicRedundancy Check DCAN ControllerArea Network DCC DualClockComparator DMA DirectMemory Access DMM Data ModificationModule EMIF ExternalMemory Interface ESM ErrorSignalingModule ETM-R4F Embedded TraceMacrocell-CortexR4F FTU FlexRayTransferUnit GIO General-PurposeInput/Output HTU HighEnd TimerTransferUnit I2C Inter-IntegratedCircuit LIN LocalInterconnectNetwork MIBSPI MultibufferSerialPeripheralInterface N2HET PlatformHigh-EndTimer POM ParameterOverlayModule RTI Real-TimeInterruptModule RTP RAM TracePort SCI SerialCommunicationsInterface SPI SerialPeripheralInterface VIM VectoredInterruptManager

5.2 Multi-Buffered12bitAnalog-to-DigitalConverter

The multibufferedA-to-Dconverter(MibADC) has a separatepower bus foritsanalog circuitrythat enhances theA-to-Dperformanceby preventingdigitalswitchingnoiseon thelogiccircuitrywhich could be presenton VSS and VCC fromcouplingintotheA-to-Danalogstage.AllA-to-Dspecificationsaregiven withrespecttoAD REFLO unlessotherwisenoted. Table5-2.MibADC Overview Description Value Resolution 12 bits Monotonic Assured Outputconversioncode 00h toFFFh [00forVAI ≤ AD REFLO ;FFF forVAI ≥ AD REFHI ]

5.2.1 Features

10-/12-bitresolution
AD REFHI and AD REFLO pins(highand lowreferencevoltages)
TotalSample/Hold/Converttime:600ns TypicalMinimum at30MHz ADCLK
One memory regionperconversiongroupisavailable(event,group1,group2)
Allocationofchannelstoconversiongroupsiscompletelyprogrammable
Memory regionsareservicedeitherby interruptorby DMA

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Programmable interruptthresholdcounterisavailableforeach group
Programmable magnitudethresholdinterruptforeach groupforany one channel
Optiontoreadeither8-bit,10-bitor12-bitvaluesfrommemory regions
Singleorcontinuousconversionmodes
Embedded self-test
Embedded calibrationlogic
Enhanced power-down mode – Optionalfeaturetoautomaticallypower down ADC corewhen no conversionisinprogress
Externaleventpin(ADEVT) programmableas general-purposeI/O

5.2.2 Event TriggerOptions

The ADC module supports3 conversiongroups:Event Group, Group1 and Group2. Each of these 3 groups can be configuredto be hardware event-triggered.In thatcase,the applicationcan selectfrom among 8 eventsourcestobe thetriggerfora group'sconversions.

5.2.2.1 DefaultMIBADC1 Event TriggerHookup

Table5-3.MIBADC1 Event TriggerHookup Event # Source SelectBitsFor G1, G2 Or Event Trigger (G1SRC[2:0],G2SRC[2:0] or EVSRC[2:0]) 1 000 ADEVT 2 001 N2HET1[8] 3 010 N2HET1[10] 4 011 RTI compare 0 interrupt 5 100 N2HET1[12] 6 101 N2HET1[14] 7 110 GIOB[0] 8 111 GIOB[1] NOTE For ADEVT, N2HET1 and GIOB triggersources,the connectionto the MibADC1 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggercondition can be generatedeitherby configuringthe functionas outputonto the pad (viathe mux control),orby drivingthefunctionfroman externaltriggersourceas input.Ifthemux control module isused toselectdifferentfunctionalityinsteadoftheADEVT, N2HET1[x] orGIOB[x] signals,thencaremust be takentodisablethesesignalsfrom triggeringconversions;there isno multiplexingon theinputconnections. NOTE For theRTI compare 0 interruptsource,theconnectionismade directlyfrom theoutputof theRTI module.That is,theinterruptconditioncan be used as a triggersourceeven ifthe actualinterruptisnotsignaledtotheCPU.

5.2.2.2 AlternateMIBADC1 Event TriggerHookup

Table5-4.AlternateMIBADC1 Event TriggerHookup Event # Source SelectBitsforG1, G2 or Event Trigger (G1SRC[2:0],G2SRC[2:0] or EVSRC[2:0]) 1 000 ADEVT 2 001 N2HET2[5] Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 117 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table5-4.AlternateMIBADC1 Event TriggerHookup (continued) Event # Source SelectBitsforG1, G2 or Event Trigger (G1SRC[2:0],G2SRC[2:0] or EVSRC[2:0]) 3 010 N2HET1[27] 4 011 RTI compare 0 interrupt 5 100 N2HET1[17] 6 101 N2HET1[19] 7 110 N2HET1[11] 8 111 N2HET2[13] The selectionbetween the defaultMIBADC1 event triggerhook-up versusthe alternateevent trigger hook-upisdone by multiplexingcontrolmodule register30 bits0 and 1. If30[0]= 1,thenthedefaultMibADC1 eventtriggerhook-upisused. If30[0]= 0 and 30[1]= 1,thenthealternateMibADC1 eventtriggerhook-upisused. NOTE ForADEVT triggersource,theconnectiontotheMibADC1 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeitherby configuringADEVT as an outputfunctionon tothepad (viathemux control),or by driving theADEVT signalfroman externaltriggersourceas input.Ifthemux controlmodule isused to selectdifferentfunctionalityinsteadof the ADEVT signal,then care must be taken to disableADEVT fromtriggeringconversions;thereisno multiplexingon theinputconnection. NOTE For N2HETx triggersources,theconnectiontotheMibADC1 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HETx module boundary).This way, a triggerconditioncan be generatedeven iftheN2HETx signalisnotselectedtobe outputon thepad. NOTE For theRTI compare 0 interruptsource,theconnectionismade directlyfrom theoutputof theRTI module.That is,theinterruptconditioncan be used as a triggersourceeven ifthe actualinterruptisnotsignaledtotheCPU.

5.2.2.3 DefaultMIBADC2 Event TriggerHookup

Table5-5.MIBADC2 Event TriggerHookup Event # Source SelectBitsforG1, G2 or Event Trigger (G1SRC[2:0],G2SRC[2:0] or EVSRC[2:0]) 1 000 AD2EVT 2 001 N2HET1[8] 3 010 N2HET1[10] 4 011 RTI compare 0 5 100 N2HET1[12] 6 101 N2HET1[14] 7 110 GIOB[0] 8 111 GIOB[1]

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 NOTE For AD2EVT, N2HET1 and GIOB triggersources,the connectionto the MibADC2 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggercondition can be generatedeitherby configuringthe functionas outputonto the pad (viathe mux control),orby drivingthefunctionfroman externaltriggersourceas input.Ifthemux control module isused toselectdifferentfunctionalityinsteadoftheAD2EVT, N2HET1[x] orGIOB[x] signals,thencaremust be takentodisablethesesignalsfrom triggeringconversions;there isno multiplexingon theinputconnections. NOTE For theRTI compare 0 interruptsource,theconnectionismade directlyfrom theoutputof theRTI module.That is,theinterruptconditioncan be used as a triggersourceeven ifthe actualinterruptisnotsignaledtotheCPU.

5.2.2.4 AlternateMIBADC2 Event TriggerHookup

Table5-6.AlternateMIBADC2 Event TriggerHookup Event # Source SelectBitsforG1, G2 or Event Trigger (G1SRC[2:0],G2SRC[2:0] or EVSRC[2:0]) 1 000 AD2EVT 2 001 N2HET2[5] 3 010 N2HET1[27] 4 011 RTI compare 0 5 100 N2HET1[17] 6 101 N2HET1[19] 7 110 N2HET1[11] 8 111 N2HET2[13] The selectionbetween the defaultMIBADC2 event triggerhook-up versusthe alternateevent trigger hook-upisdone by multiplexingcontrolmodule register30 bits0 and 1. If30[0]= 1,thenthedefaultMibADC2 eventtriggerhook-upisused. If30[0]= 0 and 30[1]= 1,thenthealternateMibADC2 eventtriggerhook-upisused. NOTE For AD2EVT triggersource,the connectionto the MibADC2 module triggerinputismade fromtheoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeither by configuringAD2EVT as an outputfunctionon to the pad (viathe mux control),or by drivingtheAD2EVT signalfroman externaltriggersourceas input.Ifthemux controlmodule isused to selectdifferentfunctionalityinsteadof the AD2EVT signal,then care must be takentodisableAD2EVT from triggeringconversions;thereisno multiplexingon theinput connections. NOTE For N2HETx triggersources,theconnectiontotheMibADC2 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HETx module boundary).This way, a triggerconditioncan be generatedeven iftheN2HETx signalisnotselectedtobe outputon thepad. Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 119 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com NOTE For theRTI compare 0 interruptsource,theconnectionismade directlyfrom theoutputof theRTI module.That is,theinterruptconditioncan be used as a triggersourceeven ifthe actualinterruptisnotsignaledtotheCPU.

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5.2.3 ADC Electricaland Timing Specifications

Table5-7.MibADC Recommended OperatingConditions Parameter MIN MAX Unit AD REFHI A-to-Dhigh-voltagereferencesource AD REFLO VCCAD V AD REFLO A-to-Dlow-voltagereferencesource VSSAD AD REFHI V VAI Analoginputvoltage AD REFLO AD REFHI V IAIC Analoginputclamp current -2 2 mA (VAI< VSSAD – 0.3orVAI > VCCAD + 0.3) Table5-8.MibADC ElectricalCharacteristicsOver FullRanges ofRecommended OperatingConditions(1) Parameter Description/Conditions MIN Type MAX Unit R mux Analoginputmux See Figure5-1 250 Ω on-resistance R samp ADC sample switch See Figure5-1 250 Ω on-resistance C mux Inputmux capacitance See Figure5-1 16 pF C samp ADC sample capacitance See Figure5-1 13 pF IAIL Analogoff-stateinput Off-stateinputleakageper VSSAD < VIN < VSSAD + 300 nA leakagecurrent,forVCCAD = ADC inputpin 100mV 3.6Vmaximum VSSAD + 100mV < VIN < 200 nA VCCAD -200mV VCCAD -200mV < VIN < 500 nA VCCAD IAIL Analogoff-stateinput Off-stateinputleakageper VIN > VSSAD , 1 µA leakagecurrent,forVCCAD = ADC inputpin VIN < VSSAD + 300mV 5.5Vmaximum VIN > VSSAD + 300mV, 250 nA VIN < VCCAD -300mV VIN > VCCAD -300mV, 1 µA VIN < VCCAD IADREFHI AD REFHI inputcurrent AD REFHI = VCCAD ,AD REFLO = VSSAD 3 mA ICCAD Staticsupplycurrent Normal operatingmode 15 mA ADC coreinpower down mode 5 µA (1) 1 LSB = (ADREFHI – AD REFLO )/212 fortheMibADC Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 121 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW VS1 On-State Leakage Off-State Leakages VS2 VS24 39*IAIL IAIL IAIL Rext Rext Rext Pin Smux Rmux Pin Smux Rmux Pin Smux Rmux Ssamp Rsamp Csamp Cext IAIL IAIL IAIL IAIL Cmux Cext Cext TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Figure5-1.MibADC InputEquivalentCircuit Table5-9.MibADC Timing Specifications Parameter MIN NOM MAX Unit tc(ADCLK) (1) Cycletime,MibADC clock 0.033 µs td(SH) (2) Delaytime,sample and hold 0.2 µs time 12-bitmode td©) Delaytime,conversiontime 0.4 µs td(SHC) (3) Delaytime,totalsample/hold 0.6 µs and conversiontime 10-bitmode td©) Delaytime,conversiontime 0.33 µs td(SHC) (4) Delaytime,totalsample/hold 0.53 µs and conversiontime (1) The MibADC clockistheADCLK, generatedby dividingdown theVCLK by a prescalefactordefinedby theADCLOCKCR registerbits 4:0. (2) The sample and holdtimefortheADC conversionsisdefinedby theADCLK frequencyand theAD <GP >SAMP registerforeach conversiongroup.The sample timeneeds tobe determinedby accountingfortheexternalimpedance connectedtotheinputchannelas wellas theADC ’s internalimpedance. (3) Thisistheminimum sample/holdand conversiontimethatcan be achieved.These parametersaredependenton many factors,e.gthe prescalesettings. (4) Thisistheminimum sample/holdand conversiontimethatcan be achieved.These parametersaredependenton many factors,e.gthe prescalesettings.

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table5-10.MibADC OperatingCharacteristicsOver FullRanges ofRecommended OperatingConditions Parameter Description/Conditions MIN Type MAX Unit CR Conversionrangeover AD REFHI -AD REFLO 3 5.5 V whichspecified accuracyis maintained ZSET ZeroScaleOffset Differencebetween thefirstidealtransition 10-bit 1 LSB (fromcode 000h to001h)and theactual mode transition 12-bit 2 LSB mode FSET FullScaleOffset Differencebetween therangeofthe 10-bit 2 LSB measured code transitions(fromfirsttolast) mode and therangeoftheidealcode transitions 12-bit 3 LSB mode EDNL Differential Differencebetween theactualstepwidthand 10-bit ± 1.5 LSB nonlinearityerror theidealvalue.(See Figure76) mode 12-bit ± 2 LSB mode EINL Integralnonlinearity Maximum deviationfromthebeststraightline 10-bit ± 2 LSB error throughtheMibADC. MibADC transfer mode characteristics,excludingthequantization 12-bit ± 2 LSBerror. mode ETOT Totalunadjustederror Maximum valueofthedifferencebetween an 10-bit ± 2 LSB (aftercalibration) analogvalueand theidealmidstepvalue. mode 12-bit ± 4 LSB mode Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 123 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW Differential Linearity Error (–½ LSB)

1 LSB

Error (–½ LSB) 0 ... 110 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) NOTE A: 1 LSB = (AD – AD )/2REFHI REFLO TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.2.4 Performance (Accuracy)Specifications

5.2.4.1 MibADC NonlinearityErrors

The differentialnonlinearityerrorshown in FigureFigure5-2 (sometimes referredto as differential linearity)isthedifferencebetween an actualstepwidthand theidealvalueof1 LSB. Figure5-2.DifferentialNonlinearity(DNL) Error

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PRODUCT□PREVIEW 0 ... 111 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) 0 ... 110 6 7 At Transition (–½ LSB) At Transition 001/010 (–1/4 LSB) Actual Transition Ideal Transition End-Point Lin. Error NOTE A: 1 LSB = (AD – AD )/2REFHI REFLO TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 The integralnonlinearityerrorshown inFigureFigure5-3(sometimesreferredtoas linearityerror)isthe deviationofthevalueson theactualtransferfunctionfroma straightline. Figure5-3.IntegralNonlinearity(INL)Error Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 125 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW 0 ... 111 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) 0 ... 110 6 7 Total Error At Step Total Error At Step 0 ... 101 (–1 1/4 LSB) NOTE A: 1 LSB = (AD – AD )/2REFHI REFLO TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.2.4.2 MibADC TotalError

The absoluteaccuracyortotalerrorofan MibADC as shown inFigureFigure5-4isthemaximum valueof thedifferencebetween an analogvalueand theidealmidstepvalue. Figure5-4.AbsoluteAccuracy (Total)Error

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5.3 General-PurposeInput/Output

The GPIO module on thisdevicesupportstwo ports,GIOA and GIOB. The I/Opinsarebidirectionaland bit-programmable.BothGIOA and GIOB supportexternalinterruptcapability.

5.3.1 Features

The GPIO module has thefollowingfeatures:

Each IO pincan be configuredas: – Input – Output – Open Drain
The interruptshave thefollowingcharacteristics: – Programmable interruptdetectioneitheron bothedges oron a singleedge (setinGIOINTDET) – Programmable edge-detectionpolarity,eitherrisingorfallingedge (setinGIOPOL register) – Individualinterruptflags(setinGIOFLG register) – Individualinterruptenables,set and clearedthroughGIOENASET and GIOENACLR registers respectively – Programmable interruptpriority,setthroughGIOLVLSET and GIOLVLCLR registers
Internalpullup/pulldownallowsunused I/Opinstobe leftunconnected Forinformationon inputand outputtimingssee Section3.8and Section3.9 Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 127 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW NHETx TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.4 Enhanced High-End Timer (N2HET)

The N2HET isan advanced intelligenttimerthatprovidessophisticatedtimingfunctionsforreal-time applications.The timerissoftware-controlled,usinga reduced instructionset,witha specializedtimer micromachineand an attachedI/O port.The N2HET can be used forpulsewidthmodulated outputs, captureor compare inputs,or general-purposeI/O..Itisespeciallywellsuitedforapplicationsrequiring multiplesensorinformationand driveactuatorswithcomplexand accuratetimepulses.

5.4.1 Features

The N2HET module has thefollowingfeatures:

Programmable timerforinputand outputtimingfunctions
Reduced instructionset(30instructions)fordedicatedtimeand anglefunctions
160 words ofinstructionRAM protectedby parity
User definednumber of25-bitvirtualcountersfortimer,eventcountersand anglecounters
7-bithardwarecountersforeach pinallowup to32-bitresolutioninconjunctionwiththe25-bitvirtual counters
Up to32 pinsusableforinputsignalmeasurements oroutputsignalgeneration
Programmable suppressionfilterforeach inputpinwithadjustablelimitingfrequency
Low CPU overheadand interruptload
EfficientdatatransfertoorfromtheCPU memory withdedicatedHigh-End-TimerTransferUnit(HTU) orDMA
Diagnosticcapabilitieswithdifferentloopbackmechanisms and pinstatusreadbackfunctionality

5.4.2 N2HET RAM Organization

The timerRAM uses 4 RAM banks,where each bank has two portaccesscapability.Thismeans thatone RAM addressmay be writtenwhileanotheraddressisread.The RAM words are96-bitswide,whichare splitintothree32-bitfields(program,control,and data).

5.4.3 InputTiming Specifications

The N2HET instructionsPCNT and WCAP impose some timingconstraintson theinputsignals. Figure5-5.N2HET InputCapture Timings

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PRODUCT□PREVIEW NHET1 NHET2 NHET_LOOP_SYNC EXT_LOOP_SYNC EXT_LOOP_SYNC NHET_LOOP_SYNC TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table5-11.Dynamic CharacteristicsfortheN2HET InputCapture Functionality PARAMETER MIN (1)(2) MAX (1)(2) UNIT

1 Inputsignalperiod,PCNT orWCAP forrisingedge 2 (hr)(lr)tc(VCLK2) + 2 225 (hr)(lr)tc(VCLK2) -2 ns

2 Inputsignalperiod,PCNT orWCAP forfallingedge 2 (hr)(lr)tc(VCLK2) + 2 225 (hr)(lr)tc(VCLK2) -2 ns

3 Inputsignalhighphase,PCNT orWCAP forrising (hr)(lr)tc(VCLK2) + 2 225 (hr)(lr)tc(VCLK2) -2 ns

4 Inputsignallowphase,PCNT orWCAP forfalling (hr)(lr)tc(VCLK2) + 2 225 (hr)(lr)tc(VCLK2) -2 ns

(1) hr= High-resolutionprescaler,configuredusingtheHRPFC fieldofthePrescaleFactorRegister(HETPFR). (2) lr= Loop-resolutionprescaler,configuredusingtheLFPRC fieldofthePrescaleFactorRegister(HETPFR) Both N2HET1 and N2HET2 have threechannelseach thatareenhanced tobe abletocaptureinputswith smallerpulsewidthsthanthatspecifiedinTable5-11.These are N2HET1 channels15,20 and 31,and N2HET2 channels12,14 and 16. The inputcapturecapabilityforthesechannelsisspecifiedinthefollowingtable. Table5-12.InputCapture CapabilityforN2HET Channels withEnhancements PARAMETER MIN MAX UNIT

1 Inputsignalperiod,PCNT orWCAP forrisingedge (hr)(lr)tc(VCLK2) + 2 225 (hr)(lr)tc(VCLK2) -2 ns

2 Inputsignalperiod,PCNT orWCAP forfallingedge (hr)(lr)tc(VCLK2) + 2 225 (hr)(lr)tc(VCLK2) -2 ns

3 Inputsignalhighphase,PCNT orWCAP forrising 2 (hr)tc(VCLK2) + 2 225 (hr)(lr)tc(VCLK2) -2 ns

4 Inputsignallowphase,PCNT orWCAP forfalling 2 (hr)tc(VCLK2) + 2 225 (hr)(lr)tc(VCLK2) -2 ns

5.4.4 N2HET1-N2HET2 Interconnections

In some applicationsthe N2HET resolutionsmust be synchronized.Some otherapplicationsrequirea singletimebase tobe used forallPWM outputsand inputtimingcaptures. The N2HET providessuch a synchronizationmechanism. The Clk_master/slave(HETGCR.16) configures theN2HET inmasterorslavemode (defaultisslavemode).A N2HET inmastermode providesa signal tosynchronizetheprescalersoftheslaveN2HET. The slaveN2HET synchronizesitsloopresolutionto theloopresolutionsignalsentby themaster.The slavedoes notrequirethissignalafteritreceivesthe firstsynchronizationsignal.However, anytimethe slavereceivesthe re-synchronizationsignalfrom the master,theslavemust synchronizeitselfagain.. Figure5-6.N2HET1 – N2HET2 SynchronizationHookup

5.4.5 N2HET Checking

5.4.5.1 InternalMonitoring

To assurecorrectnessofthehigh-endtimeroperationand outputsignals,thetwo N2HET modules can be used tomonitoreach other’s signalsas shown inFigure5-7.The directionofthemonitoringiscontrolled by theI/Omultiplexingcontrolmodule. Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 129 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW NHET1 NHET2 IOMM mux control signal x TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Figure5-7.N2HET Monitoring

5.4.5.2 Output Monitoringusing Dual Clock Comparator (DCC)

N2HET1[31] isconnectedas a clocksourceforcounter1 inDCC1. Thisallowstheapplicationtomeasure thefrequencyofthepulse-widthmodulated(PWM) signalon N2HET1[31]. Similarly,N2HET2[0] isconnectedas a clocksourceforcounter1 inDCC2. Thisallowstheapplicationto measure thefrequencyofthepulse-widthmodulated(PWM) signalon N2HET2[0]. Both N2HET1[31] and N2HET2[0] can be configuredtobe internal-onlychannels.Thatis,theconnection totheDCC module ismade directlyfromtheoutputoftheN2HETx module (fromtheinputoftheoutput buffer). Formore informationon DCC see Section4.7.3.

5.4.6 DisablingN2HET Outputs

Some applicationsrequirethe N2HET outputsto be disabledunder some faultcondition.The N2HET module providesthiscapabilityviathe"PinDisable"inputsignal.Thissignal,when drivenlow,causes the N2HET outputsidentifiedby a programmable register(HETPINDIS) to be tri-stated.Please referto the TMS570LS31X/21X TechnicalReferenceManual (SPNU499) formore detailson the"N2HET PinDisable" feature. GIOA[5] is connected to the "PinDisable"inputforN2HET1, and GIOB[2] is connected to the "Pin Disable"inputforN2HET2.

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5.4.7 High-End Timer TransferUnit(HET-TU)

A High End TimerTransferUnit(HET-TU) can performDMA typetransactionstotransferN2HET datato orfrommain memory. A Memory ProtectionUnit(MPU) isbuiltintotheHET-TU.

5.4.7.1 Features

CPU and DMA independent
MasterPorttoaccesssystemmemory
8 controlpacketssupportingdualbufferconfiguration
ControlpacketinformationisstoredinRAM protectedby parity
Eventsynchronization(HET transferrequests)
Supports32 or64 bittransactions
Addressingmodes forHET address(8 byteor 16 byte)and system memory address(fixed,32 bitor 64bit)
One shot,circularand autoswitchbuffertransfermodes
Requestlostdetection

5.4.7.2 TriggerConnections

Table5-13.HET TU1 Request LineConnection Modules Request Source HET TU1 Request N2HET1 HTUREQ[0] HET TU1 DCP[0] N2HET1 HTUREQ[1] HET TU1 DCP[1] N2HET1 HTUREQ[2] HET TU1 DCP[2] N2HET1 HTUREQ[3] HET TU1 DCP[3] N2HET1 HTUREQ[4] HET TU1 DCP[4] N2HET1 HTUREQ[5] HET TU1 DCP[5] N2HET1 HTUREQ[6] HET TU1 DCP[6] N2HET1 HTUREQ[7] HET TU1 DCP[7] Table5-14.HET TU2 Request LineConnection Modules Request Source HET TU2 Request N2HET2 HTUREQ[0] HET TU2 DCP[0] N2HET2 HTUREQ[1] HET TU2 DCP[1] N2HET2 HTUREQ[2] HET TU2 DCP[2] N2HET2 HTUREQ[3] HET TU2 DCP[3] N2HET2 HTUREQ[4] HET TU2 DCP[4] N2HET2 HTUREQ[5] HET TU2 DCP[5] N2HET2 HTUREQ[6] HET TU2 DCP[6] N2HET2 HTUREQ[7] HET TU2 DCP[7] Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 131 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW VCCIO 0.6*VCCIO 0.4*VCCIO Input tpw 0.6*VCCIO 0.4*VCCIO TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.5 FlexRay Interface

The FlexRay module performscommunicationaccordingtotheFlexRay protocolspecificationv2.1.The sample clockbitratecan be programmed tovaluesup to10 MBit per second.Additionalbus driver(BD) hardwareisrequiredforconnectiontothephysicallayer. For communicationon a FlexRay network,individualmessage bufferswithup to 254 data bytesare configurable.The message storageconsistsof a single-portedmessage RAM thatholds up to 128 message buffers.Allfunctionsconcerningthe handlingof messages are implementedinthe message handler.Those functionsaretheacceptancefiltering,thetransferofmessages between thetwo FlexRay Channel ProtocolControllersand the message RAM, maintainingthe transmissionscheduleas wellas providingmessage statusinformation. The registersetof the FlexRay module can be accessed directlyby the CPU viathe VBUS interface. These registersare used to control,configureand monitorthe FlexRay channel protocolcontrollers, message handler,global time unit,system universalcontrol,frame/symbol processing,network management, interruptcontrol,and toaccessthemessage RAM viatheinput/outputbuffer.

5.5.1 Features

The FlexRaymodule has thefollowingfeatures:

Conformance withFlexRayprotocolspecificationv2.1
Data ratesofup to10 Mbit/son each channel
Up to128 message buffers
8 Kbyteofmessage RAM forstorageofe.g.128 message bufferswithmax. 48 bytedatasectionorup to30 message bufferswith254 bytedatasection
Configurationofmessage bufferswithdifferentpayloadlengths
One configurablereceiveFIFO
Each message buffercan be configuredas receivebuffer,as transmitbufferoras partofthereceive FIFO
CPU accesstomessage buffersviainputand outputbuffer
FlexRay TransferUnit(FTU) forautomaticdatatransferbetween datamemory and message buffers withoutCPU interaction
Filteringforslotcounter,cyclecounter,and channelID
Maskablemodule interrupts
SupportsNetworkManagement

5.5.2 Electricaland Timing Specifications

Table5-15.Timing Requirements forFlexRay Inputs(1) Parameter MIN MAX UNIT tpw Inputminimum pulsewidthtomeet theFlexRaysampling tc(AVCLK2) + 2.5(2) ns requirement (1) tc(AVCLK2) = sample clockcycletimeforFlexRay= 1 /f(AVCLK2) (2) tRxAsymDelay parameter Figure5-8.FlexRay Inputs

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Table5-16.FlexRay JitterTiming(1) Parameter MIN MAX Unit tTx1bit Clockjitterand signalsymmetry 98 102 ns tTx10bit FlexRayBSS (bytestartsequence)toBSS 999 1001 ns tTx10bitAvg Averageover10000 samples 999.5 1000.5 ns tRxAsymDelay (2) Delaydifferencebetween riseand fallfromRx pintosample – 2.5 ns pointinFlexRaycore tjit(SCLK) Jitterforthe80MHz Sample Clockgeneratedby thePLL – 0.5 ns (1) Thisparameterwillbe characterized,butnotproduction-tested. (2) Thisvalueisbased on designsimulation.

5.5.3 FlexRay TransferUnit

The FlexRayTransferUnitisabletotransferdatabetween theinputbuffer(IBF)and outputbuffer(OBF) ofthecommunicationcontrollerand thesystemmemory withoutCPU interaction. Because theFlexRaymodule isaccessedthroughtheFTU, theFTU must be powered up by thesetting bit23 in the PeripheralPower Down Registersof the System Module beforeaccessingany FlexRay module register. For more informationon the FTU see the TMS570LS31X/TMS570LS21X TechnicalReferenceManual (SPNU499). Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 133 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.6 ControllerArea Network (DCAN)

The DCAN supportsthe CAN 2.0B protocolstandardand uses a serial,multimastercommunication protocolthatefficientlysupportsdistributedreal-timecontrolwithrobustcommunicationratesofup to1 megabit per second (Mbps). The DCAN is idealfor applicationsoperatingin noisy and harsh environments(e.g.,automotiveand industrialfields)that requirereliableserialcommunication or multiplexedwiring.

5.6.1 Features

FeaturesoftheDCAN module include:

SupportsCAN protocolversion2.0partA,B
Bitratesup to1 MBit/s
The CAN kernelcan be clockedby theoscillatorforbaud-rategeneration.
64 mailboxeson each DCAN
Individualidentifiermask foreach message object
Programmable FIFO mode formessage objects
Programmable loop-backmodes forself-testoperation
Automaticbus on afterBus-Offstateby a programmable32-bittimer
Message RAM protectedby parity
DirectaccesstoMessage RAM duringtestmode
CAN Rx /Tx pinsconfigurableas generalpurposeIO pins
Message RAM AutoInitialization
DMA support Formore informationon theDCAN see theTMS570LS31X/21X TechnicalReferenceManual (SPNU499).

5.6.2 Electricaland Timing Specifications

Table5-17.Dynamic CharacteristicsfortheDCANx TX and RX pins Parameter MIN MAX Unit td(CANnTX) Delaytime,transmitshiftregistertoCANnTX pin(1) 15 ns td(CANnRX) Delaytime,CANnRX pintoreceiveshiftregister 5 ns (1) These valuesdo notincluderise/falltimesoftheoutputbuffer.

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5.7 LocalInterconnectNetwork Interface(LIN)

The SCI/LINmodule can be programmed towork eitheras an SCI oras a LIN.The coreofthemodule is an SCI.The SCI’s hardwarefeaturesareaugmented toachieveLIN compatibility. The SCI module isa universalasynchronousreceiver-transmitterthatimplementsthestandardnonreturn to zero format.The SCI can be used to communicate,forexample,throughan RS-232 portor over a K-line. The LIN standardisbased on the SCI (UART) serialdata linkformat.The communicationconceptis single-master/multiple-slavewitha message identificationformulti-casttransmissionbetween any network nodes.

5.7.1 LIN Features

The followingarefeaturesoftheLIN module:

CompatibletoLIN 1.3,2.0and 2.1protocols
Multi-bufferedreceiveand transmitunitsDMA capabilityforminimalCPU intervention
Identificationmasks formessage filtering
AutomaticMasterHeader Generation – Programmable Synch BreakField – Synch Field – IdentifierField
SlaveAutomaticSynchronization – Synch breakdetection – Optionalbaudrateupdate – SynchronizationValidation
231 programmabletransmissionrateswith7 fractionalbits
Errordetection

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5.8 SerialCommunication Interface(SCI)

5.8.1 Features

Standarduniversalasynchronousreceiver-transmitter(UART) communication
Supportsfull-orhalf-duplexoperation
Standardnonreturntozero(NRZ) format
Double-bufferedreceiveand transmitfunctions
Configurableframeformatof3 to13 bitspercharacterbased on thefollowing: – Data word lengthprogrammablefromone toeightbits – Additionaladdressbitinaddress-bitmode – Parityprogrammableforzeroorone paritybit,odd oreven parity – Stopprogrammableforone ortwo stopbits
Asynchronousorisosynchronouscommunicationmodes
Two multiprocessorcommunicationformatsallowcommunicationbetween more thantwo devices.
Sleepmode isavailabletofreeCPU resourcesduringmultiprocessorcommunication.
The 24-bitprogrammablebaud ratesupports224 differentbaud ratesprovidehighaccuracybaud rate selection.
Fourerrorflagsand FivestatusflagsprovidedetailedinformationregardingSCI events.
Capabilitytouse DMA fortransmitand receivedata.

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5.9 Inter-IntegratedCircuit(I2C)

The inter-integratedcircuit(I2C)module isa multi-mastercommunicationmodule providingan interface between the TMS570 microcontrollerand devices compliantwith PhilipsSemiconductor I2C-bus specificationversion2.1and connectedby an I2C-bus.Thismodule willsupportany slaveormasterI2C compatibledevice.

5.9.1 Features

The I2C has thefollowingfeatures:

CompliancetothePhilipsI2C bus specification,v2.1(The I2C Specification,Philipsdocument number 9398 393 40011) – Bit/Byteformattransfer – 7-bitand 10-bitdeviceaddressingmodes – Generalcall – START byte – Multi-mastertransmitter/slavereceivermode – Multi-masterreceiver/slavetransmittermode – Combined mastertransmit/receiveand receive/transmitmode – Transferratesof10 kbps up to400 kbps (Phillipsfast-moderate)
Freedataformat
Two DMA events(transmitand receive)
DMA eventenable/disablecapability
Seven interruptsthatcan be used by theCPU
Module enable/disablecapability
The SDA and SCL areoptionallyconfigurableas generalpurposeI/O
Slew ratecontroloftheoutputs
Open draincontroloftheoutputs
Programmable pullup/pulldowncapabilityon theinputs
SupportsIgnoreNACK mode NOTE ThisI2C module does notsupport:
High-speed(HS)mode
C-bus compatibilitymode
The combined formatin10-bitaddressmode (theI2C sends theslaveaddresssecond byteeverytimeitsends theslaveaddressfirstbyte) Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 137 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW SDA SCL tw(SDAH) tw(SCLL) tw(SCLH) tw(SP) th(SCLL-SDAL) th(SDA-SCLL) th(SCLL-SDAL) tsu(SCLH-SDAL) tf(SCL)tc(SCL) tr(SCL) tsu(SCLH-SDAH) Stop Start Repeated Start Stop tsu(SDA-SCLH) TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.9.2 I2C I/OTiming Specifications

Table5-18.I2C Signals(SDA and SCL) SwitchingCharacteristics(1) Parameter Standard Mode FastMode Unit MIN MAX MIN MAX tc(I2CCLK) Cycletime,InternalModule clockforI2C, 75.2 149 75.2 149 ns prescaledfromVCLK tc(SCL) Cycletime,SCL 10 2.5 ms tsu(SCLH-SDAL) Setuptime,SCL highbeforeSDA low(fora 4.7 0.6 ms repeatedSTART condition) th(SCLL-SDAL) Holdtime,SCL lowafterSDA low(fora repeated 4 0.6 ms START condition) tw(SCLL) Pulseduration,SCL low 4.7 1.3 ms tw(SCLH) Pulseduration,SCL high 4 0.6 ms tsu(SDA-SCLH) Setuptime,SDA validbeforeSCL high 250 100 ns th(SDA-SCLL) Holdtime,SDA validafterSCL low(forI2C bus 0 3.45(2) 0 0.9 ms devices) tw(SDAH) Pulseduration,SDA highbetween STOP and 4.7 1.3 ms START conditions tsu(SCLH-SDAH) Setuptime,SCL highbeforeSDA high(forSTOP 4.0 0.6 ms condition) tw(SP) Pulseduration,spike(mustbe suppressed) 0 50 ns C b (3) Capacitiveloadforeach bus line 400 400 pF (1) The I2C pinsSDA and SCL do notfeaturefail-safeI/Obuffers.These pinscouldpotentiallydraw currentwhen thedeviceispowered down. (2) The maximum th(SDA-SCLL) forI2C bus deviceshas onlytobe met ifthedevicedoes notstretchthelowperiod(tw(SCLL))oftheSCL signal. (3) C b = The totalcapacitanceofone bus lineinpF. Figure5-9.I2C Timings

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A devicemust internallyprovidea hold time of at least300 ns forthe SDA signal (referredto the VIHmin of the SCL signal)to bridgethe undefinedregionof the falling edge ofSCL.
The maximum th(SDA-SCLL) has onlyto be met ifthe devicedoes not stretchthe LOW period(tw(SCLL))oftheSCL signal.
A Fast-mode I2C-busdevicecan be used ina Standard-modeI2C-bussystem,butthe requirementtsu(SDA-SCLH) ≥ 250 ns must thenbe met.Thiswillautomaticallybe thecase if the devicedoes not stretchthe LOW periodof the SCL signal.Ifsuch a devicedoes stretchtheLOW periodoftheSCL signal,itmust outputthenextdatabittotheSDA line trmax + tsu(SDA-SCLH).
C b = totalcapacitanceof one bus linein pF. Ifmixed withfast-modedevices,faster fall-timesareallowed. Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 139 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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5.10 Multi-Buffered/Standard SerialPeripheralInterface

The MibSPI is a high-speedsynchronous serialinput/outputportthatallowsa serialbitstream of programmed length(2to16 bits)tobe shiftedinand outofthedeviceata programmed bit-transferrate. TypicalapplicationsfortheSPI includeinterfacingtoexternalperipherals,such as I/Os,memories,display drivers,and analog-to-digitalconverters.

5.10.1 Features

BothStandardand MibSPI modules have thefollowingfeatures:

16-bitshiftregister
Receivebufferregister
8-bitbaud clockgenerator,supportsmax up to20Mhz baud rate
SPICLK can be internally-generated(mastermode) or receivedfrom an externalclocksource(slave mode)
Each word transferredcan have a uniqueformat
SPI I/Osnotused inthecommunicationcan be used as digitalinput/outputsignals Table5-19.MibSPI/SPIConfigurations MibSPIx/SPIx I/Os MibSPI1 MIBSPI1SIMO[1:0],MIBSPI1SOMI[1:0],MIBSPI1CLK, MIBSPI1nCS[5:0],MIBSPI1nENA MibSPI3 MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0],MIBSPI3nENA MibSPI5 MIBSPI5SIMO[3:0],MIBSPI5SOMI[3:0],MIBSPI5CLK, MIBSPI5nCS[3:0],MIBSPI5nENA SPI2 SPI2SIMO, ZSPI2SOMI, SPI2CLK, SPI2nCS[1:0],SPI2nENA SPI4 SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0],SPI4nENA

5.10.2 MibSPI Transmitand Receive RAM Organization

The MultibufferRAM iscomprisedof128 buffers.Each entryintheMultibufferRAM consistsof4 parts:a 16-bittransmitfield,a 16-bitreceivefield,a 16-bitcontrolfieldand a 16-bitstatusfield.The Multibuffer RAM can be partitionedintomultipletransfergroupwithvariablenumber ofbufferseach.

5.10.3 MibSPI TransmitTriggerEvents

Each ofthetransfergroupscan be configuredindividually.For each ofthetransfergroupsa triggerevent and a triggersourcecan be chosen.A triggereventcan be forexample a risingedge ora permanentlow levelat a selectabletriggersource.For example,up to 15 triggersourcesare availablewhich can be utilizedby each transfergroup.These triggeroptionsare listedin Table 5-20, Section5.10.3.2and Section5.10.3.3forMibSPI1,MibSPi3and MibSPI5 respectively.

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 5.10.3.1MIBSPI1 Event TriggerHookup Table5-20.MIBSPI1 Event TriggerHookup Event # TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No triggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternTickcounter NOTE For N2HET1 triggersources,the connectionto the MibSPI1 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HET1 module boundary).This way, a triggerconditioncan be generatedeven iftheN2HET1 signalisnotselectedtobe outputon thepad. NOTE For GIOx triggersources,theconnectiontotheMibSPI1 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeitherby selectingtheGIOx pinas an outputpinplusselectingthepintobe a GIOx pin,orby driving the GIOx pinfrom an externaltriggersource.Ifthe mux controlmodule isused to select differentfunctionalityinsteadof the GIOx signal,then care must be takento disableGIOx fromtriggeringMibSPI1 transfers;thereisno multiplexingon theinputconnections. 5.10.3.2MIBSPI3 Event TriggerHookup Table5-21.MIBSPI3 Event TriggerHookup Event # TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No triggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 HET[8] EVENT9 1010 N2HET1[10] Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 141 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table5-21.MIBSPI3 Event TriggerHookup (continued) Event # TGxCTRL TRIGSRC[3:0] Trigger EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternTickcounter NOTE For N2HET1 triggersources,the connectionto the MibSPI3 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HET1 module boundary).This way, a triggerconditioncan be generatedeven iftheN2HET1 signalisnotselectedtobe outputon thepad. NOTE For GIOx triggersources,theconnectiontotheMibSPI3 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeitherby selectingtheGIOx pinas an outputpinplusselectingthepintobe a GIOx pin,orby driving the GIOx pinfrom an externaltriggersource.Ifthe mux controlmodule isused to select differentfunctionalityinsteadof the GIOx signal,then care must be takento disableGIOx fromtriggeringMibSPI3 transfers;thereisno multiplexingon theinputconnections. 5.10.3.3MIBSPI5 Event TriggerHookup Table5-22.MIBSPI5 Event TriggerHookup Event# TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No triggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternTickcounter NOTE For N2HET1 triggersources,the connectionto the MibSPI5 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HET1 module boundary).This way, a triggerconditioncan be generatedeven iftheN2HET1 signalisnotselectedtobe outputon thepad.

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 NOTE For GIOx triggersources,theconnectiontotheMibSPI5 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeitherby selectingtheGIOx pinas an outputpin+ selectingthepintobe a GIOx pin,orby drivingthe GIOx pinfroman externaltriggersource.Ifthemux controlmodule isused toselectdifferent functionalityinsteadof the GIOx signal,then care must be taken to disableGIOx from triggeringMibSPI5 transfers;thereisno multiplexingon theinputconnections. Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 143 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

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5.10.4 MibSPI/SPIMaster Mode I/OTiming Specifications

Table5-23.SPI Master Mode ExternalTiming Parameters (CLOCK PHASE = 0,SPICLK = output,SPISIMO = output,and SPISOMI = input)(1)(2)(3) NO. Parameter MIN MAX Unit 1 tc(SPC)M Cycletime,SPICLK (4) 40 256tc(VCLK) ns 2(5) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 3(5) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 4(5) td(SPCH-SIMO)M Delaytime,SPISIMO validbefore 0.5tc(SPC)M – 5 ns SPICLK low(clockpolarity= 0) td(SPCL-SIMO)M Delaytime,SPISIMO validbefore 0.5tc(SPC)M – 5 SPICLK high(clockpolarity= 1) 5(5) tv(SPCL-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tf(SPC)– 3 ns SPICLK low(clockpolarity= 0) tv(SPCH-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tr(SPC)– 3 SPICLK high(clockpolarity= 1) 6(5) tsu(SOMI-SPCL)M Setuptime,SPISOMI beforeSPICLK 0.5tf(SPC)+ 2 ns low(clockpolarity= 0) tsu(SOMI-SPCH)M Setuptime,SPISOMI beforeSPICLK 0.5tf(SPC)+ 2 high(clockpolarity= 1) 7(5) th(SPCL-SOMI)M Holdtime,SPISOMI datavalidafter 5 ns SPICLK low(clockpolarity= 0) th(SPCH-SOMI)M Holdtime,SPISOMI datavalidafter 5 SPICLK high(clockpolarity= 1) 8(6) tC2TDELAY SetuptimeCS active CSHOLD = 0 C2TDELAY*t c(VCLK) + 2*tc(VCLK) (C2TDELAY+2) *tc(VCLK) - ns untilSPICLK high -tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 (clockpolarity= 0) CSHOLD = 1 C2TDELAY*t c(VCLK) + 3*tc(VCLK) (C2TDELAY+3) *tc(VCLK) - -tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 SetuptimeCS active CSHOLD = 0 C2TDELAY*t c(VCLK) + 2*tc(VCLK) (C2TDELAY+2) *tc(VCLK) - ns untilSPICLK low -tf(SPICS)+ tf(SPC)– 15 tf(SPICS)+ tf(SPC)+ 3 (clockpolarity= 1) CSHOLD = 1 C2TDELAY*t c(VCLK) + 3*tc(VCLK) (C2TDELAY+3) *tc(VCLK) - -tf(SPICS)+ tf(SPC)– 15 tf(SPICS)+ tf(SPC)+ 3 9(6) tT2CDELAY HoldtimeSPICLK lowCS untilinactive 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns (clockpolarity= 0) T2CDELAY*t c(VCLK) + tc(VCLK) - T2CDELAY*t c(VCLK) + tc(VCLK) - tf(SPC)+ tr(SPICS)-5 tf(SPC)+ tr(SPICS)+ 8 HoldtimeSPICLK highuntilCS 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns inactive(clockpolarity= 1) T2CDELAY*t c(VCLK) + tc(VCLK) - T2CDELAY*t c(VCLK) + tc(VCLK) - tr(SPC)+ tr(SPICS)-5 tr(SPC)+ tr(SPICS)+ 8 10 tSPIENA SPIENAn Sample point (C2TDELAY+1) *tc(VCLK) - (C2TDELAY+1)*tc(VCLK) ns tf(SPICS)– 25 11 tSPIENAW SPIENAn Sample pointfromwriteto (C2TDELAY+2)*tc(VCLK) ns buffer (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (3) Forriseand falltimings,see the"switchingcharacteristicsforoutputtimingsversusloadcapacitance" table. (4) When theSPI isinMastermode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)M = 2tc(VCLK) ≥ 40ns. The externalloadon theSPICLK pinmust be lessthan60pF. (5) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). (6) C2TDELAY and T2CDELAY isprogrammed intheSPIDELAY register

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PRODUCT□PREVIEW SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid SPICLK (clock polarity=0) SPISIMO SPICSn Master Out Data Is Valid SPICLK (clock polarity=1) SPIENAn Write to buffer TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Figure5-10.SPI Master Mode ExternalTiming (CLOCK PHASE = 0) Figure5-11.SPI Master Mode Chip SelectTiming (CLOCK PHASE = 0) Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 145 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table5-24.SPI Master Mode ExternalTiming Parameters (CLOCK PHASE = 1,SPICLK = output,SPISIMO = output,and SPISOMI = input)(1)(2)(3) NO. Parameter MIN MAX Unit 1 tc(SPC)M Cycletime,SPICLK (4) 40 256tc(VCLK) ns 2(5) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 3(5) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 4(5) tv(SIMO-SPCH)M Validtime,SPICLK highafter 0.5tc(SPC)M – 5 ns SPISIMO datavalid(clockpolarity= tv(SIMO-SPCL)M Validtime,SPICLK lowafter 0.5tc(SPC)M – 5 SPISIMO datavalid(clockpolarity= 5(5) tv(SPCH-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tr(SPC)– 3 ns SPICLK high(clockpolarity= 0) tv(SPCL-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tf(SPC)– 3 SPICLK low(clockpolarity= 1) 6(5) tsu(SOMI-SPCH)M Setuptime,SPISOMI before tr(SPC) ns SPICLK high(clockpolarity= 0) tsu(SOMI-SPCL)M Setuptime,SPISOMI before tf(SPC) SPICLK low(clockpolarity= 1) 7(5) tv(SPCH-SOMI)M Validtime,SPISOMI datavalidafter 5 ns SPICLK high(clockpolarity= 0) tv(SPCL-SOMI)M Validtime,SPISOMI datavalidafter 5 SPICLK low(clockpolarity= 1) 8(6) tC2TDELAY SetuptimeCS CSHOLD = 0 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns activeuntilSPICLK (C2TDELAY+2) *tc(VCLK) - (C2TDELAY+2) *tc(VCLK) - high(clockpolarity= tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 0) CSHOLD = 1 0.5*tc(SPC)M + 0.5*tc(SPC)M + (C2TDELAY+3) *tc(VCLK) - (C2TDELAY+3) *tc(VCLK) - tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 SetuptimeCS CSHOLD = 0 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns activeuntilSPICLK (C2TDELAY+2) *tc(VCLK) - (C2TDELAY+2) *tc(VCLK) - low(clockpolarity= tf(SPICS)+ tf(SPC)– 15 tf(SPICS)+ tf(SPC)+ 3 1) CSHOLD = 1 0.5*tc(SPC)M + 0.5*tc(SPC)M + (C2TDELAY+3) *tc(VCLK) - (C2TDELAY+3) *tc(VCLK) - tf(SPICS)+ tf(SPC)– 15 tf(SPICS)+ tf(SPC)+ 3 9(6) tT2CDELAY HoldtimeSPICLK lowCS until T2CDELAY*t c(VCLK) + T2CDELAY*t c(VCLK) + ns inactive(clockpolarity= 0) tc(VCLK) -tf(SPC)+ tr(SPICS)- tc(VCLK) -tf(SPC)+ tr(SPICS)+ 4 8 HoldtimeSPICLK highuntilCS T2CDELAY*t c(VCLK) + T2CDELAY*t c(VCLK) + ns inactive(clockpolarity= 1) tc(VCLK) -tr(SPC)+ tr(SPICS)- tc(VCLK) -tr(SPC)+ tr(SPICS)+ 4 8 10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)* tc(VCLK) - (C2TDELAY+1)*tc(VCLK) ns tf(SPICS)– 25 11 tSPIENAW SPIENAn Sample pointfromwriteto (C2TDELAY+2)*tc(VCLK) ns buffer (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (3) Forriseand falltimings,see the"switchingcharacteristicsforoutputtimingsversusloadcapacitance" table. (4) When theSPI isinMastermode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)M = 2tc(VCLK) ≥ 40ns. The externalloadon theSPICLK pinmust be lessthan60pF. (5) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). (6) C2TDELAY and T2CDELAY isprogrammed intheSPIDELAY register

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PRODUCT□PREVIEW SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Data Valid Master In Data Must Be Valid Master Out Data Is Valid SPICLK (clock polarity=0) SPISIMO SPICSn Master Out Data Is Valid SPICLK (clock polarity=1) SPIENAn Write to buffer TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Figure5-12.SPI Master Mode ExternalTiming (CLOCK PHASE = 1) Figure5-13.SPI Master Mode Chip SelectTiming (CLOCK PHASE = 1) Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 147 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.10.5 SPI SlaveMode I/OTimings

Table5-25.SPI SlaveMode ExternalTiming Parameters (CLOCK PHASE = 0,SPICLK = input,SPISIMO = input,and SPISOMI = output)(1)(2)(3)(4) NO. Parameter MIN MAX Unit 1 tc(SPC)S Cycletime,SPICLK (5) 40 256tc(VCLK) ns 2(6) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 0) 14 ns tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 1) 14 3(6) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 0) 14 ns tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 1) 14 4(6) td(SPCH-SOMI)S Delaytime,SPISOMI validafterSPICLK high(clock trf(SOMI)+ 18 ns polarity= 0) td(SPCL-SOMI)S Delaytime,SPISOMI validafterSPICLK low(clockpolarity trf(SOMI)+ 18 = 1) 5(6) th(SPCH-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK high(clock 2 ns polarity=0) th(SPCL-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK low(clock 2 polarity=1) 6(6) tsu(SIMO-SPCL)S Setuptime,SPISIMO beforeSPICLK low(clockpolarity= 2 ns tsu(SIMO-SPCH)S Setuptime,SPISIMO beforeSPICLK high(clockpolarity= 2 7(6) th(SPCL-SIMO)S Holdtime,SPISIMO datavalidafterSPICLK low(clock 2 ns polarity= 0) th(SPCH-SIMO)S Holdtime,SPISIMO datavalidafterS PICLK high(clock 2 polarity= 1) 8 td(SPCL-SENAH)S Delaytime,SPIENAn highafterlastSPICLK low(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) ns polarity= 0) td(SPCH-SENAH)S Delaytime,SPIENAn highafterlastSPICLK high(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) polarity= 1) 9 td(SCSL-SENAL)S Delaytime,SPIENAn lowafterSPICSn low(ifnew data tf(ENAn) tc(VCLK)+tf(ENAn)+1 ns has been writtentotheSPI buffer) 4 (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) IftheSPI isinslavemode, thefollowingmust be true:tc(SPC)S ≥ (PS + 1)tc(VCLK),where PS = prescalevaluesetinSPIFMTx.[15:8]. (3) Forriseand falltimings,see the"switchingcharacteristicsforoutputtimingsversusloadcapacitance" table. (4) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (5) When theSPI isinSlavemode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)S = 2tc(VCLK) ≥ 40ns. (6) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17).

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PRODUCT□PREVIEW SPISOMI SPICLK (clock□polarity□=□1) SPICLK (clock□polarity□=□0) SPISIMO□Data Must□Be□Valid SPISOMI□Data□Is□Valid 666 SPISIMO SPICLK (clock polarity=0) SPICSn SPICLK (clock polarity=1) SPIENAn TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Figure5-14.SPI SlaveMode ExternalTiming (CLOCK PHASE = 0) Figure5-15.SPI SlaveMode Enable Timing (CLOCK PHASE = 0) Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 149 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com Table5-26.SPI SlaveMode ExternalTiming Parameters (CLOCK PHASE = 1,SPICLK = input,SPISIMO = input,and SPISOMI = output)(1)(2)(3)(4) NO. Parameter MIN MAX Unit 1 tc(SPC)S Cycletime,SPICLK (5) 40 256tc(VCLK) ns 2(6) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 0) 14 ns tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 1) 14 3(6) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 0) 14 ns tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 1) 14 4(6) td(SOMI-SPCL)S Dealytime,SPISOMI datavalidafterSPICLK low trf(SOMI)+ 18 ns (clockpolarity= 0) td(SOMI-SPCH)S Delaytime,SPISOMI datavalidafterSPICLK high trf(SOMI)+ 18 (clockpolarity= 1) 5(6) th(SPCL-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK high 2 ns (clockpolarity=0) th(SPCH-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK low(clock 2 polarity=1) 6(6) tsu(SIMO-SPCH)S Setuptime,SPISIMO beforeSPICLK high(clock 2 ns polarity= 0) tsu(SIMO-SPCL)S Setuptime,SPISIMO beforeSPICLK low(clockpolarity 2 = 1) 7(6) tv(SPCH-SIMO)S Hightime,SPISIMO datavalidafterSPICLK high 2 ns (clockpolarity= 0) tv(SPCL-SIMO)S Hightime,SPISIMO datavalidafterSPICLK low(clock 2 polarity= 1) 8 td(SPCH-SENAH)S Delaytime,SPIENAn highafterlastSPICLK high 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) ns (clockpolarity= 0) td(SPCL-SENAH)S Delaytime,SPIENAn highafterlastSPICLK low(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) polarity= 1) 9 td(SCSL-SENAL)S Delaytime,SPIENAn lowafterSPICSn low(ifnew data tf(ENAn) tc(VCLK)+tf(ENAn)+14 ns has been writtentotheSPI buffer) 10 td(SCSL-SOMI)S Delaytime,SOMI validafterSPICSn low(ifnew data tc(VCLK) 2tc(VCLK)+trf(SOMI)+8 ns has been writtentotheSPI buffer) (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) IftheSPI isinslavemode, thefollowingmust be true:tc(SPC)S≤ (PS + 1)tc(VCLK),where PS = prescalevaluesetinSPIFMTx.[15:8]. (3) Forriseand falltimings,see the"switchingcharacteristicsforoutputtimingsversusloadcapacitance" table. (4) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (5) When theSPI isinSlavemode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)S = 2tc(VCLK) ≥ 40ns. (6) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17).

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PRODUCT□PREVIEW SPISIMO SPISOMI SPISIMO Data Must Be Valid SPISOMI Data Is Valid 666 SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISOMI Slave Out Data Is Valid SPICLK (clock polarity=0) SPICSn SPICLK (clock polarity=1) SPIENAn TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Figure5-16.SPI SlaveMode ExternalTiming (CLOCK PHASE = 1) Figure5-17.SPI SlaveMode Enable Timing (CLOCK PHASE = 1) Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 151 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW 1 2 MII_MRCLK MII_MRXD MII_MRXDV MII_MRXER V ALID TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.11 EthernetMedia Access Controller

The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween TMS570 and the network.The EMAC supportsboth10Base-T and 100Base-TX,or10 Mbits/second(Mbps)and 100 Mbps ineitherhalf-orfull-duplexmode, withhardwareflowcontroland qualityofservice(QoS) support. The EMAC controlsthe flowof packetdata from the TMS570 deviceto the PHY. The MDIO module controlsPHY configurationand statusmonitoring. Both theEMAC and theMDIO modules interfacetotheTMS570 devicethrougha custom interfacethat allowsefficientdatatransmissionand reception.Thiscustom interfaceisreferredtoas theEMAC control module,and isconsideredintegralto the EMAC/MDIO peripheral.The controlmodule isalsoused to multiplexand controlinterrupts.

5.11.1 EthernetMIIElectricaland Timing Specifications

Figure5-18.MIIReceive Timing Table5-27.MIIReceive Timing Parameter Description MIN MAX tsu(GMIIMRXD) Setuptime,GMIIMRXD toGMIIMRCLK risingedge 8ns tsu(GMIIMRXDV) Setuptime,GMIIMRXDV toGMIIMRCLK risingedge 8ns tsu(GMIIMRXER) Setuptime,GMIIMRXER toGMIIMRCLK risingedge 8ns th(GMIIMRXD) Holdtime,GMIIMRXD validafterGMIIRCLK rising 8ns edge th(GMIIMRXDV) Holdtime,GMIIMRXDV validafterGMIIRCLK rising 8ns edge th(GMIIMRXER) Holdtime,GMIIMRXDV validafterGMIIRCLK rising 8ns edge

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PRODUCT□PREVIEW MII_MTCLK MII_MTXD MII_MTXEN V ALID TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011 Figure5-19.MIITransmitTiming Table5-28.MIITransmitTiming Parameter Description MIN MAX td(GMIIMTXD) Delaytime,GMIIMTCLK risingedge toGMIIMTXD 5ns 25ns td(GMIIMTXEN) Delaytime,GMIIMTCLK risingedge toGMIIMTXEN 5ns 25ns Copyright© 2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 153 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

PRODUCT□PREVIEW MDCLK MDIO (input) MDCLK MDIO (output) TMS570LS3137 SPNS162. –SEPTEMBER 2011 www.ti.com

5.11.2 Management Data Input/Output(MDIO)

Figure5-20.MDIO InputTiming Table5-29.MDIO InputTiming Requirements NO. Parameter Value Unit MIN MAX 1 tc(MDCLK) Cycletime,MDCLK 400 - ns 2 tw(MDCLK) Pulseduration,MDCLK high/low 180 - ns 3 tt(MDCLK) Transitiontime,MDCLK - 5 ns 4 tsu(MDIO-MDCLKH) Setuptime,MDIO datainputvalidbeforeMDCLK 10 - ns High 5 th(MDCLKH-MDIO) Holdtime,MDIO datainputvalidafterMDCLK 10 - ns High Figure5-21.MDIO Output Timing Table5-30.MDIO Output Timing Requirements NO. Parameter Value Unit MIN MAX 1 tc(MDCLK) Cycletime,MDCLK 400 - ns 7 td(MDCLKL-MDIO) Delaytime,MDCLK lowtoMDIO dataoutput 0 100 ns valid

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PRODUCT□PREVIEW TMS570LS3137 www.ti.com SPNS162. –SEPTEMBER 2011

6 MechanicalData

6.1 Thermal Data

Table6-1shows thethermalresistancecharacteristicsfortheQFP -PGE mechanicalpackage. Table6-2shows thethermalresistancecharacteristicsfortheBGA -ZWT mechanicalpackage. Table6-1.Thermal ResistanceCharacteristics (PGE Package) PARAMETER °C /W R ΘJA 45 R ΘJC 5 Table6-2.Thermal ResistanceCharacteristics (ZWT Package) PARAMETER °C /W R ΘJA 18.8 R ΘJC 7.1

6.2 Packaging Information

The followingpackaginginformationreflectsthemost currentreleaseddataavailableforthedesignated device(s).Thisdataissubjecttochange withoutnoticeand withoutrevisionofthisdocument. Copyright© 2011,Texas InstrumentsIncorporated MechanicalData 155 SubmitDocumentationFeedback focus.ti.com:TMS570LS3137

www.ti.com 6-Apr-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TMX5703137BPGEQQ1 ACTIVE LQFP PGE 144 1 TBD Call TI Call TI TMX5703137BZWTQQ1 ACTIVE NFBGA ZWT 337 1 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 4040147/C 10/96 0,27 0,17 0,13 NOM 0,25 0,75 0,45 0,05 MIN Seating Plane Gage Plane 108 109 144 SQ SQ22,20 21,80 19,80 17,50 TYP 20,20 1,35 1,45 1,60 MAX M0,08 0°–7° 0,08 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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Product Information

TMX5703137BPGEQQ1 specifications and overview.

Summary

TMS570LS3137 16/32-Bit RISC Flash Microcontroller

Description

TMS570LS3137 16/32-Bit RISC Flash Microcontroller

Source title TMX5703137BPGEQQ1 Datasheet(PDF) - Texas Instruments

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