TMX5700332PZQQ1

TMS570LS0432 TI1 | Alldatasheet

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 TMS570LS0432/033216/32-BitRISCFlashMicrocontroller Check forSamples: TMS570LS0432

1 TMS570LS0432/0332 16/32-BitRISC FlashMicrocontroller

1.1 Features

• High-PerformanceAutomotive Grade • MultipleCommunication Interfaces MicrocontrollerforSafetyCriticalApplications – Two CAN Controllers(DCAN) – Dual CPU ’s Running inLockstep • DCAN1 -32 MailboxeswithParity – ECC on Flashand RAM interfaces Protection – Built-InSelfTestforCPU and On-chip RAMs • DCAN2 -16 MailboxeswithParity Protection– ErrorSignalingModule withErrorPin
• Compliant toCAN protocolVersion2.0B– Voltageand Clock Monitoring – Multi-bufferedSerialPeripheralInterface• ARM ® Cortex™ – R4 32-bitRISC CPU (MibSPI)– Efficient1.66DMIPS/MHz with8-stage
• 128 Words withParityProtectionPipeline – Two Standard SerialPeripheralInterfaces– 8-RegionMemory ProtectionUnit (SPI)– Open Architecturewith3rd PartySupport – UART (SCI)interfacewithLocalNetwork• OperatingConditions Interface(LIN2.1)support– 80MHz System Clock • High-End Timer Module (N2HET)– Core Supply Voltage(VCC ):1.2Vnominal – Up to19 Programmable Pins– I/OSupply Voltage(VCCIO ):3.3Vnominal – 128 Word InstructionRAM withParity– ADC Supply Voltage(VCCAD ):3.3VNominal Protection• IntegratedMemory – Each IncludesHardware Angle Generator– Up to384kB Program FlashwithECC – DedicatedTransferUnit(HTU)– 32kB RAM withECC • Enhanced QuadratureEncoder Pulse (eQEP)– 16kB FlashforEmulated EEPROM withECC – Motor PositionEncoder Interface• Common PlatformArchitecture • 12-bitMulti-BufferedADC Module– ConsistentMemory Map Across Family – 16channels– Real-TimeInterruptTimer (RTI)OS Timer – 64 ResultBufferswithParityProtection– 96-channelVectoredInterruptModule (VIM) • Up to45 generalpurpose I/O(GIO)capable– 2-channelCyclicRedundancy Checker (CRC) pins
• Frequency-ModulatedPhase-Locked-Loop – 8 DedicatedGeneral-PurposeI/O(GIO)Pins(FMPLL) withBuilt-InSlipDetector withup to8 ExternalInterrupts
• IEEE 1149.1JTAG, Boundary Scan and ARM • PackagesCoreSightComponents – 100-pinQuad Flatpack(PZ)[Green]• Advanced JTAG SecurityModule (AJSM) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCT PREVIEW informationconcernsproductsintheformativeordesignphase of Copyright© 2012,Texas InstrumentsIncorporateddevelopment.Characteristicdata and other specificationsare design goals.Texas Instrumentsreservestherighttochange ordiscontinuetheseproductswithoutnotice.

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1.2 Applications

• Brakingsystems (ABS and ESC)
• Electricpower steering(EPS)
• ElectricPump Control
• Batterymanagement systems
• Activedriverassistancesystems
• Aerospace and avionics
• Railwaycommunications
• Offroad vehicles

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1.3 Description

The TMS570LS0432/0332 is a high performanceautomotivegrade microcontrollerfamilyforsafety systems.The safetyarchitectureincludesDual CPUs inlockstep,CPU and Memory Built-InSelfTest (BIST)logic,ECC on boththeFlashand thedataSRAM, parityon peripheralmemories,and loopback capabilityon peripheralIOs. The TMS570LS0432/0332 integratesthe ARM ® Cortex™ -R4 CPU which offers an efficient 1.66DMIPS/MHz, and can run up to 80MHz providingup to 132 DMIPS. The devicesupportsthe big- endian[BE32]format. The TMS570LS0432/0332 has 384kB and 256kB integratedFlash (respectively)and 32kB data RAM configurationswithsinglebiterrorcorrectionand doublebiterrordetection.The flashmemory on this deviceisa nonvolatile,electricallyerasableand programmable memory implementedwitha 64-bit-wide data bus interface.The flashoperateson a 3.3V supplyinput(same levelas I/Osupply)forallread, program and eraseoperations.The flashoperateswitha system clockfrequencyof80 MHz inpipeline mode. The SRAM supportssingle-cycleread/writeaccessesinbyte,halfword,and word modes. The TMS570LS0432/0332 devicefeaturesperipheralsforreal-timecontrol-basedapplications,includinga Next GenerationHigh End Timer(N2HET) timingcoprocessorwithup to19 totalIO terminalsand a 12-bit Analog-to-Digitalconvertersupporting16 inputsinthe100 pinpackage. The N2HET isan advanced intelligenttimerthatprovidessophisticatedtimingfunctionsforreal-time applications.The timerissoftware-controlled,usinga reduced instructionset,witha specializedtimer micromachineand an attachedI/O port.The N2HET can be used forpulsewidthmodulated outputs, captureor compare inputs,or general-purposeI/O.Itisespeciallywellsuitedforapplicationsrequiring multiplesensorinformationand driveactuatorswithcomplex and accuratetimepulses.A High End Timer TransferUnit(HET-TU) can performDMA type transactionsto transferN2HET data to or from main memory. A Memory ProtectionUnit(MPU) isbuiltintotheHET-TU. The enhanced quadratureencoderpulse(eQEP) module isused fordirectinterfacewitha linearorrotary incrementalencodertogetposition,direction,and speed informationfrom a rotatingmachine as used in high-performancemotionand position-controlsystems. The devicehas a 12-bit-resolutionMibADC with16 totalchannelsand 64 words ofparityprotectedbuffer RAM. The MibADC channelscan be convertedindividuallyor can be grouped by softwareforsequential conversionsequences.There arethreeseparategroupings.Each sequence can be convertedonce when triggeredorconfiguredforcontinuousconversionmode. The devicehas multiplecommunicationinterfaces:one MibSPI, two SPIs, one UART/LIN, and two DCANs. The SPI providesa convenientmethod of serialinteractionforhigh-speedcommunications between similarshift-registertypedevices.The UART/LIN supportstheLocalInterconnectstandard2.1 and can be used as a UART infull-duplexmode usingthe standardNon-Return-to-Zero(NRZ) format. The DCAN supportsthe CAN 2.0B protocolstandardand uses a serial,multimastercommunication protocolthatefficientlysupportsdistributedreal-timecontrolwithrobustcommunicationratesofup to1 megabit per second (Mbps). The DCAN is idealfor applicationsoperatingin noisy and harsh environments(e.g.,automotiveand industrialfields)that requirereliableserialcommunication or multiplexedwiring. The frequency-modulatedphase-lockedloop (FMPLL) clockmodule is used to multiplythe external frequencyreferencetoa higherfrequencyforinternaluse.The FMPLL providesone ofthefivepossible clocksourceinputstotheglobalclockmodule (GCM). The GCM module manages themapping between theavailableclocksourcesand thedeviceclockdomains. The devicealsohas an externalclockprescaler(ECP) module thatwhen enabled,outputsa continuous externalclockon the ECLK pin.The ECLK frequencyisa user-programmableratioof the peripheral interfaceclock(VCLK) frequency.Thislowfrequencyoutputcan be monitoredexternallyas an indicatorof thedeviceoperatingfrequency. Copyright© 2012,Texas InstrumentsIncorporated TMS570LS0432/0332 16/32-BitRISC FlashMicrocontroller 3 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com The ErrorSignalingModule (ESM) monitorsalldeviceerrorsand determineswhether an interruptor externalErrorpinistriggeredwhen a faultisdetected.The nERROR can be monitoredexternallyas an indicatorofa faultconditioninthemicrocontroller. With integratedsafetyfeaturesand a wide choice of communication and controlperipherals,the TMS570LS0432/0332 is an ideal solutionfor real time controlapplicationswith safety critical requirements.

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PRODUCT□PREVIEW ESM Flash 384kB with□ECC CRC 2□Channel Peripheral Bridge PCR N2HET 128□Words with□Parity SYS GIO LIN MiBSPI1

8 Transfer

128□Buffers with□Parity DCAN1 32□Messages with□Parity nTRST TMS TCK TDI TDO nRST nPORRST TEST GIOA[7:0]/INT[7:0] LINRX LINTX MIBSPI1SIMO MIBSPI1SOMI MIBSPI1CLK MIBSPI1nCS[3:0] CAN1RX CAN1TX FLTP1 ECLK DCAN2 16□Messages with□Parity CAN2RX CAN2TX VIM 96□Channel with□Parity CCM-R4 RTCK nERROR MIBSPI1nENA FLTP2 RAM 32kB with□ECC Slave□I/F RTI MiBADC 64□Words with□Parity VCCAD / ADREFH VSSAD / ADREFLO ADEVT SPI2 SPI2SIMO SPI2SOMI SPI2CLK SPI2nCS[0] STC LBIST Debug Gasket SCR DAP with ICEPick HTU 2□Regions 8□DCP with□MPU BRIDGE Cortex-R4 with□MPU 8□regions 16kB Flash□for EEPROM w/ECC VCCP1 Cortex-R4 with□MPU 8□regions OSCIN OSCOUT VCCPLL VSSPLL Kelvin_GND OSC PLL Clock Monitor AJSM eQEPDCCIOMM eQEPAeQEPB eQEPSeQEPI SPI3 SPI3SIMO SPI3SOMI SPI3CLK SPI3nCS[3:0] SPI3nENA TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

1.4 FunctionalBlock Diagram

Figure1-1.FunctionalBlock Diagram Table1-1.Device Comparison Table OrderablePart# Part# Flash RAM Package TMX5700332PZQQ1 TMS570LS0332 256kB 32kB 100-pinQFP TMX5700432PZQQ1 TMS570LS0432 384kB 32kB 100-pinQFP Copyright© 2012,Texas InstrumentsIncorporated TMS570LS0432/0332 16/32-BitRISC FlashMicrocontroller 5 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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3.3 SwitchingCharacteristicsoverRecommended 5 PeripheralInformationand Electrical

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PRODUCT□PREVIEW MIBSPI1nCS[1] VCCP LINRX VCCIO ECLK RTCK N2HET[6] MIBSPI1nCS[2] VCCIO VSS VCC nPORRST VCC VSS SPI3nENA AD IN[21] TCK SPI3nCS[0] MIBSPI1nCS[3] ADIN[0] ADIN[7] AD IN[20] VSSA D/ADREFLO ADIN[9] VCCAD /ADREFHI ADIN[1] ADIN[10] VSS VCC CAN2RX CAN2TX VCC VSS nERROR nRST TDO TDI nTRST VSS LINTX SPI3CLK ADIN[2] ADIN[3] ADIN[4] A DIN[5] ADIN[6] ADE VT VSS CAN1 T X CAN1RX MIB SPI1 SO M I MIB SPI1 C L K MIB SPI1 nENA S PI2S O MI S PI2S IMO S PI2CLK MIBS PI1nCS[ 0] TMS VCC MIBS PI1S IMO VCCIO GIO A [3]/INT[3] VS S VCCIO G IOA[1]/I N T[1] TEST S PI2nCS [0] G IOA[7]/I N T[7] V SS K EL VIN_GN D O SCIN V C C GIO A [6]/INT[6] GIO A [5]/INT[5] GIO A [2]/INT[2] FL TP2 FL TP1 G IOA[0]/I N T[0] GIO A [4]/INT[4] OSCOUT 100 VS S V C C VSS SPI 3SOMI SPI 3SIMO ADIN[ 16] ADIN[ 17] A DIN[11] ADIN[8] N2HET[4]N2HET[2]N2HET[0] N2HET[022] N2HET[024]N2HET[8] N2HET[10] N2HET[8] N2HET[14] N2HET[12] N2HET[16] N2HET[18] TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

2 Device Package and TerminalFunctions

2.1 PZ QFP Package Pinout(100-Pin)

Figure2-1.PZ QFP Package Pinout(100-Pin) Note:Pinscan have multiplexedfunctions.Onlythedefaultfunctionisdepictedinabove diagram. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 7 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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2.2 TerminalFunctions

The followingtableidentifiesthe externalsignalnames, the associatedpin numbers along withthe mechanicalpackage designator,thepintype(Input,Output,IO,Power or Ground),whetherthepinhas any internalpullup/pulldown,whetherthepincan be configuredas a GIO, and a functionalpindescription. NOTE AllI/OsignalsexceptnRST areconfiguredas inputswhilenPORRST islowand immediately afternPORRST goes High. Alloutput-onlysignalsare configuredas inputswhilenPORRST islow,and are configured as outputsimmediatelyafternPORRST goes High. WhilenPORRST islow,theinputbuffersaredisabled,and theoutputbuffersaretri-stated.

2.2.1 High-End Timer (N2HET)

Table2-1.High-End Timer (N2HET) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ High-End Timer (N2HET) N2HET[0] 19 I/O PullDown Programmable, Timerinputcaptureoroutputcompare.The 20uA N2HET applicableterminalscan be programmedN2HET[2] 22 as general-purposeinput/output(GIO).All N2HET[4] 25 N2HET terminalsarehigh-resolution. The high-resolution(HR) SHARE featureallowsN2HET[6] 26 even HR terminalstosharethenexthigherodd N2HET[8] 74 HR structures.The nexthigherodd HR structure isalwaysimplemented,even thenexthigheroddN2HET[10] 83 HR pterminalitselfisnot.The HR sharingis N2HET[12] 89 independentofwhetherornottheodd terminalis availableexternally.Ifan odd terminalisN2HET[14] 90 availableexternallyand shared,thentheodd N2HET[16] 97 terminalcan onlybe used as a general-purpose I/O.MIBSPI1nCS[1]/EQEPS/ 93 N2HET[0] providesSPI clockwhen used forSPIN2HET[17] emulation.N2HET[18] 98 Each N2HET terminalisequippedwitha suppressionfilter.IftheterminalisconfiguredasMIBSPI1nCS[2]/N2HET[20]/ 27 an inputitenablestofilteroutpulseswhichareN2HET[19] smallerthana programmableduration.MIBSPI1nCS[2]/N2HET[20]/ 27 N2HET[19] N2HET[22] 11 N2HET[24] 64 MIBSPI1nCS[3]/N2HET[26] 39 ADEVT/ N2HET[28] 58 GIOA[7]/N2HET[29] 18 MIBSPI1nENA/NHET[23]/ 68 N2HET[30] GIOA[6]/SPI2nCS[1]/N2HET[31] 12

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2.2.2 Enhanced QuadratureEncoder Pulse Modules (eQEP)

Table2-2.PGE Enhanced QuadratureEncoder Pulse Modules (eQEP) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ SPI3CLK/EQEPA 36 Input Pullup Fixed,20uA Enhanced QEP InputA SPI3nENA/EQEPB 37 Input Enhanced QEP InputB SPI3nCS[0]/EQEPI 38 I/O Enhanced QEP Index MIBSPI1nCS[1]/EQEPS /NHET[ 93 I/O Enhanced QEP Strobe 17]

2.2.3 General-PurposeInput/Output(GIO)

Table2-3.General-PurposeInput/Output(GIO) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ GIOA[0]/SPI3nCS[3] 1 I/O PullDown Programmable, General-purposeinput/output 20uA GIOA[7:0]/INT[7:0]areinterrupt-capableGIOA[1]/SPI3nCS[2] 2 terminals. GIOA[2]/SPI3nCS[1] 5 GIOA[3]/SPI2nCS[3] 8 GIOA[4]/SPI2nCS[2] 9 GIOA[5]/EXTCLKIN 10 GIOA[6]/SPI2nCS[1]/N2HET[31] 12 GIOA[7]/N2HET[29] 18

2.2.4 ControllerArea Network InterfaceModules (DCAN1, DCAN2)

Table2-4.ControllerArea Network InterfaceModules (DCAN1, DCAN2) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ CAN1RX 63 I/O PullUp Programmable, CAN1 Receive,orgeneral-purposeI/O(GPIO) 20uACAN1TX 62 CAN1 Transmit,orGPIO CAN2RX 92 CAN2 Receive,orGPIO CAN2TX 91 CAN2 Transmit,orGPIO Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 9 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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2.2.5 Multi-BufferedSerialPeripheralInterface(MibSPI1)

Table2-5.Multi-BufferedSerialPeripheralInterface(MibSPI1) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ MIBSPI1CLK 67 I/O PullUp Programmable, MibSPI1 SerialClock,orGPIO 20uAMIBSPI1nCS[0] 73 MibSPI1 ChipSelect,orGPIO MIBSPI1nCS[1]/EQEPS/N2HET 93 [17] MIBSPI1nCS[2]/N2HET[20]/N2 27 HET[19] MIBSPI1nCS[3]/N2HET[26] 39 MIBSPI1nENA /N2HET[23]/N2H 68 MibSPI1 Enable,orGPIO ET[30] MIBSPI1SIMO 65 MibSPI1 Slave-In-Master-Out,orGPIO MIBSPI1SOMI 66 MibSPI1 Slave-Out-Master-In,orGPIO

2.2.6 Standard SerialPeripheralInterface(SPI2)

Table2-6.Standard SerialPeripheralInterface(SPI2) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ SPI2CLK 71 I/O PullUp Programmable, SPI2 SerialClock,orGPIO 20uASPI2nCS[0] 23 SPI2 ChipSelect,orGPIO GIOA[6]/SPI2nCS[1]/NHET[31] 12 GIOA[4]/SPI2nCS[2] 9 GIOA[3]/SPI2nCS[3] 8 SPI2SIMO 70 SPI2 Slave-In-Master-Out,orGPIO SPI2SOMI 69 SPI2 Slave-Out-Master-In,orGPIO The drivestrengthsfortheSPI2CLK, SPI2SIMO and SPI2SOMI signalsareselectedindividuallyby configuringtherespectiveSRS bitsof theSPIPC9 registerfoSPI2. SRS = 0 for8mA drive(fast).Thisisthedefaultmode as theSRS bitsintheSPIPC9 registerdefaultto0. SRS = 1 for2mA drive(slow) SPI3CLK /EQEPA 36 I/O PullUp Programmable, SPI3 SerialClock,orGPIO 20uASPI3nCS[0]/EQEPI 38 SPI3 ChipSelect,orGPIO GIOA[2]/SPI3nCS[1] 5 GIOA[1]/SPI3nCS[2] 2 GIOA[0]/SPI3nCS[3] 1 SPI3nENA /EQEPB 37 SPI3 Enable,orGPIO SPI3SIMO 35 SPI3 Slave-In-Master-Out,orGPIO SPI3SOMI 34 SPI3 Slave-Out-Master-In,orGPIO

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2.2.7 LocalInterconnectNetwork Controller(LIN)

Table2-7.LocalInterconnectNetwork Controller(LIN) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ LINRX 94 I/O PullUp Programmable, LIN Receive,orGPIO 20uALINTX 95 LIN Transmit,orGPIO

2.2.8 Multi-BufferedAnalog-to-DigitalConverter(MibADC)

Table2-8.Multi-BufferedAnalog-to-DigitalConverter(MibADC) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ ADEVT /N2HET[28] 58 I/O PullUp Programmable, ADC EventTriggerorGPIO 20uA ADIN[0] 42 Input - - AnalogInputs ADIN[1] 49 ADIN[2] 51 ADIN[3] 52 ADIN[4] 54 ADIN[5] 55 ADIN[6] 56 ADIN[7] 43 ADIN[8] 57 ADIN[9] 48 ADIN[10] 50 ADIN[11] 53 ADIN[16] 40 ADIN[17] 41 ADIN[20] 44 ADIN[21] 45 ADREFHI/VCCAD 46 Input/Pow - - ADC HighReferenceLevel/ADCOperating er Supply ADREFLO/VSSAD 47 Input/Grou - - ADC Low ReferenceLevel/ADCSupplyGround nd

2.2.9 System Module

Table2-9.System Module Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ ECLK 84 I/O PullDown Programmable, ExternalPrescaledClock 20uA GIOA[5]/EXTCLKIN 10 Input PullDown 20uA ExternalClockIn nPORRST 31 Input PullDown 100uA Inputmasterchippower-upreset.Externalpower supplymonitorcircuitrymust asserta power-on reset. Thisterminalhas a glitchfilter. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 11 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table2-9.System Module (continued) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ nRST 81 I/O PullUp 100uA Bidirectionalreset.The internalcircuitrycan asserta reset,and an externalsystemresetcan asserta devicereset. On thisterminal,theoutputbufferisimplemented as an open drain(driveslowonly). To ensurean externalresetisnotarbitrarily generated,TIrecommends thatan external pullupresistorisconnectedtothisterminal.This terminalhas a glitchfilter.

2.2.10 ErrorSignalingModule (ESM)

Table2-10.ErrorSignalingModule (ESM) Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ nERROR 82 I/O PullDown 20uA DedicatedErrorSignal

2.2.11 Main Oscillator

Table2-11.Main Oscillator Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ OSCIN 14 Input - - OscillatorInput OSCOUT 16 Output - - OscillatorOutput KELVIN_GND 15 Input - - Dedicatedgroundforoscillator

2.2.12 Test/Debug Interface

Table2-12.Test/Debug Interface Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ nTRST 76 Input PullDown Fixed,100uA TesthardwareresettoTAP. IEEE Standard 1149-1(JTAG) Boundary-ScanLogic RTCK 80 Output - - ReturnTestclock.(JTAG) TCK 79 Input PullDown Fixed,100uA Testclock.TCK controlsthetesthardware (JTAG) TDI 77 I/O PullUp Fixed,100uA Testdatain.TDI inputsserialdatatothetest instructionregister,testdataregister,and programmabletestaddress(JTAG). TDO 78 I/O PullDown Fixed,100uA Testdataout.TDO outputsserialdatafromthe testinstructionregister,testdataregister, identificationregister,and programmabletest address(JTAG). TMS 75 I/O PullUp Fixed,100uA SerialinputforcontrollingthestateoftheCPU testaccessport(TAP)controller(JTAG) TEST 24 I/O PullDown Fixed,100uA Testenable.Reservedforinternaluse only.This terminalhas a glitchfilter. Forproperoperation,thisterminalmust be connectedtoground,e.g.usinga external resistor.

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2.2.13 Flash

Table2-13.Flash Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ FLTP1 3 Input - - FlashTestPad 1.Forproperoperationthis terminalmust connectonlytoa testpad ornotbe connectedatall[noconnect(NC)]. The testpad must notbe exposed inthefinal productwhere itmightbe subjectedtoan ESD event. FLTP2 4 Input - - FlashTestPad 2.Forproperoperationthis terminalmust connectonlytoa testpad ornotbe connectedatall[noconnect(NC)]. The testpad must notbe exposed inthefinal productwhere itmightbe subjectedtoan ESD event. VCCP 96 Input - - Flashexternalpump voltage(3.3V).This terminalisrequiredforbothFlashreadand Flash programand eraseoperations.

2.2.14 Core Supply

Table2-14.Core Supply Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ VCC 13 - - - Digitallogicand RAM supply VCC 21 VCC 30 VCC 32 VCC 61 VCC 88 VCC 99

2.2.15 I/OSupply

Table2-15.I/OSupply Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ VCCIO 6 - - - I/OSupply VCCIO 28 VCCIO 60 VCCIO 85 Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 13 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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2.2.16 Core and I/OSupply Ground Reference

Table2-16.Core and I/OSupply Ground Reference Terminal Signal Default PullType Description Type PullStateSignalName 100 PZ VSS 7 - - - DeviceGround Reference.Thisisa single groundreferenceforallsuppliesexceptfortheVSS 17 ADC Supply. VSS 20 VSS 29 VSS 33 VSS 59 VSS 72 VSS 86 VSS 87 VSS 100

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2.3 Output Multiplexingand Control

Output multiplexingwillbe utilizedin the device.The multiplexingisutilizedto allowdevelopmentof additionalpackage/featurecombinationsas wellas to maintainpinoutcompatibilitywiththe marketing devicefamily. Inallcasesindicatedas multiplexed,theoutputbuffersaremultiplexed. Table2-17.Output Mux Options 100PZ Pin DefaultFunction Control1 Option2 Control2 Option 3 Control3

1 GIOA[0] PINMMR0[8] SPI3nCS[3] PINMMR0[9] - -

2 GIOA[1] PINMMR1[0] SPI3nCS[2] PINMMR1[1] - -

5 GIOA[2] PINMMR1[8] SPI3nCS[1] PINMMR1[9] - -

8 GIOA[3] PINMMR1[16] SPI2nCS[3] PINMMR1[17] - -

9 GIOA[4] PINMMR1[24] SPI2nCS[2] PINMMR1[25] - -

10 GIOA[5] PINMMR2[0] EXTCLKIN PINMMR2[1] - -

12 GIOA[6] PINMMR2[8] SPI2nCS[1] PINMMR2[9] N2HET[31] PINMMR2[10]

18 GIOA[7] PINMMR2[16] N2HET[29] PINMMR2[17] - -

93 MIBSPI1nCS[1] PINMMR6[8] EQEPS PINMMR6[9] N2HET[17] PINMMR6[10]

27 MIBSPI1nCS[2] PINMMR3[0] N2HET[20] PINMMR3[1] N2HET[19] PINMMR3[2]

39 MIBSPI1nCS[3] PINMMR4[8] N2HET[26] PINMMR4[9] - -

68 MIBSPI1nENA PINMMR5[8] N2HET[23] PINMMR5[9] N2HET[30] PINMMR5[10]

36 SPI3CLK PINMMR3[16] EQEPA PINMMR3[17] - -

38 SPI3nCS[0] PINMMR4[0] EQEPI PINMMR4[1] - -

37 SPI3nENA PINMMR3[24] EQEPB PINMMR3[25] - -

58 ADEVT PINMMR4[16] N2HET[28] PINMMR4[17] - -

2.3.1 Notes on Output Multiplexing

Table2-17shows theoutputsignalmultiplexingand controlsignalsforselectingthedesiredfunctionality foreach pin.

• The pinsdefaulttothesignaldefinedby the"DefaultFunction"column inTable2-17
• The "CTRL x"columns indicatethemultiplexingcontrolregisterand thebitthatmust be setinorderto selectthecorrespondingfunctionalitytobe outputon any particularpin. Forexample,considerthemultiplexingon pin18,shown below. Table2-18.Muxing Example 100PZ Pin DefaultFunction Control1 Option2 Control2 Option 3 Control3
• When GIOA[7]isconfiguredas an outputpinintheGIO module controlregister,thentheprogrammed outputlevelappearson pin18 by default.The PINMMR2[16] bitissetby defaulttoindicatethatthe GIOA[7]signalisselectedtobe output.
• Iftheapplicationneeds tooutputtheN2HET[29] signalon pin18,itmust clearPINMMR2[16] and set PINMMR2[17].
• Note thatthepinisconnectedas inputtoboththeGIO and N2HET modules.Thatis,thereisno input multiplexingon thispin.

2.3.2 GeneralRules forMultiplexingControlRegisters

• The PINMMR controlregisterscan onlybe writteninprivilegedmode. A writeina non–privilegedmode willgeneratean errorresponse.
• Iftheapplicationwritesall0’s toany PINMMR controlregister,thenthedefaultfunctionsareselected fortheaffectedpins. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 15 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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• Each byte in a PINMMR controlregisterisused to selectthe functionalityfora givenpin.Ifthe applicationsetsmore thanone bitwithina byteforany pin,thenthedefaultfunctionisselectedforthis pin.
• Some bitswithinthePINMMR registerscouldbe associatedwithinternalpads thatarenotbroughtout inthe100 pinpackage.As a result,bitsmarked reservedshouldnotbe writtenas a 1.

2.4 SpecialMultiplexedOptions

Specialcontrolsare implementedtoaffectparticularfunctionson thismicrocontroller.These controlsare describedinthissection.

2.4.1 FilteringforeQEP Inputs

2.4.1.1 eQEPA Input

• When PINMMR8[0] = 1,theeQEPA inputisdouble-synchronizedusingVCLK.
• When PINMMR8[0] = 0 and PINMMR8[1] = 1, the eQEPA inputisdouble-synchronizedand then qualifiedthrougha fixed6-bitcounterusingVCLK.
• PINMMR8[0] = 0 and PINMMR8[1] = 0 isan illegalcombinationand behaviordefaultstoPINMMR8[0] = 1. 2.4.1.2 eQEPB Input
• When PINMMR8[8] = 1,theeQEPB inputisdouble-synchronizedusingVCLK.
• When PINMMR8[8] = 0 and PINMMR8[9] = 1, the eQEPB inputisdouble-synchronizedand then qualifiedthrougha fixed6-bitcounterusingVCLK.
• PINMMR8[8] = 0 and PINMMR8[9] = 0 isan illegalcombinationand behaviordefaultstoPINMMR8[8] = 1. 2.4.1.3 eQEPI Input
• When PINMMR8[16] = 1,theeQEPI inputisdouble-synchronizedusingVCLK.
• When PINMMR8[16] = 0 and PINMMR8[17] = 1, the eQEPI inputisdouble-synchronizedand then qualifiedthrougha fixed6-bitcounterusingVCLK.
• PINMMR8[16] = 0 and PINMMR8[17] = 0 is an illegalcombinationand behaviordefaultsto PINMMR8[16] = 1. 2.4.1.4 eQEPS Input
• When PINMMR8[24] = 1,theeQEPS inputisdouble-synchronizedusingVCLK.
• When PINMMR8[24] = 0 and PINMMR8[25] = 1, the eQEPS inputisdouble-synchronizedand then qualifiedthrougha fixed6-bitcounterusingVCLK.
• PINMMR8[24] = 0 and PINMMR8[25] = 0 is an illegalcombinationand behaviordefaultsto PINMMR8[24] = 1.

2.4.2 N2HET PIN_nDISABLE InputPort

• When PINMMR9[0] = 1,GIOA[5]isconnecteddirectlytoN2HET PIN_nDISABLE inputoftheN2HET module.
• When PINMMR9[0] = 0 and PINMMR9[1] = 1,EQEPERR isinvertedand double-synchronizedusing VCLK beforeconnectingdirectlytotheN2HET PIN_nDISABLE inputoftheN2HET module.
• PINMMR9[0] = 0 and PINMMR9[1] = 0 isan illegalcombinationand behaviordefaultstoPINMMR9[0] = 1.

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3 Device OperatingConditions

3.1 AbsoluteMaximum RatingsOver OperatingFree-AirTemperature Range, (1)

VCC (2) -0.3V to1.43V Supplyvoltagerange: VCCIO ,VCCP (2) -0.3V to4.1V VCCAD -0.3V to3.6V Allinputpins -0.3V to4.1V Inputvoltagerange: ADC inputpins -0.3V to5 V IIK (VI< 0 orVI> VCCIO ) ±20 mA Allpins,exceptADIN [21:20,17:16,11:0] Inputclamp current: IIK (VI< 0 orVI> VCCAD ) ±10 mA Total ±40 mA Operatingfree-airtemperaturerange,TA: -40°C to125°C Operatingjunctiontemperaturerange,TJ: -40°C to150°C Storagetemperaturerange,Tstg -65°C to150°C (1) Stressesbeyond thoselistedunder“absolutemaximum ratings”may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder“recommended operating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.Allvoltagevaluesarewithrespecttotheirassociated grounds.

3.2 Device Recommended OperatingConditions(1)

VCC Digitallogicsupplyvoltage(Core) 1.14 1.2 1.32 V VCCIO Digitallogicsupplyvoltage(I/O) 3 3.3 3.6 V VCCAD /VADREFHI MibADC supplyvoltage/A-to-Dhigh-voltagereferencesource 3 3.3 3.6 V VCCP Flashpump supplyvoltage 3 3.3 3.6 V VSS Digitallogicsupplyground 0 V VSSAD /VADREFLO MibADC supplyground/A-to-Dlow-voltagereferencesource -0.1 0.1 V TA Operatingfree-airtemperature -40 125 °C TJ Operatingjunctiontemperature -40 150 °C (1) AllvoltagesarewithrespecttoVSS ,exceptVCCAD ,whichiswithrespecttoVSSAD Copyright© 2012,Texas InstrumentsIncorporated DeviceOperatingConditions 17 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW Address Waitstates Data Waitstates RAM Address Waitstates Data Waitstates Flash 0MHz 0MHz 0MHz 80MHz Data Waitstates EEPROM Flash (BUS2) 0MHz 0MHz 80MHz 80MHz 80MHz 80MHz Address Waitstates 0MHz 0 2 80MHz16MHz 50MHz 33MHz 3 4 67MHz 0 1 45MHz TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

3.3 SwitchingCharacteristicsover Recommended OperatingConditionsforClock Domains

Table3-1.Clock Domain Timing Specifications(1) Parameter Description Conditions MIN MAX Unit fOSC OSC -oscillatorclockfrequency 5 20 MHz fRCLK Post-ODCLK – PLL Post-dividerinputclock 400 MHz frequency fODCLK VCOCLK – PLL OutputDivider(OD) input 500 MHz clockfrequency fHCLK HCLK -System clockfrequency 80 MHz fGCLK GCLK -CPU clockfrequency(ratiofGCLK : fHCLK MHz fHCLK = 1:1) fVCLK VCLK -Primaryperipheralclockfrequency 80 MHz fVCLKA1 VCLKA1 -Primaryasynchronous 80 MHz peripheralclockfrequency fRTICLK RTICLK -clockfrequency fVCLK MHz fPROG/ERASE System clockfrequency-Flash fHCLK MHz programming/erase (1) The maximum frequencythatcan be outputon theECLK signalisdependenton thecapacitiveloadingon thissignal.The ECLK signal has a selectable2mA /8mA outputbuffer.

3.4 Wait StatesRequired

Figure3-1.Wait StatesScheme As shown inthefigureabove,theTCM RAM can supportprogram and datafetchesatfullCPU speed without any addressordatawaitstatesrequired. The TCM flashcan supportzeroaddressand datawaitstatesup toa CPU speed of45MHz innon-pipelined mode. The flashsupportsa maximum CPU clockspeed of80MHz inpipelinedmode withno addresswaitstates and one datawaitstate. The flashwrapperdefaultstonon-pipelinedmode withzeroaddresswaitstateand one random-readdatawait state.

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3.5 Power Consumption Over Recommended OperatingConditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fHCLK = 80MHz VCC digitalsupplycurrent(operatingmode) 135 mAfVCLK = 80MHz, Flash in pipelined mode, VCCmax ICC LBIST clock rate =VCC Digitalsupplycurrent(LBISTmode) 145 mA 45MHz Peak PBIST ROM clock 135VCC Digitalsupplycurrent mAfrequency= 80MHz(PBIST mode) RMS ICCIO VCCIO Digitalsupplycurrent(operatingmode. No DC load,VCCmax 15 mA ICCAD VCCAD supplycurrent(operatingmode) VCCADmax 15 mA ICCREFHI AD REFHI supplycurrent(operatingmode) AD REFHImax 5 mA readoperation 34 VCCPmax program,VCCPmax 37 ICCP VCCP pump supplycurrent mAreadfromone bank 55 and program another,VCCPmax erase,VCCPmax 27 Copyright© 2012,Texas InstrumentsIncorporated DeviceOperatingConditions 19 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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3.6 Input/OutputElectricalCharacteristicsOver Recommended OperatingConditions(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vhys Inputhysteresis Allinputs 180 mV VIL Low-levelinputvoltage Allinputs(2) -0.3 0.8 V VIH High-levelinputvoltage Allinputs(2) 2 VCCIO + 0.3 V IOL = IOLmax 0.2VCCIO IOL = 50 µA, 0.2VOL Low-leveloutputvoltage V standardoutput mode IOH = IOHmax 0.8VCCIO IOH = 50 µA, VCCIO -0.2VOH High-leveloutputvoltage V standardoutput mode VI< VSSIO -0.3orVI -2 2IIC Inputclamp current(I/Opins) mA> VCCIO + 0.3 IIH Pulldown20µA VI= VCCIO 5 40 IIH Pulldown100µA VI= VCCIO 40 195 IILPullup20µA VI= VSS -40 -5II Inputcurrent(I/Opins) µA IILPullup100µA VI= VSS -195 -40 No pullupor -1 1Allotherpins pulldown C I Inputcapacitance 2 pF C O Outputcapacitance 3 pF (1) Sourcecurrents(outofthedevice)arenegativewhilesinkcurrents(intothedevice)arepositive. (2) Thisdoes notapplytothenPORRST pin.

3.7 Output BufferDriveStrengths

Table3-2.Output BufferDriveStrengths Low-levelOutput Current, IOL forVI=VOLmax or Signals High-levelOutput Current, IOH forVI=VOHmin EQEPI, EQEPS, 8mA TMS, TDI,TDO, RTCK, nERROR TEST, 4mA MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, SPI3CLK, SPI3SIMO, SPI3SOMI, nRST AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, GIOA[0-7], LINRX, LINTX,2mA zero-dominant MIBSPI1NCS[0-3],MIBSPI1NENA N2HET[0],N2HET[2],N2HET[4],N2HET[6],N2HET[8],N2HET[10],N2HET[12],N2HET[14], N2HET[16],N2HET[18],N2HET[22],N2HET[24], SPI2NCS[0-3],SPI3NENA

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PRODUCT□PREVIEW VCCIO V IH VIH VIL Input tpw V IL TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Table3-2.Output BufferDriveStrengths (continued) Low-levelOutput Current, IOL forVI=VOLmax or Signals High-levelOutput Current, IOH forVI=VOHmin ECLK, selectable8mA /2mA SPI2CLK, SPI2SIMO, SPI2SOMI The defaultoutputbufferdrivestrengthis8mA forthesesignals.

3.8 InputTimings

Figure3-2.TTL-LevelInputs Table3-3.Timing Requirements forInputs(1) Parameter MIN MAX Unit tpw Inputminimum pulsewidth tc(VCLK) + 10(2) ns tin_slew Time forinputsignaltogo fromVILtoVIH orfromVIH toVIL 1 ns (1) tc(VCLK) = peripheralVBUS clockcycletime= 1 /f(VCLK) (2) The timingshown above isonlyvalidforpinused inGIO mode.

3.9 Output Timings

Table3-4.SwitchingCharacteristicsforOutput Timings versus Load Capacitance(CL) Parameter MIN MAX Unit Risetime,tr 8mA pins CL = 15 pF 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Falltime,tf CL = 15 pF 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Risetime,tr 4mA pins CL = 15 pF 5.6 ns CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Falltime,tf CL = 15 pF 5.6 ns CL= 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Copyright© 2012,Texas InstrumentsIncorporated DeviceOperatingConditions 21 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW tftr VCCIO V OH VOH VOL VOL Output TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table3-4.SwitchingCharacteristicsforOutput Timings versus Load Capacitance(CL)(continued) Parameter MIN MAX Unit Risetime,tr 2mA-z pins CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Falltime,tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Risetime,tr Selectable8mA /2mA-z 8mA mode CL = 15 pF 2 ns pins CL = 50 pF 4 CL = 100 pF 8 CL = 150 pF 11 Falltime,tf CL = 15 pF 2 ns CL = 50 pF 4 CL = 100 pF 8 CL = 150 pF 11 Risetime,tr 2mA-z mode CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Falltime,tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Figure3-3.CMOS-Level Outputs Table3-5.Timing Requirements forOutputs(1) Parameter MIN MAX UNIT td(parallel_out) Delaybetween lowtohigh,orhightolowtransitionofgeneral-purposeoutputsignals 5 ns thatcan be configuredby an applicationinparallel,e.g.allsignalsina GIOA port,or allN2HET signals. (1) Thisspecificationdoes notaccountforany outputbufferdrivestrengthdifferencesorany externalcapacitiveloadingdifferences.Check Table3-2foroutputbufferdrivestrengthinformationon each signal.

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4 System Informationand ElectricalSpecifications

4.1 VoltageMonitorCharacteristics

A voltagemonitorisimplementedon thisdevice.The purposeofthisvoltagemonitoristoeliminatethe requirementfora specificsequence when poweringup thecoreand I/Ovoltagesupplies.

4.1.1 ImportantConsiderations

• The voltagemonitordoes noteliminatetheneed ofa voltagesupervisorcircuittoguaranteethatthe deviceisheldinresetwhen thevoltagesuppliesareoutofrange.
• The voltagemonitoronlymonitorsthe core supply(VCC) and the I/O supply(VCCIO). The other suppliesare notmonitoredby theVMON. For example,iftheVCCAD or VCCP are suppliedfrom a sourcedifferentfrom thatforVCCIO, then thereisno internalvoltagemonitorforthe VCCAD and VCCP supplies.

4.1.2 VoltageMonitorOperation

The voltagemonitorgeneratesthePower Good MCU signal(PGMCU) as wellas theI/OsPower Good IO signal(PGIO)on thedevice.Duringpower-uporpower-down,thePGMCU and PGIO aredrivenlowwhen the core or I/O suppliesare lowerthan the specifiedminimum monitoringthresholds.The PGIO and PGMCU beinglow isolatesthecorelogicas wellas theI/Ocontrolsduringthepower-uporpower-down ofthesupplies.Thisallowsthecoreand I/Osuppliestobe powered up ordown inany order. When thevoltagemonitordetectsa low voltageon theI/Osupply,itwillasserta power-onreset.When thevoltagemonitordetectsan out-of-rangevoltageon thecoresupply,itasynchronouslymakes alloutput pinshighimpedance,and assertsa power-on reset.The voltagemonitorisdisabledwhen the device entersa lowpower mode. The VMON alsoincorporatesa glitchfilterforthenPORRST input.RefertoSection4.2.3.1forthetiming informationon thisglitchfilter. Table4-1.VoltageMonitoringSpecifications PARAMETER MIN TYP MAX UNIT VCC low-VCC levelbelowthis 0.8 0.9 1.0 V thresholdisdetectedas toolow. Voltagemonitoring VCC high-VCC levelabove this 1.35 1.7 2.1VMON thresholds thresholdisdetectedas toohigh. VCCIO low-VCCIO levelbelowthis 1.9 2.4 2.9 thresholdisdetectedas toolow.

4.1.3 Supply Filtering

The VMON has thecapabilitytofilterglitcheson theVCC and VCCIO supplies. The followingtableshows thecharacteristicsofthesupplyfiltering.Glitchesinthesupplylargerthanthe maximum specificationcannotbe filtered. Table4-2.VMON Supply GlitchFilteringCapability Parameter MIN MAX Widthofglitchon VCC thatcan be filtered 250ns 1us Widthofglitchon VCCIO thatcan be filtered 250ns 1us Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 23 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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4.2 Power Sequencing and Power On Reset

4.2.1 Power-Up Sequence

There isno timingdependency between theramp oftheVCCIO and theVCC supplyvoltage.The power- up sequence startswiththeI/Ovoltagerisingabove theminimum I/Osupplythreshold,(seeTable4-4for more details),corevoltagerisingabove theminimum coresupplythresholdand thereleaseofpower-on reset.The highfrequencyoscillatorwillstartup firstand itsamplitudewillgrow toan acceptablelevel.The oscillatorstartup timeisdependenton thetypeofoscillatorand isprovidedby theoscillatorvendor.The differentsuppliestothedevicecan be powered up inany order. The devicegoes throughthefollowingsequentialphases duringpower up. Table4-3.Power-Up Phases Oscillatorstart-upand validitycheck 1032 oscillatorcycles eFuse autoload 1180 oscillatorcycles Flashpump power-up 688 oscillatorcycles Flashbank power-up 617 oscillatorcycles Total 3517 oscillatorcycles The CPU resetisreleasedattheend oftheabove sequence and fetchesthefirstinstructionfromaddress 0x00000000.

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3.3 V VCCIOPORH

1.2 V VCCPORH VCCIOPORL V (1.2 V) V / V (3.3 V) CC CCIO CCP nPORRST 6 6 VCCPORL VIL(PORRST) V / VCCIO CCP VCC VCCPORL VIL(PORRST)VIL VIL VIL VCCIOPORH VCCPORH VCCIOPORL NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

4.2.2 Power-Down Sequence

The differentsuppliestothedevicecan be powered down inany order.

4.2.3 Power-On Reset:nPORRST

Thisresetmust be assertedby an externalcircuitrywhenever the I/Oor core suppliesare outsidethe recommended range.Thissignalhas a glitchfilteron it.Italsohas an internalpulldown. 4.2.3.1 nPORRST Electricaland Timing Requirements Table4-4.ElectricalRequirements fornPORRST NO Parameter MIN MAX Unit VCCPORL VCC lowsupplylevelwhen nPORRST must be activeduringpower- 0.5 V up VCCPORH VCC highsupplylevelwhen nPORRST must remainactiveduring 1.14 V power-upand become activeduringpower down VCCIOPORL VCCIO /VCCP lowsupplylevelwhen nPORRST must be activeduring 1.1 V power-up VCCIOPORH VCCIO /VCCP highsupplylevelwhen nPORRST must remainactive 3.0 V duringpower-upand become activeduringpower down VIL(PORRST) Low-levelinputvoltageofnPORRST VCCIO > 2.5V 0.2*VCCIO V Low-levelinputvoltageofnPORRST VCCIO < 2.5V 0.5 V 3 tsu(PORRST) Setuptime,nPORRST activebeforeVCCIO and VCCP > VCCIOPORL 0 ms duringpower-up 6 th(PORRST) Holdtime,nPORRST activeafterVCC > VCCPORH 1 ms 7 tsu(PORRST) Setuptime,nPORRST activebeforeVCC < VCCPORH duringpower 2 µs down 8 th(PORRST) Holdtime,nPORRST activeafterVCCIO and VCCP > VCCIOPORH 1 ms 9 th(PORRST) Holdtime,nPORRST activeafterVCC < VCCPORL 0 ms tf(nPORRST) FiltertimenPORRST pin; 500 2000 ns PulseslessthanMIN willbe filteredout,pulsesgreaterthanMAX willgeneratea reset. Figure4-1.nPORRST Timing Diagram Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 25 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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4.3 Warm Reset (nRST)

Thisisa bidirectionalresetsignal.The internalcircuitrydrivesthesignallow on detectingany devicereset condition.An externalcircuitcan asserta deviceresetby forcingthe signallow.On thisterminal,the outputbufferisimplementedas an open drain(driveslow only).To ensure an externalresetisnot arbitrarilygenerated,TIrecommends thatan externalpullupresistorisconnectedtothisterminal. Thisterminalhas a glitchfilter.Italsohas an internalpullup

4.3.1 Causes ofWarm Reset

Table4-5.Causes ofWarm Reset DEVICE EVENT SYSTEM STATUS FLAG Power-Up Reset ExceptionStatusRegister,bit15 Oscillatorfail GlobalStatusRegister,bit0 PLL slip GlobalStatusRegister,bits8 and 9 Watchdog exception/Debugger reset ExceptionStatusRegister,bit13 CPU Reset(drivenby theCPU STC) ExceptionStatusRegister,bit5 SoftwareReset ExceptionStatusRegister,bit4 ExternalReset ExceptionStatusRegister,bit3 4.3.2 nRST Timing Requirements Table4-6.nRST Timing Requirements(1) PARAMETER MIN MAX UNIT tv(RST) Validtime,nRST activeafter eFuse autoloadtime+ ns nPORRST inactive 1048tc(OSC) Validtime,nRST active(allother 8tc(VCLK) System resetconditions) tf(nRST) FiltertimenRST pin; 500 2000 ns PulseslessthanMIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset (1) Specifiedvaluesdo NOT includerise/falltimes.Forriseand falltimings,see Table3-4.

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4.4 ARM © Cortex-R4™ CPU Information

4.4.1 Summary ofARM Cortex-R4CPU Features

The featuresoftheARM Cortex-R4™ CPU include:

• An integerunitwithintegralEmbedded ICE-RT logic.
• High-speedAdvanced MicroprocessorBus Architecture(AMBA) Advanced eXtensibleInterfaces(AXI) forLeveltwo (L2)masterand slaveinterfaces.
• Dynamic branchpredictionwitha globalhistorybuffer,and a 4-entryreturnstack
• Low interruptlatency.
• Non-maskableinterrupt.
• A HarvardLevelone (L1)memory systemwith: – Tightly-CoupledMemory (TCM) interfaceswith supportforerrorcorrectionor paritychecking memories – ARMv7-R architectureMemory ProtectionUnit(MPU) with8 regions
• Dualcorelogicforfaultdetectioninsafety-criticalapplications.
• An L2 memory interface: – Single64-bitmasterAXI interface – 64-bitslaveAXI interfacetoTCM RAM blocks
• A debug interfacetoa CoreSightDebug Access Port(DAP).
• A VectoredInterruptController(VIC)port. Formore informationon theARM Cortex-R4CPU pleasesee www.arm.com .

4.4.2 ARM Cortex-R4CPU FeaturesEnabled by Software

The followingCPU featuresaredisabledon resetand must be enabledby theapplicationifrequired.

• ECC On Tightly-CoupledMemory (TCM) Accesses
• Hardware VectoredInterrupt(VIC)Port
• Memory ProtectionUnit(MPU)

4.4.3 Dual Core Implementation

The devicehas two Cortex-R4cores,where theoutputsignalsofbothCPUs arecompared intheCCM- R4 unit.To avoidcommon mode impactsthesignalsoftheCPUs tobe compared aredelayedby 2 clock cyclesas shown inFigure4-3. The CPUs have a diverseCPU placementgivenby followingrequirements:

• differentorientation;e.g.CPU1 = "north"orientation,CPU2 = "flipwest"orientation
• dedicatedguardringforeach CPU Figure4-2.Dual -CPU Orientation

4.4.4 DuplicateclocktreeafterGCLK

The CPU clockdomain issplitintotwo clocktrees,one foreach CPU, withthe clockof the 2nd CPU runningatthesame frequencyand inphase totheclockofCPU1. See Figure4-3. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 27 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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4.4.5 ARM Cortex-R4CPU Compare Module (CCM) forSafety

Thisdevicehas two ARM Cortex-R4CPU cores,where theoutputsignalsofbothCPUs arecompared in theCCM-R4 unit.To avoidcommon mode impactsthesignalsoftheCPUs tobe compared aredelayedin a differentway as shown inthefigurebelow. Figure4-3.Dual Core Implementation To avoidan erroneousCCM-R4 compare error,the applicationsoftwaremust initializethe registersof both CPUs beforethe registersare used,includingfunctioncallswhere the registervaluesare pushed ontothestack.

4.4.6 CPU Self-Test

The CPU STC (Self-TestController)isused totestthetwo Cortex-R4CPU Cores usingtheDeterministic LogicBIST Controlleras thetestengine. The main featuresoftheself-testcontrollerare:

• Abilitytodividethecompletetestrunintoindependenttestintervals
• Capableofrunningthecompletetestorrunninga few intervalsata time
• Abilitytocontinuefrom thelastexecutedinterval(testset)or torestartfrom thebeginning(Firsttest set)
• Completeisolationoftheself-testedCPU corefromtherestofthesystemduringtheself-testrun
• Abilitytocapturethefailureintervalnumber
• TimeoutcounterfortheCPU self-testrunas a fail-safefeature

4.4.6.1 ApplicationSequence forCPU Self-Test

1. Configureclockdomain frequencies. 2. Selectthenumber oftestintervalstobe run. 3. Configurethetimeoutperiodfortheself-testrun.

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 4. Save theCPU stateifrequired 5. Enableself-test. 6. WaitforCPU reset. 7. Intheresethandler,readCPU self-teststatustoidentifyany failures. 8. RetrieveCPU stateifrequired. Formore informationrefertothedevicetechnicalreferencemanual.

4.4.6.2 CPU Self-TestClock Configuration

The maximum clockratefortheself-testis45MHz. The STCCLK isdivideddown from theCPU clock, when necessary.Thisdividerisconfiguredby theSTCCLKDIV registerataddress0xFFFFE108. Formore informationsee thedeviceTechnicalReferenceManual..

4.4.6.3 CPU Self-TestCoverage

Table4-7 shows CPU testcoverageachievedforeach self-testinterval.Italsoliststhecumulativetest cycles.The testtimecan be calculatedby multiplyingthenumber oftestcycleswiththeSTC clockperiod. Table4-7.CPU Self-TestCoverage INTERVALS TEST COVERAGE, % TEST CYCLES 0 0 0 1 60.06 1365 2 68.71 2730 3 73.35 4095 4 76.57 5460 5 78.7 6825 6 80.4 8190 7 81.76 9555 8 82.94 10920 9 83.84 12285 10 84.58 13650 11 85.31 15015 12 85.9 16380 13 86.59 17745 14 87.17 19110 15 87.67 20475 16 88.11 21840 17 88.53 23205 18 88.93 24570 19 89.26 25935 20 89.56 27300 21 89.86 28665 22 90.1 30030 23 90.36 31395 24 90.62 32760 25 90.86 34125 26 91.06 35490 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 29 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW OSCIN OSCOUT (see Note A) Crystal (a) OSCIN OSCOUT (b) External (toggling 0-3.3V) Clock Signal Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor. Kelvin_GND Note B: Kelvin_GND should not be connected to any other GND. (see Note B) TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

4.5 Clocks

4.5.1 Clock Sources

The tablebelow liststheavailableclocksourceson thedevice.Each oftheclocksourcescan be enabled or disabledusingthe CSDISx registersin the system module. The clocksource number in the table correspondstothecontrolbitintheCSDISx registerforthatclocksource. The tablealsoshows thedefaultstateofeach clocksource. Table4-8.AvailableClock Sources Clock Name Description DefaultStateSource #

0 OSCIN Main Oscillator Enabled

1 PLL1 OutputFrom PLL1 Disabled

2 Reserved Reserved Disabled

3 EXTCLKIN1 ExternalClockInput#1 Disabled

4 CLK80K Low FrequencyOutputofInternalReferenceOscillator Enabled

HighFrequencyOutputofInternalReference5 CLK10M EnabledOscillator

6 Reserved Reserved Disabled

7 Reserved Reserved Disabled

4.5.1.1 Main Oscillator

The oscillatorisenabledby connectingtheappropriatefundamentalresonator/crystaland loadcapacitors acrossthe externalOSCIN and OSCOUT pinsas shown inFigure4-4. The oscillatorisa singlestage inverterheld in bias by an integratedbias resistor.This resistoris disabledduringleakage test measurement and lowpower modes. TI stronglyencourages each customer to submit samples of the device to the resonator/crystal vendors forvalidation.The vendors are equipped to determinewhat load capacitorswillbest tune theirresonator/crystalto the microcontrollerdevice for optimum start-upand operation over temperature/voltageextremes. An externaloscillatorsourcecan be used by connectinga 3.3V clocksignaltotheOSCIN pinand leaving theOSCOUT pinunconnected(open)as shown inthefigurebelow. Figure4-4.Recommended Crystal/ClockConnection

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 4.5.1.1.1Timing Requirements forMain Oscillator Table4-9.Timing Requirements forMain Oscillator Parameter MIN Type MAX Unit tc(OSC) Cycletime,OSCIN (when usinga sine-waveinput) 50 200 ns tc(OSC_SQR) Cycletime,OSCIN, (when inputtotheOSCIN isa 12.5 200 ns squarewave ) tw(OSCIL) Pulseduration,OSCIN low(when inputtotheOSCIN 6 ns isa squarewave) tw(OSCIH) Pulseduration,OSCIN high(when inputtotheOSCIN 6 ns isa squarewave) Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 31 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW BIAS_EN Low Power Oscillator LFEN LF_TRIM HFEN HF_TRIM CLK80K CLK10M CLK10M_V ALID nPORRST TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

4.5.1.2 Low Power Oscillator

The Low Power Oscillator(LPO) iscomprisedof two oscillators— HF LPO and LF LPO, ina single macro. 4.5.1.2.1Features The main featuresoftheLPO are:

• Suppliesa clockatextremelylow power forpower-savingmodes. Thisisconnectedas clocksource# 4 oftheGlobalClockModule.
• Suppliesa high-frequencyclockfornon-timing-criticalsystems.Thisisconnectedas clocksource# 5 oftheGlobalClockModule.
• Providesa comparisonclockforthecrystaloscillatorfailuredetectioncircuit. Figure4-5.LPO Block Diagram Figure4-5shows a blockdiagramoftheinternalreferenceoscillator.Thisisa low power oscillator(LPO) and providestwo clocksources:one nominally80KHz and one nominally10MHz. 4.5.1.2.2LPO Electricaland Timing Specifications Table4-10.LPO Specifications Parameter MIN Type MAX Unit LPO -HF oscillator untrimmedfrequency 5.5 9.6 19.5 MHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 10 µs atleast900µs) coldstartuptime 900 µs LPO -LF oscillator untrimmedfrequency 36 85 180 kHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 100 µs atleast900µs) coldstartuptime 2000 µs

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PRODUCT□PREVIEW /NR /1 to /64 OSCIN PLL INTCLK /OD /1 to /8 VCOCLK /R /1 to /32 post_ODCLK /NF /1 to /256 PLLCLK fPLLCLK = (fOSCIN / NR) * NF / (OD * R) TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

4.5.1.3 Phase Locked Loop (PLL)Clock Modules

The PLL isused tomultiplytheinputfrequencytosome higherfrequency. The main featuresofthePLL are:

• Frequencymodulationcan be optionallysuperimposedon thesynthesizedfrequencyofPLL.
• Configurablefrequencymultipliersand dividers.
• Built-inPLL Slipmonitoringcircuit.
• Optiontoresetthedeviceon a PLL slipdetection. 4.5.1.3.1Block Diagram Figurebelowshows a high-levelblockdiagramofthePLL macro on thismicrocontroller. Figure4-6.PLL Block Diagram

4.5.2 Clock Domains

4.5.2.1 Clock Domain Descriptions

The tablebelow liststhedeviceclockdomains and theirdefaultclocksources.The tablealsoshows the systemmodule controlregisterthatisused toselectan availableclocksourceforeach clockdomain. Table4-11.Clock Domain Descriptions Clock Domain Name DefaultClock Clock Source Description Source SelectionRegister HCLK OSCIN GHVSRC • IsdisabledviatheCDDISx registersbit1 GCLK OSCIN GHVSRC • Alwaysthesame frequencyas HCLK

• Inphase withHCLK
• IsdisabledseparatelyfromHCLK viatheCDDISx registersbit0
• Can be dividedby 1 up to8 when runningCPU self-test (LBIST)usingtheCLKDIV fieldoftheSTCCLKDIV registerat address0xFFFFE108 GCLK2 OSCIN GHVSRC • Alwaysthesame frequencyas GCLK
• 2 cyclesdelayedfromGCLK
• IsdisabledalongwithGCLK
• Gets dividedby thesame dividersettingas thatforGCLK when runningCPU self-test(LBIST) VCLK OSCIN GHVSRC • Divideddown fromHCLK
• Can be HCLK/1, HCLK/2, ...orHCLK/16
• IsdisabledseparatelyfromHCLK viatheCDDISx registersbit2
• Can be disabledseparatelyforeQEP usingCDDISx registers bit9 VCLK2 OSCIN GHVSRC • Divideddown fromHCLK
• Can be HCLK/1, HCLK/2, ...orHCLK/16
• Frequencymust be an integermultipleofVCLK frequency
• IsdisabledseparatelyfromHCLK viatheCDDISx registersbit3 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 33 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table4-11.Clock Domain Descriptions(continued) Clock Domain Name DefaultClock Clock Source Description Source SelectionRegister VCLKA1 VCLK VCLKASRC • DefaultstoVCLK as thesource

• Frequencycan be as fastas HCLK frequency
• IsdisabledviatheCDDISx registersbit4 RTICLK VCLK RCLKSRC • DefaultstoVCLK as thesource
• Ifa clocksourceotherthanVCLK isselectedforRTICLK, then theRTICLK frequencymust be lessthanorequaltoVCLK/3 – Applicationcan ensurethisby programmingtheRTI1DIV fieldoftheRCLKSRC register,ifnecessary
• IsdisabledviatheCDDISx registersbit6

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PRODUCT□PREVIEW VCLK /1,2,..1024 Phase_seg2 CAN□Baud□Rate Phase_seg1 DCAN1,□2 AVCLK1 /1,2,..256 SPIx,MibSPIx /2,3..224 LIN SPI LIN /1,2..32 MibADC ADCLK /1,2..65536 External□Clock ECLK VCLK2 N2HET Prop_seg HRP /1..64 LRP /20..27 Loop Resolution□Clock High Baud□Rate Baud□Rate HET TU VCLK2 HCLK□(to□SYSTEM) GCLK,□GCLK2□(to□CPU) GCM VCLK□(to□System□and VCLK2□(to□N2HET) AVCLK1□(to□DCAN1,□2) VCLK /1..16 /1..16 RTICLK□(to□RTI+DWWD) /1,□2,□4,□or□8 VCLK OSCIN Low□Power Oscillator 10MHz 80kHz FMzPLL * The□frequency□at□this□node must□not exceed□the□maximum□HCLK□frequency. Peripheral□Modules) eQEP 3EXTCLKIN CDDISx.9 TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

4.5.2.2 Mapping ofClock Domains toDevice Modules

Each clockdomain has a dedicatedfunctionalityas shown inthefigurebelow. Figure4-7.Device Clock Domains Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 35 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

4.5.3 Clock TestMode

The TMS570 platformarchitecturedefinesa specialmode thatallowsvariousclocksignalstobe brought outon totheECLK pinand N2HET[2] deviceoutputs.Thismode iscalledtheClockTestmode. Itisvery usefulfordebuggingpurposesand can be configuredviatheCLKTEST registerinthesystemmodule. Table4-12.Clock TestMode Options CLKTEST[3-0] SIGNAL ON ECLK CLKTEST[11-8] SIGNAL ON N2HET[2]

0000 Oscillator 0000 OscillatorValidStatus

Main PLL free-runningclockoutput0001 0001 Main PLL Validstatus(PLLCLK)

0010 Reserved 0010 Reserved

0011 Reserved 0011 Reserved

0100 CLK80K 0100 Reserved

0101 CLK10M 0101 CLK10M Validstatus

0110 Reserved 0110 Reserved

0111 Reserved 0111 Reserved

1000 GCLK 1000 CLK80K

1001 RTI Base 1001 OscillatorValidstatus

1010 Reserved 1010 OscillatorValidstatus

1011 VCLKA1 1011 OscillatorValidstatus

1100 Reserved 1100 OscillatorValidstatus

1101 Reserved 1101 OscillatorValidstatus

1110 Reserved 1110 OscillatorValidstatus

1111 FlashHD Pump Oscillator 1111 OscillatorValidstatus

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PRODUCT□PREVIEW f[MHz]1.375 4.875 22 78 guaranteed fail lower threshold guaranteed pass upper threshold guaranteed fail TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

4.6 Clock Monitoring

The LPO ClockDetect(LPOCLKDET) module consistsofa clockmonitor(CLKDET) and an internallow power oscillator(LPO). The LPO providestwo differentclocksources – a low frequency(CLK80K) and a high frequency (CLK10M). The CLKDET isa supervisorcircuitforan externallysuppliedclocksignal(OSCIN).Incase theOSCIN frequencyfallsoutofa frequencywindow,theCLKDET flagsthisconditionintheglobalstatusregister (GLBSTAT bit0:OSC FAIL)and switchesallclockdomains sourcedby OSCIN totheCLK10M clock(limp mode clock). The validOSCIN frequencyrangeisdefinedas:fCLK10M /4 < fOSCIN < fCLK10M *4.

4.6.1 Clock MonitorTimings

Table4-13.LPO and Clock Detection Parameter MIN Type MAX Unit ClockDetection oscillatorfailfrequency-lowerthreshold,using 1.375 2.4 4.875 MHz untrimmedLPO output oscillatorfailfrequency-higherthreshold,using 22 38.4 78 MHz untrimmedLPO output LPO -HF oscillator untrimmedfrequency 5.5 9.6 19.5 MHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 10 µs atleast900ms) coldstartuptime 900 µs ICC,CLK10M and CLK80K active 150 µA LPO -LF oscillator untrimmedfrequency 36 85 180 kHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 100 µs atleast900ms) coldstartuptime 2000 µs ICC,onlyCLK80K active 27 µA LPO totalICC STANDBY current 20 µA Figure4-8.LPO and Clock Detection,Untrimmed CLK10M

4.6.2 ExternalClock (ECLK) Output Functionality

The ECLK pincan be configuredtooutputa pre-scaledclocksignalindicativeofan internaldeviceclock. Thisoutputcan be externallymonitoredas a safetydiagnostic.

4.6.3 Dual Clock Comparator

The Dual Clock Comparator (DCC) module determinesthe accuracyof selectableclocksources by countingthe pulsesof two independentclocksources(counter0 and counter1).Ifone clockisout of spec,an errorsignalisgenerated.For example,the DCC can be configuredto use CLK10M as the referenceclock(forcounter0) and VCLK as the "clockunder test"(forcounter1).Thisconfiguration allowstheDCC tomonitorthePLL outputclockwhen VCLK isusingthePLL outputas itssource. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 37 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com An additionaluse ofthismodule istomeasure thefrequencyofa selectableclocksource,usingtheinput clockas a reference,by countingthe pulsesof two independentclocksources.Counter0 generatesa fixed-widthcountingwindow aftera preprogrammed number ofpulses.Counter1 generatesa fixed-width pulse(1 cycle)aftera pre-programmednumber ofpulses.Thispulsesetsas an errorsignalifcounter1 does notreach0 withinthecountingwindow generatedby counter0.

4.6.3.1 Features

• Takes two differentclocksourcesas inputtotwo independentcounterblocks.
• One oftheclocksourcesistheknown-good,orreferenceclock;thesecond clocksourceisthe"clock undertest."
• Each counterblockisprogrammablewithinitial,orseed values.
• The counterblocksstartcountingdown fromtheirseed valuesatthesame time;a mismatch fromthe expectedfrequencyforthe clockunder testgeneratesan errorsignalwhich isused to interruptthe CPU.

4.6.3.2 Mapping ofDCC Clock Source Inputs

Table4-14.DCC Counter 0 Clock Sources TEST MODE CLOCK SOURCE [3:0] CLOCK NAME others oscillator(OSCIN) 0 0x5 highfrequencyLPO 0xA testclock(TCK)

1 X VCLK

Table4-15.DCC Counter 1 Clock Sources TEST MODE KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME others - N2HET[31] Main PLL free-runningclock0x0 output 0x1 n/a 0x2 lowfrequencyLPO 0xA 0x3 highfrequencyLPO0 0x4 flashHD pump oscillator 0x5 EXTCLKIN 0x6 n/a 0x7 ringoscillator 0x8 -0xF VCLK

1 X X HCLK

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4.7 GlitchFilters

A glitchfilterispresenton thefollowingsignals. Table4-16.GlitchFilterTiming Specifications Pin Parameter MIN MAX Unit nPORRST tf(nPORRST) 500 2000 nsFiltertimenPORRST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset(1) nRST tf(nRST) 500 2000 nsFiltertimenRST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset TEST tf(TEST) 500 2000 nsFiltertimeTEST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willpass through (1) The glitchfilterdesignon thenPORRST signalisdesignedsuch thatno sizepulsewillresetany partofthemicrocontroller(flashpump, I/Opins,etc.)withoutalsogeneratinga validresetsignaltotheCPU. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 39 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW Flash□(384KB) RAM□(32KB) 0x00000000 0x0005FFFF 0x08000000 0x08007FFF CRC0xFE000000 Peripherals -□Frame□1 0xFF000000 0xFFF7FFFF SYSTEM□Modules 0xFFF80000 0xFFFFFFFF 0xF0000000 RAM□-□ECC 0x08400000 0x08407FFF RESERVED RESERVED Flash□(384KB)□(Mirrored□Image) 0x20000000 0x2005FFFF RESERVED RESERVED 0xF07FFFFF RESERVED Flash□Module□Bus2□Interface (Flash□ECC,□OTP andEEPROM□accesses) Peripherals□-□Frame□2 0xFC000000 0xFCFFFFFF RESERVED TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

4.8 Device Memory Map

4.8.1 Memory Map Diagram

The figurebelowshows thedevicememory map. Figure4-9.TMS570LS043 2 Memory Map

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PRODUCT□PREVIEW Flash□(256KB) RAM□(32KB) 0x00000000 0x0003FFFF 0x08000000 0x08007FFF CRC0xFE000000 Peripherals -□Frame□1 0xFF000000 0xFFF7FFFF SYSTEM□Modules 0xFFF80000 0xFFFFFFFF 0xF0000000 RAM□-□ECC 0x08400000 0x08407FFF RESERVED RESERVED Flash□(256KB)□(Mirrored□Image) 0x20000000 0x2003FFFF RESERVED RESERVED 0xF07FFFFF RESERVED Flash□Module□Bus2□Interface (Flash□ECC,□OTP andEEPROM□accesses) Peripherals□-□Frame□2 0xFC000000 0xFCFFFFFF RESERVED TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Figure4-10.TMS570LS0332 Memory Map The Flashmemory inallconfigurationsismirroredtosupportECC logictesting.The base addressofthe mirroredFlashimage is0x2000 0000. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 41 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

4.8.2 Memory Map Table

PleaserefertoFigure1-1fora blockdiagramshowingthedeviceinterconnects. Table4-17.Device Memory Map FRAME ADDRESS RANGE RESPONSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME Memories tightlycoupled totheARM Cortex-R4CPU TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 384KB TCM RAM + RAM CSRAM0 0x0800_0000 0x0BFF_3FFF 64MB 32KBECC Abort FlashmirrorMirroredFlash 0x2000_0000 0x20FF_FFFF 16MB 384KBframe FlashModule Bus2 Interface Customer OTP, 0xF000_0000 0xF000_FFFF 64KB 2KBTCM FlashBanks Customer OTP, 0xF000_E000 0xF000_FFFF 8KB 1KBEEPROM Bank Customer OTP –ECC, TCM 0xF004_0000 0xF004_03FF 1KB 512B FlashBanks Customer OTP –ECC, 0xF004_1C00 0xF004_1FFF 1KB 128B EEPROM Bank TIOTP, TCM 0xF008_0000 0xF008_FFFF 64KB 2KBFlashBanks Abort TIOTP, EEPROM 0xF008_E000 0xF008_FFFF 8KB 1KBBank TIOTP –ECC, 0xF00C_0000 0xF00C_03FF 8KB 512BTCM FlashBanks TIOTP –ECC, 0xF00C_1C00 0xF00C_1FFF 1KB 128BEEPROM Bank EEPROM 0xF010_0000 0xF013_FFFF 256KB 2KBBank–ECC EEPROM Bank 0xF020_0000 0xF03F_FFFF 2MB 16KB FlashData Space 0xF040_0000 0xF04F_FFFF 1MB 48KBECC CyclicRedundancy Checker (CRC) Module Registers CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accessesabove 0x200 generateabort. PeripheralMemories MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128KB 2KB Abortforaccessesabove 2KB Wrap aroundforaccessesto unimplementedaddressoffsetslowerDCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128KB 2KB than0x7FF.Abortgeneratedfor accessesbeyond offset0x800. Wrap aroundforaccessesto unimplementedaddressoffsetslowerDCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128KB 2KB than0x7FF.Abortgeneratedfor accessesbeyond offset0x800. Wrap aroundforaccessesto MIBADC RAM 8KB unimplementedaddressoffsetslower than0x1FFF. Look-uptableforADC wrapper.StartsPCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB atoffset0x2000 ans ends at0x217F.MIBADC Look-Up 384 Wrap aroundforaccessesbetweenTable bytes offsets0x180 and 0x3FFF.Aborts generatedforaccessesbeyond 0x4000

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Table4-17.Device Memory Map (continued) FRAME ADDRESS RANGE RESPONSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME Wrap aroundforaccessesto unimplementedaddressoffsetslowerN2HET RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB than0x3FFF.Abortgeneratedfor accessesbeyond 0x3FFF. N2HET RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort Debug Components CoreSightDebug Reads returnzeros,writeshave noCSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KBROM effect Reads returnzeros,writeshave noCortex-R4Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB effect PeripheralControlRegisters Reads returnzeros,writeshave noHTU PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B effect Reads returnzeros,writeshave noN2HET PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B effect Reads returnzeros,writeshave noGIO PS[16] 0xFFF7_BC00 0xFFF7_BCFF 256B 256B effect Reads returnzeros,writeshave noMIBADC PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B effect Reads returnzeros,writeshave noDCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B effect Reads returnzeros,writeshave noDCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B effect Reads returnzeros,writeshave noLIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B effect Reads returnzeros,writeshave noMibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B effect Reads returnzeros,writeshave noSPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B effect Reads returnzeros,writeshave noSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B effect Reads returnzeros,writeshave noEQEP PS[25] 0xFFF7_9900 0xFFF7_99FF 256B 256B effect Reads returnzeros,writeshave noEQEP (Mirrored) PS2[25] 0xFCF7_9900 0xFCF7_99FF 256B 256B effect System Modules ControlRegistersand Memories Wrap aroundforaccessesto unimplementedaddressoffsetslowerVIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4KB 1KB than0x3FF.Accessesbeyond 0x3FF willbe ignored. FlashWrapper PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort eFuse Farm PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB AbortController Reads returnzeros,writeshave noPCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B effect System Module - Reads returnzeros,writeshave noFrame 2 (see PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B effectdeviceTRM) Reads returnzeros,writeshave noPBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B effect Reads returnzeros,writeshave noSTC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B effect IOMM GeneratesaddresserrorinterruptifMultiplexing PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B enabled.controlmodule Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 43 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table4-17.Device Memory Map (continued) FRAME ADDRESS RANGE RESPONSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME Reads returnzeros,writeshave noDCC PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B effect Reads returnzeros,writeshave noESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B effect Reads returnzeros,writeshave noCCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B effect Reads returnzeros,writeshave noRAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B effect Reads returnzeros,writeshave noRAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B effect Reads returnzeros,writeshave noRTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B effect Reads returnzeros,writeshave noVIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B effect Reads returnzeros,writeshave noVIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B effect System Module - Reads returnzeros,writeshave noFrame 1 (see PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B effectdeviceTRM)

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4.8.3 Master/SlaveAccess Privileges

The tablebelowliststheaccesspermissionsforeach bus masteron thedevice.A bus masterisa module thatcan initiatea readora writetransactionon thedevice. Each slavemodule on themain interconnectislistedinthetable.A "Yes"indicatesthatthemodule listed inthe"MASTERS" column can accessthatslavemodule. Table4-18.Master /SlaveAccess Matrix MASTERS ACCESS MODE SLAVES ON MAIN SCR FlashModule Bus2 Non-CPU Accesses CRC PeripheralControl Interface: toProgram Flash Registers,All OTP, ECC, EEPROM and CPU Data RAM Peripheral Bank Memories, And All System Module ControlRegisters And Memories CPU READ User/Privilege Yes Yes Yes Yes CPU WRITE User/Privilege No Yes Yes Yes HTU Privilege No Yes Yes Yes Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 45 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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4.9 FlashMemory

4.9.1 FlashMemory Configuration

Flash Bank: A separateblockof logicconsistingof 1 to 16 sectors.Each flashbank normallyhas a customer-OTP and a TI-OTP area.These flashsectorsshare input/outputbuffers,data paths,sense amplifiers,and controllogic. Flash Sector:A contiguousregionofflashmemory whichmust be erasedsimultaneouslydue tophysical constructionconstraints. Flash Pump: A charge pump which generatesallthe voltagesrequiredforreading,programming,or erasingtheflashbanks. FlashModule: Interfacecircuitryrequiredbetween thehostCPU and theflashbanks and pump module. Table4-19.FlashMemory Banks and Sectors Memory Arrays(orBanks)(1) Block Sector Segment Low Address High Address No. No. BANK0 (384kBytes) 0 0 8K Bytes 0x0000_0000 0x0000_1FFF 1 8K Bytes 0x0000_2000 0x0000_3FFF 2 8K Bytes 0x0000_4000 0x0000_5FFF 3 8K Bytes 0x0000_6000 0x0000_7FFF 4 8K Bytes 0x0000_8000 0x0000_9FFF 5 8K Bytes 0x0000_A000 0x0000_BFFF 6 8K Bytes 0x0000_C000 0x0000_DFFF 7 8K Bytes 0x0000_E000 0x0000_FFFF 8 8K Bytes 0x0001_0000 0x0001_1FFF 9 8K Bytes 0x0001_2000 0x0001_3FFF 10 8K Bytes 0x0001_4000 0x0001_5FFF 11 8K Bytes 0x0001_6000 0x0001_7FFF 12 32K Bytes 0x0001_8000 0x0001_FFFF 1 13 128K Bytes 0x0002_0000 0x0003_FFFF 2 14(2) 128K Bytes 0x0004_0000 0x0005_FFFF BANK7 (16kBytes)forEEPROM 0 0 4K Bytes 0xF020_0000 0xF020_0FFF emulation(3)(4) 1 1 4K Bytes 0xF020_1000 0xF020_1FFF 2 2 4K Bytes 0xF020_2000 0xF020_2FFF 3 3 4K Bytes 0xF020_3000 0xF020_3FFF (1) The Flashbanks are144-bitwidebank withECC support. (2) Sector14 isnotaccessibleorincludedintheTMS570LS0332 configuration. (3) Flashbank7 isan FLEE bank and can be programmed whileexecutingcode fromflashbank0. (4) Code executionisnotallowedfromflashbank7.

4.9.2 Main FeaturesofFlashModule

• Supportformultipleflashbanks forprogramand/ordatastorage
• Simultaneousreadaccesson a bank whileperformingprogramoreraseoperationon any otherbank
• Integratedstatemachinestoautomateflasheraseand programoperations
• Softwareinterfaceforflashprogramand eraseoperations
• Pipelinedmode operationtoimproveinstructionaccessinterfacebandwidth
• SupportforSingleErrorCorrectionDoubleErrorDetection(SECDED) blockinsideCortex-R4CPU – Erroraddressiscapturedforhostsystemdebugging
• Supportfora richsetofdiagnosticfeatures

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4.9.3 ECC ProtectionforFlashAccesses

Allaccessestotheprogramflashmemory areprotectedby SingleErrorCorrectionDoubleErrorDetection (SECDED) logicembedded insidetheCPU. The flashmodule provides8 bitsofECC code for64 bitsof instructionsordatafetchedfromtheflashmemory. The CPU calculatestheexpectedECC code based on the64 bitsreceivedand compares itwiththeECC code returnedby theflashmodule.A signle-biterroris correctedand flaggedby theCPU, whilea multi-biterrorisonlyflagged.The CPU signalsan ECC error viaitsEventbus.Thissignalingmechanism isnotenabledby defaultand must be enabledby settingthe "X"bitofthePerformanceMonitorControlRegister,c9. MRCp15,#0,r1,c9,c12,#0;EnablingEventmonitorstates ORRr1,r1,#0x00000010 MCRp15,#0,r1,c9,c12,#0;Set4thbit(‘X’)ofPMNCregister MRCp15,#0,r1,c9,c12,#0 The applicationmust alsoexplicitlyenablethe CPU's ECC checkingforaccesses on the CPU's ATCM and BTCM interfaces.These are connected to the program flashand data RAM respectively.ECC checkingfortheseinterfacescan be done by settingtheB1TCMPCEN, B0TCMPCEN and ATCMPCEN bitsoftheSystem Controlcoprocessor'sAuxiliaryControlRegister,c1. MRCp15,#0,r1,c1,c0,#1 ORRr1,r1,#0x0e000000;EnableECCcheckingforATCMandBTCMs DMB MCRp15,#0,r1,c1,c0,#1

4.9.4 FlashAccess Speeds

Forinformationon flashmemory accessspeeds and therelevantwaitstatesrequired,refertoSection3.4. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 47 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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4.10 FlashProgram and Erase Timings forProgram Flash

Table4-20.Timing SpecificationsforProgram Flash Parameter MIN NOM MAX Unit tprog (144bit) Wide Word (144bit)programmingtime 40 300 µs tprog (Total) 384KByte programmingtime(1) -40°C to125°C 4 s 0°C to60°C, forfirst 1 2 s 25 cycles terase Sector/Bankerasetime -40°C to125°C 0.30 4 s 0°C to60°C, forfirst 14 100 ms 25 cycles twec Write/erasecycleswith15 yearData Retention -40°C to125°C 1000 cycles requirement (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoes notincludedatatransfertime.The programmingtimeassumes programming144 bitsata timeatthemaximum specifiedoperatingfrequency.

4.11 FlashProgram and Erase Timings forData Flash

Table4-21.Timing SpecificationsforData Flash Parameter MIN NOM MAX Unit tprog (72bit) Wide Word (72bit)programmingtime 40 300 µs tprog (Total) 64KByte programmingtime(1) -40°C to125°C 1.3 s 0°C to60°C, forfirst 330 660 ms 25 cycles terase Sector/Bankerasetime -40°C to125°C 0.200 8 s 0°C to60°C, forfirst 14 100 ms 25 cycles twec Write/erasecycleswith15 yearData Retention -40°C to125°C 100000 cycles requirement (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoes notincludedatatransfertime.The programmingtimeassumes programming144 bitsata timeatthemaximum specifiedoperatingfrequency.

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PRODUCT□PREVIEW EVEN Address TCM□BUS ODD Address TCM□BUS 64□Bit□data□bus 64□Bit□data□bus Upper□32□bits data□& 4□ECC□bits Lower32□bits data□& 4□ECC□bits 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM Upper□32□bits data□& 4□ECC□bits Lower32□bits data□& 4□ECC□bits 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM TCRAM Interface□1 PMT I/FVBUSP I/F Cortex□R4™ TCM TCM A TCM TCRAM Interface□2 PMT I/FVBUSP I/F TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

4.12 Tightly-CoupledRAM InterfaceModule

Figure4-11illustratestheconnectionoftheTightlyCoupledRAM (TCRAM) totheCortex-R4™ CPU. Figure4-11.TCRAM Block Diagram

4.12.1 Features

The featuresoftheTightlyCoupledRAM (TCRAM) Module are:

• Actsas slavetotheCortex-R4CPU's BTCM interface
• SupportsCPU's internalECC scheme by providing64-bitdataand 8-bitECC code
• MonitorsCPU EventBus and generatessingleormulti-biterrorinterrupts
• Storesaddressesforsingleand multi-biterrors
• ProvidesCPU addressbus integritycheckingby supportingparitycheckingon theaddressbus
• PerformsredundantaddressdecodingfortheRAM bank chipselectand ECC selectgenerationlogic
• Providesenhanced safetyforthe RAM addressingby implementingtwo 36-bitwide byte-interleaved RAM banks and generatingindependentRAM accesscontrolsignalstothetwo banks
• Supportsauto-initializationoftheRAM banks alongwiththeECC bits
• No supportforbit-wiseRAM accesses

4.12.2 TCRAMW ECC Support

The TCRAMW passes on theECC code foreach datareadby theCortex-R4CPU fromtheRAM. Italso storesthe CPU's ECC portcontentsin the ECC RAM when the CPU does a writeto the RAM. The TCRAMW monitorsthe CPU's eventbus and providesregistersforindicatingsingle/multi-biterrorsand alsoforidentifyingtheaddressthatcaused thesingleormulti-biterror.The eventsignalingand theECC checkingfortheRAM accessesmust be enabledinsidetheCPU. Formore informationsee thedeviceTechnicalReferenceManual.

4.13 ParityProtectionforAccesses toperipheralRAMs

Accesses tosome peripheralRAMs areprotectedby odd/evenparitychecking.Duringa readaccessthe parityiscalculatedbased on thedataread from theperipheralRAM and compared withthegood parity valuestoredintheparityRAM forthatperipheral.Ifany word failstheparitycheck,themodule generates a parityerrorsignalthatis mapped to the ErrorSignalingModule. The module also capturesthe peripheralRAM addressthatcaused theparityerror. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 49 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com The parityprotectionforperipheralRAMs is not enabled by defaultand must be enabled by the application.Each individualperipheralcontainscontrolregistersto enable the parityprotectionfor accessestoitsRAM. NOTE The CPU read access getstheactualdatafrom theperipheral.The applicationcan choose togeneratean interruptwhenever a peripheralRAM parityerrorisdetected.

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4.14 On-Chip SRAM Initializationand Testing

4.14.1 On-Chip SRAM Self-TestUsing PBIST

4.14.1.1Features

• Extensiveinstructionsettosupportvariousmemory testalgorithms
• ROM-based algorithmsallowapplicationtorunTIproduction-levelmemory tests
• Independenttestingofallon-chipSRAM 4.14.1.2PBIST RAM Groups Table4-22.PBIST RAM Grouping TestPattern(Algorithm) March 13N (1) March 13N (1) tripleread tripleread two port singleportMemory RAM Group TestClock MEM Type slow read fastread (cycles) (cycles) ALGO MASK ALGO MASK ALGO MASK ALGO MASK 0x1 0x2 0x4 0x8 PBIST_ROM 1 ROM CLK ROM X X STC_ROM 2 ROM CLK ROM X X DCAN1 3 VCLK DualPort 12720 DCAN2 4 VCLK DualPort 6480 ESRAM1 6 HCLK SinglePort 133160 MIBSPI1 7 VCLK DualPort 33440 VIM 10 VCLK DualPort 12560 MIBADC 11 VCLK DualPort 4200 N2HET1 13 VCLK DualPort 25440 HET TU1 14 VCLK DualPort 6480 (1) Thereareseveralmemory testingalgorithmsstoredinthePBIST ROM. However,TIrecommends theMarch13N algorithmfor applicationtesting. The PBIST ROM clockcan be divideddown from HCLK. The dividerisselectedby programming the ROM_DIV fieldoftheMemory Self-TestGlobalControlRegister(MSTGCR) ataddress0xFFFFFF58. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 51 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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4.14.2 On-Chip SRAM Auto Initialization

This microcontrollerallowssome of the on-chipmemories to be initializedviathe Memory Hardware Initializationmechanism in the System module. This hardware mechanism allowsan applicationto program thememory arrayswitherrordetectioncapabilitytoa known statebased on theirerrordetection scheme (odd/evenparityorECC). The MINITGCR registerenablesthe memory initializationsequence,and the MSINENA registerselects thememories thataretobe initialized. Formore informationon theseregistersrefertothedeviceTechnicalReferenceManual. The mapping ofthedifferenton-chipmemories tothespecificbitsoftheMSINENA registersisshown in Table4-23. Table4-23.Memory Initialization ADDRESS RANGE CONNECTING MODULE MSINENA REGISTER BIT #(1) BASE ADDRESS ENDING ADDRESS RAM 0x08000000 0x08007FFF 0 MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(2) DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 MIBADC RAM 0xFF3E0000 0xFF3FFFFF 8 N2HET RAM 0xFF460000 0xFF47FFFF 3 HET TU RAM 0xFF4E0000 0xFF4FFFFF 4 VIM RAM 0xFFF82000 0xFFF82FFF 2 (1) Unassignedregisterbitsarereserved. (2) The MibSPI1 module performsan initializationofthetransmitand receiveRAMs as soon as themodule isbroughtoutofresetusingthe SPI GlobalControlRegister0 (SPIGCR0).ThisisindependentofwhethertheapplicationchoosestoinitializetheMibSPI1 RAMs using thesystemmodule auto-initializationmethod.

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4.15 VectoredInterruptManager

The vectoredinterruptmanager (VIM) provideshardware assistanceforprioritizingand controllingthe many interruptsourcespresenton thisdevice.Interruptsarecaused by eventsoutsideofthenormalflow ofprogram execution.Normally,theseeventsrequirea timelyresponsefrom thecentralprocessingunit (CPU);therefore,when an interruptoccurs,theCPU switchesexecutionfromthenormalprogram flowto an interruptserviceroutine(ISR).

4.15.1 VIM Features

The VIM module has thefollowingfeatures:

• Supports96 interruptchannels. – Providesprogrammablepriorityand enableforinterruptrequestlines.
• Providesa directhardwaredispatchmechanism forfastestIRQ dispatch.
• Providestwo softwaredispatchmechanisms when theCPU VIC portisnotused. – Indexinterrupt – Registervectoredinterrupt
• Parityprotectedvectorinterrupttableagainstsofterrors.

4.15.2 InterruptRequest Assignments

Table4-24.InterruptRequest Assignments Modules InterruptSources DefaultVIM Interrupt Channel ESM ESM Highlevelinterrupt(NMI) 0 Reserved Reserved 1 RTI RTI compare interrupt0 2 RTI RTI compare interrupt1 3 RTI RTI compare interrupt2 4 RTI RTI compare interrupt3 5 RTI RTI overflowinterrupt0 6 RTI RTI overflowinterrupt1 7 Reserved Reserved 8 GIO GIO interruptA 9 N2HET N2HET level0 interrupt 10 HET TU HET TU level0 interrupt 11 MIBSPI1 MIBSPI1 level0 interrupt 12 LIN LIN level0 interrupt 13 MIBADC MIBADC eventgroupinterrupt 14 MIBADC MIBADC sw group1 interrupt 15 DCAN1 DCAN1 level0 interrupt 16 SPI2 SPI2 level0 interrupt 17 Reserved Reserved 18 Reserved Reserved 19 ESM ESM Low levelinterrupt 20 SYSTEM Softwareinterrupt(SSI) 21 CPU PMU interrupt 22 GIO GIO interruptB 23 N2HET N2HET level1 interrupt 24 HET TU HET TU level1 interrupt 25 MIBSPI1 MIBSPI1 level1 interrupt 26 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 53 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table4-24.InterruptRequest Assignments (continued) Modules InterruptSources DefaultVIM Interrupt Channel LIN LIN level1 interrupt 27 MIBADC MIBADC sw group2 interrupt 28 DCAN1 DCAN1 level1 interrupt 29 SPI2 SPI2 level1 interrupt 30 MIBADC MIBADC magnitudecompare interrupt 31 Reserved Reserved 32-34 DCAN2 DCAN2 level0 interrupt 35 Reserved Reserved 36 SPI3 SPI3 level0 interrupt 37 SPI3 SPI3 level1 interrupt 38 Reserved Reserved 39-41 DCAN2 DCAN2 level1 interrupt 42 Reserved Reserved 43-60 FMC FSM_DONE interrupt 61 Reserved Reserved 62-79 HWAG HWA_INT_REQ_H 80 Reserved Reserved 81 DCC DCC done interrupt 82 Reserved Reserved 83 eQEPINTn eQEP Interrupt 84 PBIST PBIST Done Interrupt 85 Reserved Reserved 86-87 HWAG HWA_INT_REQ_L 88 Reserved Reserved 89-95 NOTE Address location0x00000000 in the VIM RAM isreservedforthe phantom interruptISR entry;thereforeonlyrequestchannels0..94can be used and areoffsetby 1 addressinthe VIM RAM.

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PRODUCT□PREVIEW RTICLK External control CAP event□source□0 CAP event□source□1 =Up□counter Capture up□counter Compare up□counter Free□running□counter Capture RTIFRCx free□running□counter RTICAFRCx OVLINTx RTICPUCx RTIUCx RTICAUCx To□Compare Unit TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

4.16 Real Time InterruptModule

The real-timeinterrupt(RTI) module providestimer functionalityfor operatingsystems and for benchmarkingcode.The RTI module can incorporateseveralcountersthatdefinethetimebasesneeded forschedulingan operatingsystem. The timersalsoallowyou tobenchmark certainareasofcode by readingthevaluesofthecountersatthe beginningand theend ofthedesiredcode rangeand calculatingthedifferencebetween thevalues.

4.16.1 Features

The RTI module has thefollowingfeatures:

• Two independent64 bitcounterblocks
• Four configurablecompares forgeneratingoperatingsystem ticks.Each eventcan be drivenby either counterblock0 orcounterblock1.
• Fastenabling/disablingofevents
• Two time-stamp(capture)functionsforsystemorperipheralinterrupts,one foreach counterblock

4.16.2 Block Diagrams

Figure4-12 shows a high-levelblockdiagram forone of the two 64-bitcounterblocksinsidethe RTI module.Boththecounterblocksareidentical. Figure4-12.Counter Block Diagram Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 55 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW Compare control INTy Compare Update compare From□counter block□0 From□counter block□1 RTIUDCPy RTICOMPy TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Figure4-13.Compare Block Diagram

4.16.3 Clock Source Options

The RTI module uses theRTICLK clockdomain forgeneratingtheRTI timebases. The applicationcan selecttheclocksourcefortheRTICLK by configuringtheRCLKSRC registerinthe System module ataddress0xFFFFFF50. The defaultsourceforRTICLK isVCLK. Formore informationon clocksourcesrefertoTable4-8and Table4-11.

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4.17 ErrorSignalingModule

The ErrorSignalingModule (ESM) manages thevariouserrorconditionson theTMS570 microcontroller. The errorconditionishandledbased on a fixedseveritylevelassignedtoit.Any severeerrorcondition can be configuredtodrivea low levelon a dedicateddeviceterminalcallednERROR. Thiscan be used as an indicatortoan externalmonitorcircuittoputthesystemintoa safestate.

4.17.1 Features

The featuresoftheErrorSignalingModule are:

• 128 interrupt/errorchannelsaresupported,dividedinto3 differentgroups – 64 channelswithmaskableinterruptand configurableerrorpinbehavior – 32 errorchannelswithnon-maskableinterruptand predefinederrorpinbehavior – 32 channelswithpredefinederrorpinbehavioronly
• Errorpintosignalseveredevicefailure
• Configurabletimebaseforerrorsignal
• Errorforcingcapability

4.17.2 ESM Channel Assignments

The ErrorSignalingModule (ESM) integratesallthedeviceerrorconditionsand groupsthem intheorder ofseverity.Group1 isused forerrorsofthelowestseveritywhileGroup3 isused forerrorsofthehighest severity.The deviceresponse to each erroris determinedby the severitygroup itis connected to. Table4-26shows thechannelassignmentforeach group. Table4-25.ESM Groups ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR PIN Group1 maskable,loworhighpriority configurable Group2 non-maskable,highpriority fixed Group3 no interruptgenerated fixed Table4-26.ESM Channel Assignments ERROR SOURCES GROUP CHANNELS Reserved Group1 0 Reserved Group1 1 Reserved Group1 2 Reserved Group1 3 Reserved Group1 4 Reserved Group1 5 FMC -correctableerror:bus1 and bus2 interfaces(doesnotincludeaccessesto Group1 6 EEPROM bank) N2HET -parity Group1 7 HET TU -parity Group1 8 HET TU -MPU Group1 9 PLL -Slip Group1 10 ClockMonitor-interrupt Group1 11 Reserved Group1 12 Reserved Group1 13 Reserved Group1 14 VIM RAM -parity Group1 15 Reserved Group1 16 MibSPI1 -parity Group1 17 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 57 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table4-26.ESM Channel Assignments (continued) ERROR SOURCES GROUP CHANNELS Reserved Group1 18 MibADC -parity Group1 19 Reserved Group1 20 DCAN1 -parity Group1 21 Reserved Group1 22 DCAN2 -parity Group1 23 Reserved Group1 24 Reserved Group1 25 RAM even bank (B0TCM) -correctableerror Group1 26 CPU -selftest Group1 27 RAM odd bank (B1TCM) -correctableerror Group1 28 Reserved Group1 29 DCC -error Group1 30 CCM-R4 -selftest Group1 31 Reserved Group1 32 Reserved Group1 33 Reserved Group1 34 FMC -correctableerror(EEPROM bank access) Group1 35 FMC -uncorrectableerror(EEPROM bank access) Group1 36 IOMM -Mux configurationerror Group1 37 Reserved Group1 38 Reserved Group1 39 eFuse farm– thiserrorsignalisgeneratedwhenever any bitintheeFuse farm Group1 40 errorstatusregisterisset.The applicationcan choose togenerateand interrupt whenever thisbitissetinordertoserviceany eFuse farmerrorcondition. eFuse farm-selftesterror.Itisnotnecessarytogeneratea separateinterrupt Group1 41 when thisbitgetsset. Reserved Group1 42 Reserved Group1 43 Reserved Group1 44 Reserved Group1 45 Reserved Group1 46 Reserved Group1 47 Reserved Group1 48 Reserved Group1 49 Reserved Group1 50 Reserved Group1 51 Reserved Group1 52 Reserved Group1 53 Reserved Group1 54 Reserved Group1 55 Reserved Group1 56 Reserved Group1 57 Reserved Group1 58 Reserved Group1 59 Reserved Group1 60 Reserved Group1 61 Reserved Group1 62

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Table4-26.ESM Channel Assignments (continued) ERROR SOURCES GROUP CHANNELS Reserved Group1 63 Reserved Group2 0 Reserved Group2 1 CCMR4 -compare Group2 2 Reserved Group2 3 FMC -uncorrectableerror(addressparityon bus1 accesses) Group2 4 Reserved Group2 5 RAM even bank (B0TCM) -uncorrectableerror Group2 6 Reserved Group2 7 RAM odd bank (B1TCM) -uncorrectableerror Group2 8 Reserved Group2 9 RAM even bank (B0TCM) -addressbus parityerror Group2 10 Reserved Group2 11 RAM odd bank (B1TCM) -addressbus parityerror Group2 12 Reserved Group2 13 Reserved Group2 14 Reserved Group2 15 Flash(ATCM) -ECC livelockdetect Group2 16 Reserved Group2 17 Reserved Group2 18 Reserved Group2 19 Reserved Group2 20 Reserved Group2 21 Reserved Group2 22 Reserved Group2 23 RTI_WWD_NMI Group2 24 Reserved Group2 25 Reserved Group2 26 Reserved Group2 27 Reserved Group2 28 Reserved Group2 29 Reserved Group2 30 Reserved Group2 31 Reserved Group3 0 eFuse Farm -autoloaderror Group3 1 Reserved Group3 2 RAM even bank (B0TCM) -ECC uncorrectableerror Group3 3 Reserved Group3 4 RAM odd bank (B1TCM) -ECC uncorrectableerror Group3 5 Reserved Group3 6 FMC -uncorrectableerror:bus1 and bus2 interfaces(doesnotincludeaddress Group3 7 parityerrorand errorson accessestoEEPROM bank) Reserved Group3 8 Reserved Group3 9 Reserved Group3 10 Reserved Group3 11 Reserved Group3 12 Reserved Group3 13 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 59 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table4-26.ESM Channel Assignments (continued) ERROR SOURCES GROUP CHANNELS Reserved Group3 14 Reserved Group3 15 Reserved Group3 16 Reserved Group3 17 Reserved Group3 18 Reserved Group3 19 Reserved Group3 20 Reserved Group3 21 Reserved Group3 22 Reserved Group3 23 Reserved Group3 24 Reserved Group3 25 Reserved Group3 26 Reserved Group3 27 Reserved Group3 28 Reserved Group3 29 Reserved Group3 30 Reserved Group3 31

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4.18 Reset /Abort /ErrorSources

Table4-27.Reset/Abort/ErrorSources ESM HOOKUPERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel CPU TRANSACTIONS Precisewriteerror(NCNB/StronglyOrdered) User/Privilege PreciseAbort(CPU) n/a Precisereaderror(NCB/DeviceorNormal) User/Privilege PreciseAbort(CPU) n/a Imprecisewriteerror(NCB/DeviceorNormal) User/Privilege ImpreciseAbort(CPU) n/a UndefinedInstructionTrapIllegalinstruction User/Privilege n/a(CPU)(1) MPU accessviolation User/Privilege Abort(CPU) n/a SRAM B0 TCM (even)ECC singleerror(correctable) User/Privilege ESM 1.26 Abort(CPU),ESM =>B0 TCM (even)ECC doubleerror(non-correctable) User/Privilege 3.3nERROR B0 TCM (even)uncorrectableerror(i.e.redundantaddress User/Privilege ESM => NMI => nERROR 2.6decode) B0 TCM (even)addressbus parityerror User/Privilege ESM => NMI => nERROR 2.10 B1 TCM (odd)ECC singleerror(correctable) User/Privilege ESM 1.28 Abort(CPU),ESM =>B1 TCM (odd)ECC doubleerror(non-correctable) User/Privilege 3.5nERROR B1 TCM (odd)uncorrectableerror(i.e.redundantaddress User/Privilege ESM => NMI => nERROR 2.8decode) B1 TCM (odd)addressbus parityerror User/Privilege ESM => NMI => nERROR 2.12 FLASH WITH CPU BASED ECC FMC correctableerror-Bus1 and Bus2 interfaces(doesnot User/Privilege ESM 1.6includeaccessestoEEPROM bank) FMC uncorrectableerror-Bus1 accesses Abort(CPU),ESM =>User/Privilege 3.7(doesnotincludeaddressparityerror) nERROR FMC uncorrectableerror-Bus2 accesses (doesnotincludeaddressparityerrorand EEPROM bank User/Privilege ESM => nERROR 3.7 accesses) FMC uncorrectableerror-addressparityerroron Bus1 User/Privilege ESM => NMI => nERROR 2.4accesses FMC correctableerror-AccessestoEEPROM bank User/Privilege ESM 1.35 FMC uncorrectableerror-AccessestoEEPROM bank User/Privilege ESM 1.36 HET TU (HTU) NCNB (StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=> VIM n/a Externalimpreciseerror(Illegaltransactionwithok response) User/Privilege Interrupt=> VIM n/a Memory accesspermissionviolation User/Privilege ESM 1.9 Memory parityerror User/Privilege ESM 1.8 N2HET Memory parityerror User/Privilege ESM 1.7 MIBSPI MibSPI1 memory parityerror User/Privilege ESM 1.17 MIBADC MibADC Memory parityerror User/Privilege ESM 1.19 DCAN DCAN1 memory parityerror User/Privilege ESM 1.21 DCAN2 memory parityerror User/Privilege ESM 1.23 (1) The UndefinedInstructionTRAP isNOT detectableoutsidetheCPU. The trapistakenonlyiftheinstructionreachestheexecutestage oftheCPU. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 61 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table4-27.Reset/Abort/ErrorSources (continued) ESM HOOKUPERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel PLL PLL sliperror User/Privilege ESM 1.10 CLOCK MONITOR Clockmonitorinterrupt User/Privilege ESM 1.11 DCC DCC error User/Privilege ESM 1.30 CCM-R4 Selftestfailure User/Privilege ESM 1.31 Compare failure User/Privilege ESM => NMI => nERROR 2.2 VIM Memory parityerror User/Privilege ESM 1.15 VOLTAGE MONITOR VMON outofvoltagerange n/a Reset n/a CPU SELFTEST (LBIST) CPU Selftest(LBIST)error User/Privilege ESM 1.27 PIN MULTIPLEXING CONTROL Mux configurationerror User/Privilege ESM 1.37 eFuse Controller eFuse ControllerAutoloaderror User/Privilege ESM => nERROR 3.1 eFuse Controller-Any bitsetintheerrorstatusregister User/Privilege ESM 1.40 eFuse Controllerself-testerror User/Privilege ESM 1.41 WINDOWED WATCHDOG WWD Non-MaskableInterruptexception n/a ESM => NMI => nERROR 2.24 ERRORS REFLECTED IN THE SYSESR REGISTER Power-Up Reset n/a Reset n/a Oscillatorfail/PLL slip(2) n/a Reset n/a Watchdog exception n/a Reset n/a CPU Reset(drivenby theCPU STC) n/a Reset n/a SoftwareReset n/a Reset n/a ExternalReset n/a Reset n/a (2) Oscillatorfail/PLLslipcan be configuredinthesystemregister(SYS.PLLCTL1) togeneratea reset.

4.19 DigitalWindowed Watchdog

Thisdeviceincludesa digitalwindowed watchdog (DWWD) module thatprotectsagainstrunaway code execution. The DWWD module allowstheapplicationtoconfigurethetimewindow withinwhichtheDWWD module expectstheapplicationtoservicethewatchdog.A watchdogviolationoccursiftheapplicationservicesthe watchdog outsideof thiswindow, or failsto servicethe watchdog at all.The applicationcan choose to generatea systemresetora non-maskableinterrupttotheCPU incase ofa watchdogviolation. The watchdog isdisabledby defaultand must be enabledby theapplication.Once enabled,thewatchdog can onlybe disabledupon a systemreset.

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PRODUCT□PREVIEW TRST TMS TCK TDI TDO RTCK ICEPICK_C Boundary□Scan BSR/BSDL Boundary□Scan□I/F Secondary□Tap□0 DAP Debug APB Debug ROM1 APB□slave Cortex Test□Tap□0 eFuse□Farm Secondary□Tap□2 AJSM TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

4.20 Debug Subsystem

4.20.1 Block Diagram

The devicecontainsan ICEPICK module toallowJTAG accesstothescan chains. Figure4-14.ZWT Debug Subsystem Block Diagram

4.20.2 Debug Components Memory Map

Table4-28.Debug Components Memory Map FRAME ADDRESS RANGE RESPONSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME CoreSightDebug Reads returnzeros,writeshave noCSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KBROM effect Reads returnzeros,writeshave noCortex-R4Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB effect

4.20.3 JTAG IdentificationCode

The JTAG ID code forthisdeviceis0x0B97102F. Thisisthesame as thedeviceICEPickIdentification Code.

4.20.4 Debug ROM

The Debug ROM storesthelocationofthecomponents on theDebug APB bus: Table4-29.Debug ROM table ADDRESS DESCRIPTION VALUE 0x000 pointertoCortex-R4 0x0000 1003 0x001 Reserved 0x0000 2002 0x002 Reserved 0x0000 3002 0x003 Reserved 0x0000 4002 0x004 end oftable 0x0000 0000 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 63 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW 1 1 TMS TDI TDO RTCK TCK TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

4.20.5 JTAG Scan InterfaceTimings

Table4-30.JTAG Scan InterfaceTiming(1) No. Parameter Min MAX Unit fTCK TCK frequency(atHCLKmax) 12 MHz fRTCK RTCK frequency(atTCKmax and HCLKmax) 10 MHz 1 td(TCK-RTCK) Delaytime,TCK toRTCK 24 ns 2 tsu(TDI/TMS-RTCKr) Setuptime,TDI,TMS beforeRTCK rise(RTCKr) 15 ns 3 th(RTCKr-TDI/TMS) Holdtime,TDI,TMS afterRTCKr 0 ns 4 th(RTCKr-TDO) Holdtime,TDO afterRTCKf 0 ns 5 td(TCKf-TDO) Delaytime,TDO validafterRTCK fall(RTCKf) 10 ns (1) TimingsforTDO arespecifiedfora maximum of50pF loadon TDO Figure4-15.JTAG Timing

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PRODUCT□PREVIEW H L H L H L L H .□.□. .□.□. 128-bit□comparator H L L H H L L H UNLOCK Flash□Module□Output OTP Contents Unlock□By□Scan Register Internal□Tie-Offs (example□only) (example) L H H L LInternal□Tie-Offs (example□only) L H H TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

4.20.6 Advanced JTAG SecurityModule

Thisdeviceincludesa an Advanced JTAG SecurityModule (AJSM).whichprovidesmaximum securityto thedevice’s memory contentby allowinguserstosecurethedeviceafterprogramming. Figure4-16.AJSM Unlock The deviceisunsecure by defaultby virtueof a 128-bitvisibleunlockcode programmed in the OTP address0xF0000000.The OTP contentsare XOR-ed withthe "UnlockBy Scan" registercontents.The outputsoftheseXOR gatesare againcombined witha setofsecretinternaltie-offs.The outputofthis combinationallogicis compared againsta secrethard-wired128-bitvalue.A match resultsin the UNLOCK signalbeingasserted,so thatthedeviceisnow unsecure. A usercan securethedeviceby changingatleastone bitinthevisibleunlockcode from1 to0.Changing a 0 to1 isnotpossiblesincethevisibleunlockcode isstoredintheOne Time Programmable (OTP) flash region.Also,changingallthe128 bitstozerosisnota validconditionand willpermanentlysecurethe device. Once secured,a user can unsecurethe deviceby scanningan appropriatevalueintothe "UnlockBy Scan" registeroftheAJSM module.The valuetobe scanned issuch thattheXOR oftheOTP contents and theUnlock-By-Scanregistercontentsresultsintheoriginalvisibleunlockcode. The Unlock-By-Scanregisterisresetonlyupon assertingpower-onreset(nPORRST). A securedeviceonlypermitsJTAG accessestotheAJSM scan chainviatheSecondary Tap # 2 ofthe ICEPickmodule.Allothersecondarytaps,testtapsand theboundaryscan interfacearenotaccessiblein thisstate. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 65 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TRST TMS TCK TDI TDO RTCK IC EPICK Boundary BSDL Boundary Scan Interface Scan Device Pins (conceptual) TDI TDO TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

4.20.7 Boundary Scan Chain

The devicesupportsBSDL-compliantboundary scan fortestingpin-to-pincompatibility.The boundary scan chainisconnectedtotheBoundaryScan InterfaceoftheICEPICK module. Figure4-17.Boundary Scan Implementation(ConceptualDiagram) Data isseriallyshiftedintoallboundary-scanbuffersviaTDI,and outviaTDO.

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5 PeripheralInformationand ElectricalSpecifications

5.1 PeripheralLegend

Table5-1.PeripheralLegend Abbreviation FullName MibADC Multi-BufferedAnalogtoDigitalConverter CCM-R4 CPU Compare Module – CortexR4 CRC CyclicRedundancy Check DCAN ControllerArea Network DCC DualClockComparator ESM ErrorSignalingModule GIO General-PurposeInput/Output HTU HighEnd TimerTransferUnit LIN LocalInterconnectNetwork MibSPI Multi-BufferedSerialPeripheralInterface N2HET PlatformHighEnd Timer RTI Real-TimeInterruptModule SCI SerialCommunicationsInterface SPI SerialPeripheralInterface VIM VectoredInterruptManager eQEP Enhanced QuadratureEncoderPulse

5.2 Multi-Buffered12-bitAnalog-to-DigitalConverter

The multibufferedA-to-Dconverter(MibADC) has a separatepower bus foritsanalog circuitrythat enhances theA-to-Dperformanceby preventingdigitalswitchingnoiseon thelogiccircuitrywhich could be presenton VSS and VCC fromcouplingintotheA-to-Danalogstage.AllA-to-Dspecificationsaregiven withrespecttoAD REFLO unlessotherwisenoted. Table5-2.MibADC Overview Description Value Resolution 12 bits Monotonic Assured Outputconversioncode 00h toFFFh [00forVAI ≤ AD REFLO ;FFF forVAI ≥ AD REFHI ]

5.2.1 Features

• 12-bitresolution
• AD REFHI and AD REFLO pins(highand lowreferencevoltages)
• TotalSample/Hold/Converttime:600ns TypicalMinimum at30MHz ADCLK
• One memory regionperconversiongroupisavailable(event,group1,group2)
• Allocationofchannelstoconversiongroupsiscompletelyprogrammable
• Memory regionsareservicedby interrupt
• Programmable interruptthresholdcounterisavailableforeach group
• Programmable magnitudethresholdinterruptforeach groupforany one channel
• Optiontoreadeither8-bit,10-bitor12-bitvaluesfrommemory regions
• Singleorcontinuousconversionmodes
• Embedded self-test
• Embedded calibrationlogic Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 67 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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• Enhanced power-down mode – Optionalfeaturetoautomaticallypower down ADC corewhen no conversionisinprogress
• Externaleventpin(ADEVT) programmableas general-purposeI/O 5.2.2 The ADC module supports3 conversiongroups:Event Group, Group1 and Group2. Each of these3 groupscan be configuredtobe hardwareevent-triggered.Inthatcase,theapplicationcan selectfrom among 8 eventsourcestobe thetriggerfora group'sconversions.

5.2.2.1 DefaultMIBADC Event TriggerHookup

Table5-3.MIBADC Event TriggerHookup Event # Source SelectBitsFor G1, G2 Or Event Trigger (G1SRC[2:0],G2SRC[2:0] or EVSRC[2:0]) 1 000 ADEVT 2 001 N2HET[8] 3 010 N2HET[10] 4 011 RTI compare 0 interrupt 5 100 N2HET[12] 6 101 N2HET[14] 7 110 N2HET[17] 8 111 N2HET[19] NOTE For ADEVT, N2HET triggersources,theconnectiontotheMibADC module triggerinputis made fromtheoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generated eitherby configuringthefunctionas outputontothepad,or by drivingthefunctionfrom an externaltriggersource as input.Ifthe mux controllermodule isused to selectdifferent functionalityinsteadof ADEVT or N2HET[x],care must be takento disablethesesignals fromtriggeringconversions;thereisno multiplexingon inputconnections. NOTE For theRTI compare 0 interruptsource,theconnectionismade directlyfrom theoutputof theRTI module.That is,theinterruptconditioncan be used as a triggersourceeven ifthe actualinterruptisnotsignaledtotheCPU.

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PRODUCT□PREVIEW VS1 On-State Leakage Off-State Leakages VS2 VS24 23*IAIL IAIL IAIL Rext Rext Rext Pin Smux Rmux Pin Smux Rmux Pin Smux Rmux Ssamp Rsamp Csamp Cext IAIL IAIL IAIL IAIL Cmux Cext Cext TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

5.2.3 ADC Electricaland Timing Specifications

Table5-4.MibADC Recommended OperatingConditions Parameter MIN MAX Unit AD REFHI A-to-Dhigh-voltagereferencesource AD REFLO VCCAD V AD REFLO A-to-Dlow-voltagereferencesource VSSAD AD REFHI V VAI Analoginputvoltage AD REFLO AD REFHI V IAIC Analoginputclamp current -2 2 mA (VAI< VSSAD – 0.3orVAI > VCCAD + 0.3) Table5-5.MibADC ElectricalCharacteristicsOver FullRanges ofRecommended OperatingConditions(1) Parameter Description/Conditions MIN Type MAX Unit R mux Analoginputmux on- See Figure5-1 95 250 Ω resistance R samp ADC sample switchon- See Figure5-1 60 250 Ω resistance C mux Inputmux capacitance See Figure5-1 7 16 pF C samp ADC sample capacitance See Figure5-1 8 13 pF IAIL Analogoff-stateinput Off-stateinputleakageper VSSAD < VIN < VCCAD -0.3 250 nA leakagecurrent,forVCCAD = ADC inputpin 3.6Vmaximum IADREFHI AD REFHI inputcurrent AD REFHI = VCCAD ,AD REFLO = VSSAD 3 mA ICCAD Staticsupplycurrent Normal operatingmode 15 mA ADC coreinpower down mode 5 µA (1) 1 LSB = (ADREFHI – AD REFLO )/2n where n = 10 in10-bitmode and 12 in12-bitmode Figure5-1.MibADC InputEquivalentCircuit Table5-6.MibADC Timing Specifications Parameter MIN NOM MAX Unit tc(ADCLK) (1) Cycletime,MibADC clock 33 ns (1) The MibADC clockistheADCLK, generatedby dividingdown theVCLK by a prescalefactordefinedby theADCLOCKCR registerbits 4:0. Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 69 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table5-6.MibADC Timing Specifications(continued) Parameter MIN NOM MAX Unit td(SH)(2) Delaytime,sample and hold 200 ns time 12-bitmode td(C) Delaytime,conversiontime 400 ns td(SHC)(3) Delaytime,totalsample/hold 600 ns and conversiontime 10-bitmode td(C) Delaytime,conversiontime 330 ns td(SHC)(3) Delaytime,totalsample/hold 530 ns and conversiontime (2) The sample and holdtimefortheADC conversionsisdefinedby theADCLK frequencyand theAD <GP >SAMP registerforeach conversiongroup.The sample timeneeds tobe determinedby accountingfortheexternalimpedance connectedtotheinputchannelas wellas theADC ’s internalimpedance. (3) Thisistheminimum sample/holdand conversiontimethatcan be achieved.These parametersaredependenton many factors,e.gthe prescalesettings.

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Table5-7.MibADC OperatingCharacteristicsOver FullRanges ofRecommended OperatingConditions Parameter Description/Conditions MIN Type MAX Unit CR Conversionrangeover AD REFHI -AD REFLO 3 3.6 V whichspecified accuracyis maintained ZSET OffsetError Differencebetween thefirstidealtransition 10-bit 1 LSB (fromcode 000h to001h)and theactual mode transition 12-bit 2 LSB mode FSET Gain Error Differencebetween thelastidealtransition 10-bit 2 LSB (fromcode FFEh toFFFh) and theactual mode transitionminus offset. 12-bit 3 LSB mode EDNL Differential Differencebetween theactualstepwidthand 10-bit ± 1.5 LSB nonlinearityerror theidealvalue.(See Figure5-2) mode 12-bit ± 2 LSB mode EINL Integralnonlinearity Maximum deviationfromthebeststraightline 10-bit ± 2 LSB error throughtheMibADC. MibADC transfer mode characteristics,excludingthequantization 12-bit ± 2 LSBerror.(See Figure5-3) mode ETOT Totalunadjustederror Maximum valueofthedifferencebetween an 10-bit ± 2 LSB (aftercalibration) analogvalueand theidealmidstepvalue. mode (See Figure5-4) 12-bit ± 4 LSB mode Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 71 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW Differential Linearity Error (–½ LSB)

1 LSB

Error (–½ LSB) 0 ... 110 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) NOTE A: 1 LSB = (AD – AD )/REFHI REFLO 2 where n=10 in 10-bit mode and 12 in 12-bit mode n TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

5.2.4 Performance (Accuracy)Specifications

5.2.4.1 MibADC NonlinearityErrors

The differentialnonlinearityerrorshown in FigureFigure5-2 (sometimes referredto as differential linearity)isthedifferencebetween an actualstepwidthand theidealvalueof1 LSB. Figure5-2.DifferentialNonlinearity(DNL) Error

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PRODUCT□PREVIEW 0 ... 111 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) 0 ... 110 6 7 At Transition (–½ LSB) At Transition 001/010 (–1/4 LSB) Actual Transition Ideal Transition End-Point Lin. Error NOTE A: 1 LSB = (AD – AD )/REFHI REFLO 2 where n=10 in 10-bit mode and 12 in 12-bit mode n TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 The integralnonlinearityerrorshown inFigureFigure5-3(sometimesreferredtoas linearityerror)isthe deviationofthevalueson theactualtransferfunctionfroma straightline. Figure5-3.IntegralNonlinearity(INL)Error Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 73 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW 0 ... 111 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) 0 ... 110 6 7 Total Error At Step Total Error At Step 0 ... 101 (–1 1/4 LSB) NOTE A: 1 LSB = (AD – AD )/REFHI REFLO 2 where n=10 in 10-bit mode and 12 in 12-bit mode n TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

5.2.4.2 MibADC TotalError

The absoluteaccuracyortotalerrorofan MibADC as shown inFigureFigure5-4isthemaximum valueof thedifferencebetween an analogvalueand theidealmidstepvalue. Figure5-4.AbsoluteAccuracy (Total)Error

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5.3 General-PurposeInput/Output

The GPIO module on thisdevice supportsone portGIOA. The I/O pins are bidirectionaland bit- programmable.GIOA supportsexternalinterruptcapability.

5.3.1 Features

The GPIO module has thefollowingfeatures:

• Each IO pincan be configuredas: – Input – Output – Open Drain
• The interruptshave thefollowingcharacteristics: – Programmable interruptdetectioneitheron bothedges oron a singleedge (setinGIOINTDET) – Programmable edge-detectionpolarity,eitherrisingorfallingedge (setinGIOPOL register) – Individualinterruptflags(setinGIOFLG register) – Individualinterruptenables,set and clearedthroughGIOENASET and GIOENACLR registers respectively – Programmable interruptpriority,setthroughGIOLVLSET and GIOLVLCLR registers
• Internalpullup/pulldownallowsunused I/Opinstobe leftunconnected Forinformationon inputand outputtimingssee Section3.8and Section3.9 Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 75 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW N2HETx TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com

5.4 Enhanced High-End Timer (N2HET)

The N2HET isan advanced intelligenttimerthatprovidessophisticatedtimingfunctionsforreal-time applications.The timerissoftware-controlled,usinga reduced instructionset,witha specializedtimer micromachineand an attachedI/O port.The N2HET can be used forpulsewidthmodulated outputs, captureor compare inputs,or general-purposeI/O..Itisespeciallywellsuitedforapplicationsrequiring multiplesensorinformationand driveactuatorswithcomplexand accuratetimepulses.

5.4.1 Features

The N2HET module has thefollowingfeatures:

• Programmable timerforinputand outputtimingfunctions
• Reduced instructionset(30instructions)fordedicatedtimeand anglefunctions
• 128 words ofinstructionRAM protectedby parity
• User definednumber of25-bitvirtualcountersfortimer,eventcountersand anglecounters
• 7-bithardwarecountersforeach pinallowup to32-bitresolutioninconjunctionwiththe25-bitvirtual counters
• Up to19 pinsusableforinputsignalmeasurements oroutputsignalgeneration
• Programmable suppressionfilterforeach inputpinwithadjustablelimitingfrequency
• Low CPU overheadand interruptload
• EfficientdatatransfertoorfromtheCPU memory withdedicatedHigh-End-TimerTransferUnit(HTU)
• Diagnosticcapabilitieswithdifferentloopbackmechanisms and pinstatusreadbackfunctionality

5.4.2 N2HET RAM Organization

The timerRAM uses 4 RAM banks,where each bank has two portaccesscapability.Thismeans thatone RAM addressmay be writtenwhileanotheraddressisread.The RAM words are96-bitswide,whichare splitintothree32-bitfields(program,control,and data).

5.4.3 InputTiming Specifications

The N2HET instructionsPCNT and WCAP impose some timingconstraintson theinputsignals. Figure5-5.N2HET InputCapture Timings

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Table5-8.Dynamic CharacteristicsfortheN2HET InputCapture Functionality(1)(2) PARAMETER MIN MAX UNIT

1 Inputsignalperiod,PCNT orWCAP forrisingedge (HRP) (LRP)tc(VCLK2) + 2 225 (HRP) (LRP)tc(VCLK2) -2 ns

2 Inputsignalperiod,PCNT orWCAP forfallingedge (HRP) (LRP)tc(VCLK2) + 2 225 (HRP) (LRP)tc(VCLK2) -2 ns

3 Inputsignalhighphase,PCNT orWCAP forrising 2(HRP) tc(VCLK2) + 2 225 (HRP) (LRP)tc(VCLK2) -2 ns

4 Inputsignallowphase,PCNT orWCAP forfalling 2(HRP) tc(VCLK2) + 2 225 (HRP) (LRP)tc(VCLK2) -2 ns

(1) Intheabove table,LRP = Low ResolutionClockPeriodand HRP = HighResolutionClockPeriod (2) Timingsintheabove tablerepresenttheinclusionoftheNHET channelenhancement toallowa finerresolutionon inputcapture.

5.4.4 N2HET Checking

5.4.4.1 Output Monitoringusing Dual Clock Comparator (DCC)

N2HET[31] isconnectedas a clocksourceforcounter1 inDCC1. Thisallowstheapplicationtomeasure thefrequencyofthepulse-widthmodulated(PWM) signalon N2HET[31]. N2HET[31] can be configuredtobe an internal-onlychannel.Thatis,theconnectiontotheDCC module is made directlyfromtheoutputoftheN2HET module (fromtheinputoftheoutputbuffer). Formore informationon DCC see Section4.6.3.

5.4.5 DisablingN2HET Outputs

Some applicationsrequirethe N2HET outputsto be disabledunder some faultcondition.The N2HET module providesthiscapabilityviathe"PinDisable"inputsignal.Thissignal,when drivenlow,causes the N2HET outputsidentifiedby a programmable register(HETPINDIS) to be tri-stated.Please referto the deviceTechnicalReferenceManual formore detailson the"N2HET PinDisable"feature. GIOA[5] and EQEPERR are connectedto the "PinDisable"inputforN2HET. In the case of GIOA[5] connection,thisconnectionismade from the outputof the inputbuffer.In the case of EQEPERR, the EQEPERR outputsignalisassertedinthe eventof a phase error.Thissignalisinvertedand double- synchronizedtoVCLK2 forinputintotheN2HET PIN_nDISABLE port. The PIN_nDISABLE portinputsourceisselectablebetween theGIOA[5]and EQEPERR sources.Thisis achievedviathePINMMR9[1:0] bits. Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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5.4.6 High-End Timer TransferUnit(N2HET)

A HighEnd TimerTransferUnit(N2HET) can performDMA typetransactionstotransferN2HET datatoor frommain memory. A Memory ProtectionUnit(MPU) isbuiltintotheN2HET.

5.4.6.1 Features

• CPU independent
• MasterPorttoaccesssystemmemory
• 8 controlpacketssupportingdualbufferconfiguration
• ControlpacketinformationisstoredinRAM protectedby parity
• Eventsynchronization(N2HET transferrequests)
• Supports32 or64 bittransactions
• Addressingmodes forN2HET address(8byteor16 byte)and systemmemory address(fixed,32 bitor 64bit)
• One shot,circularand autoswitchbuffertransfermodes
• Requestlostdetection

5.4.6.2 TriggerConnections

Table5-9.N2HET Request LineConnection Modules Request Source HET TU1 Request N2HET HTUREQ[0] HET TU1 DCP[0] N2HET HTUREQ[1] HET TU DCP[1] N2HET HTUREQ[2] HET TU DCP[2] N2HET HTUREQ[3] HET TU DCP[3] N2HET HTUREQ[4] HET TU DCP[4] N2HET HTUREQ[5] HET TU DCP[5] N2HET HTUREQ[6] HET TU DCP[6] N2HET HTUREQ[7] HET TU DCP[7]

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5.5 ControllerArea Network (DCAN)

The DCAN supportsthe CAN 2.0B protocolstandardand uses a serial,multimastercommunication protocolthatefficientlysupportsdistributedreal-timecontrolwithrobustcommunicationratesofup to1 megabit per second (Mbps). The DCAN is idealfor applicationsoperatingin noisy and harsh environments(e.g.,automotiveand industrialfields)that requirereliableserialcommunication or multiplexedwiring.

5.5.1 Features

FeaturesoftheDCAN module include:

• SupportsCAN protocolversion2.0partA,B
• Bitratesup to1 MBit/s
• The CAN kernelcan be clockedby theoscillatorforbaud-rategeneration.
• 32 and 16 mailboxeson DCAN1 and DCAN2, respectively
• Individualidentifiermask foreach message object
• Programmable FIFO mode formessage objects
• Programmable loop-backmodes forself-testoperation
• Automaticbus on afterBus-Offstateby a programmable32-bittimer
• Message RAM protectedby parity
• DirectaccesstoMessage RAM duringtestmode
• CAN Rx /Tx pinsconfigurableas generalpurposeIO pins
• Message RAM AutoInitialization Formore informationon theDCAN see thedeviceTechnicalReferenceManual.

5.5.2 Electricaland Timing Specifications

Table5-10.Dynamic CharacteristicsfortheDCANx TX and RX pins Parameter MIN MAX Unit td(CANnTX) Delaytime,transmitshiftregistertoCANnTX pin(1) 15 ns td(CANnRX) Delaytime,CANnRX pintoreceiveshiftregister 5 ns (1) These valuesdo notincluderise/falltimesoftheoutputbuffer. Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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5.6 LocalInterconnectNetwork Interface(LIN)

The SCI/LINmodule can be programmed towork eitheras an SCI oras a LIN.The coreofthemodule is an SCI.The SCI’s hardwarefeaturesareaugmented toachieveLIN compatibility. The SCI module isa universalasynchronousreceiver-transmitterthatimplementsthestandardnonreturn tozeroformat.The SCI can be used tocommunicate,forexample,throughan RS-232 portorovera K- line. The LIN standardisbased on the SCI (UART) serialdata linkformat.The communicationconceptis single-master/multiple-slavewitha message identificationformulti-casttransmissionbetween any network nodes.

5.6.1 LIN Features

The followingarefeaturesoftheLIN module:

• CompatibletoLIN 1.3,2.0and 2.1protocols
• Multi-bufferedreceiveand transmitunits
• Identificationmasks formessage filtering
• AutomaticMasterHeader Generation – Programmable Synch BreakField – Synch Field – IdentifierField
• SlaveAutomaticSynchronization – Synch breakdetection – Optionalbaudrateupdate – SynchronizationValidation
• 231 programmabletransmissionrateswith7 fractionalbits
• Errordetection
• 2 Interruptlineswithpriorityencoding

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5.7 Multi-Buffered/Standard SerialPeripheralInterface

The MibSPI is a high-speedsynchronous serialinput/outputportthatallowsa serialbitstream of programmed length(2to16 bits)tobe shiftedinand outofthedeviceata programmed bit-transferrate. TypicalapplicationsfortheSPI includeinterfacingtoexternalperipherals,such as I/Os,memories,display drivers,and analog-to-digitalconverters.

5.7.1 Features

BothStandardand MibSPI modules have thefollowingfeatures:

• 16-bitshiftregister
• Receivebufferregister
• 8-bitbaud clockgenerator,supportsmax up to20Mhz baud rate
• SPICLK can be internally-generated(mastermode) or receivedfrom an externalclocksource(slave mode)
• Each word transferredcan have a uniqueformat
• SPI I/Osnotused inthecommunicationcan be used as digitalinput/outputsignals Table5-11.MibSPI/SPIDefaultConfigurations MibSPIx/SPIx I/Os MibSPI1 MIBSPI1SIMO[0],MIBSPI1SOMI[0],MIBSPI1CLK, MIBSPI1nCS[3:0],MIBSPI1nENA SPI2 SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[0] SPI3 SPI3SIMO, SPI3SOMI, SPI3CLK, SPI3nENA, SPI3nCS[0]

5.7.2 MibSPI Transmitand Receive RAM Organization

The MultibufferRAM iscomprisedof128 buffers.Each entryintheMultibufferRAM consistsof4 parts:a 16-bittransmitfield,a 16-bitreceivefield,a 16-bitcontrolfieldand a 16-bitstatusfield.The Multibuffer RAM can be partitionedintomultipletransfergroupwithvariablenumber ofbufferseach.

5.7.3 MibSPI TransmitTriggerEvents

Each ofthetransfergroupscan be configuredindividually.For each ofthetransfergroupsa triggerevent and a triggersourcecan be chosen.A triggereventcan be,forexample,a risingedge ora permanentlow levelata selectabletriggersource.Up to15 triggersourcesare availablewhich can be utilizedby each transfergroup.These triggeroptionsarelistedinTable5-12and . Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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5.7.3.1 MIBSPI1 Event TriggerHookup

Table5-12.MIBSPI1 Event TriggerHookup Event # TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No triggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET[8] EVENT9 1010 N2HET[10] EVENT10 1011 N2HET[12] EVENT11 1100 N2HET[14] EVENT12 1101 N2HET[16] EVENT13 1110 N2HET[18] EVENT14 1111 InternTickcounter NOTE ForN2HET triggersources,theconnectiontotheMibSPI1 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HET module boundary).This way, a trigger conditioncan be generatedeven iftheN2HET signalisnotselectedtobe outputon thepad. NOTE For GIOx triggersources,theconnectiontotheMibSPI1 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeitherby selectingtheGIOx pinas an outputpin,or by drivingtheGIOx pinfrom an externaltrigger source.

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5.7.4 MibSPI/SPIMaster Mode I/OTiming Specifications

Table5-13.SPI Master Mode ExternalTiming Parameters (CLOCK PHASE = 0,SPICLK = output,SPISIMO = output,and SPISOMI = input)(1)(2)(3) NO. Parameter MIN MAX Unit 1 tc(SPC)M Cycletime,SPICLK (4) 30 256tc(VCLK) ns 2(5) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 3(5) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 4(5) td(SPCH-SIMO)M Delaytime,SPISIMO validbefore 0.5tc(SPC)M – 5 ns SPICLK low(clockpolarity= 0) td(SPCL-SIMO)M Delaytime,SPISIMO validbefore 0.5tc(SPC)M – 5 SPICLK high(clockpolarity= 1) 5(5) tv(SPCL-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tf(SPC)– 3 ns SPICLK low(clockpolarity= 0) tv(SPCH-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tr(SPC)– 3 SPICLK high(clockpolarity= 1) 6(5) tsu(SOMI-SPCL)M Setuptime,SPISOMI beforeSPICLK 0.5tf(SPC)+ 2 ns low(clockpolarity= 0) tsu(SOMI-SPCH)M Setuptime,SPISOMI beforeSPICLK 0.5tf(SPC)+ 2 high(clockpolarity= 1) 7(5) th(SPCL-SOMI)M Holdtime,SPISOMI datavalidafter 5 ns SPICLK low(clockpolarity= 0) th(SPCH-SOMI)M Holdtime,SPISOMI datavalidafter 5 SPICLK high(clockpolarity= 1) 8(6) tC2TDELAY SetuptimeCS active CSHOLD = 0 C2TDELAY*t c(VCLK) + 2*tc(VCLK) (C2TDELAY+2) *tc(VCLK) - ns untilSPICLK high -tf(SPICS)+ tr(SPC)– 5 tf(SPICS)+ tr(SPC)+ 3 (clockpolarity= 0) CSHOLD = 1 C2TDELAY*t c(VCLK) + 3*tc(VCLK) (C2TDELAY+3) *tc(VCLK) - -tf(SPICS)+ tr(SPC)– 5 tf(SPICS)+ tr(SPC)+ 3 SetuptimeCS active CSHOLD = 0 C2TDELAY*t c(VCLK) + 2*tc(VCLK) (C2TDELAY+2) *tc(VCLK) - ns untilSPICLK low -tf(SPICS)+ tf(SPC)– 5 tf(SPICS)+ tf(SPC)+ 3 (clockpolarity= 1) CSHOLD = 1 C2TDELAY*t c(VCLK) + 3*tc(VCLK) (C2TDELAY+3) *tc(VCLK) - -tf(SPICS)+ tf(SPC)– 5 tf(SPICS)+ tf(SPC)+ 3 9(6) tT2CDELAY HoldtimeSPICLK lowCS untilinactive 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns (clockpolarity= 0) T2CDELAY*t c(VCLK) + tc(VCLK) - T2CDELAY*t c(VCLK) + tc(VCLK) - tf(SPC)+ tr(SPICS)-5 tf(SPC)+ tr(SPICS)+ 8 HoldtimeSPICLK highuntilCS 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns inactive(clockpolarity= 1) T2CDELAY*t c(VCLK) + tc(VCLK) - T2CDELAY*t c(VCLK) + tc(VCLK) - tr(SPC)+ tr(SPICS)-5 tr(SPC)+ tr(SPICS)+ 8 10 tSPIENA SPIENAn Sample point (C2TDELAY+1) *tc(VCLK) - (C2TDELAY+1)*tc(VCLK) ns tf(SPICS)– 25 11 tSPIENAW SPIENAn Sample pointfromwriteto (C2TDELAY+2)*tc(VCLK) ns buffer (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (3) Forriseand falltimings,see Table3-4. (4) When theSPI isinMastermode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 30ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)M = 2tc(VCLK) ≥ 30ns. The externalloadon theSPICLK pinmust be lessthan60pF. (5) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). (6) C2TDELAY and T2CDELAY isprogrammed intheSPIDELAY register Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW SPICLK (clock polarity=0) SPISIMO SPICSn Master Out Data Is Valid SPICLK (clock polarity=1) SPIENAn Write to buffer SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Figure5-6.SPI Master Mode ExternalTiming (CLOCK PHASE = 0) Figure5-7.SPI Master Mode Chip SelectTiming (CLOCK PHASE = 0)

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Table5-14.SPI Master Mode ExternalTiming Parameters (CLOCK PHASE = 1,SPICLK = output,SPISIMO = output,and SPISOMI = input)(1)(2)(3) NO. Parameter MIN MAX Unit 1 tc(SPC)M Cycletime,SPICLK (4) 30 256tc(VCLK) ns 2(5) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 3(5) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 4(5) tv(SIMO-SPCH)M Validtime,SPICLK highafter 0.5tc(SPC)M – 2 ns SPISIMO datavalid(clockpolarity= tv(SIMO-SPCL)M Validtime,SPICLK lowafter 0.5tc(SPC)M – 2 SPISIMO datavalid(clockpolarity= 5(5) tv(SPCH-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tr(SPC)– 3 ns SPICLK high(clockpolarity= 0) tv(SPCL-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tf(SPC)– 3 SPICLK low(clockpolarity= 1) 6(5) tsu(SOMI-SPCH)M Setuptime,SPISOMI before tr(SPC) ns SPICLK high(clockpolarity= 0) tsu(SOMI-SPCL)M Setuptime,SPISOMI before tf(SPC) SPICLK low(clockpolarity= 1) 7(5) tv(SPCH-SOMI)M Validtime,SPISOMI datavalidafter 5 ns SPICLK high(clockpolarity= 0) tv(SPCL-SOMI)M Validtime,SPISOMI datavalidafter 5 SPICLK low(clockpolarity= 1) 8(6) tC2TDELAY SetuptimeCS CSHOLD = 0 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns activeuntilSPICLK (C2TDELAY+2) *tc(VCLK) - (C2TDELAY+2) *tc(VCLK) - high(clockpolarity= tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 0) CSHOLD = 1 0.5*tc(SPC)M + 0.5*tc(SPC)M + (C2TDELAY+3) *tc(VCLK) - (C2TDELAY+3) *tc(VCLK) - tf(SPICS)+ tr(SPC)– 5 tf(SPICS)+ tr(SPC)+ 3 SetuptimeCS CSHOLD = 0 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns activeuntilSPICLK (C2TDELAY+2) *tc(VCLK) - (C2TDELAY+2) *tc(VCLK) - low(clockpolarity= tf(SPICS)+ tf(SPC)– 5 tf(SPICS)+ tf(SPC)+ 3 1) CSHOLD = 1 0.5*tc(SPC)M + 0.5*tc(SPC)M + (C2TDELAY+3) *tc(VCLK) - (C2TDELAY+3) *tc(VCLK) - tf(SPICS)+ tf(SPC)– 5 tf(SPICS)+ tf(SPC)+ 3 9(6) tT2CDELAY HoldtimeSPICLK lowCS until T2CDELAY*t c(VCLK) + T2CDELAY*t c(VCLK) + ns inactive(clockpolarity= 0) tc(VCLK) -tf(SPC)+ tr(SPICS)- tc(VCLK) -tf(SPC)+ tr(SPICS)+ 5 8 HoldtimeSPICLK highuntilCS T2CDELAY*t c(VCLK) + T2CDELAY*t c(VCLK) + ns inactive(clockpolarity= 1) tc(VCLK) -tr(SPC)+ tr(SPICS)- tc(VCLK) -tr(SPC)+ tr(SPICS)+ 5 8 10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)* tc(VCLK) - (C2TDELAY+1)*tc(VCLK) ns tf(SPICS)– 25 11 tSPIENAW SPIENAn Sample pointfromwriteto (C2TDELAY+2)*tc(VCLK) ns buffer (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (3) Forriseand falltimings,see theTable3-4. (4) When theSPI isinMastermode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 30ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)M = 2tc(VCLK) ≥ 30ns. The externalloadon theSPICLK pinmust be lessthan60pF. (5) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). (6) C2TDELAY and T2CDELAY isprogrammed intheSPIDELAY register Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW SPICLK (clock polarity=0) SPISIMO SPICSn Master Out Data Is Valid SPICLK (clock polarity=1) SPIENAn Write to buffer SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Data Valid Master In Data Must Be Valid Master Out Data Is Valid TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Figure5-8.SPI Master Mode ExternalTiming (CLOCK PHASE = 1) Figure5-9.SPI Master Mode Chip SelectTiming (CLOCK PHASE = 1)

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5.7.5 SPI SlaveMode I/OTimings

Table5-15.SPI SlaveMode ExternalTiming Parameters (CLOCK PHASE = 0,SPICLK = input,SPISIMO = input,and SPISOMI = output)(1)(2)(3)(4) NO. Parameter MIN MAX Unit 1 tc(SPC)S Cycletime,SPICLK (5) 30 256tc(VCLK) ns 2(6) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 0) 14 ns tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 1) 14 3(6) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 0) 14 ns tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 1) 14 4(6) td(SPCH-SOMI)S Delaytime,SPISOMI validafterSPICLK high(clock trf(SOMI)+ 10 ns polarity= 0) td(SPCL-SOMI)S Delaytime,SPISOMI validafterSPICLK low(clockpolarity trf(SOMI)+ 10 = 1) 5(6) th(SPCH-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK high(clock 2 ns polarity=0) th(SPCL-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK low(clock 2 polarity=1) 6(6) tsu(SIMO-SPCL)S Setuptime,SPISIMO beforeSPICLK low(clockpolarity= 2 ns tsu(SIMO-SPCH)S Setuptime,SPISIMO beforeSPICLK high(clockpolarity= 2 7(6) th(SPCL-SIMO)S Holdtime,SPISIMO datavalidafterSPICLK low(clock 2 ns polarity= 0) th(SPCH-SIMO)S Holdtime,SPISIMO datavalidafterS PICLK high(clock 2 polarity= 1) 8 td(SPCL-SENAH)S Delaytime,SPIENAn highafterlastSPICLK low(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) ns polarity= 0) td(SPCH-SENAH)S Delaytime,SPIENAn highafterlastSPICLK high(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) polarity= 1) 9 td(SCSL-SENAL)S Delaytime,SPIENAn lowafterSPICSn low(ifnew data tf(ENAn) tc(VCLK)+tf(ENAn)+1 ns has been writtentotheSPI buffer) 4 (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) IftheSPI isinslavemode, thefollowingmust be true:tc(SPC)S ≥ (PS + 1)tc(VCLK),where PS = prescalevaluesetinSPIFMTx.[15:8]. (3) Forriseand falltimings,see Table3-4. (4) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (5) When theSPI isinSlavemode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)S = 2tc(VCLK) ≥ 40ns. (6) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW SPICLK (clock polarity=0) SPICSn SPICLK (clock polarity=1) SPIENAn SPISOMI SPICLK (clock□polarity□=□1) SPICLK (clock□polarity□=□0) SPISIMO□Data Must□Be□Valid SPISOMI□Data□Is□Valid 666 SPISIMO TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Figure5-10.SPI SlaveMode ExternalTiming (CLOCK PHASE = 0) Figure5-11.SPI SlaveMode Enable Timing (CLOCK PHASE = 0)

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Table5-16.SPI SlaveMode ExternalTiming Parameters (CLOCK PHASE = 1,SPICLK = input,SPISIMO = input,and SPISOMI = output)(1)(2)(3)(4) NO. Parameter MIN MAX Unit 1 tc(SPC)S Cycletime,SPICLK (5) 30 256tc(VCLK) ns 2(6) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 0) 14 ns tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 1) 14 3(6) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 0) 14 ns tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 1) 14 4(6) td(SOMI-SPCL)S Dealytime,SPISOMI datavalidafterSPICLK low trf(SOMI)+ 10 ns (clockpolarity= 0) td(SOMI-SPCH)S Delaytime,SPISOMI datavalidafterSPICLK high trf(SOMI)+ 10 (clockpolarity= 1) 5(6) th(SPCL-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK high 2 ns (clockpolarity=0) th(SPCH-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK low(clock 2 polarity=1) 6(6) tsu(SIMO-SPCH)S Setuptime,SPISIMO beforeSPICLK high(clock 2 ns polarity= 0) tsu(SIMO-SPCL)S Setuptime,SPISIMO beforeSPICLK low(clockpolarity 2 = 1) 7(6) tv(SPCH-SIMO)S Hightime,SPISIMO datavalidafterSPICLK high 2 ns (clockpolarity= 0) tv(SPCL-SIMO)S Hightime,SPISIMO datavalidafterSPICLK low(clock 2 polarity= 1) 8 td(SPCH-SENAH)S Delaytime,SPIENAn highafterlastSPICLK high 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) ns (clockpolarity= 0) td(SPCL-SENAH)S Delaytime,SPIENAn highafterlastSPICLK low(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) polarity= 1) 9 td(SCSL-SENAL)S Delaytime,SPIENAn lowafterSPICSn low(ifnew data tf(ENAn) tc(VCLK)+tf(ENAn)+14 ns has been writtentotheSPI buffer) (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) IftheSPI isinslavemode, thefollowingmust be true:tc(SPC)S≤ (PS + 1)tc(VCLK),where PS = prescalevaluesetinSPIFMTx.[15:8]. (3) Forriseand falltimings,see Table3-4. (4) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (5) When theSPI isinSlavemode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)S = 2tc(VCLK) ≥ 40ns. (6) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW SPISOMI Slave Out Data Is Valid SPICLK (clock polarity=0) SPICSn SPICLK (clock polarity=1) SPIENAn SPISIMO SPISOMI SPISIMO Data Must Be Valid SPISOMI Data Is Valid 666 SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Figure5-12.SPI SlaveMode ExternalTiming (CLOCK PHASE = 1) Figure5-13.SPI SlaveMode Enable Timing (CLOCK PHASE = 1)

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PRODUCT□PREVIEW EQEP A VIM EQEPINTn EQEP Module I/O MUX CTRL EQEPENCLK EQEPIO EQEPI VBUSP Interface VCLK EQEPB EQEPIOE EQEPSO EQEPS EQEPSOE NHETnDIS_SEL EQEP CLK GA TE CDDISx.9 VCLK ACK CLKSTOP_REQ SYS_nRST NHET VCLK2 nDIS GIOA[5] EQEPERR nEQEPERR _SYNC TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

5.8 Enhanced QuadratureEncoder (eQEP)

Figure5-14shows theeQEP module interconnectionson thedevice. Figure5-14.eQEP Module Interconnections

5.8.1 Clock Enable ControlforeQEPx Modules

The devicelevelcontroloftheeQEP clockisaccomplishedthroughtheenable/disableoftheVCLK clock domain foreQEP only.Thisisrealizedusingbit9 oftheCLKDDIS register.The eQEP clocksourceis enabledby default.

5.8.2 Using eQEPx Phase Error

The eQEP module setsthe EQEPERR signaloutputwhenever a phase errorisdetectedinitsinputs EQEPxA and EQEPxB. ThiserrorsignalfromboththeeQEP modules isinputtotheconnectionselection multiplexor.As shown inFigure5-14,theoutputofthisselectionmultiplexorisinvertedand connectedto the N2HET module. This connectionallowsthe applicationto definethe response to a phase error indicatedby theeQEP modules.

5.8.3 InputConnections toeQEPx Modules

The inputconnectionsto each of the eQEP modules can be selectedbetween a double-VCLK- synchronizedinputora double-VCLK-synchronizedand filteredinput,as shown inTable5-17. Table5-17.Device-LevelInputSynchronization InputSignal ControlforDouble-SynchronizedConnection to ControlforDouble-Synchronizedand Filtered eQEPx Connection toeQEPx eQEPA PINMMR8[0] = 1 PINMMR8[0] = 0 and PINMMR8[1] = 1 eQEPB PINMMR8[8] = 1 PINMMR8[8] = 0 and PINMMR8[9] = 1 eQEPI PINMMR8[16] = 1 PINMMR8[16] = 0 and PINMMR8[17] = 1 eQEPS PINMMR8[24] = 1 PINMMR8[24] = 0 and PINMMR8[25] = 1 Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

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5.8.4 Enhanced QuadratureEncoder Pulse (eQEPx) Timing

Table5-18.eQEPx Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw(QEPP) QEP inputperiod Synchronous 2 tc(VCLK) cycles Synchronous,withinput 2 tc(VCLK) + filterwidth cycles filter tw(INDEXH) QEP IndexInputHighTime Synchronous 2 tc(VCLK) cycles Synchronous,withinput 2 tc(VCLK) + filterwidth cycles filter tw(INDEXL) QEP IndexInputLow Time Synchronous 2 tc(VCLK) cycles Synchronous,withinput 2 tc(VCLK) + filterwidth cycles filter tw(STROBH) QEP StrobeInputHighTime Synchronous 2 tc(VCLK) cycles Synchronous,withinput 2 tc(VCLK) + filterwidth cycles filter tw(STROBL) QEP StrobeInputLow Time Synchronous 2 tc(VCLK) cycles Synchronous,withinput 2 tc(VCLK) + filterwidth cycles filter Table5-19.eQEPx SwitchingCharacteristics PARAMETER MIN MAX UNIT td(CNTR)xin Delaytime,externalclocktocounterincrement 4 tc(VCLK) cycles td(PCS-OUT)QEP Delaytime,QEP inputedge topositioncompare syncoutput 6 tc(VCLK) cycles

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6 Device and Documentation Support

6.1 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall devicesand supporttools.Each commercialfamilymember has one of threeprefixes:TMX, TMP, or TMS. Texas Instrumentsrecommends two ofthreepossibleprefixdesignatorsforitssupporttools:TMDX and TMDS. These prefixesrepresentevolutionarystages of productdevelopment from engineering prototypes(TMX/TMDX) throughfullyqualifiedproductiondevices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatis not necessarilyrepresentativeof the finaldevice'selectrical specifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthas notcompleted qualityand reliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproduct that has not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-supporttoolsare shipped againstthe following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devicesand TMDS development-supporttoolshave been characterizedfully,and the qualityand reliabilityofthedevicehave been demonstratedfully.TI'sstandardwarrantyapplies. Predictionsshow thatprototypedevices(TMX or TMP) have a greaterfailureratethan the standard productiondevices.Texas Instrumentsrecommends thatthesedevicesnot be used inany production systembecause theirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobe used. Copyright© 2012,Texas InstrumentsIncorporated Deviceand DocumentationSupport 93 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW Prefix: TM TMS□=□Fully□Qualified TMP =□Prototype TMX□=□Samples Core Technology: 570□=□Cortex□R4 Architecture: (not□included□in□orderable□part□#) Flash□Memory□Size: 04□=□384kB RAM□MemorySize: 3□=□32kB Peripheral□Set: Die□Revision: Package Type: PZ□=□100□Pin□Package Temperature□Range: Q□=□-40...+125 C o Quality□Designator: Q1□= Automotive Shipping□Options: R□= Tape□and□Reel Full□Part□# TMS 570 LS 04 3 2 PZ Q Q1 R Orderable□Part□# TMX 570 04 3 2 PZ Q Q1 R Prefix: TM TMS□=□Fully□Qualified TMP =□Prototype TMX□=□Samples Core Technology: 570□=□Cortex□R4 Architecture: (not□included□in□orderable□part□#) Flash□Memory□Size: 04□=□384kB 03□=□256kB RAM□MemorySize: 3□=□32kB Peripheral□Set: Die□Revision: Package Type: PZ□=□100□Pin□Package Temperature□Range: Q□=□-40...+125 C o Quality□Designator: Q1□= Automotive Shipping□Options: R□= Tape□and□Reel TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com The figurebelowillustratesthenumberingand symbolnomenclaturefortheTMS570LS0432/0332 . Figure6-1.Device Numbering Conventions

6.2 Device Identification

6.2.1 Device IdentificationCode Register

The deviceidentificationcode registeridentifiesseveralaspectsofthedeviceincludingthesiliconversion. The detailsofthedeviceidentificationcode registerareshown inTable6-1.The deviceidentificationcode registervalueforthisdeviceis:

• Rev 0 = 0x8048AD05

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012 Figure6-2.Device ID BitAllocationRegister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CP-15 UNIQUE ID TECH R-1 R-00000000100100 R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TECH I/O PERIPH FLASH ECC RAM VERSION 1 0 1 VOLT PARITY ECC AGE R-101 R-0 R-1 R-10 R-1 R-00000 R-1 R-0 R-1 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Copyright© 2012,Texas InstrumentsIncorporated Deviceand DocumentationSupport 95 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 SPNS186 –OCTOBER 2012 www.ti.com Table6-1.Device ID BitAllocationRegisterFieldDescriptions Bit Field Value Description

31 CP15 Indicatesthepresenceofcoprocessor15

1 CP15 present

30-17 UNIQUE ID 100100 Siliconversion(revision)bits. Thisbitfieldholdsa uniquenumber fora dedicateddeviceconfiguration(die). 16-13 TECH Processtechnologyon whichthedeviceismanufactured.

0101 F021

12 I/OVOLTAGE I/Ovoltageofthedevice. 0 I/Oare3.3v

11 PERIPHERAL PeripheralParity

1 Parityon peripheralmemories

10 Program memory withECC

8 RAM ECC IndicatesifRAM memory ECC ispresent.

1 ECC implemented

7-3 REVISION 0 RevisionoftheDevice. 2-0 FAMILY ID 101 The platformfamilyID isalways0b101

6.2.2 Die IdentificationRegisters

The fourdieID registersataddresses0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a 128-bitdieidwiththeinformationas shown inTableTable6-2. Table6-2.Die-IDRegisters Item # ofBits BitLocation X Coord.on Wafer 8 7..0 Y Coord.on Wafer 8 15..8 Wafer # 6 21..16 Lot# 24 45..22 Reserved 82 127..46

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PRODUCT□PREVIEW TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 –OCTOBER 2012

7 MechanicalData

7.1 Thermal Data

Table7-1shows thethermalresistancecharacteristicsforthePQFP -PZ mechanicalpackages. Table7-1.Thermal ResistanceCharacteristics (S-PQFP Package) [PZ] PARAMETER °C/W R θJA 48 R θJC 5

7.2 Packaging Information

The followingpackaginginformationreflectsthemost currentreleaseddataavailableforthedesignated device(s).Thisdataissubjecttochange withoutnoticeand withoutrevisionofthisdocument. Copyright© 2012,Texas InstrumentsIncorporated MechanicalData 97 SubmitDocumentationFeedback ProductFolderLinks:TMS570LS0432 TMS570LS0332

PRODUCT□PREVIEW FunctionalSafetyDisclaimerforSafetyCriticalSolutions TI'ssafetycriticalsolutions,includingintegratedcircuits,softwareand toolshelpTI'scustomerscreateend productsthatmay be used inappropriatelydesignedsafety-criticalapplicationstocomplywithfunctionalsafetystandardsorrequirements. Buyers representand agree thatthey have allthe necessaryexpertiseto design,manage and assure effectivesystem-level safeguardsto anticipate,monitorand controlsystem failuresin safety-criticalapplications.Buyers agree and accept sole responsibilitytomeet and comply withallapplicableregulatorystandardsand safety-relatedrequirementsconcerningtheirsystems and end-productswhich use TI'ssafety-criticalapplications.Buyers willfullyindemnifyTI and itsrepresentativesagainstany damages arisingoutoftheuse ofTIproductsinsafety-criticalapplications. TIintegratedcircuitsarenotauthorizedforuse inFDA ClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficers ofthepartieshave executeda specialagreementspecificallygoverningsuch use.

www.ti.com 3-May-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TMS5700332APZQQ1 ACTIVE LQFP PZ 100 TBD Call TI Call TI -40 to 125 TMX5700432APZQQ1 ACTIVE LQFP PZ 100 1 TBD Call TI Call TI -40 to 125 TMX5700432PZQQ1 ACTIVE LQFP PZ 100 1 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149/B 11/96 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 12,00 TYP 0,17 100 SQ SQ15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0°–7° Seating Plane 0,08 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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