TMX470R1A64PN

TMS470R1A64 TI | Alldatasheet

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Technical content

Features

(MibADC) Core Supply Voltage (VCC): 1.71 V 2.05 V 8-Channel I/O Supply Voltage (VCCIO): 3.0 V 3.6 V 64-Word FIFO Buffer Low-Power Modes: STANDBY and HALT Single- or Continuous-Conversion Modes Industrial Temperature Ranges 1.55 µ s Minimum Sample and Conversion Time 470+ System Module Calibration Mode and Self-Test (AWD) Timer Dedicated General-Purpose I/O (GIO) Pins, Input-Only GIO Pin, and Additional Real-Time Interrupt (RTI) Peripheral I/Os System Integrity and Failure Detection External Clock Prescale (ECP) Module Zero-Pin Phase-Locked Loop (ZPLL)-Based Programmable Low-Frequency External Clock Module With Prescaler Clock (CLK) Multiply-by-4 or Internal ZPLL Option On-Chip Scan-Base Emulation Logic, IEEE ZPLL Bypass Mode Standard 1149.1 (1) (JTAG) Test-Access Port Six Communication Interfaces: 80-Pin Plastic Low-Profile Quad Flatpack (PN Two Serial Peripheral Interfaces (SPIs) Suffix) 255 Programmable Baud Rates (1) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Two Serial Communication Interfaces (SCIs) Scan Architecture specification. Boundary scan is not sup- Selectable Baud Rates ported on this device. ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited. ADVANCE INFORMATION concerns new products in the sampling Copyright 2004, Texas Instruments Incorporated or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

www.ti.com ADVANCE INFORMATION TMS470R1A64 80-PIN PN PACKAGE (TOP VIEW) SPI1ENA 1

20 PLLDIS

HET[8] V SSIO VCCIO CLKOUT CANSRX CANSTX SCI1CLK SCI1TX SCI1RX VSS VCC ADEVT ADIN[6] ADIN[4] ADIN[2] ADIN[0]

80 TRST

HET[7] HET[6] HET[4] HET[2] VCCP FLTP2 VCC VSS HET[0] VSS TMS2 TMS VSSAD VCCAD ADREFLO ADREFHI ADIN[8] ADIN[12] ADIN[10] ADIN[14] GIOA[0]/INT0(A) GIOA[1]/ECLK/INT1 SCI2RX SCI2TX HET[24] C2SIaLPN C2SIaTX C2SIaRX VSS VCC SPI2CLK SPI2SIMO SPI2SOMI SPI2ENA HET[22] HET[20] HET[18] AWD SPI1SCS SPI1SIMO SPI1SOMI SPI1CLK VSS OSCOUT OSCIN VCC RST VSSIO VCCIO HET[16] HET[14] HET[12] PORRST GIOA[7]/INT7 GIOA[6]/INT6 GIOA[5]/INT5 GIOA[4]/INT4

DESCRIPTION

GIOA[0]/INT0 (pin 23) is an input-only GIO pin. The TMS470R1A64 (1) device is a member of the Texas Instruments TMS470R1x family of gen- eral-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The A64 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining high code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from The TMS470R1A64 utilizes the big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. High-end embedded control

applications

costs. The A64 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption. The A64 device contains the following: ARM7TDMI 16/32-Bit RISC CPU TMS470R1x system module (SYS) with 470+ enhancements 64K-byte Flash 4K-byte SRAM (1) Throughout the remainder of this document, the TMS470R1A64 device will be referred to as either the full device name, TMS470R1A64, or asA64.

www.ti.com ADVANCE INFORMATION TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Zero-pin phase-locked loop (ZPLL) clock module Analog watchdog (AWD) timer Real-time interrupt RTI) module Two serial peripheral interface (SPI) modules Two serial communication interface (SCI) modules Standard CAN controller (SCC) Class II serial interface (C2SIa) 10-bit multi-buffered analog-to-digital converter (MibADC), 8-input channels High-end timer (HET) controlling I/Os External Clock Prescale (ECP) Up to I/O pins and input-only pin The functions performed by the 470+ system module (SYS) include: Address decoding Memory protection Memory and peripherals bus supervision Reset and abort exception management Prioritization for all internal interrupt sources Device clock control Parallel signature analysis (PSA) This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional module, see the TMS470R1x System Module Reference Guide (literature number SPNU189). The A64 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The Flash memory on the A64 device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface.The Flash operates with a system clock frequency of up to MHz. In pipeline mode, the Flash operates with a system clock frequency of up to MHz. For more detailed information on the Flash, see the F05 Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). The A64 device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIa. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communi- cation rates of up to megabit per second (Mbps). The SCC is ideal for (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIa allows the A64 to transmit and receive messages on a class II network following an SAE J1850 (2) standard. For more detailed functional information on the SPI, SCI, and SCC peripherals, see the specific TMS470R1x Peripheral Reference Guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). For more detailed functional information on the C2SIa peripheral, see the TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218). The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). (2) SAE Standard J1850 Class B Data Communication Network Interface.

www.ti.com ADVANCE INFORMATION TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The A64 device has a 10-bit-resolution sample-and-hold MibADC. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which are triggerable by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides the system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A64 device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212). NOTE: ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference. The A64 device also has an external clock prescaler (ECP) module that, when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

www.ti.com ADVANCE INFORMATION Device Characteristics TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The TMS470R1A64 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table identifies all the characteristics of the TMS470R1A64 device except the SYSTEM and CPU, which are generic. Table Device Characteristics CHARACTERISTICS DEVICE device, see the "Memory Selection Assignment" table Table Flash is pipeline-capable. 64K-Byte Flash INTERNAL MEMORY The A64 RAM is implemented in one array selected by two mem- 4K-Byte SRAM ory-select signals (see the "Memory Selection Assignment" table, Table PERIPHERALS For the device-specific interrupt priority configurations, see the "Interrupt Priority" table Table For the peripheral address ranges and their peripheral selects, see the "A64 Peripherals, System Module, and Flash Base Addresses" table Table CLOCK ZPLL Zero-pin PLL has no external loop filter pins. I/O Port A has external pins GIOA[2]/INT2 and GIOA[3]/INT3 are not GENERAL-PURPOSE I/Os Input only available. ECP YES C2SIa (3-pin) SCI2 has no external clock pin, only transmit/receive pins (SCI2TX and SCI (2-pin) SCI2RX) CAN (HECC and/or SCC) SCC Standard CAN controller SPI (5-pin, 4-pin or 3-pin) (5-pin) SPI2 has no chip select pin. (4-pin) The A64 device has both the logic and registers for a full 32-I/O HET implemented, even though not all pins are available externally. The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. This HR sharing is independent of HET with XOR Share I/O whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a gen- eral-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). HET RAM 64-Instruction Capacity 10-bit, 8-channel 8-channel MibADC. Both the logic and registers for a full 16-channel MibADC 64-word FIFO MibADC are present. CORE VOLTAGE 1.71 2.05 V I/O VOLTAGE 3.0 3.6 V PINS PACKAGE PN

www.ti.com ADVANCE INFORMATION SPI1SCS ZPLL MibADC with 64-Word FIFO PLLDIS OSCOUT 6, 4, 2, 0] ADEVT ADREFLO ADREFHI HET with XOR Share (64-Word) SPI2 SCI1 SCC VSSAD 4, 2, 0] CANSRX CANSTX SCI1TX SCI1CLK VCCAD RAM (4K Bytes) TMS470R1x CPU CPU Address/Data Bus TMS470R1x 470+ SYSTEM MODULE OSCIN External Pins VCCP FLTP2 TCK TMS TDO TDI TRST AWD RST TMS2 PORRST CLKOUT FLASH 64K Bytes (5 Sectors) C2SIa C2SIaTX C2SIaLPN C2SIaRX SCI1RX Crystal External Pins SPI1 SPI2CLK SPI2ENA SPI2SIMO SPI2SOMI GIOGIOA[0]/ GIOA[7:4]/ TEST GIOA[1]/INT[1]/ ECPECLK SCI2 SCI2TX SCI2RX SPI1CLK SPI1ENA SPI1SIMO SPI1SOMI INT[7:4] Expansion Address/Data Bus INT0 TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Functional Block Diagram GIOA[0]/INT[0] is an input-only GIO pin.

www.ti.com ADVANCE INFORMATION TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Table Terminal Functions TERMINAL INTERNAL TYPE (1) (2) PULLUP/ (3) NUMBER HIGH-END TIMER (HET) HET[0] HET[2] The A64 device has both the logic and registers for a full 32-I/O HET implemented, even though not all pins are available externally HET[4] HET[6] Timer input capture or output compare. The HET[31:0] applicable pins can be programmed as general-purpose input/output (GIO) pins. HET[7] HET pins [22, 20, 18, 16, 14, 12, and are high-resolution pins HET[8] for A64. HET[24] is a standard-resolution pin. HET[12] 3.3-V I/O IPD The high-resolution (HR) SHARE feature allows even-numbered HR pins to HET[14] share the next higher odd-numbered HR pin structures. This HR sharing is HET[16] independent of whether or not the odd-numbered pin is available externally. If an odd-numbered pin is available externally and shared, then the odd pin can HET[18] only be used as a general-purpose I/O. For more information on HR SHARE, HET[20] see the TMS470R1x High-End Timer Reference Guide (literature number SPNU199). HET[22] HET[24] STANDARD CAN CONTROLLER (SCC) CANSRX 3.3-V I/O SCC receive pin or GIO pin CANSTX 3.3-V I/O IPU SCC transmit pin or GIO pin CLASS II SERIAL INTERFACE (C2SIA) C2SIaLPN 3.3-V I/O IPD C2SIa module loopback enable pin or GIO pin C2SIaRX 3.3-V I/O C2SIa module receive data input pin or GIO pin C2SIaTX 3.3-V I/O IPD C2SIa module transmit data output pin or GIO pin GENERAL-PURPOSE I/O (GIO) GIOA[0]/INT 3.3-V I GIOA[1]/INT 1/ECLK General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin. GIOA[4]/ GIOA[7:0]/INT[7:0] are interrupt-capable pins. INT4 IPD The GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out GIOA[5]/ function of the external clock prescale (ECP) module. 3.3-V I/O INT5 GIOA[2]/INT[2] and GIOA[3]/INT[3]] pins are not applicable on the A64 device. GIOA[6]/ INT6 GIOA[7]/ INT7 MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) ADEVT 3.3-V I/O MibADC event input. ADEVT can be programmed as a GIO pin. ADIN[0] MibADC analog input pins ADIN[2] The A64 device has only input channels but all S/W registers are capable. ADIN[15,13, 11, and pins are not applicable to the A64 device. ADIN[4] ADIN[6] IPD 3.3-V I ADIN[8] ADIN[10] ADIN[12] ADIN[14] (1) I input, O output, PWR power, GND ground, REF reference voltage, NC no connect (2) All I/O pins, except RST are configured as inputs while PORRST is low and immediately after PORRST goes high. (3) IPD internal pulldown, IPU internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)

www.ti.com ADVANCE INFORMATION TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Table Terminal Functions (continued) TERMINAL INTERNAL TYPE (1) (2) PULLUP/ (3) NUMBER 3.3-V AD REFHI MibADC module high-voltage reference input REF I GND AD REFLO MibADC module low-voltage reference input REF I 3.3-V V CCAD MibADC analog supply voltage PWR V SSAD GND MibADC analog ground reference SERIAL PERIPHERAL INTERFACE (SPI1) SPI1CLK SPI1 clock. SPI1CLK can be programmed as a GIO pin. SPI1ENA SPI1 chip enable. SPI1ENA can be programmed as a GIO pin. SPI1SCS SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin. 3.3-V I/O IPD SPI1SIMO SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as a GIO pin. SPI1SOMI SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as a GIO pin. SERIAL PERIPHERAL INTERFACE (SPI2) SPI2CLK SPI2 clock. SPI2CLK can be programmed as a GIO pin. SPI2ENA SPI2 chip enable. SPI2ENA can be programmed as a GIO pin. SPI2SIMO SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as a 3.3-V I/O IPD GIO pin. SPI2SOMI SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as a GIO pin. ZERO-PIN PHASE-LOCKED LOOP (ZPLL) OSCIN 1.8-V I Crystal connection pin or external clock input OSCOUT 1.8-V O External crystal connection pin PLLDIS Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator becomes the system clock. If not in bypass mode, TI recommends that 3.3-V I IPD PLLDIS be connected to ground or pulled down to ground by an external resistor. SERIAL COMMUNICATIONS INTERFACE (SCI1) SCI1CLK 3.3-V I/O IPD SCI1 clock. SCI1CLK can be programmed as a GIO pin. SCI1RX 3.3-V I/O IPU SCI1 data receive. SCI1RX can be programmed as a GIO pin. SCI1TX 3.3-V I/O IPU SCI1 data transmit. SCI1TX can be programmed as a GIO pin. SERIAL COMMUNICATIONS INTERFACE (SCI2) SCI2RX 3.3-V I/O IPU SCI2 data receive. SCI2RX can be programmed as a GIO pin. SCI2TX 3.3-V I/O IPU SCI2 data transmit. SCI2TX can be programmed as a GIO pin. SYSTEM MODULE (SYS) CLKOUT Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of 3.3-V I/O IPD SYSCLK, ICLK, or MCLK. PORRST Input master chip power-up reset. External V CC monitor circuitry must assert a 3.3-V I IPD power-on reset. RST Bidirectional reset. The internal circuitry can assert a reset, and an external system reset can assert a device reset. 3.3-V I/O IPU On RST the output buffer is implemented as an open drain (drives low only. To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor be connected to RST

www.ti.com ADVANCE INFORMATION TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Table Terminal Functions (continued) TERMINAL INTERNAL TYPE (1) (2) PULLUP/ (3) NUMBER WATCHDOG/REAL-TIME INTERRUPT (WD/RTI) Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not written in time by the system, providing an external RC network circuit is connected. If the user is not using AWD, TI recommends that AWD be connected to ground or pulled down to ground by an external resistor. AWD 3.3-V I/O IPD For more details on the external RC network circuit, see the TMS470R1x System Module Reference Guide (literature number SPNU189) and the application note Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints (literature number SPNA005). TEST/DEBUG (T/D) TCK 3.3-V I IPD Test clock. TCK controls the test hardware (JTAG) TDI Test data in. TDI inputs serial data to the test instruction register, test data 3.3-V I IPU register, and programmable test address (JTAG). TDO Test data out. TDO outputs serial data from the test instruction register, test 3.3-V O IPD data register, identification register, and programmable test address (JTAG). Test enable. Reserved for internal use only. TI recommends that TEST be TEST 3.3-V I IPD connected to ground or pulled down to ground by an external resistor. Serial input for controlling the state of the CPU test access port (TAP) TMS 3.3-V I IPU controller (JTAG) Serial input for controlling the second TAP. TI recommends that TMS2 be TMS2 3.3-V I IPU connected to VCCIO or pulled up to VCCIO by an external resistor. Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) TRST 3.3-V I IPD Boundary-Scan Logic. TI recommends that TRST be pulled down to ground by an external resistor. FLASH NC Flash test pad For proper operation,FLTP2 must not be connected (no FLTP2 connect [NC]). 3.3-V Flash external pump voltage (3.3 V CCP PWR SUPPLY VOLTAGE CORE (1.8 1.8-V V CC Core logic supply voltage PWR SUPPLY VOLTAGE DIGITAL I/O (3.3 3.3-V V CCIO Digital I/O supply voltage PWR SUPPLY GROUND CORE V SS GND Core supply ground reference SUPPLY GROUND DIGITAL I/O V SSIO GND Digital I/O supply ground reference

www.ti.com ADVANCE INFORMATION A64 DEVICE-SPECIFIC INFORMATION memory 0xFFFF_FFFF System Module Control Registers (512K Bytes) Exception, Interrupt, and Reset Vectors Memory (4G Bytes) Program and Data Area Peripheral Control Registers (512K Bytes) Reserved MPU Control Registers Reserved 0xFFF8_0000 0xFFF7_FFFF 0xFFF0_0000 0xFFE8_BFFF 0xFFE8_7FFF 0xFFE8_4024 0xFFE8_4023 0xFFE8_4000 0xFFE0_0000 0x0000_0020 0x0000_001F 0x0000_0000 FIQ IRQ Reserved Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset 0x0000_ 001F 0x0000_ 001C 0x0000_ 0018 0x0000_ 0014 0x0000_ 0010 0x0000_ 000C 0x0000_ 0008 0x0000_ 0004 0x0000_ 0000 Reserved 0xFFFF_FFFF 0xFFFF_FD00 0xFFF8_0000 HET 0xFFF7_FC00 0xFFF7_F800 0xFFF7_F400 0xFFF7_F000 0xFFF7_EC00 0xFFF7_E400 SPI1 SCI1 MibADC GIO/ECP Reserved RAM (4K Bytes) FLASH (64K Bytes)

5 Sectors

0xFFEF_FFFF 0xFFE8_C000 0xFFE8_8000 SCC RAM SCC 0xFFF7_E000 0xFFF7_DC00 0xFFF7_D800 0xFFF7_D400 C2SIa Reserved 0xFFF0_0000 SYSTEM 0xFFE8_3FFF SCI2 0xFFF7_F500 Reserved Reserved SPI2 0xFFF7_C800 0xFFF7_CC00 TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Figure shows the memory map of the A64 device. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000. The CPU registers are not part of the memory map. Figure Memory Map

www.ti.com ADVANCE INFORMATION memory selects TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Memory selects allow the user to address memory arrays (i.e., Flash, RAM, and HET RAM) at user-defined addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx and MFBALRx) that, together, define the array's starting (base) address, block size, and protection. The base address of each memory select is configurable to any memory address boundary that is a multiple of the decoded block size. For more information on how to control and configure these memory select registers, see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number SPNU189). For the memory selection assignments and the memory selected, see Table Table Memory Selection Assignment MEMORY MEMORY SELECTED MEMORY MEMORY BASE STATIC MEM MPU SELECT (ALL INTERNAL) SIZE ADDRESS REGISTER CTL REGISTER (fine) FLASH NO MFBAHR0 and MFBALR0 64K (fine) FLASH NO MFBAHR1 and MFBALR1 (fine) RAM YES MFBAHR2 and MFBALR2 (1) (fine) RAM YES MFBAHR3 and MFBALR3 (fine) HET RAM MFBAHR4 and MFBALR4 SMCR1 (1) The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the memory-base address register. RAM The A64 device contains bytes of internal static RAM configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. This A64 RAM is implemented in one array selected by two memory-select signals. This A64 configuration imposes an additional constraint on the memory map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples of the size of the physical RAM (i.e., for the A64 device). The A64 RAM is addressed through memory selects and The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an operating system while allowing access to the current task. For more detailed information on the MPU portion of the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference Guide (literature number SPNU189). F05 Flash The F05 Flash memory is a nonvolatile electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The F05 Flash has an external state machine for programming and erase functions. See the Flash read and Flash program and erase sections below. Flash protection keys The A64 devices provide Flash protection keys. These four 32-bit protection keys prevent pro- gram/erase/compaction operations from occurring until after the four protection keys have been matched by the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the A64 are located in the last words of the first sector. For more detailed information on the Flash protection keys and the FMPKEY control register, see the protection keys portions of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).

www.ti.com ADVANCE INFORMATION TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Flash read The A64 Flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The Flash is addressed through memory selects and NOTE: The Flash external pump voltage (VCCP) is required for all operations (program, erase, and read). Flash pipeline mode When in pipeline mode, the Flash operates with a system clock frequency of up to MHz (versus a system clock in normal mode of up to MHz). Flash in pipeline mode is capable of accessing 64-bit words and provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the Flash can be read with no wait states when memory addresses are contiguous (after the initial 1-or 2-wait-state reads). NOTE: After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In other words, the A64 device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the Flash configuration mode bit (GLBCTRL.4) will override pipeline mode. Flash program and erase The A64 device Flash has one 64K-byte bank that consists of five sectors. These five sectors are shown in Table Table Flash Sectors SECTOR NO. SEGMENT LOW ADDRESS HIGH ADDRESS Bytes 0x0000_0000 0x0000_1FFF Bytes 0x0000_2000 0x0000_3FFF 16K Bytes 0x0000_4000 0x0000_7FFF 16K Bytes 0x0000_8000 0x0000_BFFF 16K Bytes 0x0000_C000 0x0000_FFFF The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit word. NOTE: The Flash external pump voltage CCP is required for all operations (program, erase, and read). For more detailed information on Flash program and erase operations, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). HET RAM The A64 device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET RAM is addressed through memory select XOR share The A64 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

www.ti.com ADVANCE INFORMATION peripheral selects and base addresses TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The A64 device uses of the peripheral selects to decode the base addresses of the peripherals. These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the SYS module. Control registers for the peripherals, SYS module, and Flash begin at the base addresses shown in Table Table A64 Peripherals, System Module, and Flash Base Addresses ADDRESS RANGE CONNECTING MODULE BASE ADDRESS ENDING ADDRESS PERIPHERAL SELECTS SYSTEM 0xFFFF_FD00 0xFFFF_FFFF N/A RESERVED 0xFFF8_0000 0xFFFF_FCFF N/A HET 0xFFF7_FC00 0xFFF7_FFFF PS[0] SPI1 0xFFF7_F800 0xFFF7_FBFF PS[1] SCI2 0XFFF7_F500 0XFFF7_F7FF PS[2] SCI1 0xFFF7_F400 0xFFF7_F4FF ADC 0xFFF7_F000 0xFFF7_F3FF PS[3] GIO/ECP 0xFFF7_EC00 0xFFF7_EFFF PS[4] RESERVED 0xFFF7_E400 0xFFF7_EBFF PS[5] PS[6] SCC 0xFFF7_E000 0xFFF7_E3FF PS[7] SCC RAM 0xFFF7_DC00 0xFFF7_DFFF PS[8] RESERVED 0XFFF7_D800 0XFFF7_DBFF PS[9] SPI2 0XFFF7_D400 0XFFF7_D7FF PS[10] RESERVED 0xFFF7_CC00 0xFFF7_D3FF PS[11] PS[12] C2SIa 0xFFF7_C800 0xFFF7_CBFF PS[13] RESERVED 0xFFF7_C000 0xFFF7_C7FF PS[14] PS[15] RESERVED 0xFFF0_0000 0xFFF7_BFFF N/A FLASH CONTROL REGISTERS 0xFFE8_8000 0xFFE8_BFFF N/A MPU CONTROL REGISTERS 0xFFE8_4000 0xFFE8_4023 N/A

www.ti.com ADVANCE INFORMATION interrupt priority TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.). Although the CIM can accept up to interrupt request signals, the A64 device only uses of those interrupt request signals. The request channels are maskable so that individual channels can be selectively disabled. All interrupt requests can be programmed in the CIM to be of either type: Fast interrupt request (FIQ) Normal interrupt request (IRQ) The precedences of request channels decrease with ascending channel order in the CIM (0, highest, and 31, lowest, priority). For these channel priorities and the associated modules, see Table Table Interrupt Priority MODULES INTERRUPT SOURCES INTERRUPT LEVEL/CHANNEL SPI1 SPI1 end-transfer/overrun RTI COMP2 interrupt RTI COMP1 interrupt RTI TAP interrupt SPI2 SPI2 end-transfer/overrun GIO Interrupt A Reserved HET Interrupt A Reserved SCI1/SCI2 SCI1/SCI2 error interrupt SCI1 SCI1 receive interrupt C2SIa C2SIa interrupt Reserved Reserved SCC Interrupt A Reserved MibADC End event conversion SCI2 SCI2 receive interrupt Reserved Reserved SCI1 SCI1 transmit interrupt System SW interrupt (SSI) Reserved HET Interrupt B Reserved SCC Interrupt B SCI2 SCI2 transmit interrupt MibADC End Group conversion Reserved GIO Interrupt B MibADC End Group conversion Reserved

www.ti.com ADVANCE INFORMATION MibADC TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a 10-bit digital value. The A64 MibADC module can function in two modes: compatibility mode, where its programmer's model is compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion group (event, group1 [G1], and group2 [G2]). In buffered mode, the MibADC buffers can be serviced by interrupts. MibADC event trigger enhancements The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC. Both group1 and the event group can be configured for event-triggered operation, providing up to two event-triggered groups. The trigger source and polarity can be selected individually for both group1 and the event group from the three options identified in Table Table MibADC Event Hookup Configuration SOURCE SELECT BITS FOR OR EVENT EVENT SIGNAL PIN NAME (G1SRC[1:0] or EVSRC[1:0]) EVENT1 ADEVT EVENT2 HET18 EVENT3 HET19 EVENT4 Reserved For group these event-triggered selections are configured via the group1 source select bits (G1SRC[1:0]) in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are configured via the event group source select bits (EVSRC[1:0]) in the AD event source register (ADEVTSRC.[1:0]). For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

www.ti.com ADVANCE INFORMATION documentation support TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types of documentation available include: data sheets with design specifications; complete user's guides; and errata sheets. Useful reference documentation includes: Bulletin TMS470 Microcontroller Family Product Bulletin (literature number SPNB086) Data Sheets TMS470R1A128 16/32Bit RISC Microcontroller (literature number SPNS098) TMS470R1A64 16/32Bit RISC Microcontroller (literature number SPNS099) TMS470R1A256 16/32Bit RISC Microcontroller (literature number SPNS100) User's Guides TMS470R1x System Module Reference Guide (literature number SPNU189) TMS470R1x GeneralPurpose Input/Output (GIO) Reference Guide (literature number SPNU192) TMS470R1x Serial Peripheral Interface (SPI) Reference Guide SPNU195 TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196) TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197) TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199) TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202) TMS470R1x MultiBuffered AnalogtoDigital (MibADC) Reference Guide (literature number SPNU206) TMS470R1x ZeroPin PhaseLocked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212) TMS470R1x F05 Flash Reference Guide (literature number SPNU213) TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214) TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218) TMS470 Peripherals Overview Reference Guide (literature number SPNU248) Errata Sheet: TMS470R1A64 TMS470 Microcontrollers Silicon Errata (literature number SPNZ134)

www.ti.com ADVANCE INFORMATION device numbering conventions PREFIX 470 FAMILY DEVICE TYPE A PN = 80-Pin Plastic Low−Profile Quad Flatpack (LQFP) TMS 470 = TMS470 RISC − Embedded Microcontroller Family A PACKAGE TYPE ARCHITECTURE R1 = ARM7TDM1 CPU TMS = Fully Qualified Device 64 = 64K-Bytes Flash Memory REVISION CHANGE Blank = Original Blank = No options OPTIONS FLASH MEMORY With 64K−Bytes Flash memory: 1.8V Core, 3.3V I/O Flash Program Memory Temperature Range: −40° to +85° Celsius ZPLL Clock 4K−Byte Static RAM 1K−Byte HET RAM (64 Instructions) Analog Watchdog (AWD) Real−Time Interrupt (RTI) 10−bit, 8−input MibADC Two SPI Modules Two SCI Modules C2SIa CAN [SCC] HET, 13 Channels ECP PN TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Figure illustrates the numbering and symbol nomenclature for the TMS470R1x family. Figure TMS470R1x Family Nomenclature

www.ti.com ADVANCE INFORMATION device identification code register TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The device identification code register identifies the silicon version, the technology family (TF), a ROM or Flash device, and an assigned device-specific part number (see Figure The A64 device identification code register value is 0x083F. Reserved VERSION TF R/F PART NUMBER R-K R-K R-K R-K R-1 R-1 R-1 LEGEND: R Read only; value constant after RESET value after RESET Figure TMS470 Device ID Bit Allocation Register Table TMS470 Device ID Bit Allocation Register effect. 15-12 VERSION Silicon version (revision) These bits identify the silicon version of the device. TF Technology Family This bit distinguishes the technology family core power supply: 3.3 V for F10/C10 devices 1.8 V for F05/C05 devices R/F ROM/Flash This bit distinguishes between ROM and Flash devices: Flash device ROM device PART NUMBER Device-specific part number These bits identify the assigned device-specific part number. The assigned device-specific part number for the A64 device is 0000111. Mandatory High Bits 2,1, and are tied high by default.

www.ti.com ADVANCE INFORMATION DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (1) DEVICE RECOMMENDED OPERATING CONDITIONS (1) TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Supply voltage ranges: V CC (2) -0.5 V to 2.5 V Supply voltage ranges: V CCIO V CCAD V CCP (Flash pump) (2) -0.5 V to 4.1 V Input voltage range: All input pins -0.5 V to 4.1 V Input clamp current: I IK I or V I V CCIO mA All pins except ADIN[0:11], PORRST TRST TEST and TCK I IK I or V I V CCAD mA ADIN[0:11] Operating free-air temperature ranges, T A -40 C to C Operating junction temperature range, T J -40 C to 150 C Storage temperature range, T stg -65 C to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to their associated grounds. MIN NOM MAX UNIT V CC Digital logic and Flash supply voltage (Core) 1.71 2.05 V V CCIO Digital logic supply voltage (I/O) 3.3 3.6 V V CCAD ADC supply voltage 3.3 3.6 V V CCP Flash pump supply voltage 3.3 3.6 V V SS Digital logic supply ground V V SSAD ADC supply ground -0.1 0.1 V T A Operating free-air temperature -40 C T J Operating junction temperature -40 150 C (1) All voltages are with respect to V SS except V CCAD which is with respect to V SSAD

www.ti.com ADVANCE INFORMATION ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERA- TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 TURE RANGE (1) TY PARAMETER TEST CONDITIONS MIN MAX UNIT P V hys Input hysteresis 0.15 V V IL Low-level input voltage All inputs (2) 0.8 V V IH High-level input voltage All inputs V CCIO V V th Input threshold voltage AWD only 1.35 1.8 V Drain to source on resist- RDS ON AWD only (3) VOL 0.35V IOL 8mA Ω ance I OL I OL MAX 0.2 V CCIO V OL Low-level output voltage (4) V I OL µ A 0.2 I OH I OH MIN 0.8 V CCIO V OH High-level output voltage (4) V I OH µ A V CCIO V I V SSIO -0. or V I V CCIO I IC Input clamp current (I/O pins) (5) mA I IL Pulldown V I V SS I IH Pulldown V I V CCIO I I Input current (I/O pins) I IL Pullup V I V SS -40 µ A I IH Pullup V I V CCIO All other pins No pullup or pulldown CLKOUT, AWD, V OL V OL MAX TDO RST SPI1CLK, SPI1SOMI, SPI1SIMO, I OL Low-level output current V OL V OL MAX mA SPI2CLK, SPI2SOMI, SPI2SIMO All other output V OL V OL MAX pins (6) CLKOUT, TDO V OH V OH MIN SPI1CLK, SPI1SOMI, SPI1SIMO, V OH V OH MIN SPI2CLK, I OH High-level output current mA SPI2SOMI, SPI2SIMO All other output pins except V OH V OH MIN RST (6) C I Input capacitance pF C O Output capacitance pF SYSCLK MHz, ICLK pipeline mA MHz, V CC 2.05 V V CC Digital supply current (operating mode) SYSCLK MHz, ICLK non-pipeline mA I CC MHz, V CC 2.05 V V CC Digital supply current (standby mode) (7) OSCIN MHz, V CC 2.05 V 3.0 mA V CC Digital supply current (halt mode) (7) All frequencies, V CC 2.05 V 1.0 mA (1) Source currents (out of the device) are negative while sink currents (into the device) are positive. (2) This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section. (3) These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide (literature number SPNU189). (4) V OL and V OH are linear with respect to the amount of load current OL OH applied. (5) Parameter does not apply to input-only or output-only pins. (6) The mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value will always be low. (7) For Flash banks/pumps in sleep mode.

www.ti.com ADVANCE INFORMATION TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERA- TURE RANGE (continued) TY PARAMETER TEST CONDITIONS MIN MAX UNIT P V CCIO Digital supply current (operating mode) No DC load, V CCIO 3.6 V (8) mA I CCIO V CCIO Digital supply current (standby mode) No DC load, V CCIO 3.6 V (8) 300 µ A V CCIO Digital supply current (halt mode) No DC load, V CCIO 3.6 V (8) 300 µ A V CCAD supply current (operating mode) All frequencies, V CCAD 3.6 V mA I CCAD V CCAD supply current (standby mode) All frequencies, V CCAD 3.6 V µ A V CCAD supply current (halt mode) All frequencies, V CCAD 3.6 V µ A V CCP 3.6 V read operation mA V CCP 3.6 V program and mA erase I CCP V CCP pump supply current V CCP 3.6 V standby mode µ A operation (7) V CCP 3.6 V halt mode oper- µ A ation (7) (8) I/O pins configured as inputs or outputs with no load. All pulldown inputs 0.2 All pullup inputs V CCIO -0.2

www.ti.com ADVANCE INFORMATION Parameter Measurement Information Tester Pin Electronics VLOAD IOL CL IOH Output Under Test 50 Ω Where: IOL = IOL MAX for the respective pin(A) IOH = IOH MIN for the respective pin(A) VLOAD = 1.5 V CL = 150-pF typical load-circuit capacitance(B) TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 For these values, see the electrical characteristics over recommended operating free-air temperature range table. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted. Figure Test Load Circuit

www.ti.com ADVANCE INFORMATION timing parameter symbology TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: CM Compaction, CMPCT RD Read CO CLKOUT RST Reset, RST ER Erase RX SCInRX ICLK Interface clock S Slave mode M Master mode SCC SCInCLK OSC, OSCI OSCIN SIMO SPInSIMO OSCO OSCOUT SOMI SPInSOMI P Program, PROG SPC SPInCLK R Ready SYS System clock Read margin RDMRGN0 TX SCInTX Read margin RDMRGN1 Lowercase subscripts and their meanings are: a access time r rise time c cycle time (period) su setup time d delay time t transition time f fall time v valid time h hold time w pulse duration (width) The following additional letters are used with these meanings: H High X Unknown, changing, or don t care level L Low Z High impedance V Valid

www.ti.com ADVANCE INFORMATION external reference resonator/crystal oscillator clock option External Clock Signal (toggling 0± 1.8 V) OSCOUTOSCIN C2(A)C1(A) Crystal OSCOUTOSCIN (a) (b) TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The oscillator is enabled by connecting the appropriate fundamental MHz resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure The oscillator is a single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the res- onator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over tempera- ture/voltage extremes. An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure The values of and should be provided by the resonator/crystal vendor. Figure Crystal/Clock Connection

www.ti.com ADVANCE INFORMATION ZPLL and clock specifications TIMING REQUIREMENTS FOR ZPLL CIRCUITS ENABLED OR DISABLED SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS FOR TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 MIN MAX UNIT f (OSC) Input clock frequency MHz t c(OSC) Cycle time, OSCIN ns t w(OSCIL) Pulse duration, OSCIN low ns t w(OSCIH) Pulse duration, OSCIN high ns f (OSCRST) OSC FAIL frequency (1) kHz (1) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal to For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number SPNU189). CLOCKS (1) (2) PARAMETER TEST CONDITIONS (3) MIN MAX UNIT f (SYS) System clock frequency (4) Pipeline mode enabled MHz Pipeline mode disabled f (CONFIG) System clock frequency Flash config mode MHz f (ICLK) Interface clock frequency Pipeline mode enabled MHz Pipeline mode disabled f (ECLK) External clock output frequency for ECP Module Pipeline mode enabled MHz Pipeline mode disabled t c(SYS) Cycle time, system clock Pipeline mode enabled 20.8 ns Pipeline mode disabled 41.6 t c(CONFIG) Cycle time, system clock Flash config mode 41.6 ns t c(ICLK) Cycle time, interface clock Pipeline mode enabled ns Pipeline mode disabled 41.6 t c(ECLK) Cycle time, ECP module external clock output Pipeline mode enabled ns Pipeline mode disabled 41.6 (1) f (SYS) M f (OSC) where M or 8}, R {1,2,3,4,5,6,7,8} when PLLDIS R is the system-clock divider determined by the CLKDIVPRE [2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register (GLBCTRL.3). f (SYS) f (OSC) where R {1,2,3,4,5,6,7,8} when PLLDIS f (ICLK) f (SYS) where X X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module. (2) f (ECLK) f (ICLK) where N to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module. (3) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0). (4) Flash Vread must be set to to achieve maximum System Clock Frequency.

www.ti.com ADVANCE INFORMATION SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS FOR EX- CLKOUT ECLK TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 TERNAL CLOCKS (1) (2) (3) (See Figure and Figure NO. PARAMETER TEST CONDITION MIN MAX UNIT SYSCLK or MCLK\` (4) 0.5t c(SYS) t f t w(COL) Pulse duration, CLKOUT low ICLK, X is even or (5) 0.5t c(ICLK) t f ns ICLK, X is odd and not (5) 0.5t c(ICLK) 0.5t c(SYS) t f SYSCLK or MCLK (4) 0.5t c(SYS) t r t w(COH) Pulse duration, CLKOUT high ICLK, X is even or (5) 0.5tc(ICLK) tr ns ICLK, X is odd and not (5) 0.5t c(ICLK) 0.5t c(SYS) t r N is even and X is even or odd 0.5t c(ECLK) t f t w(EOL) Pulse duration, ECLK low N is odd and X is even 0.5t c(ECLK) t f ns N is odd and X is odd and not 0.5t c(ECLK) 0.5t c(SYS) t f N is even and X is even or odd 0.5t c(ECLK) t r t w(EOH) Pulse duration, ECLK high N is odd and X is even 0.5t c(ECLK) t r ns N is odd and X is odd and not 0.5t c(ECLK) 0.5t c(SYS) t r (1) X X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module. (2) N to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module. (3) CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active. (4) Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] binary) or MCLK (CLKCNTL.[6:5] binary). (5) Clock source bits selected as ICLK (CLKCNTL.[6:5] binary). Figure CLKOUT Timing Diagram Figure ECLK Timing Diagram

www.ti.com ADVANCE INFORMATION RST and PORRST timings TIMING REQUIREMENTS FOR PORRST VCCP/VCCIO VCC VCC VCCP/VCCIO VCCPORH VCCIOPORL VIL(PORRST) VCCIOPORH VCCIOPORH VCCIOPORL VCCPORL VCC PORRST VCCIO VCCPORH VCCPORL VILVIL VIL VILVIL(PORRST) TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (see Figure NO. MIN MAX UNIT V CCPORL V CC low supply level when PORRST must be active during power up 0.6 V V CC high supply level when PORRST must remain active during power up V CCPORH 1.5 V and become active during power down V CCIOPORL V CCIO low supply level when PORRST must be active during power up 1.1 V V CCIO high supply level when PORRST must remain active during power V CCIOPORH 2.75 V up and become active during power down V IL Low-level input voltage after V CCIO V CCIOPORH 0.2 V CCIO V V IL(PORRST) Low-level input voltage of PORRST before V CCIO V CCIOPORL 0.5 V t su(PORRST)r Setup time, PORRST active before V CCIO V CCIOPORL during power up ms t su(VCCIO)r Setup time, V CCIO V CCIOPORL before V CC V CCPORL ms t h(PORRST)r Hold time, PORRST active after V CC V CCPORH ms t su(PORRST)f Setup time, PORRST active before V CC V CCPORH during power down ms t h(PORRST)rio Hold time, PORRST active after V CC V CCIOPORH ms t h(PORRST)d Hold time, PORRST active after V CC V CCPORL ms t su(PORRST)fio Setup time, PORRST active before V CC V CCIOPORH during power down ms t su(VCCIO)f Setup time, V CC V CCPORE before V CCIO V CCIOPORL ms Figure PORRST Timing Diagram

www.ti.com ADVANCE INFORMATION SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS FOR RST (1) JTAG SCAN INTERFACE TIMING 1 1 TMS TDI TDO TCK TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 PARAMETER MIN MAX UNIT Valid time, RST active after PORRST inactive 4112t c(OSC) t v(RST) ns Valid time, RST active (all others) c(SYS) (1) Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (JTAG clock specification 10-MHz and 50-pF load on TDO output) NO. MIN MAX UNIT t c(JTAG) Cycle time, JTAG low and high period ns t su(TDI/TMS TCKr) Setup time, TDI, TMS before TCK rise (TCKr) ns t h(TCKr -TDI/TMS) Hold time, TDI, TMS after TCKr ns t h(TCKf -TDO) Hold time, TDO after TCKf ns t d(TCKf -TDO) Delay time, TDO valid after TCK fall (TCKf) ns Figure JTAG Scan Timing

www.ti.com ADVANCE INFORMATION OUTPUT TIMINGS SWITCHING CHARACTERISTICS FOR OUTPUT TIMINGS VERSUS LOAD CAPACITANCE L tftr VCC80% 80% 20% 20% 0 Output TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (See Figure PARAMETER MIN MAX UNIT C L pF 0.5 2.50 C L pF 1.5 t r Rise time, CLKOUT, AWD, TDO ns C L 100 pF C L 150 pF 4.5 12.5 C L pF 0.5 2.5 C L pF 1.5 t f Fall time, CLKOUT, AWD, TDO ns C L 100 pF C L 150 pF 4.5 12.5 C L pF 2.5 C L pF Rise time, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK, t r ns SPI2SOMI, SPI2SIMO C L 100 pF C L 150 pF C L pF 2.5 C L pF Fall time, RST, SPI1CLK, SPI1SOMI, SPI1SIMO, t f ns SPI2CLK, SPI2SOMI, SPI2SIMO C L 100 pF C L 150 pF C L pF 2.5 C L pF 6.0 t r Rise time, all other output pins ns C L 100 pF C L 150 pF C L pF C L pF 8.5 t f Fall time, all other output pins ns C L 100 pF C L 150 pF Figure 10. CMOS-Level Outputs

www.ti.com ADVANCE INFORMATION INPUT TIMINGS TIMING REQUIREMENTS FOR INPUT TIMINGS (1) Input tpw VCC80% 80% 20% 20% 0 FLASH TIMINGS TIMING REQUIREMENTS FOR PROGRAM FLASH (1) TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (See Figure MIN MAX UNIT t pw Input minimum pulse width t c(ICLK) ns (1) t c(ICLK) interface clock cycle time f (ICLK) Figure 11. CMOS-Level Inputs MIN TYP MAX UNIT t prog(16-bit) Half word (16-bit) programming time 200 µ s t prog(Total) 64K-byte programming time (2) s t erase(sector) Sector erase time s t wec Write/erase cycles at T A 125 C 100 cycles (1) For more detailed information on the Flash core sectors, see the Flash program and erase section of this data sheet. (2) The 64K-byte programming times include overhead of state machine.

www.ti.com ADVANCE INFORMATION SPIn MASTER MODE TIMING PARAMETERS SPIn MASTER MODE EXTERNAL TIMING PARAMETERS SPInSOMI SPInSIMO SPInCLK (clock polarity = 1) SPInCLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (CLOCK PHASE SPInCLK output, SPInSIMO output, and SPInSOMI input) (1) (2) (3) (see Figure NO. MIN MAX UNIT t c(SPC)M Cycle time, SPInCLK (4) 100 256t c(ICLK) ns t w(SPCH)M Pulse duration, SPInCLK high (clock polarity 0.5t c(SPC)M t r 0.5t c(SPC)M (5) ns t w(SPCL)M Pulse duration, SPInCLK low (clock polarity 0.5t c(SPC)M t f 0.5t c(SPC)M t w(SPCL)M Pulse duration, SPInCLK low (clock polarity 0.5t c(SPC)M t f 0.5t c(SPC)M (5) ns t w(SPCH)M Pulse duration, SPInCLK high (clock polarity 0.5t c(SPC)M t r 0.5t c(SPC)M t d(SPCH-SIMO)M Delay time, SPInCLK high to SPInSIMO valid (clock polarity (5) ns t d(SPCL-SIMO)M Delay time, SPInCLK low to SPInSIMO valid (clock polarity Valid time, SPInSIMO data valid after SPInCLK low t v(SPCL-SIMO)M t c(SPC)M t f (clock polarity (5) ns Valid time, SPInSIMO data valid after SPInCLK high t v(SPCH-SIMO)M t c(SPC)M t r (clock polarity Setup time, SPInSOMI before SPInCLK low t su(SOMI-SPCL)M (clock polarity (5) ns Setup time, SPInSOMI before SPInCLK high t su(SOMI-SPCH)M (clock polarity Valid time, SPInSOMI data valid after SPInCLK low t v(SPCL-SOMI)M (clock polarity (5) ns Valid time, SPInSOMI data valid after SPInCLK high t v(SPCH-SOMI)M (clock polarity (1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared. (2) t c(ICLK interface clock cycle time 1/f (ICLK) (3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (4) When the SPI is in master mode, the following must be true: For PS values from to 255: t c(SPC)M (PS +1)t c(ICLK) 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits. For PS values of t c(SPC)M c(ICLK) 100 ns. (5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). Figure 12. SPIn Master Mode External Timing (CLOCK PHASE

www.ti.com ADVANCE INFORMATION SPIn MASTER MODE EXTERNAL TIMING PARAMETERS Data Valid SPInSOMI SPInSIMO SPInCLK (clock polarity = 1) SPInCLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (CLOCK PHASE SPInCLK output, SPInSIMO output, and SPInSOMI input) (1) (2) (3) (see Figure NO. MIN MAX UNIT t c(SPC)M Cycle time, SPInCLK (4) 100 256t c(ICLK) ns t w(SPCH)M Pulse duration, SPInCLK high (clock polarity 0.5t c(SPC)M t r 0.5t c(SPC)M (5) ns t w(SPCL)M Pulse duration, SPInCLK low (clock polarity 0.5t c(SPC)M t f 0.5t c(SPC)M t w(SPCL)M Pulse duration, SPInCLK low (clock polarity 0.5t c(SPC)M t f 0.5t c(SPC)M (5) ns t w(SPCH)M Pulse duration, SPInCLK high (clock polarity 0.5t c(SPC)M t r 0.5t c(SPC)M Valid time, SPInCLK high after SPInSIMO data valid 0.5t c(SPC)M t v(SIMO-SPCH)M (clock polarity (5) ns Valid time, SPInCLK low after SPInSIMO data valid 0.5t c(SPC)M t v(SIMO-SPCL)M (clock polarity Valid time, SPInSIMO data valid after SPInCLK high t v(SPCH-SIMO)M t c(SPC)M t f (clock polarity (5) ns Valid time, SPInSIMO data valid after SPInCLK low t v(SPCL-SIMO)M t c(SPC)M t r (clock polarity Setup time, SPInSOMI before SPInCLK high t su(SOMI-SPCH)M (clock polarity (5) ns Setup time, SPInSOMI before SPInCLK low t su(SOMI-SPCL)M (clock polarity Valid time, SPInSOMI data valid after SPInCLK high t v(SPCH-SOMI)M (clock polarity (5) ns Valid time, SPInSOMI data valid after SPInCLK low t v(SPCL-SOMI)M (clock polarity (1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set. (2) t c(ICLK) interface clock cycle time f (ICLK) (3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (4) When the SPI is in master mode, the following must be true: For PS values from to 255: t c(SPC)M (PS +1)t c(ICLK) 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits. For PS values of t c(SPC)M c(ICLK) 100 ns. (5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). Figure 13. SPIn Master Mode External Timing (CLOCK PHASE

www.ti.com ADVANCE INFORMATION SPIn SLAVE MODE TIMING PARAMETERS SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (CLOCK PHASE SPInCLK input, SPInSIMO input, and SPInSOMI output) (1) (2) (3) (4) (see Figure NO. MIN MAX UNIT t c(SPC)S Cycle time, SPInCLK (5) 100 256t c(ICLK) ns 0.5t c(SPC)S 0.5t c(SPC)S t w(SPCH)S Pulse duration, SPInCLK high (clock polarity 0.25t c(ICLK) 0.25t c(ICLK) (6) ns 0.5t c(SPC)S 0.5t c(SPC)S t w(SPCL)S Pulse duration, SPInCLK low (clock polarity 0.25t c(ICLK) 0.25t c(ICLK) 0.5t c(SPC)S 0.5t c(SPC)S t w(SPCL)S Pulse duration, SPInCLK low (clock polarity 0.25t c(ICLK) 0.25t c(ICLK) (6) ns 0.5t c(SPC)S 0.5t c(SPC)S t w(SPCH)S Pulse duration, SPInCLK high (clock polarity 0.25t c(ICLK) 0.25t c(ICLK) t d(SPCH- Delay time, SPInCLK high to SPInSOMI valid t r SOMI)S (clock polarity (6) ns t d(SPCL- Delay time, SPInCLK low to SPInSOMI valid t f SOMI)S (clock polarity t v(SPCH- Valid time, SPInSOMI data valid after SPInCLK high t c(SPC)S t r SOMI)S (clock polarity (6) ns t v(SPCL- Valid time, SPInSOMI data valid after SPInCLK low t c(SPC)S t f SOMI)S (clock polarity t su(SIMO- Setup time, SPInSIMO before SPInCLK low SPCL)S (clock polarity (6) ns t su(SIMO- Setup time, SPInSIMO before SPInCLK high SPCH)S (clock polarity t v(SPCL- Valid time, SPInSIMO data valid after SPInCLK low SIMO)S (clock polarity (6) ns t v(SPCH- Valid time, SPInSIMO data valid after SPInCLK high SIMO)S (clock polarity (1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared. (2) If the SPI is in slave mode, the following must be true: t c(SPC)S (PS t c(ICLK) where PS prescale value set in SPInCTL1.[12:5]. (3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (4) t c(ICLK) interface clock cycle time (ICLK) (5) When the SPIn is in slave mode, the following must be true: For PS values from to 255: t c(SPC)S (PS +1)t c(ICLK) 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits. For PS values of t c(SPC)S c(ICLK) 100 ns. (6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

www.ti.com ADVANCE INFORMATION SPInSIMO SPInSOMI SPInCLK (clock polarity = 1) SPInCLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE

www.ti.com ADVANCE INFORMATION SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (CLOCK PHASE SPInCLK input, SPInSIMO input, and SPInSOMI output) (1) (2) (3) (4) (see Figure UNI NO. MIN MAX T t c(SPC)S Cycle time, SPInCLK (5) 100 256t c(ICLK) ns 0.5t c(SPC)S 0.5t c(SPC)S t w(SPCH)S Pulse duration, SPInCLK high (clock polarity 0.25t c(ICLK) 0.25t c(ICLK) (6) ns 0.5t c(SPC)S 0.5t c(SPC)S t w(SPCL)S Pulse duration, SPInCLK low (clock polarity 0.25t c(ICLK) 0.25t c(ICLK) 0.5t c(SPC)S 0.5t c(SPC)S t w(SPCL)S Pulse duration, SPInCLK low (clock polarity 0.25t c(ICLK) 0.25t c(ICLK) (6) ns 0.5t c(SPC)S 0.5t c(SPC)S t w(SPCH)S Pulse duration, SPInCLK high (clock polarity 0.25t c(ICLK) 0.25t c(ICLK) t v(SOMI- Valid time, SPInCLK high after SPInSOMI data valid 0.5t c(SPC)S t r SPCH)S (clock polarity (6) ns t v(SOMI- Valid time, SPInCLK low after SPInSOMI data valid 0.5t c(SPC)S t f SPCL)S (clock polarity t v(SPCH- Valid time, SPInSOMI data valid after SPInCLK high 0.5t c(SPC)S t r SOMI)S (clock polarity (6) ns t v(SPCL- Valid time, SPInSOMI data valid after SPInCLK low 0.5t c(SPC)S t f SOMI)S (clock polarity t su(SIMO- Setup time, SPInSIMO before SPInCLK high SPCH)S (clock polarity (6) ns t su(SIMO- Setup time, SPInSIMO before SPInCLK low SPCL)S (clock polarity t v(SPCH- Valid time, SPInSIMO data valid after SPInCLK high SIMO)S (clock polarity (6) ns t v(SPCL- Valid time, SPInSIMO data valid after SPInCLK low SIMO)S (clock polarity (1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set. (2) If the SPI is in slave mode, the following must be true: t c(SPC)S (PS t c(ICLK) where PS prescale value set in SPInCTL1.[12:5]. (3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (4) t c(ICLK) interface clock cycle time (ICLK) (5) When the SPIn is in slave mode, the following must be true: For PS values from to 255: t c(SPC)S (PS +1)t c(ICLK) 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits. For PS values of t c(SPC)S c(ICLK) 100 ns. (6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

www.ti.com ADVANCE INFORMATION Data Valid SPInSIMO SPInSOMI SPInCLK (clock polarity = 1) SPInCLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE

www.ti.com ADVANCE INFORMATION SCIn isosynchronous mode timings internal clock TIMING REQUIREMENTS FOR INTERNAL CLOCK SCIn ISOSYNCHRONOUS MODE (1) (2) (3) Data Valid Data Valid SCICLK SCITX SCIRX TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (see Figure (BAUD (BAUD IS EVEN OR BAUD IS ODD AND BAUD NO. UNIT MIN MAX MIN MAX t c(SCC) Cycle time, SCInCLK c(ICLK) t c(ICLK) c(ICLK) -1) t c(ICLK) ns Pulse duration, t w(SCCL) 0.5t c(SCC) t f 0.5t c(SCC) 0.5t c(SCC) 0.5t c(ICLK) t f 0.5t c(SCC) 0.5t c(ICLK) ns SCInCLK low Pulse duration, t w(SCCH) 0.5t c(SCC) t r 0.5t c(SCC) 0.5t c(SCC) 0.5t c(ICLK) t r 0.5t c(SCC) 0.5t c(ICLK) ns SCInCLK high t d(SCCH- Delay time, SCInCLK ns TXV) high to SCInTX valid Valid time, SCInTX t v(TX) data after SCInCLK t c(SCC) t c(SCC) ns low Setup time, SCInRX t su(RX-SCCL) t c(ICLK) t f t c(ICLK) t f ns before SCInCLK low Valid time, SCInRX t v(SCCL-RX) data after SCInCLK t c(ICLK) t f t c(ICLK) t f ns low (1) BAUD 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers. (2) t c(ICLK) interface clock cycle time f (ICLK) (3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK falling edge. Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock

www.ti.com ADVANCE INFORMATION SCIn isosynchronous mode timings external clock TIMING REQUIREMENTS FOR EXTERNAL CLOCK SCIn ISOSYNCHRONOUS MODE (1) (2) Data Valid Data Valid SCICLK SCITX SCIRX TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 (see Figure NO. MIN MAX UNIT t c(SCC) Cycle time, SCInCLK (3) c(ICLK) ns t w(SCCH) Pulse duration, SCInCLK high 0.5t c(SCC) 0.25t c(ICLK) 0.5t c(SCC) 0.25t c(ICLK) ns t w(SCCL) Pulse duration, SCInCLK low 0.5t c(SCC) 0.25t c(ICLK) 0.5t c(SCC) 0.25t c(ICLK) ns t d(SCCH-TXV) Delay time, SCInCLK high to SCInTX valid c(ICLK) t r ns t v(TX) Valid time, SCInTX data after SCInCLK low c(SCC) ns t su(RX-SCCL) Setup time, SCInRX before SCInCLK low ns t v(SCCL-RX) Valid time, SCInRX data after SCInCLK low c(ICLK) ns (1) t c(ICLK) interface clock cycle time f (ICLK) (2) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (3) When driving an external SCInCLK, the following must be true: t c(SCC) c(ICLK) Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK falling edge. Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock

www.ti.com ADVANCE INFORMATION high-end timer (HET) timings Minimum PWM output pulse width: Minimum input pulses we can capture: standard CAN controller (SCC) mode timings dynamic characteristics for the CANSTX and CANSRX pins TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale factor (hr), which is user defined, giving prescale factors of to 64, with a linear increment of codes. Therefore, the minimum PWM output pulse width HRP(min) hr(min)/SYSCLK 1/SYSCLK For example, for a SYSCLK of MHz, the minimum PWM output pulse width 33.33ns The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which is user defined, with a power of increment of codes. That is, the value of lr can be 16, or 32. Therefore, the minimum input pulse width LRP(min) hr(min) lr(min)/SYSCLK 1/SYSCLK For example, with a SYSCLK of MHz, the minimum input pulse width 33.33 ns NOTE: Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is, the captured value gives the number of HRP clocks inside the pulse.) Abbreviations: hr HET high resolution divide rate 3,...63, lr HET low resolution divide rate 16, High resolution clock period HRP hr/SYSCLK Loop resolution clock period LRP hr*lr/SYSCLK PARAMETER MIN MAX UNIT t d(CANSTX) Delay time, transmit shift register to CANSTX pin (1) ns t d(CANSRX) Delay time, CANSRX pin to receive shift register ns (1) These values do not include rise/fall times of the output buffer.

www.ti.com ADVANCE INFORMATION MULTI-BUFFERED A-TO-D CONVERTER (MibADC) TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry. This power bus enhances the A-to-D performance by preventing digital switching noise on the logic circuitry that could be present on V SS and V CC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to AD REFLO unless otherwise noted. Resolution bits (1024 values) Monotonic Assured Output conversion code 00h to 3FFh [00 for V AI AD REFLO 3FF for V AI AD REFHI MibADC recommended operating conditions (1) MIN MAX UNIT AD REFHI A-to-D high-voltage reference source V SSAD V CCAD V AD REFLO A-to-D low-voltage reference source V SSAD V CCAD V V AI Analog input voltage V SSAD 0.3 V CCAD 0.3 V Analog input clamp current (2) I AIC mA AI V SSAD 0.3 or V AI V CCAD 0.3) (1) For V CCAD and V SSAD recommended operating conditions, see the "device recommended operating conditions" table. (2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels. operating characteristics over full ranges of recommended operating conditions (1) (2) PARAMETER DESCRIPTION/CONDITIONS MIN TYP MAX UNIT R i Analog input resistance See Figure 250 500 Ω Conversion pF C i Analog input capacitance See Figure Sampling pF I AIL Analog input leakage current See Figure µ A I ADREFHI AD REFHI input current AD REFHI 3.6 AD REFLO V SSAD mA Conversion range over which specified CR AD REFHI AD REFLO 3.6 V accuracy is maintained Difference between the actual step width and the ideal E DNL Differential nonlinearity error LSB value after offset correction. See Figure Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, exclud- E INL Integral nonlinearity error LSB ing the quantization error after offset correction. See Figure Maximum value of the difference between an analog E TOT Total error/Absolute accuracy LSB value and the ideal midstep value. See Figure (1) V CCAD AD REFHI (2) LSB (AD REFHI AD REFLO for the MibADC

www.ti.com ADVANCE INFORMATION Parasitic CapacitanceVsrc Ri MibADC Input PinRs Sample CapacitorCi Rleak Sample Switch External TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 Figure 18. MibADC Input Equivalent Circuit multi-buffer ADC timing requirements MIN MAX UNIT t c(ADCLK) Cycle time, MibADC clock 0.05 µ s t d(SH) Delay time, sample and hold time µ s t d(C) Delay time, conversion time 0.55 µ s t d(SHC) (1) Delay time, total sample/hold and conversion time 1.55 µ s (1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

www.ti.com ADVANCE INFORMATION Analog Input Value (LSB) Digital Output Code Differential Linearity Error (1/2 LSB)

1 LSB

Error (± 1/2 LSB)1 LSB 0 1 2 3 4 5 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 ... 110 0 1 2 3 4 5 6 7 At Transition (± 1/2 LSB) End-Point Lin. Error At Transition Ideal Transition Actual Transition 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 111 0 ... 110 Digital Output Code 0 ... 001 0 ... 000 Analog Input Value (LSB) TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The differential nonlinearity error shown in Figure (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of LSB. LSB (AD REFHI AD REFLO )/2 Figure 19. Differential Nonlinearity (DNL) The integral nonlinearity error shown in Figure (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. LSB (AD REFHI AD REFLO )/2 Figure 20. Integral Nonlinearity (INL) Error

www.ti.com ADVANCE INFORMATION 0 1 2 3 4 5 6 7 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 ... 111 0 ... 110 Analog Input Value (LSB) Digital Output Code Total Error At Step Total Error At Step 0 ... 101 (± 1 1/4 LSB) Thermal Characteristics TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 NOVEMBER 2004 The absolute accuracy or total error of an MibADC as shown in Figure is the maximum value of the difference between an analog value and the ideal midstep value. LSB (AD REFHI AD REFLO )/2 Figure 21. Absolute Accuracy (Total) Error PARAMETER C/W R Θ JA R Θ JC

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TMX470R1A64PN PREVIEW LQFP PN 80 1 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2005 Addendum-Page 1

MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 4040135 /B 11/96 0,17 0,27 0,13 NOM 0,25 0,45 0,75 0,05 MIN Seating Plane Gage Plane 4160 SQ SQ 13,80 14,20 12,20 9,50 TYP 11,80 1,45 1,35 1,60 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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