TMSDM6467CCUT7TAN

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Digital Media System-on-Chip

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 TMS320DM6467 DigitalMedia System-on-Chip Check forSamples: TMS320DM6467

1 DigitalMedia System-on-Chip (DMSoC)

1.1 Features

High-PerformanceDigitalMedia SoC • C64x+ L1/L2Memory Architecture – 594-,729-MHz C64x+ ™ Clock Rate – 32K-Byte L1P Program RAM/Cache (Direct Mapped)– 297-,364.5-MHz ARM926EJ-S ™ Clock Rate – 32K-Byte L1D Data RAM/Cache (2-Way Set-– Eight32-BitC64x+ Instructions/Cycle Associative)– 4752,5832 C64x+ MIPS – 128K-Byte L2 UnifiedMapped RAM/Cache– FullySoftware-CompatibleWith (FlexibleRAM/Cache Allocation)C64x/ARM9 ™
ARM926EJ-S Core– Supports SmartReflex™ [-594only] – Support for32-Bitand 16-Bit(Thumb ®• Class 0 Mode) InstructionSets• 1.05-Vand 1.2-VAdaptiveCore Voltage – DSP InstructionExtensionsand SingleCycle– Extended Temp Available[-594only] MAC– IndustrialTemp Available[-729only] – ARM ® Jazelle® Technology• Advanced Very-Long-Instruction-Word(VLIW) – EmbeddedICE-RT ™ Logic forReal-TimeTMS320C64x+ ™ DSP Core Debug– EightHighlyIndependentFunctionalUnits • ARM9 Memory Architecture• SixALUs (32-/40-Bit),Each Supports – 16K-Byte InstructionCacheSingle32-Bit,Dual 16-Bit,or Quad 8-Bit – 8K-Byte Data CacheArithmeticper Clock Cycle – 32K-Byte RAM• Two MultipliersSupport Four 16 x 16-Bit – 8K-Byte ROMMultiplies(32-BitResults)per Clock Cycle or Eight8 x 8-BitMultiplies(16-Bit • Embedded Trace Buffer™ (ETB11™ )With 4KB Results)per Clock Cycle Memory forARM9 Debug – Load-StoreArchitectureWith Non-Aligned • Endianness:LittleEndian forARM and DSP Support • Dual Programmable High-DefinitionVideo – 64 32-BitGeneral-PurposeRegisters Image Co-Processor (HDVICP) Engines – InstructionPacking Reduces Code Size – Supports a Range ofEncode, Decode, and Transcode Operations– AllInstructionsConditional
H.264,MPEG2, VC1, MPEG4 SP/ASP– AdditionalC64x+ ™ Enhancements
99-/108-MHzVideo PortInterface(VPIF)• ProtectedMode Operation – Two 8-BitSD (BT.656),Single16-BitHD• ExceptionsSupport forErrorDetection (BT.1120),or SingleRaw (8-/10-/12-Bit)Videoand Program Redirection Capture Channels• Hardware Support forModulo Loop – Two 8-BitSD (BT.656)or Single16-BitHDOperation (BT.1120)Video DisplayChannels• C64x+ InstructionSet Features
Video Data Conversion Engine (VDCE)– Byte-Addressable(8-/16-/32-/64-BitData) – Horizontaland VerticalDownscaling– 8-BitOverflowProtection – Chroma Conversion (4:2:2↔4:2:0)– Bit-FieldExtract,Set,Clear
Two TransportStream Interface(TSIF)Modules– Normalization,Saturation,Bit-Counting (One Parallel/Serialand One SerialOnly)– Compact 16-BitInstructions – TSIF forMPEG TransportStream– AdditionalInstructionstoSupport Complex – Simultaneous Synchronous orMultiplies Asynchronous Input/OutputStreams Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2007–2012,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com – AbsoluteTime Stamp Detection • Three ConfigurableUART/IrDA/CIR Modules (One With Modem ControlSignals)– PID FilterWith 7 PID FilterTables – Supports up to1.8432Mbps UART– Corresponding Clock ReferenceGenerator (CRGEN) Modules forSystem Time-Clock – SIR and MIR (0.576MBAUD) Recovery – CIR With Programmable Data Encoding

ExternalMemory Interfaces(EMIFs) • One SerialPeripheralInterface(SPI)With Two – 297-/310.5-MHz32-BitDDR2 SDRAM Memory Chip-Selects ControllerWith 512M-Byte Address Space • Master/SlaveInter-IntegratedCircuit(I2C Bus ™ ) (1.8-VI/O) • Two MultichannelAudio SerialPorts(McASPs) – DigitalMedia– Conforms toPCI Specification2.3 – Networked Media Encode/Decode• Two 64-BitGeneral-PurposeTimers (Each – Video ImagingConfigurableas Two 32-BitTimers) – Video Infrastructure• One 64-BitWatchdog Timer – Video Conferencing

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1.2 Description

The TMS320DM6467 (alsoreferencedas DM6467) leveragesTI’s DaVinci™ technologyto meet the networked media encode and decode digitalmedia processingneeds of next-generationembedded devices. The DM6467 enablesOEMs and ODMs to quicklybringto market devicesfeaturingrobustoperating systems support,richuser interfaces,high processingperformance,and long batterylifethroughthe maximum flexibilityofa fullyintegratedmixed processorsolution. The dual-corearchitectureof the DM6467 providesbenefitsof both DSP and Reduced InstructionSet Computer (RISC) technologies,incorporatinga high-performanceTMS320C64x+ DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bitRISC processorcore thatperforms32-bitor 16-bitinstructionsand processes32-bit,16-bit,or 8-bitdata.The core uses pipeliningso thatallpartsof the processorand memory systemcan operatecontinuously. The ARM coreincorporates:

A coprocessor15 (CP15)and protectionmodule
Data and programMemory Management Units(MMUs) withtablelook-asidebuffers.
Separate16K-byteinstructionand 8K-bytedata caches.Both are four-wayassociativewithvirtual indexvirtualtag(VIVT). The TMS320C64x+ ™ DSPs are the highest-performancefixed-pointDSP generation in the TMS320C6000 ™ DSP platform.Itis based on an enhanced versionof the second-generationhigh- performance,advanced very-long-instruction-word(VLIW) architecturedevelopedby Texas Instruments (TI),making theseDSP coresan excellentchoicefordigitalmedia applications.The C64x isa code- compatiblemember of the C6000 ™ DSP platform.The TMS320C64x+ DSP isan enhancement of the C64x+ DSP withadded functionalityand an expanded instructionset. Any referencetotheC64x DSP orC64x CPU alsoapplies,unlessotherwisenoted,totheC64x+ DSP and C64x+ CPU, respectively. With performanceofup to5832 millioninstructionsper second (MIPS) ata clockrateof729 MHz, the C64x+ coreofferssolutionstohigh-performanceDSP programmingchallenges.The DSP corepossesses theoperationalflexibilityofhigh-speedcontrollersand thenumericalcapabilityofarrayprocessors.The C64x+ DSP core processorhas 64 general-purposeregistersof 32-bitword lengthand eighthighly independentfunctionalunits— two multipliersfora 32-bitresultand sixarithmeticlogicunits(ALUs).The eightfunctionalunitsincludeinstructionstoacceleratetheperformanceinvideoand imagingapplications. The DSP corecan producefour16-bitmultiply-accumulates(MACs) per cyclefora totalof2376 million MACs persecond (MMACS), oreight8-bitMACs percyclefora totalof4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and InstructionSet Reference Guide (literaturenumber SPRU732). The DM6467 also has application-specifichardware logic,on-chipmemory, and additionalon-chip peripheralssimilartotheotherC6000 DSP platformdevices.The DM6467 coreuses a two-levelcache- based architecture.The Level1 program cache (L1P)isa 256K-bitdirectmapped cache and theLevel1 datacache (L1D)isa 640K-bit2-way set-associativecache.The Level2 memory/cache (L2)consistsof an 512K-bitmemory space thatis shared between program and data space. L2 memory can be configuredas mapped memory, cache,orcombinationsofthetwo. The peripheralsetincludes:a configurablevideoport;a 10/100/1000Mb/s EthernetMAC (EMAC) witha Management Data Input/Output(MDIO) module;a 4-bittransfer/4-bitreceiveVLYNQ interface;an inter- integratedcircuit(I2C)Bus interface;a multichannelaudio serialport(McASP0) with4 serializers;a secondarymultichannelaudio serialport(McASP1) witha singletransmitserializer;2 64-bitgeneral- purposetimerseach configurableas 2 independent32-bittimers;1 64-bitwatchdog timer;a configurable 32-bithostportinterface(HPI);up to33-pinsofgeneral-purposeinput/output(GPIO) withprogrammable Copyright© 2007–2012,Texas InstrumentsIncorporated DigitalMedia System-on-Chip(DMSoC) 3 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com interrupt/eventgenerationmodes, multiplexedwithotherperipherals;3 UART/IrDA/CIR interfaceswith modem interfacesignalson UART0; 2 pulse width modulator(PWM) peripherals;an ATA/ATAPI-6 interface;a 33-MHz peripheralcomponent interface(PCI);and 2 externalmemory interfaces:an asynchronousexternalmemory interface(EMIFA) forslowermemories/peripherals,and a higherspeed synchronousmemory interfaceforDDR2. The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween theDM6467 and the network.The DM6467 EMAC supportboth 10Base-T and 100Base-TX, or 10 Mbits/second(Mbps) and 100 Mbps ineitherhalf-or full-duplexmode; and 1000Base-TX (1 Gbps) infull-duplexmode with hardwareflowcontroland qualityofservice(QOS) support. The Management Data Input/Output(MDIO) module continuouslypollsall32 MDIO addressesinorderto enumerate allPHY devicesinthe system.Once a PHY candidatehas been selectedby the ARM, the MDIO module transparentlymonitorsitslinkstateby readingthePHY statusregister.Linkchange events are storedintheMDIO module and can optionallyinterrupttheARM, allowingtheARM topollthelink statusofthedevicewithoutcontinuouslyperformingcostlyMDIO accesses. The PCI,HPI,I2C,SPI,USB2.0, and VLYNQ portsallowtheDM6467 toeasilycontrolperipheraldevices and/orcommunicatewithhostprocessors. The DM6467 also includesa High-DefinitionVideo/ImagingCo-processor(HDVICP) and Video Data ConversionEngine (VDCE) to offloadmany videoand imagingprocessingtasksfrom the DSP core, making more DSP MIPS availableforcommon videoand imagingalgorithms.For more informationon the HDVICP enhanced codecs, such as H.264 and MPEG4, please contactyour nearest TI sales representative. The richperipheralsetprovidesthe abilityto controlexternalperipheraldevicesand communicate with externalprocessors.For detailson each oftheperipherals,see therelatedsectionslaterinthisdocument and theassociatedperipheralreferenceguides. The DM6467 has a completeset of developmenttoolsforboth the ARM and DSP. These includeC compilers,a DSP assembly optimizerto simplifyprogramming and scheduling,and a Windows ™ debuggerinterfaceforvisibilityintosourcecode execution.

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Switched Central Resource (SCR) JTAG Interface System Control PLLs/Clock Generator Power/Sleep Controller Pin Multiplexing ARM Subsystem ARM926EJ-S CPU 16KB I-Cache 32KB RAM 8KB D-Cache 8KB ROM DSP Subsystem C64x+ DSP CPU TM 32KB L1 Pgm 128KB L2 RAM 32KB L1 Data High-Definition Video-Imaging Coprocessor (HDVICP0) Input Clock(s) High-Definition Video-Imaging Coprocessor (HDVICP1) Peripherals EDMA I2C SPI UART Serial Interfaces DDR2 Mem Ctlr (16b/32b) Async EMIF/ NAND/ SmartMedia ATA Program/Data Storage Watchdog Timer PWM System General- Purpose Timer USB 2.0 PHY VLYNQ EMAC With MDIO Connectivity HPI McASP Video Port I/F PCI (33 MHz)TSIF CRGEN VDCE TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012

1.3 FunctionalBlock Diagram

Figure1-1shows thefunctionalblockdiagramofthedevice. Figure1-1.TMS320DM6467 FunctionalBlock Diagram Copyright© 2007–2012,Texas InstrumentsIncorporated DigitalMedia System-on-Chip(DMSoC) 5 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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2 RevisionHistory

Thisdatamanual revisionhistoryhighlightsthetechnicalchanges made totheSPRS403G device-specific datamanual tomake itan SPRS403H revision. Scope: Applicableupdates to the DM646x DMSoC device family,specificallyrelatingto the TMS320DM6467 device(allSiliconRevisions3.0,1.1,and 1.0)whichisnow intheproductiondata(PD) stageofdevelopmenthave been incorporated.

The ZUT 529-pinPBGA deviceorderableshave now been classifiedas end oflife(EOL) productand replacedwithCUT 529-pinPBGA (Pb-Freediebump and solderball)package orderables.

3 Device Overview

3.1 Device Characteristics

Table3-1 providesan overviewoftheTMS320DM6467 SoC. The tableshows significantfeaturesofthe device,includingthecapacityofon-chipRAM, peripherals,internalperipheralbus frequencyrelativetothe C64x+ DSP, and thepackage typewithpincount. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 7 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-1.CharacteristicsoftheDM6467 Processor HARDWARE FEATURES DM6467 DDR2 Memory Controller DDR2 (16/32-bitbus width)297-MHz (-594) 310.5-MHz (-729) Asynchronous(8/16-bitbus width)RAM, FlashAsynchronousEMIF (EMIFA) (NOR, NAND) 64 independentchannelsEDMA 8 QDMA channels 2 64-BitGeneralPurpose(eachconfigurableas 2 Timers separate32-bittimers) 1 64-BitWatchdog 3 (withSIR,MIR, CIR supportand RTS/CTS flow UART control) (UART0 SupportsModem Interface) SPI 1 (supports2 slavedevices) I2C 1 (Master/Slave) 2 (onetransmit/receivewith4 serializers, MultichannelAudioSerialPort(McASP) one DIT transmitonlywith1 serializerforS/PDIF output) 10/100/1000EthernetMAC withManagement Data 1 (withMII/GMIIInterface)Peripherals Input/Output(MDIO) VLYNQ 1Not allperipheralspinsare availableatthesame time General-PurposeInput/OutputPort(GPIO) Up to33 pins(formore detail,see the PWM 2 outputsDeviceConfigurations section). ATA 1 (ATA/ATAPI-6) PCI 1 (32-bit,33 MHz) HPI 1 (16-/32-bitmultiplexedaddress/data) 1 [horizontaland verticaldownscaling,VDCE chroma conversion(4:2:2↔4:2:0)] ClockRecoveryGenerator(CRGEN) 1 Power SleepController(PSC) 1 (peripheral/moduleclockgating) 2 8-bitBT.656 capturechannelsor ConfigurableVideoPortInterface(VPIF) 1 16-bitY/C capturechannelor 99-MHz (-594) 1 8-/10-/12-bitraw videocapturechanneland 108-MHz (-729) 2 8-bitBT.656 displaychannelsor 1 16-bitY/C displaychannel MPEG transportstreaminterface 1 with8-bitparallelorserialinputand output TransportStream Interface(TSIF) 1 withserial-onlyinputand output Each withcorrespondingclockrecoverygenerator (CRGEN) forexternalVCXO control. High-and Full-SpeedDeviceUSB 2.0 High-,Full-,and Low-Speed Host Size(Bytes) 248KB RAM, 8KB ROM DSP

32KB L1 Program (L1P)/Cache(upto32KB)
32KB L1 Data (L1D)/Cache(upto32KB)
128KB UnifiedMapped RAM/Cache (L2) On-ChipMemory Organization ARM
16KB I-cache
8KB D-cache
32KB RAM
8KB ROM CPU ID + CPU Rev ID ControlStatusRegister(CSR.[31:16]) 0x1000

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-1.CharacteristicsoftheDM6467 Processor (continued) HARDWARE FEATURES DM6467 C64x+ Megamodule RevisionID Register(MM_REVID[15:0]) 0x0000Revision (addresslocation:0x0181 2000) JTAGID Register See Section7.29.1,JTAG ID (JTAGID)RegisterJTAG BSDL_ID (addresslocation:0x01C4 0028) Description(s) DSP 594 MHz (-594) DSP 729 MHz (-729) CPU Frequency MHz ARM926 297 MHz(-594) ARM926 364.5MHz(-729) DSP 1.68ns (-594) DSP 1.37ns (-729) CycleTime ns ARM926 3.37ns (-594) ARM926 2.74ns (-729) Normal 1.2V (-594,-594A,-729,-729D) Voltage Core (V) 1.2V (-594V,-594AV)SmartReflex (seeTable4-39) 1.05V (-594V,-594AV) DEV_CLKIN frequencymultiplier(PLLC1) x1 (Bypass),x14 tox22 (-594) (27-MHz reference) x1 (Bypass),x14 tox27 (-729) PLL Options DEV_CLKIN frequencymultiplier(PLLC2) x1 (Bypass),x14 tox22 (-594) (27-MHz reference) x1 (Bypass),x14 tox23 (-729) AUX_CLKIN frequency 24/48-MHz reference ProcessTechnology μm 0.09μm ProductPreview(PP), ProductStatus(1) Advance Information(AI), PD orProductionData (PD) (1) PRODUCTION DATA informationiscurrentas ofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexas Instrumentsstandardwarranty.Productionprocessingdoes notnecessarilyincludetestingofallparameters. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.2 Device Compatibility

The ARM926EJ-S RISC CPU iscompatiblewithotherARM9 CPUs fromARM Holdingsplc. The C64x+ DSP core iscode-compatiblewiththe C6000 ™ DSP platformand supportsfeaturesof the C64x DSP family.

3.3 ARM Subsystem

The ARM Subsystem isdesignedto givethe ARM926EJ-S (ARM9) master controlof the device.In general,theARM isresponsibleforconfigurationand controlofthedevice;includingtheDSP Subsystem, theVPSS Subsystem,and a majorityoftheperipheralsand externalmemories. The ARM Subsystem includesthefollowingfeatures:

ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit)instructionset
Littleendianoperation
Co-Processor15 (CP15)
MMU
16KB Instructioncache
8KB Data cache
WriteBuffer
32KB InternalTightly-CoupledMemory (TCM) RAM (32-bitwideaccess)
8KB InternalROM (ARM bootloaderfornon-EMIFA bootoptions)
Embedded TraceModule and Embedded TraceBuffer(ETM/ETB)
ARM InterruptController
PLL Controller
Power and SleepController(PSC)
System Module

3.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integratestheARM926EJ-S processor.The ARM926EJ-S processorisa member of ARM9 familyofgeneral-purposemicroprocessors.Thisprocessoristargetedatmulti-taskingapplications where fullmemory management, highperformance,low diesize,and low power are allimportant.The ARM926EJ-S processorsupportsthe32-bitARM and 16 bitTHUMB instructionsets,enablingtheuserto tradeoffbetween high performanceand high code density.Specifically,the ARM926EJ-S processor supportstheARMv5TEJ instructionset,whichincludesfeaturesforefficientexecutionofJava bytecodes, providingJava performancesimilarto JustinTime (JIT)Java interpreter,but withoutassociatedcode overhead. The ARM926EJ-S processorsupportsthe ARM debug architectureand includeslogicto assistinboth hardware and softwaredebug. The ARM926EJ-S processorhas a Harvardarchitectureand providesa completehighperformancesubsystem,including:

ARM926EJ -S integercore
CP15 systemcontrolcoprocessor
Memory Management Unit(MMU)
Separateinstructionand dataCaches
Writebuffer
Separateinstructionand dataTightly-CoupledMemories (TCMs) [internalRAM] interfaces
Separateinstructionand dataAHB bus interfaces
Embedded TraceModule and Embedded TraceBuffer(ETM/ETB)

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 For more completedetailson theARM9, refertotheARM926EJ-S TechnicalReferenceManual,available athttp://www.arm.com

3.3.2 CP15

The ARM926EJ-S system controlcoprocessor(CP15) isused to configureand controlinstructionand data caches,Tightly-CoupledMemories (TCMs), Memory Management Unit(MMU), and otherARM subsystem functions.The CP15 registersare programmed usingthe MRC and MCR ARM instructions, when theARM ina privilegedmode such as supervisororsystemmode.

3.3.3 MMU

The ARM926EJ-S MMU providesvirtualmemory featuresrequiredby operatingsystemssuch as Linux® , Windows ® CE, Ultron® ,ThreadX® ,etc.A singlesetoftwo levelpage tablesstoredinmain memory is used tocontroltheaddresstranslation,permissionchecksand memory regionattributesforbothdataand instructionaccesses.The MMU uses a singleunifiedTranslationLookasideBuffer(TLB) to cache the informationheldinthepage tables.The MMU featuresare:

StandardARM architecturev4 and v5 MMU mapping sizes,domains and accessprotectionscheme.
Mapping sizesare: – 1MB (sections) – 64KB (largepages) – 4KB (smallpages) – 1KB (tinypages)
Access permissionsforlargepages and smallpages can be specifiedseparatelyforeach quarterof thepage (subpagepermissions)
Hardware page tablewalks
InvalidateentireTLB, usingCP15 register8
InvalidateTLB entry,selectedby MVA, usingCP15 register8
Lockdown ofTLB entries,usingCP15 register10

3.3.4 Caches and WriteBuffer

The sizeoftheInstructionCache is16KB, Data cache is8KB. Additionally,theCaches have thefollowing features:

Virtualindex,virtualtag,and addressedusingtheModifiedVirtualAddress(MVA)
Four-waysetassociative,witha cache linelengthofeightwords perline(32-bytesperline)and with two dirtybitsintheDcache
Dcache supportswrite-throughand write-back(orcopy back)cache operation,selectedby memory regionusingtheC and B bitsintheMMU translationtables.
Critical-wordfirstcache refilling
Cache lockdownregistersenablecontroloverwhich cache ways are used forallocationon a linefill, providinga mechanism forbothlockdown,and controllingcache corruption
Dcache storesthePhysicalAddress TAG (PA TAG) correspondingtoeach Dcache entryintheTAG RAM foruse duringthe cache linewrite-backs,inadditionto the VirtualAddress TAG storedinthe TAG RAM. Thismeans thattheMMU isnotinvolvedinDcache write-backoperations,removingthe possibilityofTLB missesrelatedtothewrite-backaddress.
Cache maintenanceoperationsprovideefficientinvalidationof,theentireDcache orIcache,regionsof theDcache orIcache,and regionsofvirtualmemory. The writebufferisused forallwritestoa noncachablebufferableregion,write-throughregionand write misses toa write-backregion.A separatebufferisincorporatedintheDcache forholdingwrite-backfor cache lineevictionsorcleaningofdirtycache lines.The main writebufferhas 16-worddatabufferand a four-addressbuffer.The Dcache write-backhas eightdataword entriesand a singleaddressentry. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.3.5 TightlyCoupled Memory (TCM)

ARM internalRAM isprovidedforstoringreal-timeand performance-criticalcode/dataand theInterrupt Vectortable.ARM internalROM enablesnon-EMIFA bootoptions,such as NAND and UART. The RAM and ROM memories interfacedtotheARM926EJ-S viathetightlycoupledmemory interfacethatprovides forseparateinstructionand databus connections.SincetheARM TCM does notallowinstructionson the D-TCM bus or data on the I-TCM bus,an arbiterisincludedso thatboth data and instructionscan be storedin the internalRAM/ROM. The arbiteralsoallowsaccesses to the RAM/ROM from extra-ARM sources(e.g.,EDMA orothermasters).The ARM926EJ-S has built-inDMA supportfordirectaccessesto theARM internalmemory froma non-ARM master.Because ofthetime-criticalnatureoftheTCM linkto theARM internalmemory, allaccessesfromnon-ARM devicesaretreatedas DMA transfers. Instructionand Data accesses are differentiatedviaaccessingdifferentmemory map regions,withthe instructionregionfrom0x0000 through0x7FFF and datafrom0x10000 through0x17FFF. The instruction regionat0x0000 and dataregionat0x10000 map tothesame physical32-KB TCM RAM. Placingthe instructionregionat0x0000 isnecessarytoallowtheARM InterruptVectortabletobe placedat0x0000, as requiredby the ARM architecture.The internal32-KB RAM issplitintotwo physicalbanks of 16KB each,which allowssimultaneousinstructionand dataaccessestobe accomplishedifthecode and data areinseparatebanks.

3.3.6 Advanced High-PerformanceBus (AHB)

The ARM Subsystem uses theAHB portoftheARM926EJ-S toconnecttheARM totheConfigbus and theexternalmemories.Arbitersareemployed toarbitrateaccesstotheseparateD-AHB and I-AHB by the ConfigBus and theexternalmemories bus.

3.3.7 Embedded Trace Macrocell(ETM) and Embedded Trace Buffer(ETB)

To supportreal-timetrace,theARM926EJ-S processorprovidesan interfacetoenableconnectionofan Embedded Trace Macrocell(ETM). The ARM926ES-J Subsystem in the DM6467 also includesthe Embedded TraceBuffer(ETB).The ETM consistsoftwo parts:

TracePortprovidesreal-timetracecapabilityfortheARM9.
Triggeringfacilitiesprovidetriggerresources,which includeaddressand data comparators,counter, and sequencers. The DM6467 traceportisnotpinnedoutand isinsteadonlyconnectedtotheEmbedded Trace Buffer. The ETB has a 4KB buffermemory. ETB enableddebug toolsarerequiredtoread/interpretthecaptured tracedata.

3.3.8 ARM Memory Mapping

The ARM memory map isshown inSection3.5,Memory Map Summary ofthisdocument.The ARM has accesstomemories shown inthefollowingsections.

3.3.8.1 ARM InternalMemories

The ARM has accesstothefollowingARM internalmemories:

32KB ARM InternalRAM on TCM interface,logicallyseparatedintotwo 16KB pages to allow simultaneousaccesson any givencycleifthereareseparateaccessesforcode (I-TCMbus)and data (D-TCM) tothedifferentmemory regions.
8KB ARM InternalROM

3.3.8.2 ExternalMemories

The ARM has accesstothefollowingexternalmemories:

DDR2 SynchronousDRAM
AsynchronousEMIF /NOR Flash/NAND Flash
ATA

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3.3.8.3 DSP Memories

The ARM has accesstothefollowingDSP memories:

L2 RAM
L1P RAM
L1D RAM

3.3.8.4 ARM-DSP Integration

DM6467 ARM and DSP integrationfeaturesareas follows:

DSP visibilityfromARM ’s memory map, see Section3.5,Memory Map Summary ,fordetails
BootModes forDSP -see DeviceConfigurationssection,Section4.4.1,DSP Boot,fordetails
ARM controlofDSP boot/reset- see DeviceConfigurationssection,Section4.4.2.4,ARM Boot,for details
ARM controlofDSP isolationand powerdown /powerup - see Section4,DeviceConfigurations,for details
ARM & DSP Interrupts-see Section7.8.1,ARM CPU Interrupts,and Section7.8.2,DSP Interrupts,for details

3.3.9 Peripherals

The ARM9 has accesstoalloftheperipheralson theDM6467 device.

3.3.10 PLL Controller(PLLC)

The ARM Subsystem includesthe PLL Controller.The PLL Controllercontainsa set of registersfor configuringDM6467 ’s two internalPLLs (PLL1 and PLL2).The PLL Controllerprovidesthe following configurationand control:

PLL Bypass Mode
SetPLL multiplierparameters
SetPLL dividerparameters
PLL power down
Oscillatorpower down The PLLs arebrieflydescribedinthisdocument intheClockingsection.For more detailedinformationon the PLLs and PLL Controllerregisterdescriptions,see the TMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ).

3.3.11 Power and Sleep Controller(PSC)

The ARM Subsystem includesthe Power and Sleep Controller(PSC). Through registersettings accessibleby theARM9, thePSC providestwo levelsofpower savings:peripheral/moduleclockgating and power domain shut-off.Briefdetailson thePSC aregiveninSection7.3,Power Supplies.For more detailedinformationand completeregisterdescriptionsforthe PSC, see the TMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ).

3.3.12 ARM InterruptController(AINTC)

The ARM InterruptController(AINTC)acceptsdeviceinterruptsand maps them toeithertheARM ’s IRQ (interruptrequest)or FIQ (fastinterruptrequest).The ARM InterruptControllerisbrieflydescribedinthis document in the Interruptssection.For detailedinformationon the ARM InterruptController,see the TMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.3.13 System Module

The ARM Subsystem includestheSystem module.The System module consistsofa setofregistersfor configuringand controllinga varietyof system functions.For detailsand registerdescriptionsforthe System module, see Section4, Device Configurationsand see the TMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ).

3.3.14 Power Management

DM6467 has severalmeans of managing power consumption.There isextensiveuse of clockgating, which reduces the power used by globaldevice clocks and individualperipheralclocks.Clock management can be utilizedto reduce clockfrequenciesinorderto reduce switchingpower.For more detailson power management techniques,see Section4, Device Configurations, Section7, Peripheral and ElectricalSpecifications, and see the TMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). DM6467 givestheprogrammer fullflexibilitytouse any and allofthepreviouslymentionedcapabilitiesto customizean optimalpower management strategy.Severaltypicalpower management scenariosare describedinthefollowingsections.

3.4 DSP Subsystem

The DSP Subsystem includesthefollowingfeatures:

C64x+ DSP CPU
32KB L1 Program (L1P)/Cache(upto32KB)
32KB L1 Data (L1D)/Cache(upto32KB)
128KB UnifiedMapped RAM/Cache (L2)
Littleendian

3.4.1 C64x+ DSP CPU Description

The C64x+ CentralProcessingUnit(CPU) consistsof eightfunctionalunits,two registerfiles,and two datapathsas shown inFigure3-1.The two general-purposeregisterfiles(A and B) each contain32 32- bitregistersfora totalof64 registers.The general-purposeregisterscan be used fordataorcan be data addresspointers.The datatypessupportedincludepacked 8-bitdata,packed 16-bitdata,32-bitdata,40- bitdata,and 64-bitdata.Valueslargerthan32 bits,such as 40-bit-longor64-bit-longvaluesarestoredin registerpairs,withthe32 LSBs ofdataplacedinan even registerand theremaining8 or32 MSBs inthe nextupperregister(whichisalwaysan odd-numberedregister). performa generalsetofarithmetic,logical,and branchfunctions.The .D unitsprimarilyloaddata from memory totheregisterfileand storeresultsfromtheregisterfileintomemory. The C64x+ CPU extendstheperformanceoftheC64x corethroughenhancements and new features. Each C64x+ .M unitcan performone ofthefollowingeach clockcycle:one 32 x 32 bitmultiply,one 16 x 32 bitmultiply,two 16 x 16 bitmultiplies,two 16 x 32 bitmultiplies,two 16 x 16 bitmultiplieswith add/subtractcapabilities,four8 x 8 bitmultiplies,four8 x 8 bitmultiplieswithadd operations,and four 16 x 16 multiplieswithadd/subtractcapabilities(includinga complex multiply).There isalsosupportfor Galoisfieldmultiplicationfor8-bitand 32-bitdata.Many communicationsalgorithmssuch as FFTs and modems requirecomplex multiplication.The complex multiply(CMPY) instructiontakesfor16-bitinputs and producesa 32-bitrealand a 32-bitimaginaryoutput.There arealsocomplex multiplieswithrounding capabilitythatproducesone 32-bitpacked outputthatcontain16-bitrealand 16-bitimaginaryvalues.The 32 x 32 bitmultiplyinstructionsprovidethe extended precisionnecessaryforaudio and otherhigh- precisionalgorithmson a varietyofsignedand unsigned32-bitdatatypes.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 The .Lor (ArithmeticLogicUnit)now incorporatestheabilitytodo paralleladd/subtractoperationson a pairofcommon inputs.Versionsofthisinstructionexisttowork on 32-bitdataor on pairsof16-bitdata performingdual16-bitadd and subtractsinparallel.Therearealsosaturatedformsoftheseinstructions. The C64x+ core enhances the .S unitinseveralways. In the C64x core,dual16-bitMIN2 and MAX2 comparisonswere onlyavailableon the.Lunits.On theC64x+ coretheyarealsoavailableon the.S unit which increasesthe performanceof algorithmsthatdo searchingand sorting.Finally,to increasedata packingand unpackingthroughput,the.S unitallowssustainedhighperformanceforthequad 8-bit/16-bit and dual16-bitinstructions.Unpack instructionsprepare8-bitdata forparallel16-bitoperations.Pack instructionsreturnparallelresultstooutputprecisionincludingsaturationsupport. Othernew featuresinclude:

SPLOOP -A smallinstructionbufferintheCPU thataidsincreationofsoftwarepipeliningloopswhere multipleiterationsof a loop are executed in parallel.The SPLOOP bufferreduces the code size associatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOP bufferarefullyinterruptible.
Compact Instructions- The nativeinstructionsizefortheC6000 devicesis32 bits.Many common instructionssuch as MPY, AND, OR, ADD, and SUB can be expressed as 16 bitsifthe C64x+ compilercan restrictthe code to use certainregistersin the registerfile.This compression is performedby thecode generationtools.
InstructionSet Enhancement - As noted above, there are new instructionssuch as 32-bit multiplications,complex multiplications,packing,sorting,bitmanipulation,and 32-bitGaloisfield multiplication.
Exceptions Handling - Intendedtoaidtheprogrammer inisolatingbugs.The C64x+ CPU isableto detectand respondtoexceptions,bothfrominternallydetectedsources(suchas illegalop-codes)and fromsystemevents(suchas a watchdogtimeexpiration).
Privilege- Definesuserand supervisormodes ofoperation,allowingtheoperatingsystem togivea basiclevelofprotectiontosensitiveresources.Localmemory isdividedintomultiplepages,each with read,write,and executepermissions.
Time-Stamp Counter -PrimarilytargetedforReal-TimeOperatingSystem (RTOS) robustness,a free- runningtime-stampcounterisimplementedintheCPU whichisnot sensitivetosystemstalls. For more detailson theC64x+ CPU and itsenhancements overtheC64x architecture,see thefollowing documents:
TMS320C64x/C64x+ DSP CPU and InstructionSetReferenceGuide (literaturenumber SPRU732)
TMS320C64x TechnicalOverview(literaturenumber SPRU395) Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 15 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

Á Á Á Á Á Á Á .D1 .M1 Á Á Á Á Á Á Á Á Á Á Á Á Á .S1 Á Á Á Á Á Á Á Á Á Á .L1 long src odd dst src2 src1 Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á Á Á Á Á src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd register file A (A1, A3, A5...A31) Á Á Á Odd register file B (B1, B3, B5...B31) Á Á Á .D2 Á Á Á Á src1 dst src2DA2 LD2a LD2b src2 .M2 src1 Á Á Á dst1 Á Á Á .S2 src1 Á Á Á Á even dst long src odd dst ST2a ST2b long src .L2 Á Á Á Á even dst odd dst Á Á Á src1 Data path B Control Register

32 MSB

32 LSB

dst2 (A) (B) (B) (A) (C) (C) Even register file A (A0, A2, A4...A30) Even register file B (B0, B2, B4...B30) (D) (D) (D) (D) A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure3-1.TMS320C64x+ ™ CPU (DSP Core)Data Paths

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3.4.2 DSP Memory Mapping

The DSP memory map isshown in Section3.5, Memory Map Summary . Configurationof the control registersforDDR2, EMIFA, and ARM InternalRAM issupportedby the ARM. The DSP has access to memories shown inthefollowingsections.

3.4.2.1 ARM InternalMemories

The DSP has accesstothe32KB ARM InternalRAM on theARM D-TCM interface(i.e.,dataonly).

3.4.2.2 ExternalMemories

The DSP has accesstothefollowingExternalmemories:

DDR2 SynchronousDRAM
AsynchronousEMIF /NOR Flash
ATA

3.4.2.3 DSP InternalMemories

The DSP has accesstothefollowingDSP memories:

L2 RAM
L1P RAM
L1D RAM

3.4.2.4 C64x+ CPU

The C64x+ core uses a two-levelcache-basedarchitecture.The Level1 Program memory/cache (L1P) consistsof32 KB memory space thatcan be configuredas mapped memory ordirectmapped cache.The Level1 Data memory/cache (L1D)consistsof32 KB thatcan be configuredas mapped memory or2-way setassociatedcache.The Level2 memory/cache (L2)consistsofa 128 KB RAM memory space thatis sharedbetween program and dataspace.L2 memory can be configuredas mapped memory, cache,ora combinationofboth. Table3-2shows a memory map oftheC64x+ CPU cache registersforthedevice. Table3-2.C64x+ Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 0000 L2CFG L2 Cache configurationregister 0x0184 0020 L1PCFG L1P SizeCache configurationregister 0x0184 0024 L1PCC L1P FreezeMode Cache configurationregister 0x0184 0040 L1DCFG L1D SizeCache configurationregister 0x0184 0044 L1DCC L1D FreezeMode Cache configurationregister 0x0184 0048 -0x0184 0FFC - Reserved 0x0184 1000 EDMAWEIGHT L2 EDMA accesscontrolregister 0x0184 1004 -0x0184 1FFC - Reserved 0x0184 2000 L2ALLOC0 L2 allocationregister0 0x0184 2004 L2ALLOC1 L2 allocationregister1 0x0184 2008 L2ALLOC2 L2 allocationregister2 0x0184 200C L2ALLOC3 L2 allocationregister3 0x0184 2010 -0x0184 3FFF - Reserved 0x0184 4000 L2WBAR L2 writebackbase addressregister 0x0184 4004 L2WWC L2 writebackword countregister 0x0184 4010 L2WIBAR L2 writebackinvalidatebase addressregister 0x0184 4014 L2WIWC L2 writebackinvalidateword countregister 0x0184 4018 L2IBAR L2 invalidatebase addressregister Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-2.C64x+ Cache Registers(continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 401C L2IWC L2 invalidateword countregister 0x0184 4020 L1PIBAR L1P invalidatebase addressregister 0x0184 4024 L1PIWC L1P invalidateword countregister 0x0184 4030 L1DWIBAR L1D writebackinvalidatebase addressregister 0x0184 4034 L1DWIWC L1D writebackinvalidateword countregister 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D BlockWriteback 0x0184 4044 L1DWWC L1D BlockWriteback 0x0184 4048 L1DIBAR L1D invalidatebase addressregister 0x0184 404C L1DIWC L1D invalidateword countregister 0x0184 4050 -0x0184 4FFF - Reserved 0x0184 5000 L2WB L2 writebackallregister 0x0184 5004 L2WBINV L2 writebackinvalidateallregister 0x0184 5008 L2INV L2 GlobalInvalidatewithoutwriteback 0x0184 500C -0x0184 5027 - Reserved 0x0184 5028 L1PINV L1P GlobalInvalidate 0x0184 502C -0x0184 5039 - Reserved 0x0184 5040 L1DWB L1D GlobalWriteback 0x0184 5044 L1DWBINV L1D GlobalWritebackwithInvalidate 0x0184 5048 L1DINV L1D GlobalInvalidatewithoutwriteback 0x0184 8000 -0x0184 803C MAR0 -MAR15 Reserved(correspondstobyteaddress0x0000 0000 -0x0FFF FFFF) Memory AttributeRegistersforARM TCM (correspondstobyteaddress0x0184 8040 MAR16 0x1000 0000 -0x10FF FFFF) 0x0184 8044 -0x0184 80FC MAR17 -MAR63 Reserved(correspondstobyteaddress0x1100 0000 -0x3FFF FFFF) 0x0184 8100 MAR64 Reserved(correspondstobyteaddress0x4000 0000 -0x40FF FFFF) 0x0184 8104 MAR65 Reserved(correspondstobyteaddress0x4100 0000 -0x41FF FFFF) Memory AttributeRegistersforEMIFA (correspondstobyteaddress0x42000x0184 8108 -0x0184 8124 MAR66 -MAR73 0000 -0x49FF FFFF) 0x0184 8128 -0x0184 812C MAR74 -MAR75 Reserved(correspondstobyteaddress0x4A00 0000 -0x4BFF FFFF) Memory AttributeRegistersforVLYNQ (correspondstobyteaddress0x0184 8130 -0x0184 813C MAR76 -MAR79 0x4C00 0000 -0x4FFF FFFF) 0x0184 8140 -0x0184 81FC MAR80 -MAR127 Reserved(correspondstobyteaddress0x5000 0000 -0x7FFF FFFF) Memory AttributeRegistersforDDR2 (correspondstobyteaddress0x80000x0184 8200 -0x0184 82FC MAR128 -MAR191 0000 -0xBFFF FFFF) 0x0184 8300 -0x0184 83FC MAR192 -MAR255 Reserved(correspondstobyteaddress0xC000 0000 -0xFFFF FFFF)

3.4.3 Peripherals

The DSP has access/controllabilityofthefollowingperipherals:

HDVICP0/1
EDMA
McASP0/1
2 Timers(Timer0and Timer1)thatcan each be configuredas 1 64-bitor2 32-bittimers

3.4.4 DSP InterruptController

The DSP InterruptControlleraccepts device interruptsand appropriatelymaps them to the DSP ’s availableinterrupts.The DSP InterruptControllerisbrieflydescribedinthisdocument inthe Interrupts section.For more detailedon the DSP InterruptController,see the TMS320C64x+ DSP Megamodule ReferenceGuide (literaturenumber SPRU871 ).

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3.5 Memory Map Summary

Table3-3shows thememory map addressrangesofthedevice.Table3-4depictstheexpanded map of theConfigurationSpace (0x01800000 through0x0FFF FFFF).The devicehas multipleon-chipmemories associatedwithitstwo processorsand varioussubsystems.To help simplifysoftwaredevelopmenta unifiedmemory map isused where possibletomaintaina consistentviewofdeviceresourcesacrossall bus masters. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-3.Memory Map Summary MASTER PERIPHERAL ACCESSIBILITY (1) START END SIZE EDMA/ARM C64x+ Video TSIFADDRESS ADDRESS (Bytes) PERIPHERAL VDCE EMAC HPI PCI USB VLYNQ ATAPort (0/1) 0x0000 0000 0x0000 3FFF 16K ARM RAM0 (Instruction) 0x0000 4000 0x0000 7FFF 16K ARM RAM1 (Instruction) 0x0000 8000 0x0000 FFFF 32K ARM ROM (Instruction) 0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) 0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) 0x0001 8000 0x0001 FFFF 32K ARM ROM (Data) Reserved Reserved 0x0002 0000 0x000F FFFF 896K 0x0010 0000 0x003F FFFF 3M 0x0040 0000 0x004F FFFF 1M 0x0050 0000 0x005F FFFF 1M Reserved 0x0060 0000 0x006F FFFF 1M 0x0070 0000 0x007F FFFF 1M 0x0080 0000 0x0080 FFFF 64K 0x0081 0000 0x0081 7FFF 32K Reserved Hole(MPPA Disable)(2) Reserved 0x0081 8000 0x0083 7FFF 128K L2 RAM/Cache 0x0083 8000 0x008F FFFF 800K Reserved 0x0090 0000 0x0092 FFFF 192K 0x0093 0000 0x009F FFFF 832K 0x00A0 0000 0x00DF FFFF 4M Reserved 0x00E0 0000 0x00E0 7FFF 32K L1P RAM/Cache 0x00E0 8000 0x00EF FFFF 992K Reserved 0x00F0 0000 0x00F0 7FFF 32K L1D RAM/Cache Reserved 0x00F0 8000 0x017F FFFF 9184K Reserved 0x0180 0000 0x01BB FFFF 3840K 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers CFG Space 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher 0x01BC 1900 0x01BC 1BFF 768 Reserved 0x01BC 1C00 0x01BF FFFF 249K 0x01C0 0000 0x0FFF FFFF 228M CFG Bus Peripherals CFG Bus Peripherals CFG Bus Peripherals ✓(3) ✓(3) ✓(3) 0x1000 0000 0x1000 FFFF 64K Reserved 0x1001 0000 0x1001 3FFF 16K ARM RAM0 (Data) ARM RAM0 (Data) ✓ ✓ ✓ ✓ ✓ ✓ ✓ 0x1001 4000 0x1001 7FFF 16K ARM RAM1 (Data) ARM RAM1 (Data) ✓ ✓ ✓ ✓ ✓ ✓ ✓ 0x1001 8000 0x1001 FFFF 32K ARM ROM (Data) ARM ROM (Data) ✓ ✓ ✓ ✓ ✓ ✓ ✓ 0x1002 0000 0x10FF FFFF 16256K 0x1100 0000 0x113F FFFF 4M Reserved 0x1140 0000 0x114F FFFF 1M 0x1150 0000 0x115F FFFF 1M Reserved Reserved 0x1160 0000 0x116F FFFF 1M 0x1170 0000 0x117F FFFF 1M 0x1180 0000 0x1180 FFFF 64K 0x1181 0000 0x1181 7FFF 32K Reserved Hole(MPPA Disable)(2) Reserved 0x1181 8000 0x1183 7FFF 128K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache ✓ ✓ ✓ ✓ ✓ ✓ 0x1183 8000 0x118F FFFF 800K Reserved Reserved Reserved 0x1190 0000 0x11DF FFFF 5M 0x11E0 0000 0x11E0 7FFF 32K L1P RAM/Cache L1P RAM/Cache L1P RAM/Cache ✓ ✓ ✓ ✓ ✓ 0x11E0 8000 0x11EF FFFF 992K Reserved Reserved Reserved (1) These peripheralshave theirown DMA engineormasterportinterfacetotheDMSoC systembus and do not use theEDMA fordata transfers.The ✓ symbolindicatesthattheperipheralhas a validconnectionthroughthedeviceswitchfabrictothememory region identifiedintheEDMA accesscolumn. (2) MPPA shouldbe used todisablethehole.Formore informationon MPPA, see theTMS320C64x+ DSP Megamodule ReferenceGuide (SPRU871 ). (3) The HPI's,PCI's,and VLYNQ 's accesstotheconfigurationbus peripheralsislimited,see Table3-4,ConfigurationMemory Map Summary forthedetails.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-3.Memory Map Summary (continued) MASTER PERIPHERAL ACCESSIBILITY (1) START END SIZE EDMA/ARM C64x+ Video TSIFADDRESS ADDRESS (Bytes) PERIPHERAL VDCE EMAC HPI PCI USB VLYNQ ATAPort (0/1) 0x11F0 0000 0x11F0 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache ✓ ✓ ✓ ✓ ✓ 0x11F0 8000 0x11FF FFFF 992K Reserved Reserved Reserved 0x1200 0000 0x1FFF FFFF 224M 0x2000 0000 0x2000 7FFF 32K DDR2 Control DDR2 Control DDR2 Control ✓Registers Registers Registers 0x2000 8000 0x2000 FFFF 32K EMIFA Control EMIFA Registers EMIFA Registers Registers 0x2001 0000 0x2001 7FFF 32K VLYNQ Control VLYNQ Registers VLYNQ Registers Registers 0x2001 8000 0x200F FFFF 928K Reserved Reserved Reserved 0x2010 0000 0x2FFF FFFF 255M 0x3000 0000 0x3FFF FFFF 256M PCI Data PCI Data 0x4000 0000 0x403F FFFF 4M Reserved Reserved Reserved 0x4040 0000 0x4043 FFFF 256K 0x4044 0000 0x4047 FFFF 256K 0x4048 0000 0x404B FFFF 256K 0x404C 0000 0x404F FFFF 256K 0x4050 0000 0x405F FFFF 1M 0x4060 0000 0x4063 FFFF 256K Reserved Reserved Reserved 0x4064 0000 0x4067 FFFF 256K 0x4068 0000 0x406B FFFF 256K 0x406C 0000 0x406F FFFF 256K 0x4070 0000 0x41FF FFFF 25M 0x4200 0000 0x43FF FFFF 32M EMIFA Data (CS2)(4) EMIFA Data (CS2)(4) EMIFA Data (CS2)(4) ✓ ✓ ✓ ✓ 0x4400 0000 0x45FF FFFF 32M EMIFA Data (CS3)(4) EMIFA Data (CS3)(4) EMIFA Data (CS3)(4) ✓ ✓ ✓ ✓ 0x4600 0000 0x47FF FFFF 32M EMIFA Data (CS4)(4) EMIFA Data (CS4)(4) EMIFA Data (CS4)(4) ✓ ✓ ✓ ✓ 0x4800 0000 0x49FF FFFF 32M EMIFA Data (CS5)(4) EMIFA Data (CS5)(4) EMIFA Data (CS5)(4) ✓ ✓ ✓ ✓ 0x4A00 0000 0x4BFF FFFF 32M Reserved Reserved Reserved 0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) VLYNQ (Remote Data) VLYNQ (Remote Data) ✓ ✓ ✓ ✓ ✓ ✓ ✓ 0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory DDR2 Memory DDR2 Memory ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 0xA000 0000 0xBFFF FFFF 512M Reserved Reserved Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved Reserved Reserved (4) EMIFA CS0 and CS1 arenot functionallysupportedon theDM6467, and therefore,arenot pinnedout. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-4.ConfigurationMemory Map Summary MASTER PERIPHERAL START END SIZE ACCESSIBILITYARM/EDMA C64x+ADDRESS ADDRESS (Bytes) HPI PCI VLYNQ 0x0180 0000 0x0180 FFFF 64K C64x+ InterruptController 0x0181 0000 0x0181 0FFF 4K C64x+ Powerdown Controller 0x0181 1000 0x0181 1FFF 4K C64x+ SecurityID 0x0181 2000 0x0181 2FFF 4K C64x+ RevisionID Reserved 0x0182 0000 0x0182 FFFF 64K C64x+ EMC 0x0183 0000 0x0183 FFFF 64K Reserved 0x0184 0000 0x0184 FFFF 64K C64x+ Memory System 0x0185 0000 0x01BB FFFF 3520K Reserved 0x01BC 0000 0x01BC 00FF 256 0x01BC 0100 0x01BC 01FF 256 ARM ETB Memory 0x01BC 0200 0x01BC 0FFF 3.5K Reserved 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher 0x01BC 1900 0x01BF FFFF 255744 Reserved 0x01C0 0000 0x01C0 FFFF 64K EDMA CC EDMA CC 0x01C1 0000 0x01C1 03FF 1K EDMA TC0 EDMA TC0 0x01C1 0400 0x01C1 07FF 1K EDMA TC1 EDMA TC1 0x01C1 0800 0x01C1 0BFF 1K EDMA TC2 EDMA TC2 0x01C1 0C00 0x01C1 0FFF 1K EDMA TC3 EDMA TC3 0x01C1 1000 0x01C1 1FFF 4K Reserved Reserved 0x01C1 2000 0x01C1 23FF 1K VideoPort 0x01C1 2400 0x01C1 27FF 1K Reserved Reserved 0x01C1 2800 0x01C1 2FFF 2K VDCE 0x01C1 3000 0x01C1 33FF 1K TSIF0 0x01C1 3400 0x01C1 37FF 1K TSIF1 0x01C1 3800 0x01C1 9FFF 26K Reserved Reserved 0x01C1 A000 0x01C1 A7FF 2K PCI ControlRegisters 0x01C1 A800 0x01C1 FFFF 22K Reserved Reserved 0x01C2 0000 0x01C2 03FF 1K UART0 ✓ ✓ ✓ 0x01C2 0400 0x01C2 07FF 1K UART1 ✓ ✓ ✓ 0x01C2 0800 0x01C2 0BFF 1K UART2 ✓ ✓ ✓ 0x01C2 0C00 0x01C2 0FFF 1K Reserved Reserved ✓ ✓ ✓ 0x01C2 1000 0x01C2 13FF 1K I2C ✓ ✓ ✓ 0x01C2 1400 0x01C2 17FF 1K Timer0 Timer0 ✓ ✓ ✓ 0x01C2 1800 0x01C2 1BFF 1K Timer1 Timer1 ✓ ✓ ✓ 0x01C2 1C00 0x01C2 1FFF 1K Timer2(Watchdog) ✓ ✓ ✓ 0x01C2 2000 0x01C2 23FF 1K PWM0 ✓ ✓ ✓ 0x01C2 2400 0x01C2 27FF 1K PWM1 ✓ ✓ ✓ 0x01C2 2800 0x01C2 5FFF 14K Reserved Reserved ✓ ✓ ✓ 0x01C2 6000 0x01C2 63FF 1K CRGEN0 ✓ ✓ ✓ 0x01C2 6400 0x01C2 67FF 1K CRGEN1 ✓ ✓ ✓ 0x01C2 6800 0x01C3 FFFF 102K Reserved Reserved ✓ ✓ ✓ 0x01C4 0000 0x01C4 07FF 2K System Module System Module ✓ ✓ ✓ 0x01C4 0800 0x01C4 0BFF 1K PLL Controller1 ✓ ✓ ✓ 0x01C4 0C00 0x01C4 0FFF 1K PLL Controller2 ✓ ✓ ✓ 0x01C4 1000 0x01C4 1FFF 4K Power and SleepController Power and SleepController ✓ ✓ ✓ 0x01C4 2000 0x01C4 7FFF 24K Reserved Reserved ✓ ✓ ✓ 0x01C4 8000 0x01C4 83FF 1K ARM InterruptController Reserved ✓ ✓ ✓ 0x01C4 8400 0x01C6 3FFF 111K Reserved Reserved ✓ ✓ ✓ 0x01C6 4000 0x01C6 5FFF 8K USB2.0 Registers/RAM ✓ ✓ ✓

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-4.ConfigurationMemory Map Summary (continued) MASTER PERIPHERAL START END SIZE ACCESSIBILITYARM/EDMA C64x+ADDRESS ADDRESS (Bytes) HPI PCI VLYNQ 0x01C6 6000 0x01C6 67FF 2K ATA ✓ ✓ ✓ 0x01C6 6800 0x01C6 6FFF 2K SPI ✓ ✓ ✓ 0x01C6 7000 0x01C6 77FF 2K GPIO ✓ ✓ ✓ 0x01C6 7800 0x01C6 7FFF 2K HPI HPI ✓ ✓ ✓ 0x01C6 8000 0x01C7 FFFF 96K Reserved Reserved ✓ ✓ ✓ 0x01C8 0000 0x01C8 0FFF 4K EMAC ControlRegisters ✓ ✓ ✓ 0x01C8 1000 0x01C8 1FFF 4K EMAC ControlModule Registers ✓ ✓ ✓ Reserved 0x01C8 2000 0x01C8 3FFF 8K EMAC ControlModule RAM ✓ ✓ ✓ 0x01C8 4000 0x01C8 47FF 2K MDIO ControlRegisters ✓ ✓ ✓ 0x01C8 4800 0x01D0 0FFF 498K Reserved Reserved ✓ ✓ ✓ 0x01D0 1000 0x01D0 13FF 1K McASP0 Registers McASP0 Registers ✓ ✓ ✓ 0x01D0 1400 0x01D0 17FF 1K McASP0 Data Port McASP0 Data Port ✓ ✓ ✓ 0x01D0 1800 0x01D0 1BFF 1K McASP1 Registers McASP1 Registers ✓ ✓ ✓ 0x01D0 1C00 0x01D0 1FFF 1K McASP1 Data Port McASP1 Data Port ✓ ✓ ✓ 0x01D0 2000 0x01DF FFFF 1016K Reserved Reserved 0x01E0 0000 0x01FF FFFF 2M Reserved Reserved 0x0200 0000 0x021F FFFF 2M Reserved Reserved 0x0220 0000 0x023F FFFF 2M Reserved Reserved 0x0240 0000 0x0FFF FFFF 220M Reserved Reserved

3.6 Pin Assignments

Extensiveuse ofpinmultiplexingisused toaccommodate thelargestnumber ofperipheralfunctionsin the smallestpossiblepackage. Pin multiplexingis controlledusing a combinationof hardware configurationat deviceresetand softwareprogrammable registersettings.For more informationon pin muxing,see Section4.7,MultiplexedPinConfigurations,ofthisdocument.

3.6.1 Pin Map (Bottom View)

Figure3-2throughFigure3-7show thebottomviewofthepackage pinassignmentsinsixquadrants(A, B,C, D, E,and F). Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

GP[4]/ STC_CLKIN VP_DOUT1/ BTMODE1 VP_DOUT6/ DSPBOOT VP_DOUT5/ PCIEN VP_DOUT14/ TS1_PSTIN VP_DOUT9/ TS1_ENAO VSS AHCLKR0 GP[3]/ AUDIO_CLK0 TOUT1U VP_DOUT0/ BTMODE0 VP_DOUT3/ BTMODE3 VP_DOUT7/ V ADJEN VP_DOUT15/ TS1_DIN ACLKX0 ACLKR0 AMUTEIN0 GP[2]/ AUDIO_CLK1 TOUT1L TINP0U VP_DOUT4/ CS2BW VP_DOUT12/ TS1_WAITO AHCLKX0 AMUTE0 AFSR0 AFSX0 TOUT2 TINP1L TINP0L VP_DOUT2/ BTMODE2 ACLKX1 AHCLKX1 AXR0[3] AXR0[2] GP[0] RESET TOUT0U TOUT0L SPI_CLK AXR1[0] AXR0[0] AXR0[1] GP[1] VSS DVDD33 DVDD33 VL YNQ_ CLOCK VL YNQ_ SCRUN SPI_CS1 SDA SCL DVDD33 CVDD VL YNQ_TXD1 VL YNQ_TXD2 VL YNQ_TXD3 SPI_CS0 SPI_EN 1 2 AC AB AA Y W V U T MTCLK VL YNQ_RXD2 VL YNQ_RXD3 VL YNQ_TXD0 SPI_SOMI MTXD7 GMTCLK VL YNQ_RXD1 VL YNQ_RXD0 SPI_SIMO MTXD3 MTXD4 MTXD5 MTXD6 R P N 3 4 5 6 7 8 1 2 3 4 5 6 7 8 AC AB AA Y W V U T R P N VSS VSS DVDD33 CVDD CVDDDVDD33VSS VSS CVDD CVDD VSSVSSVSSVSS A B C D E F TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure3-2.Pin Map [SectionA]

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VP_CLKIN3/ TS1_CLKO VP_CLKO3/ TS0_CLKO TS1_CLKIN UCTS0/ USD0 VP_CLKIN0 VP_DIN4/ TS0_DOUT4/ TS1_WAITO VP_DIN0/ TS0_DOUT0 VP_DIN8/ TS0_DIN0 VP_DOUT8/ TS1_WAITIN VP_DOUT1 1/ TS1_DOUT UDSR0/ TS0_PSTO/ GP[37] VSS URXD0/ TS1_DIN VP_DIN5/ TS0_DOUT5/ TS1_EN_WAITO VP_DIN1/ TS0_DOUT1 VP_DIN9/ TS0_DIN1 VP_CLKO2 VP_DOUT10/ TS1_PSTO UDCD0/ TS0_WAITIN/ GP[38] DVDD33 URTS0/ UIRTX0/ TS1_EN_WAITO VP_DIN6/ TS0_DOUT6/ TS1_PSTIN VP_DIN2/ TS0_DOUT2 VP_DIN10/ TS0_DIN2 VP_DOUT13/ TS1_EN_WAITO VP_CLKIN2 URIN0/ GP[8]/ TS1_WAITIN UDTR0/ TS0_ENAO/ GP[36] UTXD0/ URCTX0/ TS1_PSTIN VP_DIN7/ TS0_DOUT7/ TS1_DIN VP_DIN3/ TS0_DOUT3 VP_DIN1 1/ TS0_DIN3 DVDD33 CVDD 9 10 AC AB AA Y W V U T R P N 1 1 12 13 14 15 16 9 10 1 1 12 13 14 15 16 AC AB AA Y W V U T R P N DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 CVDDCVDDCVDDCVDDCVDDCVDDCVDD VSS VSSVSS VSS CVDDCVDDCVDDCVDDCVDD CVDDCVDD CVDD VSSCVDDCVDDCVDD VSSVSSCVDDCVDD CVDD CVDDCVDDCVDD VSSVSSCVDDCVDD CVDD CVDDCVDDCVDD VSSVSSVSSVSSVSSVSSVSSVSS TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure3-3.Pin Map [SectionB] Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

VP_DIN12/ TS0_DIN4 VP_DIN15_ VP_VSYNC/ TS0_DIN7 TS0_CLKIN URTS2/ UIRTX2/ TS0_PSTIN/ GP[41] UCTS2/USD2/ CRG0_VCXI/ GP[42]/ TS1_PSTO VSS VP_DIN13_ FIELD/ TS0_DIN5 VP_CLKIN1 UTXD1/ URCTX1/ TS0_DOUT7/ GP[24] VSS DDR_D[23] VP_DIN14_ VP_HSYNC/ TS0_DIN6 URTS1/ UIRTX1/ TS0_WAITO/ GP[25] UTXD2/URCTX2/ CRG1_PO/ GP[40]/ CRG0_PO DVDDR2 DDR_D[28] DDR_D[21] DDR_D[20] UCTS1/USD1/ TS0_EN_WAITO/ GP[26] URXD1/ TS0_DIN7/ GP[23] DDR_D[31] DDR_D[29] DDR_D[22] DDR_DQM[2] PWM0/ CRG0_PO/ TS1_ENAO 17 18 AC AB AA Y W V U T R P N 19 20 21 22 23 17 18 19 20 21 22 23 AC AB AA Y W V U T R P N A B C D E F PWM1/ TS1_DOUT VSS DDR_D[30] DV DDR2 VSS DDR_DQS[2] DDR_D[19]DDR_DQS[2]DDR_DQS[3]DDR_DQM[3]VSSVSS DDR_DQS[3] DDR_D[27]DVDDR2 DDR_D[24] DDR_D[18]DDR_D[16]VSSVSS DVDDR2VSS DVDDR2 DDR_A[10]DDR_D[17]DDR_D[26] DDR_D[25]DVDDR2 DDR_DQGA TE2 DDR_A[1]DDR_A[3]DDR_DQGA TE3 DDR_A[12]DDR_BA[2] DDR_VREFVSSDVDDR2 DDR_A[14]DDR_A[9]DDR_A[5]DDR_A[7]DDR_BA[0]VSSVSS VSSVSS DVDD33 DVDDR2 VSS URXD2/ CRG1_VCXI/ GP[39]/ CRG0_VCXI VSS VSS TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure3-4.Pin Map [SectionC]

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L K J H G F E D C B A 3 4 5 6 7 8 1 2 3 4 5 6 7 8 L K J H G F E D C B A A B C D E F DVDD33 PCI_AD0/ HD0/ EM_D0 PCI_AD2/ HD2/ EM_D2 PCI_AD4/ HD4/ EM_D4 VSS DVDD33 CVDD VSSVSS PCI_AD9/ HD9/ EM_D9 PCI_CBE0 A T A_CS0 GP[33]/ EM_A[18] PCI_AD6/ HD6/ EM_D6 PCI_AD3/ HD3/ EM_D3 PCI_AD1/ HD1/ EM_D1 PCI_AD13/ HD13/ EM_D13 PCI_AD15/ HD15/ EM_D15 PCI_AD1 1/ HD1 1/ EM_D1 1 PCI_P AR/ / HAS EM_DQM0 PCI_IDSEL/ HDDIR/ EM_R/W PCI_AD18/ DD2/ HD18/ EM_A[2] PCI_TRDY/ HHWIL/ EM_A[16]/(ALE) PCI_AD7/ HD7/ EM_D7 PCI_AD5/ HD5/ EM_D5 PCI_AD10/ HD10/ EM_D10 PCI_AD8/ HD8/ EM_D8 PCI_AD12/ HD12/ EM_D12 PCI_AD24/ DD8/ HD24/ EM_A[8] PCI_AD20/ DD4/ HD20/ EM_A[4] PCI_FRAME HINT EM_BA[0] PCI_STOP EM_WE HCNTL0/ PCI_AD26/ DD10/ HD26/ EM_A[10] PCI_CBE2 HDS2 EM_CS2 PCI_CBE1 A T A_CS1 GP[32]/ EM_A[19] PCI_AD14/ HD14/ EM_D14 PCI_PERR HCS EM_DQM1 PCI_AD22/ DD6/ HD22/ EM_A[6] PCI_AD16/ DD0/ HD16/ EM_A[0] PCI_AD21/ DD5/ HD21/ EM_A[5] PCI_AD29/ DD13/ HD29/ EM_A[13] PCI_AD17/ DD1/ HD17/ EM_A[1] PCI_SERR HDS1 EM_OE VSS PCI_DEVSEL/ HCNTL1/ EM_BA[1] PCI_AD25/ DD9/ HD25/ EM_A[9] PCI_AD23/ DD7/ HD23/ EM_A[7] PCI_AD31/ DD15/ HD31/ EM_A[15] VSS PCI_AD27/ DD1 1/ HD27/ EM_A[1 1] PCI_CBE3 W EM_CS3 HR/ / PCI_AD19/ DD3/ HD19/ EM_A[3] PCI_IRDY HRDY EM_A[17]/(CLE) RSV2RSV1 MTXD1 MTXD2M MVSS VSSVSSVSS VSS VSSVSSVSS CVDDDVDD33DVDD33VSSMRXD5 VSS DVDD33 CVDDCVDD CVDDCVDDDVDD33VSS MRXD0 DVDD33 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure3-5.Pin Map [SectionD] Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 27 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

L K J H G F E D C B A 1 1 12 13 14 15 16 9 10 1 1 12 13 14 15 16 L K J H G F E D C B A RSV7 TRST TDIGP[6]/ CVDDADJ0 TMS AUX_CVDDDEV_CVDDDEV_DVSS PCI_RSV3 GP[19]/ EM_WAIT5/ (RDY5/ ) DIOR BSY5 PCI_RSV1/ DA0/ GP[17]/ EM_A[20] PCI_GNT DMACK EM_CS4 GP[12]/ PCI_AD28/ DD12/ HD28/ EM_A[12] PCI_RSV5/ IORDY/ GP[21]/ EM_WAIT3/ (RDY3/ )BSY3 AUX_DVDD18DEV_DVDD18RSV5TDO AUX_DVSSRTCK PCI_RST/ DA2/ GP[13]/ EM_A[22] PCI_AD30/ DD14/ HD30/ EM_A[14] PCI_INT A BSY2 EM_WAIT2/ (RDY2/ ) DEV_VSSPLL1VSSCLKOUT0 TCK PCI_RSV2/ INTRQ/ GP[18]/ EM_RSV0 PCI_REQ EM_CS5 DMARQ/ GP[1 1]/ GP[5] PLL1VDD18EMU1 PLL2VSSVSS DEV_MXOEMU0GP[7]/ CVDDADJ1 PCI_RSV4/ GP[20]/ EM_WAIT4/ (RDY4/ ) DIOW BSY4 PCI_CLK/ GP[10] PCI_RSV0/ DA1/ GP[16]/ EM_A[21] M MVSS VSSVSSVSS VSS VSSVSSVSS CVDDVSS CVDDCVDDVSS DEV_MXI/ DEV_CLKIN VSS VSS VSS VSSVSS VSS VSS CVDD CVDD CVDD CVDDCVDDCVDD CVDDVSSCVDD CVDD CVDD CVDDCVDDCVDD CVDDCVDD VSS VSS VSS CVDD CVDD CVDD CVDDCVDDCVDDCVDD DVDD33DVDD33DVDD33DVDD33DVDD33DVDD33DVDD33 PLL2VDD18 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure3-6.Pin Map [SectionE]

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DDR_A[2] DDR_CLKDDR_ZP DDR_WE DDR_CASVSS DVDDR2 DDR_RAS DVDDR2 DDR_A[1 1] DDR_DQGA TE0 DDR_CS DDR_DQGA TE1 DDR_A[4] DDR_A[8] DDR_D[7] DDR_A[13] DDR_D[15] DDR_A[0] DVDDR2 17 18 L K J H G F E D C B A 19 20 21 22 23 17 18 19 20 21 22 23 L K J H G F E D C B A A B C D E F DVDDR2 DDR_D[4] DDR_D[6] DDR_D[13] DDR_D[14] DDR_D[12]DDR_DQM[1]DDR_D[5]DDR_DQM[0]VSSUSB_VDDA3P3 DDR_DQS[0] DVDDR2VSS DDR_D[1] DDR_D[1 1]USB_VDD1P8 USB_ VDDA1P2LDO USB_R1POR VSS DDR_DQS[1]DDR_DQS[1]DDR_DQS[0] DDR_D[2]USB_VSSREF DDR_D[8]DDR_D[10]DDR_D[0] DDR_D[3] USB_ DRVVBUS/ GP[22] DDR_D[9] VSSDVDDR2 RSV4RSV3USB_DNUSB_DPVSSAUX_MXO VSS AUX_MXI/ AUX_CLKIN RSV6 AUX_VSS VSS DDR_ODT0 VSS VSS DDR_A[6] DDR_CLKDDR_ZN DDR_CKE DDR_BA[1]VSSM MVSS VSS DVDDR2 VSS DVDDR2 VSS VSS VSS VSS VSS TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure3-7.Pin Map [SectionF]

3.7 TerminalFunctions

The terminalfunctionstables(Table 3-5 throughTable 3-32) identifythe externalsignalnames, the associatedpin(ball)numbers alongwiththemechanicalpackage designator,thepintype,whetherthepin has any internalpullupor pulldown resistors,and a functionalpin description.For more detailed informationon deviceconfiguration,peripheralselection,multiplexed/sharedpin,and see the Device Configurationssectionofthisdatamanual. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.1 BOOT

Table3-5.BOOT TerminalFunctions SIGNAL OTHER (2) TYPE (1) DESCRIPTION(3) NAME NO. BOOT ARM BootMode configurationbits.These pinsaremultiplexedbetween ARM bootmode and theVideoPortInterface(VPIF).Atreset,the bootmode inputsBTMODE[3:0] aresampled todeterminetheARM bootconfiguration.See belowthebootmodes setby theseinputs.For more detailson thetypesofbootmodes, see theSection4.4.1,BootModes .Afterreset,thesepinsareVideoportdataoutputs3 through0 (VP_DOUT[3:0]). BTMODE[3:0] ARM Boot Mode

0000 EmulationBoot(PCIEN = 0)

0001 Reserved

HPI Boot(16-Bitwidth)(ifPCIEN = 0) VP_DOUT0/ IPD 0010 orAB5 I/O/ZBTMODE0 DV DD33 PCI Bootwithoutauto-initialization(ifPCIEN = 1) HPI Boot(32-Bitwidth)(ifPCIEN = 0) 0011 or PCI Bootwithauto-initialization(ifPCIEN = 1) EMIFA DirectBoot(ROM/NOR) (PCIEN = 0)[errorifPCIEN =0100 1;defaultstoUART0] VP_DOUT1/ IPD 0101 ReservedAC4 I/O/ZBTMODE1 DV DD33

0110 I2C Boot

0111 NAND FlashBoot(PCIEN = 0)[errorifPCIEN = 1]

1000 UART0 Boot

1001 ReservedVP_DOUT2/ IPDY8 I/O/ZBTMODE2 DV DD33 1010 Reserved

1011 Reserved

VP_DOUT3/ IPDAB6 I/O/Z 1110 SPI BootBTMODE3 DV DD33

1111 Reserved

EMIFA CS2 space databus width.Thispinismultiplexedbetween EMIFA control and theVPIF.Atreset,theinputstateissampled tosettheEMIFA databus width fortheCS2 (boot)chipselectregion.VP_DOUT4/ IPDAA7 I/O/ZCS2BW DV DD33 Foran 8-bit-wideEMIFA databus,CS2BW = 0. Fora 16-bit-wideEMIFA databus,CS2BW = 1. Afterreset,thispinisvideoportdataoutput4 (VP_DOUT4). PCI Enable.Thispinismultiplexedbetween PCI Controland theVPIF.Atreset,the inputstateissampled toenable/disablethePCI interfacepinmultiplexing.Note: When PCI bootmode isnot used,forproperdeviceoperationoutofresetPCIEN must be "0". VP_DOUT5/ IPDAC6 I/O/ZPCIEN DV DD33 0 = PCI pinfunctionisdisabled;EMIFA orHPI pinfunctionenabled 1 = PCI pinfunctionisenabled Afterreset,thispinisvideoportdataoutput5 (VP_DOUT5).- (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-5.BOOT TerminalFunctions(continued) SIGNAL OTHER (2) TYPE (1) DESCRIPTION(3) NAME NO. DSP bootsourcebit.Thispinismultiplexedbetween DSP bootand theVPIF.At reset,theinputstateissampled tosettheDSP bootsourceDSPBOOT. VP_DOUT6/ IPD The DSP isbootedby theARM when DSPBOOT = 0.AC5 I/O/ZDSPBOOT DV DD33 The DSP bootsfromEMIFA when DSPBOOT = 1 (andARM HPI orPCI bootmode isnot selected). Afterreset,thispinisvideoportdataoutput6 (VP_DOUT6). VoltageAdjustEnable(SmartReflex).Thispinismultiplexedbetween SmartReflex OutputControlEnableand theVPIF.Atreset,theinputstateissampled to determinewhethertheSmartReflexControlOutputsareenbabledordisabled. VP_DOUT7 / IPDAB7 I/O/Z 0 = SmartReflexoutputsdisabled[default].GP[6]/CVDDADJ0 andVADJEN DV DD33 GP[7]/CVDDADJ1 pinsfunctionas GPIO. 1 = SmartReflexoutputsenabled.GP[6]/CVDDADJ0 and GP[7]/CVDDADJ1 pins functionas SmartReflexcontroloutputstotheadjustablecorepower supply[1.2V or1.05V]. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 31 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.2 Oscillator/PLL

Table3-6.Oscillator/PLLTerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. OSCILLATOR, PLL DEV_MXI/ CrystalinputDEV_MXI forDEV oscillator(systemoscillator,typically27 MHz). IftheB15 I DEV_DV DD18DEV_CLKIN internaloscillatorisbypassed,thispinisthe1.8-Vexternaloscillatorclockinput. CrystaloutputforDEV oscillator.Iftheinternaloscillatorisbypassed,DEV_MXODEV_MXO A15 O DEV_DV DD18 shouldbe leftas a No Connect. 1.8-Vpower supplyforDEV oscillator.Iftheinternaloscillatorisbypassed,DEV_DV DD18 D15 S (3) DEV_DV DD18 shouldstillbe connectedtothe1.8-Vpower supply. I/OgroundforDEV oscillator.Iftheinternaloscillatorisbypassed,DEV_DV SSDEV_DV SS E14 GND (3) shouldbe connectedtogroundVSS . 1.2-/1.05-Vpower supplyforDEV oscillator.Iftheinternaloscillatorisbypassed,DEV_CV DD E15 S (3) DEV_CV DD shouldbe connectedtothe1.2-/1.05-Vpower supply(CVDD ). Ground forDEV oscillator.Connecttocrystalloadcapacitors.Do not connectto DEV_V SS C15 GND (3) boardground(VSS ).Iftheinternaloscillatorisbypassed,DEV_V SS shouldstillbe connectedtogroundVSS . CrystalinputforAuxiliary(AUX) oscillator(24/48MHz forUSB, and UART2/1/0 and AUX_MXI/ McASP1/0).Iftheinternaloscillatorisbypassed,thispinisthe1.8-VexternalB17 I AUX_DV DD18AUX_CLKIN oscillatorclockinput.When theperipheralisnot used,AUX_MXI shouldbe leftas a No Connect. CrystaloutputforAUX oscillator.Iftheinternaloscillatorisbypassed,AUX_MXO AUX_MXO A17 O AUX_DV DD18 shouldbe leftas a No Connect.When theperipheralisnot used,AUX_MXO should be leftas a No Connect. 1.8-Vpower supplyforAUX oscillator.Iftheinternaloscillatorisbypassed, AUX_DV DD18 shouldstillbe connectedtothe1.8-Vpower supply.When theAUX_DV DD18 D16 S (3) peripheralisnot used,AUX_DV DD18 shouldbe connectedtothe1.8-Vpower supply. I/OgroundforAUX oscillator.Iftheinternaloscillatorisbypassed,AUX_DV SS AUX_DV SS C16 GND (3) shouldbe connectedtoground(VSS ).When theperipheralisnot used,AUX_DV SS shouldbe connectedtoground(VSS ). 1.2-/1.05-Vpower supplyforAUX oscillator.Iftheinternaloscillatorisbypassed, AUX_CV DD shouldbe connectedtothe1.2-/1.05-Vpower supply(CVDD ).When theAUX_CV DD E16 S (3) peripheralisnot used,AUX_CV DD shouldbe connectedtothe1.2-/1.05-Vpower supply(CVDD ). Ground forAUX oscillator.Connecttocrystalloadcapacitors.Do not connectto boardground(VSS ).Iftheinternaloscillatorisbypassed,AUX_V SS shouldstillbeAUX_V SS C17 GND (3) connectedtoground(VSS ).When theperipheralisnot used,AUX_V SS shouldbe connectedtoground(VSS ). PLL1V DD18 B14 S (3) 1.8-Vpower supplyforPLLs. PLL2V DD18 B16 PLL1V SS C14 GND (3) Ground forPLLs. PLL2V SS A16 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal (3) Formore information,see theRecommended OperatingConditionstable

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3.7.3 Clock Generator

Table3-7.Clock GeneratorTerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. CLOCK GENERATOR CLKOUT0 C13 O/Z DV DD33 Configurableoutputclock. GP[3]/ IPD Thispinismultiplexedbetween GPIO and theAudioClockSelector.FortheaudioAB3 I/O/ZAUDIO_CLK0 DV DD33 clockselector,thispinistheconfigurableAUDIO_CLK0 output. GP[2]/ IPD Thispinismultiplexedbetween GPIO and theAudioClockSelector.FortheaudioAA4 I/O/ZAUDIO_CLK1 DV DD33 clockselector,thispinistheconfigurableAUDIO_CLK1 output. Thispinismultiplexedbetween GPIO and theTSIF ClockSelector.ForTSIF,thisGP[4]/ IPDAC3 I/O/Z pinistheSTC_CLKIN whichcan be used as an externalclocksourcefortheTSIFSTC_CLKIN DV DD33 countersoras TSIF outputclock. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 33 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.4 RESET and JTAG

Table3-8.RESET and JTAG TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. RESET IPURESET W6 I Devicereset.DV DD33 IPUPOR D17 I Power-onreset.DV DD33 JTAG IPU JTAG test-portmode selectinput.TMS D12 I DV DD33 Forproperdeviceoperation,do not oppose theIPU on thispin. –TDO D13 O/Z JTAG test-portdataoutput.DV DD33 IPUTDI E13 I JTAG test-portdatainput.DV DD33 IPUTCK B12 I JTAG test-portclockinput.DV DD33 –RTCK C12 O/Z JTAG test-portreturnclockoutput.DV DD33 IPD JTAG test-portreset.ForIEEE 1149.1JTAG compatibility,see theIEEE 1149.1TRST E12 I DV DD33 JTAG compatibilitystatementportionofthisdatamanual. IPUEMU1 B13 I/O/Z Emulationpin1DV DD33 IPUEMU0 A13 I/O/Z Emulationpin0DV DD33 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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3.7.5 Asynchronous ExternalMemory Interface(EMIFA)

Table3-9.Asynchronous ExternalMemory Interface(EMIFA) TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EMIFA BOOT CONFIGURATION EMIFA CS2 space databus width.Thispinismultiplexedbetween EMIFA control and theVPIF.Atreset,theinputstateissampled tosettheEMIFA databus widthfortheCS2 (boot)chipselectregion.VP_DOUT4/ IPDAA7 I/O/ZCS2BW DV DD33 Foran 8-bit-wideEMIFA databus,CS2BW = 0. Fora 16-bit-wideEMIFA databus,CS2BW = 1. Afterreset,thispinisvideoportdataoutput4 (VP_DOUT4). DSP bootsourcebit.Thispinismultiplexedbetween DSP bootand theVPIF.At reset,theinputstateissampled tosettheDSP bootsourceDSPBOOT. VP_DOUT6/ IPDAC5 I/O/Z The DSP isbootedby theARM when DSPBOOT = 0.DSPBOOT DV DD33 The DSP bootsfromEMIFA when DSPBOOT=1. Afterreset,thispinisvideoportdataoutput6 (VP_DOUT6). EMIFA FUNCTIONAL PINS: ASYNC PCI_IDSEL/ IPU Thispinismultiplexedbetween PCI,ATA, and EMIFA.HDDIR/ E8 I/O/Z DV DD33 InEMIFA mode, thispinistheread/writeoutputEM_R/ W (O/Z).EM_R/ W PCI_SERR/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HDS1/ B2 I/O/Z DV DD33 InEMIFA mode, thispinistheoutputenableoutputEM_OE (O/Z).EM_OE PCI_STOP/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HCNTL0/ D5 I/O/Z DV DD33 InEMIFA mode, thispinisthewriteenableoutputEM_WE (O/Z).EM_WE PCI_PERR/ IPUHCS/ C3 I/O/Z DV DD33EM_DQM1 These pinsaremultiplexedbetween PCI,HPI,and EMIFA. InEMIFA mode, thesepinsareEM_DQM[1:0] and actas byteenables(O/Z).PCI_PAR/ IPUHAS/ D4 I/O/Z DV DD33EM_DQM0 PCI_INTA/ Thispinismultiplexedbetween PCI and EMIFA.IPUEM_WAIT2 / C11 I/O/Z InEMIFA mode, thispiniswaitstateextensioninput2 EM_WAIT2 (I).DV DD33(RDY2/BSY2) When used forEMIFA (NAND), thispinistheready/busy2 input(RDY2/BSY2). PCI_RSV5/IORDY/ Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.IPUGP[21]/EM_WAIT3 / D11 I/O/Z InEMIFA mode, thispiniswaitstateextensioninput3 EM_WAIT3 (I).DV DD33(RDY3/BSY3) When used forEMIFA (NAND), thispinistheready/busy3 input(RDY3/BSY3). (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 35 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-9.Asynchronous ExternalMemory Interface(EMIFA) TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_RSV4/DIOW/ Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.IPUGP[20]/EM_WAIT4 / A11 I/O/Z InEMIFA mode, thispiniswaitstateextensioninput4 EM_WAIT4 (I).DV DD33(RDY4/BSY4) When used forEMIFA (NAND), thispinistheready/busy4 input(RDY4/BSY4). PCI_RSV3/DIOR/ Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.IPUGP[19]/EM_WAIT5 / E10 I/O/Z ForEMIFA, thispiniswaitstateextensioninput5 EM_WAIT5 (I).DV DD33(RDY5/BSY5) When used forEMIFA (NAND), thispinistheready/busy5 input(RDY5/BSY5). Thispinismultiplexedbetween PCI,HPI,and EMIFA. ForEMIFA, thisistheBank Address0 outputEM_BA[0] (O/Z).PCI_FRAME/ IPU When connectedtoa 16-bitasynchronousmemory, thispinhas thesameHINT/ D6 I/O/Z DV DD33 functionas EMIF addresspin22 (EM_A[22]).EM_BA[0] When connectedtoan 8-bitasynchronousmemory, thispinisthelowestorderbit ofthebyteaddress. Thispinismultiplexedbetween PCI,HPI,and EMIFA. ForEMIFA, thisistheBank Address1 outputEM_BA[1] (O/Z).PCI_DEVSEL/ IPU When connectedtoa 16 bitasynchronousmemory thispinisthelowestorderbitHCNTL1/ B3 I/O/Z DV DD33 ofthe16-bitword address.EM_BA[1] When connectedtoan 8-bitasynchronousmemory, thispinisthesecond bitof theaddress. PCI_IRDY/ Thispinismultiplexedbetween PCI,HPI,and EMIFA.IPUHRDY/ A3 I/O/Z InEMIFA mode, thispinisaddressbit17 outputEM_A[17] (O/Z).DV DD33EM_A[17]/(CLE) When used forEMIFA (NAND), thispinisCommand LatchEnableoutput(CLE). PCI_TRDY/ Thispinismultiplexedbetween PCI,HPI,and EMIFA.IPUHHWIL/ E6 I/O/Z ForEMIFA, thispinisaddressbit16 outputEM_A[16] (O/Z).DV DD33EM_A[16]/(ALE) When used forEMIFA (NAND), thispinisAddressLatchEnableoutput(ALE).

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-9.Asynchronous ExternalMemory Interface(EMIFA) TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. Thispinismultiplexedbetween PCI,ATA, HPI,and EMIFA. ForEMIFA, thispinisaddressbit0 outputEM_A[0] (O/Z),whichistheleastPCI_AD16/ IPD significantbiton a 32-bitword address.DD0/ C6 I/O/Z DV DD33 When connectedtoa 16-bitasynchronousmemory, thispinisthesecond bitofHD16/EM_A[0] theaddress. Foran 8-bitasynchronousmemory, thispinisthethirdbitoftheaddress. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 37 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-9.Asynchronous ExternalMemory Interface(EMIFA) TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_AD15/ IPDE5 I/O/ZHD15/EM_D15 DV DD33 PCI_AD14/ IPDC1 I/O/ZHD14 /EM_D14 DV DD33 PCI_AD13/ IPDE4 I/O/ZHD13/EM_D13 DV DD33 PCI_AD12/ IPDD3 I/O/ZHD12/EM_D12 DV DD33 PCI_AD11/ IPDE3 I/O/ZHD11/EM_D11 DV DD33 PCI_AD10/ IPDD2 I/O/ZHD10/EM_D10 DV DD33 PCI_AD9/ IPDF5 I/O/ZHD9/EM_D9 DV DD33 These pinsaremultiplexedbetween PCI,HPI,and EMIFA.PCI_AD8/ IPDD1 I/O/Z ForEMIFA mode, thesepinsarethe16-bitbidirectionaldatabus (EM_D[15:0])HD8/EM_D8 DV DD33 [I/O/Z]. PCI_AD7/ IPD When EMIFA isconfiguredforan 8-bitasynchronousmemory, onlyEM_D[7:0]E2 I/O/ZHD7/EM_D7 DV DD33 pinsareused. PCI_AD6/ IPDF3 I/O/ZHD6/EM_D6 DV DD33 PCI_AD5/ IPDE1 I/O/ZHD5/EM_D5 DV DD33 PCI_AD4/ IPDG5 I/O/ZHD4/EM_D4 DV DD33 PCI_AD3/ IPDF2 I/O/ZHD3/EM_D3 DV DD33 PCI_AD2/ IPDG4 I/O/ZHD2/EM_D2 DV DD33 PCI_AD1/ IPDF1 I/O/ZHD1/EM_D1 DV DD33 PCI_AD0/ IPDG3 I/O/ZHD0/EM_D0 DV DD33 EMIFA FUNCTIONAL PINS: NAND PCI_IRDY/ Thispinismultiplexedbetween PCI,HPI,and EMIFA.IPUHRDY/ A3 I/O/Z InEMIFA mode, thispinisaddressbit17 outputEM_A[17] (O/Z).DV DD33EM_A[17]/(CLE) When used forEMIFA (NAND), thispinisCommand LatchEnableoutput(CLE). PCI_TRDY/ Thispinismultiplexedbetween PCI,HPI,and EMIFA.IPUHHWIL/ E6 I/O/Z ForEMIFA, thispinisaddressbit16 outputEM_A[16] (O/Z).DV DD33EM_A[16]/(ALE) When used forEMIFA (NAND), thispinisAddressLatchEnableoutput(ALE). PCI_INTA/ Thispinismultiplexedbetween PCI and EMIFA.IPUEM_WAIT2 / C11 I/O/Z InEMIFA mode, thispiniswaitstateextensioninput2 EM_WAIT2 (I).DV DD33(RDY2/BSY2) When used forEMIFA (NAND), thispinistheready/busy2 input(RDY2/BSY2). IORDY/ Thispinismultiplexedbetween ATA, GPIO, and EMIFA.IPUGP[21]/EM_WAIT3 / D11 I/O/Z InEMIFA mode, thispiniswaitstateextensioninput3 EM_WAIT3 (I).DV DD33(RDY3/BSY3) When used forEMIFA (NAND), thispinistheready/busy3 input(RDY3/BSY3). DIOW/ Thispinismultiplexedbetween ATA, GPIO, and EMIFA.IPUGP[20]/EM_WAIT4 / A11 I/O/Z InEMIFA mode, thispiniswaitstateextensioninput4 EM_WAIT4 (I).DV DD33(RDY4/BSY4) When used forEMIFA (NAND), thispinistheready/busy4 input(RDY4/BSY4). DIOR/ Thispinismultiplexedbetween ATA, GPIO, and EMIFA.IPUGP[19]/EM_WAIT5 / E10 I/O/Z ForEMIFA, thispiniswaitstateextensioninput5 EM_WAIT5 (I).DV DD33(RDY5/BSY5) When used forEMIFA (NAND), thispinistheready/busy5 input(RDY5/BSY5). PCI_SERR/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HDS1/ B2 I/O/Z DV DD33 InEMIFA mode, thispinistheoutputenableoutputEM_OE (O/Z).EM_OE

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-9.Asynchronous ExternalMemory Interface(EMIFA) TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_STOP/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HCNTL0/ D5 I/O/Z DV DD33 InEMIFA mode, thispinisthewriteenableoutputEM_WE (O/Z).EM_WE PCI_AD15/ IPDE5 I/O/ZHD15/EM_D15 DV DD33 PCI_AD14/ IPDC1 I/O/ZHD14 /EM_D14 DV DD33 PCI_AD13/ IPDE4 I/O/ZHD13/EM_D13 DV DD33 PCI_AD12/ IPDD3 I/O/ZHD12/EM_D12 DV DD33 PCI_AD11/ IPDE3 I/O/ZHD11/EM_D11 DV DD33 PCI_AD10/ IPDD2 I/O/ZHD10/EM_D10 DV DD33 PCI_AD9/ IPDF5 I/O/ZHD9/EM_D9 DV DD33 These pinsaremultiplexedbetween PCI,HPI,and EMIFA.PCI_AD8/ IPDD1 I/O/Z ForEMIFA mode, thesepinsarethe16-bitbidirectionaldatabus (EM_D[15:0])HD8/EM_D8 DV DD33 [I/O/Z]. PCI_AD7/ IPD When EMIFA isconfiguredforan 8-bitasynchronousmemory, onlyEM_D[7:0]E2 I/O/ZHD7/EM_D7 DV DD33 pinsareused. PCI_AD6/ IPDF3 I/O/ZHD6/EM_D6 DV DD33 PCI_AD5/ IPDE1 I/O/ZHD5/EM_D5 DV DD33 PCI_AD4/ IPDG5 I/O/ZHD4/EM_D4 DV DD33 PCI_AD3/ IPDF2 I/O/ZHD3/EM_D3 DV DD33 PCI_AD2/ IPDG4 I/O/ZHD2/EM_D2 DV DD33 PCI_AD1/ IPDF1 I/O/ZHD1/EM_D1 DV DD33 PCI_AD0/ IPDG3 I/O/ZHD0/EM_D0 DV DD33 Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 39 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.6 DDR2 Memory Controller

Table3-10.DDR2 Memory ControllerTerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. DDR2 Memory Controller DDR_CLK M23 O/Z DV DDR2 DDR2 Clock DDR_CLK L23 O/Z DV DDR2 DDR2 Differentialclock DDR_CKE M20 O/Z DV DDR2 DDR2 ClockEnable DDR_CS J20 O/Z DV DDR2 DDR2 Activelowchipselect DDR_WE L20 O/Z DV DDR2 DDR2 ActivelowWriteenable DDR_RAS K19 O/Z DV DDR2 DDR2 Row Access Signaloutput DDR_CAS L21 O/Z DV DDR2 DDR2 Column Access Signaloutput DDR_DQM[3] V20 O/Z DV DDR2 DDR2 Data mask outputs DDR_DQM[3]: Forupperbytedatabus DDR_D[31:24]DDR_DQM[2] Y23 O/Z DV DDR2 DDR_DQM[2]: ForDDR_D[23:16] DDR_DQM[1] F22 O/Z DV DDR2 DDR_DQM[1]: ForDDR_D[15:8] DDR_DQM[0]: ForlowerbyteDDR_D[7:0]DDR_DQM[0] F20 O/Z DV DDR2 DDR_DQS[3] U20 I/O/Z DV DDR2 Data strobeinput/outputsforeach byteofthe32-bitdatabus.They areoutputsto theDDR2 memory when writingand inputswhen reading.They areused toDDR_DQS[2] V22 I/O/Z DV DDR2 synchronizethedatatransfers. DDR_DQS[1] D22 I/O/Z DV DDR2 DDR_DQS[3] :ForupperbyteDDR_D[31:24] DDR_DQS[2]: ForDDR_D[23:16] DDR_DQS[1]: ForDDR_D[15:8]DDR_DQS[0] D21 I/O/Z DV DDR2 DDR_DQS[0]: ForbottombyteDDR_D[7:0] DDR_DQS[3] V21 I/O/Z DV DDR2 Complimentarydatastrobeinput/outputsforeach byteofthe32-bitdatabus.They areoutputstotheDDR2 memory when writingand inputswhen reading.They areDDR_DQS[2] W23 I/O/Z DV DDR2 used tosynchronizethedatatransfers. DDR_DQS[1] D23 I/O/Z DV DDR2 DDR_DQS[3] :ForupperbyteDDR_D[31:24] DDR_DQS[2]: ForDDR_D[23:16] DDR_DQS[1]: ForDDR_D[15:8]DDR_DQS[0] E20 I/O/Z DV DDR2 DDR_DQS[0]: ForbottombyteDDR_D[7:0] DDR_ODT0 K20 O/Z DV DDR2 DDR2 on-dieterminationcontrol DDR_BA[2] P19 DDR_BA[1] M21 O/Z DV DDR2 Bank addressoutputs(BA[2:0]). DDR_BA[0] N19 DDR_A[14] N23 DDR_A[13] H21 DDR_A[12] P20 DDR_A[11] K23 DDR_A[10] T23 DDR_A[9] N22 DDR_A[8] J23 DDR_A[7] N20 O/Z DV DDR2 DDR2 addressbus DDR_A[6] M22 DDR_A[5] N21 DDR_A[4] J22 DDR_A[3] R22 DDR_A[2] L22 DDR_A[1] R23 DDR_A[0] H23 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal (3) Formore information,see theRecommended OperatingConditionstable

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-10.DDR2 Memory ControllerTerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. DDR_D[31] Y20 DDR_D[30] W20 DDR_D[29] Y21 DDR_D[28] AA21 DDR_D[27] U21 DDR_D[26] T21 DDR_D[25] R20 DDR_D[24] T20 DDR_D[23] AB22 DDR_D[22] Y22 DDR_D[21] AA22 DDR_D[20] AA23 DDR_D[19] V23 DDR_D[18] U23 DDR_D[17] T22 DDR_D[16] U22 I/O/Z DV DDR2 DDR2 databus can be configuredas 32 bitswideor16 bitswide. DDR_D[15] H22 DDR_D[14] G23 DDR_D[13] G22 DDR_D[12] F23 DDR_D[11] E23 DDR_D[10] C22 DDR_D[9] B22 DDR_D[8] C23 DDR_D[7] H20 DDR_D[6] G21 DDR_D[5] F21 DDR_D[4] G20 DDR_D[3] B21 DDR_D[2] C20 DDR_D[1] D20 DDR_D[0] C21 DDR_DQGATE0 J19 O/Z DV DDR2 DDR2 strobegatesignalforlower-halfdatabus DDR_DQGATE1 J21 I DV DDR2 DDR2 strobegatesignalreturnforlower-halfdatabus DDR_DQGATE2 R19 O/Z DV DDR2 DDR2 strobegatesignalforupper-halfdatabus DDR_DQGATE3 R21 I DV DDR2 DDR2 strobegatesignalreturnforupper-halfdatabus DDR_VREF P23 S (4) ReferencevoltageinputfortheSSTL_18 IO buffers. Impedance controlforDDR2 outputs.Thismust be connectedviaa 50-Ω (±5%DDR_ZP L19 O (4) tolerance)resistortoVSS . Impedance controlforDDR2 outputs.Thismust be connectedviaa 50-Ω (±5%DDR_ZN M19 O (4) tolerance)resistortoDV DDR2 . (4) Formore information,see theRecommended OperatingConditionstable Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 41 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.7 PeripheralComponent Interconnect(PCI)

Table3-11.PeripheralComponent Interconnect(PCI)TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI Note:When PCI bootmode isnot used,forproperdeviceoperationoutofresetPCIEN must be "0". The PCI pinfunctionsareenabledwhen PCIEN = 1 (PCImode).Thiscan be done viaan externalPU on thePCIEN pin(AC6)orby setting thePCIEN bit(bit2)inthePINMUX0 registertoa "1"afterdevicereset.Formore detailson thePCIEN pin,see Table3-5,BootTerminal Functions. InPCI mode (PCIEN = 1),theinternalpullups/pulldowns(IPUs/IPDs)aredisabledon allPCI pinsand itisrecommended tohave external pullupresistorson thePCI_RSV[5:0]pins.Formore detailedinformationon externalpullup/pulldownresistors,see Section4.8.1, Pullup/PulldownResistors. AlsoinPCI mode (PCIEN = 1),theinternalpulldowns(IPDs)aredisabledon theGP[5:7]pins.Itisrecommended tohave externalpullup resistorson theGP[5]pinwhen PCIEN = 1 and on GP[6:7]pinswhen PCIEN = 1 and VADJEN = 0. [IPU] Thispinismultiplexedbetween PCI and GPIO.PCI_CLK /GP[10] A10 I/O/Z DV DD33 InPCI mode, thispinisthePCI clockinputPCI_CLK (I). PCI_RST /DA2/ [IPD] Thispinismultiplexedbetween thePCI,ATA, GPIO, and EMIFA.C10 I/O/ZGP[13]/EM_A[22] DV DD33 InPCI mode, thispinisPCI resetPCI_RST (I). Thispinismultiplexedbetween PCI,ATA, and EMIFA.PCI_IDSEL / [IPU]E8 I/O/Z InPCI mode, thispinisthePCI initializationdeviceselect,PCI_IDSELHDDIR/EM_R/ W DV DD33 (I). PCI_DEVSEL / [IPU] Thispinismultiplexedbetween PCI,HPI,and EMIFA.B3 I/O/ZHCNTL1/EM_BA[1] DV DD33 InPCI mode, thispinisthePCI deviceselect,PCI_DEVSEL (I/O/Z). PCI_FRAME / [IPU] Thispinismultiplexedbetween PCI,HPI,and EMIFA.D6 I/O/ZHINT/EM_BA[0] DV DD33 InPCI mode, thispinisthePCI cycleframe,PCI_FRAME (I/O/Z). PCI_IRDY /HRDY/ [IPU] Thispinismultiplexedbetween PCI,HPI,and EMIFA.A3 I/O/ZEM_A[17]/(CLE) DV DD33 InPCI mode, thispinisthePCI initiatorready,PCI_IRDY (I/O/Z). PCI_ TRDY /HHWIL/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.E6 I/O/ZEM_A[16]/(ALE) DV DD33 InPCI mode, thispinisthePCI targetready,PCI_ TRDY (I/O/Z). PCI_STOP / [IPU] Thispinismultiplexedbetween PCI,HPI,and EMIFA.D5 I/O/ZHCNTL0/ EM_WE DV DD33 InPCI mode, thispinisthePCI stop,PCI_STOP (I/O/Z). PCI_SERR / [IPU] Thispinismultiplexedbetween PCI,HPI,and EMIFA.B2 I/O/ZHDS1/ EM_OE DV DD33 InPCI mode, thispinisthePCI systemerror,PCI_SERR (I/O/Z). PCI_PERR / [IPU] Thispinismultiplexedbetween PCI,HPI,and EMIFA.C3 I/O/ZHCS/ EM_DQM1 DV DD33 InPCI mode, thispinisthePCI parityerror,PCI_PERR (I/O/Z). PCI_PAR / [IPU] Thispinismultiplexedbetween PCI,HPI,and EMIFA.D4 I/O/ZHAS/EM_DQM0 DV DD33 InPCI mode, thispinisthePCI parity,PCI_PAR (I/O/Z). PCI_INTA / [IPU] Thispinismultiplexedbetween thePCI and EMIFA.EM_WAIT2/ C11 I/O/Z DV DD33 InPCI mode, thispinisthePCI interruptA,PCI_INTA (O/Z).(RDY2/BSY2) PCI_REQ / [IPU] Thispinismultiplexedbetween thePCI,ATA, GPIO, and EMIFA.DMARQ/ B9 I/O/Z DV DD33 InPCI mode, thispinisthePCI bus request,PCI_REQ (O/Z).GP[11]/EM_CS5 PCI_GNT / [IPU] Thispinismultiplexedbetween thePCI,ATA, GPIO, and EMIFA.DMACK/ D10 I/O/Z DV DD33 InPCI mode, thispinisPCI bus grant,PCI_GNT (I).GP[12]/EM_CS4 Thispinismultiplexedbetween PCI,HPI,and EMIFA.PCI_CBE3 / [IPU]A5 I/O/Z InPCI mode, thispinisthePCI command/byte enable3,PCI_CBE3HR/W/EM_CS3 DV DD33 (I/O/Z). Thispinismultiplexedbetween PCI,HPI,and EMIFA.PCI_CBE2 / [IPU]C4 I/O/Z InPCI mode, thispinisthePCI command/byte enable2,PCI_CBE2HDS2/ EM_CS2 DV DD33 (I/O/Z). (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-11.PeripheralComponent Interconnect(PCI)TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_CBE1 / Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.[IPU]ATA_CS1/ C2 I/O/Z InPCI mode, thispinisthePCI command/byte enable1 PCI_CBE1DV DD33GP[32]/EM_A[19] (I/O/Z). PCI_CBE0 / Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.[IPU]ATA_CS0/ F4 I/O/Z InPCI mode, thispinisthePCI command/byte enable0 PCI_CBE0DV DD33GP[33]/EM_A[18] (I/O/Z). Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 43 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-11.PeripheralComponent Interconnect(PCI)TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_AD31 /DD15/ [IPD]A8 I/O/ZHD31/EM_A[15] DV DD33 PCI_AD30 /DD14/ [IPD]C9 I/O/ZHD30/EM_A[14] DV DD33 PCI_AD29 /DD13/ [IPD]B8 I/O/ZHD29/EM_A[13] DV DD33 PCI_AD28 /DD12/ [IPD]D9 I/O/ZHD28/EM_A[12] DV DD33 PCI_AD27 /DD11/ [IPD]A6 I/O/ZHD27/EM_A[11] DV DD33 PCI_AD26 /DD10/ [IPD]C8 I/O/ZHD26/EM_A[10] DV DD33 PCI_AD25 /DD9/ [IPD]B6 I/O/ZHD25/EM_A[9] DV DD33 PCI_AD24 /DD8/ [IPD]D8 I/O/Z These pinsaremultiplexedbetween PCI,ATA, HPI,and EMIFA.HD24/EM_A[8] DV DD33 InPCI mode, thesepinsarethePCI address/databus,PCI_AD[31:16] PCI_AD23 /DD7/ [IPD] (I/O/Z).B5 I/O/ZHD23/EM_A[7] DV DD33 PCI_AD22 /DD6/ [IPD]C7 I/O/ZHD22/EM_A[6] DV DD33 PCI_AD21 /DD5/ [IPD]C5 I/O/ZHD21/EM_A[5] DV DD33 PCI_AD20 /DD4/ [IPD]D7 I/O/ZHD20/EM_A[4] DV DD33 PCI_AD19 /DD3/ [IPD]A4 I/O/ZHD19/EM_A[3] DV DD33 PCI_AD18/DD2/ [IPU]E7 I/O/ZHD18/EM_A[2] DV DD33 PCI_AD17 /DD1/ [IPD]B4 I/O/ZHD17/EM_A[1] DV DD33 PCI_AD16 /DD0/ [IPD]C6 I/O/ZHD16/EM_A[0] DV DD33 PCI_AD15 / [IPD]E5 I/O/ZHD15/EM_D15 DV DD33 PCI_AD14 / [IPD]C1 I/O/ZHD14/EM_D14 DV DD33 PCI_AD13 / [IPD]E4 I/O/ZHD13/EM_D13 DV DD33 PCI_AD12 / [IPD]D3 I/O/ZHD12/EM_D12 DV DD33 These pinsaremultiplexedbetween PCI,HPI,and EMIFA. ForPCI,thesepinsarePCI data/addressbus,PCI_AD 15:0.PCI_AD11 / [IPD]E3 I/O/ZHD11/EM_D11 DV DD33 PCI_AD10 / [IPD]D2 I/O/ZHD10/EM_D10 DV DD33 PCI_AD9 / [IPU]F5 I/O/ZHD9/EM_D9 DV DD33 PCI_AD8 / [IPD]D1 I/O/ZHD8/EM_D8 DV DD33

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-11.PeripheralComponent Interconnect(PCI)TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_AD7 / [IPD]E2 I/O/ZHD7/EM_D7 DV DD33 PCI_AD6 / [IPD]F3 I/O/ZHD6/EM_D6 DV DD33 PCI_AD5 / [IPD]E1 I/O/ZHD5/EM_D5 DV DD33 PCI_AD4 / [IPD]G5 I/O/ZHD4/EM_D4 DV DD33 These pinsaremultiplexedbetween PCI,HPI,and EMIFA. ForPCI,thesepinsarePCI data/addressbus 15:0PCI_AD3 / [IPD]F2 I/O/ZHD3/EM_D3 DV DD33 PCI_AD2 / [IPD]G4 I/O/ZHD2/EM_D2 DV DD33 PCI_AD1 / [IPD]F1 I/O/ZHD1/EM_D1 DV DD33 PCI_AD0 / [IPD]G3 I/O/ZHD0/EM_D0 DV DD33 PCI_RSV0 /DA1/ [IPD]A9 I/O/Z PCI reservedforfutureenhancements (I)(1) GP[16]/EM_A[21] DV DD33 PCI_RSV1 /DA0/ [IPD]E9 I/O/Z PCI reservedforfutureenhancements (O/Z)(1) GP[17]/EM_A[20] DV DD33 PCI_RSV2 /INTRQ/ [IPD]B10 I/O/Z PCI reservedforfutureenhancements (I)(1) GP[18]/EM_RSV 0 DV DD33 PCI_RSV3 /DIOR/ [IPU]GP[19]/ E10 I/O/Z PCI reservedforfutureenhancements (O/Z)(1) DV DD33EM_WAIT5 PCI_RSV4 /DIOW/ [IPU]GP[20]/ A11 I/O/Z PCI reservedforfutureenhancements (I/O/Z)(1) DV DD33EM_WAIT4 PCI_RSV5 /IORDY/ [IPU]GP[21]/ D11 I/O/Z PCI reservedforfutureenhancements (I/O/Z)(1) DV DD33EM_WAIT3 (1) InPCI mode (PCIEN = 1),itisrecommended tohave an externalpullupresistoron thispin. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 45 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.8 EMAC [G]MIIand MDIO

Table3-12.EMAC [G]MIIand MDIO TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EMAC [G]MII IPDRFTCLK H1 I Gigabit(GMII)referencetransmitclock(125MHz)DV DD33 -GMTCLK P2 O/Z GMII sourceasynchronoustransmitclockDV DD33 IPDMTCLK R1 I [G]MIItransmitclockinputDV DD33 MTXD7 P1 MTXD6 N4 MTXD5 N3 MTXD4 N2 - [G]MIItransmitdata[7:0].For1000 GMII operation,MTXD[7:0]areused.For10/100O/Z DV DD33 MIIoperation,onlyMTXD[3:0]areused.MTXD3 N1 MTXD2 M4 MTXD1 M1 MTXD0 L1 -MTXEN L2 O/Z [G]MIItransmitdataenableoutputDV DD33 IPDMCOL L4 I [G]MIIcollisiondetect(sense)inputDV DD33 IPDMCRS L3 I [G]MIIcarriersense inputDV DD33 IPUMRCLK K1 I [G]MIIreceiveclockDV DD33 MRXD7 K2 MRXD6 K3 MRXD5 K4 MRXD4 J1 IPU [G]MIIreceivedata[7:0].For1000 GMII operation,MRXD[7:0] areused.For10/100I DV DD33 MIIoperation,onlyMRXD[3:0] areused.MRXD3 J2 MRXD2 J3 MRXD1 H2 MRXD0 G2 IPUMRXDV J4 I [G]MIIreceivedatavalidinputDV DD33 IPUMRXER H3 I [G]MIIreceivedataerrorinputDV DD33 MDIO IPUMDCLK G1 O/Z Management dataserialclockoutputDV DD33 IPUMDIO H4 I/O/Z Management Data IODV DD33 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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3.7.9 VLYNQ

Table3-13.VLYNQ TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. VLYNQ IPUVLYNQ_CLOCK U1 I/O/Z VLYNQ serialclockDV DD33 IPUVLYNQ_SCRUN U2 I/O/Z VLYNQ serialclockrunrequestDV DD33 VLYNQ_TXD3 T3 VLYNQ_TXD2 T2 –O/Z VLYNQ transmitbus [3:0]DV DD33VLYNQ_TXD1 T1 VLYNQ_TXD0 R4 VLYNQ_RXD3 R3 VLYNQ_RXD2 R2 IPDI VLYNQ receivebus [3:0]DV DD33VLYNQ_RXD1 P3 VLYNQ_RXD0 P4 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 47 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.10 Host-PortInterface(HPI)

Table3-14.HPI TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. Host-PortInterface(HPI) HPI isenabledby thePINMUX0.HPIEN =1 (and PCIEN = 0 and ATAEN dependentfor16-/32-bitmodes).Formore detailedinformationon theHPI pinmuxing,see Section4.7.3.1,PCI,HPI,EMIFA, and ATA PinMuxing. PCI_PERR/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HCS / C3 I/O/Z DV DD33 InHPI mode, thispinistheHPI active-lowchipselectinput,HCS (I).EM_DQM1 PCI_STOP/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HCNTL0 / D5 I/O/Z DV DD33 InHPI mode, thispinistheHPI controlinput0,HCNTL0 (I)EM_WE PCI_DEVSEL/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HCNTL1 / B3 I/O/Z DV DD33 InHPI mode, thispinistheHPI controlinput1,HCNTL1 (I).EM_BA[1] Thispinismultiplexedbetween PCI,HPI,and EMIFA. PCI_PAR/ HAS / IPU InHPI mode, thispinistheHPI addressstrobe,HAS (I).D4 I/O/ZEM_DQM0 DV DD33 NOTE: The DM6467 HPI does not supporttheHAS feature.ForproperHPI operationifthepinisroutedout,itmust be pulledup viaan externalresistor. PCI_SERR/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.B2 I/O/ZHDS1 /EM_OE DV DD33 InHPI mode, thispinistheHPI datastrobeinput1,HDS1 (I). PCI_CBE2/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.C4 I/O/ZHDS2 /EM_CS2 DV DD33 InHPI mode, thispinistheHPI datastrobeinput2,HDS2 (I). PCI_CBE3/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.A5 I/O/ZHR/W /EM_CS3 DV DD33 InHPI mode, thispinistheHPI hostread/writeselectinput,HR/W (I). PCI_TRDY/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HHWIL / E6 I/O/Z DV DD33 InHPI mode, thispinistheHPI half-wordidentificationinputcontrol,HHWIL (I).EM_A[16]/(ALE) PCI_AD31/ DD15/ A8 HD31 /EM_A[15] PCI_AD30/ DD14/ C9 HD30 /EM_A[14] PCI_AD29/ DD13/ B8 HD29 /EM_A[13] PCI_AD28/ DD12/ D9 These pinsaremultiplexedbetween PCI,ATA, HPI,and EMIFA.HD28 /EM_A[12] IPDI/O/Z InHPI-32mode, thesepinsaretheHPI upperdatabus,HD31:16.DV DD33PCI_AD27/ InHPI-16mode, theHD[31:16]pinsarenot used by theHPI . DD11/ A6 HD27 /EM_A[11] PCI_AD26/ DD10/ C8 HD26 /EM_A[10] PCI_AD25/ DD9/ B6 HD25 /EM_A[9] PCI_AD24/ DD8/ D8 HD24 /EM_A[8] (1) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (2) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-14.HPI TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_AD23/ DD7/ B5 HD23 /EM_A[7] PCI_AD22/ DD6/ C7 HD22 /EM_A[6] PCI_AD21/ DD5/ C5 HD21 /EM_A[5] PCI_AD20/ DD4/ D7 These pinsaremultiplexedbetween PCI,ATA, HPI,and EMIFA.HD20 /EM_A[4] IPDI/O/Z InHPI-32mode, thesepinsaretheHPI upperdatabus,HD31:16.DV DD33PCI_AD19/ InHPI-16mode, theHD[31:16]pinsarenot used by theHPI . DD3/ A4 HD19 /EM_A[3] PCI_AD18/ DD2/ E7 HD18 /EM_A[2] PCI_AD17/ DD1/ B4 HD17 /EM_A[1] PCI_AD16/ DD0/ C6 HD16 /EM_A[0] PCI_AD15/ E5HD15 /EM_D15 PCI_AD14/ C1HD14 /EM_D14 PCI_AD13/ E4HD13 /EM_D13 PCI_AD12/ D3 These pinsaremultiplexedbetween PCI,HPI,and EMIFA.HD12 /EM_D12 IPDI/O/Z InHPI-16mode, thesepinsaretheHPI databus,HD15:0.DV DD33PCI_AD11/ InHPI-32mode, thesepinsaretheHPI lowerdatabus,HD15:0.E3HD11 /EM_D11 PCI_AD10/ D2HD10 /EM_D10 PCI_AD9/ F5HD9 /EM_D9 PCI_AD8/ D1HD8 /EM_D8 PCI_AD7/ E2HD7 /EM_D7 PCI_AD6/ F3HD6 /EM_D6 PCI_AD5/ E1HD5 /EM_D5 PCI_AD4/ G5 These pinsaremultiplexedbetween PCI,HPI,and EMIFA.HD4 /EM_D4 IPDI/O/Z InHPI-16mode, thesepinsaretheHPI databus,HD15:0.DV DD33PCI_AD3/ InHPI-32mode, thesepinsaretheHPI lowerdatabus,HD15:0.F2HD3 /EM_D3 PCI_AD2/ G4HD2 /EM_D2 PCI_AD1/ F1HD1 /EM_D1 PCI_AD0/ G3HD0 /EM_D0 Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 49 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-14.HPI TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_IRDY/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.HRDY / A3 I/O/Z DV DD33 InHPI mode, thispinistheHPI hostreadyoutputfromDSP tohost,HRDY (O/Z).EM_A[17]/(CLE) PCI_FRAME/ IPU Thispinismultiplexedbetween PCI,HPI,and EMIFA.D6 I/O/ZHINT /EM_BA[0] DV DD33 InHPI mode, thispinistheHPI hostinterruptoutput,HINT (O/Z).

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3.7.11 USB

Table3-15.USB TerminalFunctions SIGNAL OTHER (2)(3) TYPE (1) DESCRIPTION(4) NAME NO. USB 2.0 USB_DP A19 A I/O USB bidirectionalData Differentialsignalpair[positive/negative]. When theUSB peripheralisnot used,theUSB_DP signalshouldbe pulledup USB_DN A20 A I/O (high)and theUSB_DN signalshouldbe pulleddown (low)viaa 10-kΩ resistor. USB currentreferenceoutput.When theUSB peripheralisused,thispinmust be connectedviaa 10-kΩ ±1% resistortoUSB_V SSREF .USB_R1 D18 A I/O (4) When theUSB peripheralisnot used,thispinmust be connectedviaa 10-kΩ resistortoUSB_V SSREF . Thispinismultiplexedbetween USB and GPIO. USB_DRVVBUS / IPD When thispinisused as USB_DRVVBUS (PINMUX0.VBUSDIS = 0),and theUSBB18 I/O/ZGP[22] DV DD33 Controllerisoperatingas a Host(USBCTL.USBID = 0 and Sessionisinprogress), thissignalisused by theUSB ControlertoenabletheexternalVBUS chargepump. Ground forreferencecurrent.Thispinmust be connectedviaa 10-kΩ ±1% resistor toUSB_R1.USB_V SSREF C18 GND (4) When theUSB peripheralisnot used,theUSB_V SSREF signalshouldbe connected toVSS . Analog3.3V power supplyforUSB PHY. USB_V DDA3P3 F18 S (4) When theUSB peripheralisnot used,theUSB_V DDA3P3 signalshouldbe connectedtoDV DD33 . 1.8-VI/Opower supplyforUSB PHY. USB_V DD1P8 E18 S (4) When theUSB peripheralisnot used,theUSB_V DD1P8 signalshouldbe connected to1.8-Vpower supply. Core power supplyLDO outputforUSB PHY. Thispinmust be connectedviaa 1- μF capacitortoVSS .USB_V DDA1P2LDO E17 S (4) When theUSB peripheralisnot used,theUSB_V DDA1P2LDO signalshouldstillbe connectedviaa 1-μF capacitortoVSS . (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal (4) Formore information,see theRecommended OperatingConditionstable Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 51 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.12 Video-PortInterface(VPIF)

Table3-16.Video-PortInterface(VPIF)TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. VIDEO-PORT INTERFACE (VPIF)– CAPTURE IPDVP_CLKIN0 AC13 I VPIF capturechannel0 inputclock(I).DV DD33 IPDVP_CLKIN1 AB18 I VPIF capturechannel1 inputclock(I).DV DD33 Thispinismultiplexedbetween theVPIF and TSIF0.VP_DIN15_VP_VSYNC / IPDAC18 I When used fortheVPIF,thispiniscapturedatabit15 ortheverticalsyncTS0_DIN7 DV DD33 input,VP_DIN15_VSYNC (I). Thispinismultiplexedbetween theVPIF and TSIF0.VP_DIN14_VP_HSYNC / IPDAA17 I When used fortheVPIF,thispiniscapturedatabit14 orthehorizontalsyncTS0_DIN6 DV DD33 input,VP_DIN14_HSYNC (I). Thispinismultiplexedbetween theVPIF and TSIF0.VP_DIN13_FIELD / IPDAB17 I When used fortheVPIF,thispiniscapturedatabit13 orthefieldindicatorTS0_DIN5 DV DD33 input,VP_DIN13_FIELD (I). VP_DIN12 / AC17TS0_DIN4 VP_DIN11 / Y16TS0_DIN3 VP_DIN10 / IPD These pinsaremultiplexedbetween theVPIF and TSIF0.AA16 ITS0_DIN2 DV DD33 When used fortheVPIF,thesepinsarecapturedatabits,VP_DIN12:8. VP_DIN9 / AB16TS0_DIN1 VP_DIN8 / AC16TS0_DIN0 VP_DIN7 / TS0_DOUT7/ Y14 TS1_DIN VP_DIN6 / TS0_DOUT6/ AA14 TS1_PSTIN IPD These pinsaremultiplexedbetween theVPIF,TSIF0,and TSIF1.I/O/Z DV DD33 When used fortheVPIF,thesepinsarecapturedatabits,VP_DIN7:4.VP_DIN5 / TS0_DOUT5/ AB14 TS1_EN_WAITO VP_DIN4 / TS0_DOUT4/ AC14 TS1_WAITO VP_DIN3 / Y15TS0_DOUT3 VP_DIN2 / AA15TS0_DOUT2 IPD These pinsaremultiplexedbetween theVPIF and TSIF0.I/O/Z DV DD33 When used fortheVPIF,thesepinsarecapturedatabits,VP_DIN3:0.VP_DIN1 / AB15TS0_DOUT1 VP_DIN0 / AC15TS0_DOUT0 VIDEO-PORT INTERFACE (VPIF)– DISPLAY IPDVP_CLKIN2 Y10 I VPIF displaychannel2 sourceinputclock(I).DV DD33 Thispinismultiplexedbetween theVPIF and TSIF1.VP_CLKIN3 / IPDAC9 I/O/Z When used forVPIF,thispinisdisplaychannel3 sourceclock,VP_CLKIN3TS1_CLKO DV DD33 (I). (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-16.Video-PortInterface(VPIF)TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. -VP_CLKO2 AA9 O/Z VPIF displaychannel2 outputclock(O/Z).DV DD33 Thispinismultiplexedbetween theVPIF and TSIF0.VP_CLKO3 / -AC10 O/Z When used forVPIF,thispinisthedisplaychannel3 outputclock,TS0_CLKO DV DD33 VP_CLKO3 (O/Z). VP_DOUT15 / AB8 I/O/ZTS1_DIN VP_DOUT14 / AC7 I/O/ZTS1_PSTIN VP_DOUT13 / Y9 I/O/ZTS1_EN_WAITO VP_DOUT12 / AA8 I/O/Z These pinsaremultiplexedbetween theVPIF and TSIF1.TS1_WAITO IPD When used fortheVPIF,thesepinsaredisplaydatabits,VP_DOUT[15:8]DV DD33VP_DOUT11 / (O/Z).AB10 O/ZTS1_DOUT VP_DOUT10 / AA10 O/ZTS1_PSTO VP_DOUT9 / AC8 O/ZTS1_ENAO VP_DOUT8 / AB9 O/ZTS1_WAITIN VP_DOUT7 / AB7VADJEN VP_DOUT6 / AC5DSPBOOT VP_DOUT5 / AC6PCIEN VP_DOUT4 / AA7 These pinsaremultiplexedbetween theVPIF and bootconfiguration.CS2BW IPDI/O/Z Afterreset,thesepinsareused by theVPIF as displaydatabits,DV DD33VP_DOUT3 / VP_DOUT[7:0] (O/Z).AB6BTMODE3 VP_DOUT2 / Y8BTMODE2 VP_DOUT1 / AC4BTMODE1 VP_DOUT0 / AB5BTMODE0 Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 53 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.13 TransportStream Interface0 (TSIF0)

Table3-17.TransportStream Interface0 (TSIF0)TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. TSIF0 PARALLEL INPUT (PINMUX0.PTSIMUX = 10) IPDTS0_CLKIN AC19 I TSIF0 receiveclockinput(I).DV DD33 Thispinismultiplexedbetween UART1, TSIF0,and GPIO.UCTS1/USD1/ IPU When TSIF0 inputisenabled(PINMUX0.PTSIMUX = 1x),insynchronousTS0_EN_WAITO / Y17 I/O/Z DV DD33 mode, thispinisthedataenableindicator(I)or inasynchronousmode, thisGP[26] pinisthewaitoutput(O/Z),TS0_EN_WAITO. Thispinismultiplexedbetween UART1, TSIF0,and GPIO. URTS1/UIRTX1/ IPU When TSIF0 inputisenabled(PINMUX0.PTSIMUX = 1x),inasynchronousAA18 I/O/ZTS0_WAITO /GP[25] DV DD33 mode, thispinisthewaitoutput,TS0_WAITO (O/Z). ThisTSIF pinfunctionisnotused insynchronousmode. Thispinismultiplexedbetween UART2, TSIF0,and GPIO.URTS2/UIRTX2/ IPUAC20 I/O/Z When TSIF0 inputisenabled(PINMUX0.PTSIMUX = 1x),thispinistheTS0_PSTIN /GP[41] DV DD33 packetstartinputindicator,TS0_PSTIN (I). VP_DIN15_VP_VSYNC/ AC18TS0_DIN7 VP_DIN14_VP_HSYNC/ AA17TS0_DIN6 VP_DIN13_FIELD/ AB17TS0_DIN5 VP_DIN12/ AC17 These pinsaremultiplexedbetween theVPIF and TSIF0.TS0_DIN4 IPDI/O/Z When TSIF0 parallelinputmux mode isenabled(PINMUX0.PTSIMUX = 10),DV DD33VP_DIN11/ thesepinsareinputdatabitsTS0_DIN7:0.Y16TS0_DIN3 VP_DIN10/ AA16TS0_DIN2 VP_DIN9/ AB16TS0_DIN1 VP_DIN8/ AC16TS0_DIN0 TSIF0 SERIAL INPUT (PINMUX0.PTSIMUX = 11) IPDTS0_CLKIN AC19 I TSIF0 receiveclockinput(I).DV DD33 Thispinismultiplexedbetween UART1, TSIF0,and GPIO.UCTS1/USD1/ IPU When TSIF0 inputisenabled(PINMUX0.PTSIMUX = 1x),insynchronousTS0_EN_WAITO / Y17 I/O/Z DV DD33 mode, thispinisthedataenableindicator(I)or inasynchronousmode, thisGP[26] pinisthewaitoutput(O/Z),TS0_EN_WAITO. Thispinismultiplexedbetween UART2, TSIF0,and GPIO. URTS2/UIRTX2/ IPU When TSIF0 inputisenabled(PINMUX0.PTSIMUX = 1x),inAC20 I/O/ZTS0_PSTIN /GP[41] DV DD33 synchronous/asynchronousmodes, thispinisthepacketstartinputindicator, TS0_PSTIN (I). Thispinismultiplexedbetween UART1, TSIF0,and GPIO. URXD1/ IPD When TSIF0 serialinputmux mode isenabled(PINMUX0.PTSIMUX = 11),inY18 I/O/ZTS0_DIN7 /GP[23] DV DD33 synchronous/asynchronousmodes, thispinistheserialinputdatabit(I), TS0_DIN7(I). (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-17.TransportStream Interface0 (TSIF0)TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. TSIF0 PARALLEL OUTPUT (PINMUX0.PTSIMUX = 10) Thispinismultiplexedbetween theVPIF and TSIF0.VP_CLKO3/ -AC10 O/Z When TSIF0 outputisenabled(PINMUX0.PTSOMUX = 1x),thispinistheTS0_CLKO DV DD33 transmitclockoutput,TS0_CLKO (O/Z). Thispinismultiplexedbetween UART0, TSIF0,and GPIO. UDTR0/ IPU When TSIF0 outputisenabled(PINMUX0.PTSOMUX = 1x),thispinistheY12 I/O/ZTS0_ENAO /GP[36] DV DD33 dataenableindicator,TS0_ENAO (O/Z)ineithersynchronous/asynchronous modes. Thispinismultiplexedbetween UART0, TSIF0,and GPIO.UDSR0/ IPU When TSIF0 outputisenabled(PINMUX0.PTSOMUX = 1x),thispinistheTS0_PSTO / AB11 I/O/Z DV DD33 packetstartoutputindicator,TS0_PSTO (O/Z)ineitherGP[37] synchronous/asynchronousmodes. Thispinismultiplexedbetween UART0, TSIF0,and GPIO.UDCD0/ IPU When TSIF0 outputisenabled(PINMUX0.PTSOMUX = 1x),inasynchronousTS0_WAITIN / AA11 I/O/Z DV DD33 mode, thispinisthewaitinput,TS0_WAITIN (I).GP[38] ThisTSIF pinfunctionisnotused insynchronousmode. VP_DIN7/ TS0_DOUT7 / Y14 TS1_DIN VP_DIN6/ These pinsaremultiplexedbetween theVPIF,TSIF0,and TSIF1.TS0_DOUT6 / AA14 When parallelTSIF0 outputisenabled(PINMUX0.PTSOMUX = 10),andTS1_PSTIN IPDI/O/Z TSIF1 VPIF_DIN muxing isnot enabled(TSSI_MUX ≠ 11),thesepinsareDV DD33VP_DIN5/ theoutputdatabitsTS0_DOUT[7:4] (O/Z)ineither TS0_DOUT5 / AB14 synchronous/asynchronousmodes. TS1_EN_WAITO VP_DIN4/ TS0_DOUT4 / AC14 TS1_WAITO VP_DIN3/ Y15TS0_DOUT3 VP_DIN2/ These pinsaremultiplexedbetween theVPIF and TSIF0.AA15TS0_DOUT2 IPD When parallelTSIF0 outputisenabled(PINMUX0.PTSOMUX = 10),theseI/O/Z DV DD33 pinsaretheoutputdatabitsTS0_DOUT[3:0] (O/Z)ineitherVP_DIN1/ AB15 synchronous/asynchronousmodes.TS0_DOUT1 VP_DIN0/ AC15TS0_DOUT0 TSIF0 SERIAL OUTPUT (PINMUX0.PTSIMUX = 11) Thispinismultiplexedbetween theVPIF and TSIF0.VP_CLKO3/ -AC10 O/Z When TSIF0 outputisenabled(PINMUX0.PTSOMUX = 1x),thispinistheTS0_CLKO DV DD33 transmitclockoutput,TS0_CLKO (O/Z). Thispinismultiplexedbetween UART0, TSIF0,and GPIO. UDTR0/ IPU When TSIF0 outputisenabled(PINMUX0.PTSOMUX = 1x),thispinistheY12 I/O/ZTS0_ENAO /GP[36] DV DD33 dataenableindicator,TS0_ENAO (O/Z)ineithersynchronous/asynchronous modes. Thispinismultiplexedbetween UART0, TSIF0,and GPIO. UDSR0/ IPU When TSIF0 outputisenabled(PINMUX0.PTSOMUX = 1x),thispinistheAB11 I/O/ZTS0_PSTO /GP[37] DV DD33 packetstartoutputindicator,TS0_PSTO (O/Z)ineither synchronous/asynchronousmodes. Thispinismultiplexedbetween UART0, TSIF0,and GPIO. UDCD0/ IPU When TSIF0 outputisenabled(PINMUX0.PTSOMUX = 1x),inasynchronousAA11 I/O/ZTS0_WAITIN /GP[38] DV DD33 mode, thispinisthewaitinput,TS0_WAITIN (I). ThisTSIF pinfunctionisnotused insynchronousmode. Thispinismultiplexedbetween UART1, TSIF0,and GPIO. UTXD1/URCTX1/ IPD When serialTSIF0 outputisenabled(PINMUX0.PTSOMUX = 11),inAB19 I/O/ZTS0_DOUT7 /GP[24] DV DD33 synchronous/asynchronousmodes, thispinistheserialoutputdatabit, TS0_DOUT[7] (O/Z). Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 55 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.14 TransportStream Interface1 (TSIF1)

Table3-18.TransportStream Interface1 (TSIF1)TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. TSIF1 INPUT – UART0 MUXING (PINMUX0.TSSIMUX = 01) IPDTS1_CLKIN AC11 I TSIF1 receiveclockinput(I).DV DD33 Thispinismultiplexedbetween UART0 and TSIF1.URXD0/ IPDAB13 I When TSIF1 inputon UART0 muxing isenabled(PINMUX0.TSSIMUX = 01),thisTS1_DIN DV DD33 pinistheserialdatainput,TS1_DIN (I). Thispinismultiplexedbetween UART0 and TSIF1. URTS0/UIRTX0/ IPU When TSIF1 inputon UART0 muxing isenabled(PINMUX0.TSSIMUX = 01),inAA13 I/O/ZTS1_EN_WAITO DV DD33 synchronousmode, thispinisthedataenableindicator(I)or inasynchronous mode, thispinisthewaitoutput,TS1_EN_WAITO (O/Z). Thispinismultiplexedbetween UART0 and TSIF1.UTXD0/URCTX0/ IPDY13 I/O/Z When TSIF1 inputon UART0 muxing isenabled(PINUMX0.TSSIMUX = 01),thisTS1_PSTIN DV DD33 pinisthepacketstartindicator,TS1_PSTIN (I). TSIF1 INPUT – VPIF DOUT MUXING (PINMUX0.TSSIMUX = 10) IPDTS1_CLKIN AC11 I TSIF1 receiveclockinput(I).DV DD33 Thispinismultiplexedbetween VPIF and TSIF1.VP_DOUT15/ IPDAB8 I/O/Z When TSIF1 inputon VPIF DOUT muxing isenabled(PINMUX0.TSSIMUX = 10),TS1_DIN DV DD33 thispinistheserialdatainput,TS1_DIN (I). Thispinismultiplexedbetween VPIF and TSIF1. VP_DOUT13/ IPD When TSIF1 inputon VPIF DOUT muxing isenabled(PINMUX0.TSSIMUX = 10),inY9 I/O/ZTS1_EN_WAITO DV DD33 synchronousmode, thispinisthedataenableindicator(I)or inasynchronous mode, thispinisthewaitoutput,TS1_EN_WAITO (O/Z). Thispinismultiplexedbetween VPIF and TSIF1. VP_DOUT14/ IPD When TSIF1 inputon VPIF DOUT muxing isenabled(PINMUX0.TSSIMUX = 10),inAC7 I/O/ZTS1_PSTIN DV DD33 synchronous/asynchronousmodes, thispinisthepacketstartindicator, TS1_PSTIN (I). TSIF1 INPUT – VPIF DIN MUXING (PINMUX0.TSSIMUX = 11) IPDTS1_CLKIN AC11 I TSIF1 receiveclockinput(I).DV DD33 VP_DIN7/ Thispinismultiplexedbetween VPIF,TSIF0,and TSIF1.IPDTS0_DOUT7/ Y14 I/O/Z When TSIF1 inputon VPIF DIN muxing isenabled(PINMUX0.TSSIMUX = 11),inDV DD33TS1_DIN synchronous/asynchronousmodes, thispinistheserialdatainput,TS1_DIN (I). Thispinismultiplexedbetween VPIF,TSIF0,and TSIF1.VP_DIN5/ IPD When TSIF1 inputon VPIF DIN muxing isenabled(PINMUX0.TSSIMUX = 11),inTS0_DOUT5/ AB14 I/O/Z DV DD33 synchronousmode, thispinisthedataenableindicator(I)or inasynchronousTS1_EN_WAITO mode, thispinisthewaitoutput,TS1_EN_WAITO (O/Z). Thispinismultiplexedbetween VPIF,TSIF0,and TSIF1.VP_DIN6/ IPD When TSIF1 inputon VPIF DIN muxing isenabled(PINMUX0.TSSIMUX = 11),inTS0_DOUT6/ AA14 I/O/Z DV DD33 synchronous/asynchronousmodes, thispinisthepacketstartindicator,TS1_PSTIN TS1_PSTIN (I). (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-18.TransportStream Interface1 (TSIF1)TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. TSIF1 OUTPUT – VPIF DOUT MUXING (PINMUX0.TSSOMUX = 10) Thispinismultiplexedbetween theVPIF and TSIF1. VP_CLKIN3/ IPD When TSIF1 outputisenabled(PINMUX0.TSSOMUX = 1x),inAC9 I/O/ZTS1_CLKO DV DD33 synchronous/asynchronousmodes, thispinisthetransmitclockoutput, TS1_CLKO (O/Z). Thispinismultiplexedbetween theVPIF and TSIF1. VP_DOUT11/ IPD When TSIF1 outputon VPIF DOUT muxing isenabled(PINMUX0.TSSOMUX = 10),AB10 I/O/ZTS1_DOUT DV DD33 insynchronous/asynchronousmodes, thispinistheserialdataoutput, TS1_DOUT (O/Z). Thispinismultiplexedbetween theVPIF and TSIF1. VP_DOUT9/ IPD When TSIF1 outputon VPIF DOUT muxing isenabled(PINMUX0.TSSOMUX = 10),AC8 I/O/ZTS1_ENAO DV DD33 insynchronous/asynchronousmodes, thispinisthedataenableindicator, TS1_ENAO (O/Z). Thispinismultiplexedbetween theVPIF and TSIF1. VP_DOUT10/ IPD When TSIF1 outputon VPIF DOUT muxing isenabled(PINMUX0.TSSOMUX = 10),AA10 I/O/ZTS1_PSTO DV DD33 insynchronous/asynchronousmodes, thispinisthepacketstartindicatoroutput, TS1_PSTO (O/Z). Thispinismultiplexedbetween theVPIF and TSIF1. VP_DOUT8/ IPD When TSIF1 outputon VPIF DOUT muxing isenabled(PINMUX0.TSSOMUX = 10),AB9 I/O/ZTS1_WAITIN DV DD33 inasynchronousmode, thispinisthewaitindicatorinput,TS1_WAITIN (I). ThisTSIF pinfunctionisnotused insynchronousmode. TSIF1 OUTPUT – UART/PWM MUXING (PINMUX0.TSSOMUX = 11) Thispinismultiplexedbetween theVPIF and TSIF1. VP_CLKIN3/ IPD When TSIF1 outputisenabled(PINMUX0.TSSOMUX = 1x),inAC9 I/O/ZTS1_CLKO DV DD33 synchronous/asynchronousmodes, thispinisthetransmitclockoutput, TS1_CLKO (O/Z). Thispinismultiplexedbetween PWM1 and TSIF1. PWM1/ - When TSIF1 outputon UART/PWM isenabled(PINMUX0.TSSOMUX = 11),inW18 I/O/ZTS1_DOUT DV DD33 synchronous/asynchronousmodes, thispinistheserialdataoutput, TS1_DOUT (O/Z). Thispinismultiplexedbetween PWM0, CRGEN0, and TSIF1.PWM0/ - When TSIF1 outputon UART/PWM isenabled(PINMUX0.TSSOMUX = 11),inCRG0_PO/ W17 O/Z DV DD33 synchronous/asynchronousmodes, thispinisthedataenableindicatoroutput,TS1_ENAO TS1_ENAO (O/Z) UCTS2/USD2/ Thispinismultiplexedbetween UART2, CRGEN0, GPIO, and TSIF1. CRG0_VCX1/ IPU When TSIF1 outputon UART/PWM isenabled(PINMUX0.TSSOMUX = 11),inAC21 I/O/ZGP[42]/ DV DD33 synchronous/asynchronousmodes, thispinisthepacketstartindicatoroutput, TS1_PSTO TS1_PSTO (O/Z). Thispinismultiplexedbetween UART0, GPIO, and TSIF1. URIN0/GP[8]/ IPD When TSIF1 outputon UART/PWM isenabled(PINMUX0.TSSOMUX = 11),inY11 I/O/ZTS1_WAITIN DV DD33 asynchronousmode, thispinisthewaitindicatorinput,TS1_WAITIN (I). ThisTSIF pinfunctionisnotused insynchronousmode. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 57 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.15 Inter-IntegratedCircuit(I2C)

Table3-19.I2C TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. I2C - I2C clockoutputSCL. Forproperdeviceoperation,thispinmust be pulledup viaSCL U5 I/O/Z DV DD33 externalresistor. - I2C bidirectionaldatasignalSDA. Forproperdeviceoperation,thispinmust beSDA U4 I/O/Z DV DD33 pulledup viaexternalresistor. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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3.7.16 SerialPeripheralInterface(SPI)

Table3-20.SPI TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. SPI IPDSPI_CLK V1 I/O/Z SPI clockDV DD33 IPDSPI_EN T5 I/O/Z SPI deviceenableDV DD33 IPDSPI_CS0 T4 I/O/Z SPI chipselect0DV DD33 IPDSPI_CS1 U3 I/O/Z SPI chipselect1DV DD33 IPDSPI_SOMI R5 I/O/Z SPI slaveout,masterindatapinDV DD33 IPDSPI_SIMO P5 I/O/Z SPI slavein,masteroutdatapinDV DD33 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 59 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.17 MultichannelAudio SerialPort(McASP)

Table3-21.MultichannelAudio SerialPort(McASP) TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. McASP0 IPDACLKR0 AA2 I/O/Z McASP0 receivebitclockDV DD33 IPDAHCLKR0 AB2 I/O/Z McASP0 receivehigh-frequencymasterclockDV DD33 IPDAFSR0 Y3 I/O/Z McASP0 receiveframesyncDV DD33 IPDACLKX0 AA1 I/O/Z McASP0 transmitbitclockDV DD33 IPDAHCLKX0 Y1 I/O/Z McASP0 transmithigh-frequencymasterclockDV DD33 IPDAFSX0 Y4 I/O/Z McASP0 transmitframesyncDV DD33 AXR0[3] W3 AXR0[2] W4 IPDI/O/Z McASP0 transmit/receivedatapins[3:0]DV DD33AXR0[1] V4 AXR0[0] V3 IPDAMUTE0 Y2 I/O/Z McASP0 mute outputDV DD33 IPDAMUTEIN0 AA3 I McASP0 mute inputDV DD33 McASP1 IPDACLKX1 W1 I/O/Z McASP1 transmitbitclockDV DD33 IPDAHCLKX1 W2 I/O/Z McASP1 transmithigh-frequencymasterclockDV DD33 IPDAXR1[0] V2 I/O/Z McASP1 transmitdatapin[0]DV DD33 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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3.7.18 Clock Recovery Generator(CRGEN)

Table3-22.Clock Recovery Generator(CRGEN) TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. CRGEN1 ONLY MODE (PINMUX0.CRGMUX = 001) URXD2/ Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0.CRG1_VCXI / IPDAB20 I/O/Z When CRGEN1 isenabled(PINMUX0.CRGMUX = 001),thispinisCRGEN1 inputGP[39]/ DV DD33 clockfromexternalVCXO, CRG1_VCXI (I).CRG0_VCXI UTXD2/ URCTX2/ Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0.CRG1_PO / IPDAA19 I/O/Z When CRGEN1 isenabled(PINMUX0.CRGMUX = 001),thispinisCRGEN1GP[40]/ DV DD33 pulsewidthmodulationoutput,CRG1_PO (O/Z).CRG0_PO CRGEN0 ONLY (UART2/PWM0 MUX) MODE (PINMUX0.CRGMUX = 100) UCTS2/ USD2/ Thispinismultiplexedbetween UART2, CRGEN0, GPIO, and TSIF1.CRG0_VCXI / IPUAC21 I/O/Z When CRGEN0 on UART2/PWM muxing isenabled(PINMUX0.CRGMUX = 10x),GP[42]/ DV DD33 thispinisCRGEN0 inputclockfromexternalVCXO, CRG0_VCXI (I).TS1_PSTO PWM0/ Thispinismultiplexedbetween PWM0, CRGEN0, and TSIF1.–CRG0_PO / W17 O/Z When CRGEN0 on UART2/PWM muxing isenabled(PINMUX0.CRGMUX = 10x),DV DD33TS1_ENAO thispinisCRGEN0 pulsewidthmodulationoutput,CRG0_PO (O/Z). CRGEN0 AND CRGEN1 MODE (PINMUX0.CRGMUX = 101) URXD2/ Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0.CRG1_VCXI / IPDAB20 I/O/Z When CRGEN1 isenabled(PINMUX0.CRGMUX = x01),thispinisCRGEN1 inputGP[39]/ DV DD33 clockfromexternalVCXO, CRG1_VCXI (I).CRG0_VCXI UTXD2/ URCTX2/ Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0.CRG1_PO / IPDAA19 I/O/Z When CRGEN1 isenabled(PINMUX0.CRGMUX = x01),thispinisCRGEN1GP[40]/ DV DD33 pulsewidthmodulationoutput,CRG1_PO (O/Z).CRG0_PO UCTS2/ USD2/ Thispinismultiplexedbetween UART2, CRGEN0, GPIO, and TSIF1.CRG0_VCXI / IPUAC21 I/O/Z When CRGEN0 on UART2/PWM muxing isenabled(PINMUX0.CRGMUX = 10x),GP[42]/ DV DD33 thispinisCRGEN0 inputclockfromexternalVCXO, CRG0_VCXI (I).TS1_PSTO PWM0/ Thispinismultiplexedbetween PWM0, CRGEN0, and TSIF1.–CRG0_PO / W17 O/Z When CRGEN0 on UART2/PWM muxing isenabled(PINMUX0.CRGMUX = 10x),DV DD33TS1_ENAO thispinisCRGEN0 pulsewidthmodulationoutput,CRG0_PO (O/Z). CRGEN0 ONLY (UART2 MUX) MODE (PINMUX0.CRGMUX = 110) URXD2/ Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0.CRG1_VCXI/ IPDAB20 I/O/Z When CRGEN0 on UART2 muxing isenabled(PINMUX0.CRGMUX = 110),thisGP[39]/ DV DD33 pinisCRGEN0 inputclockfromexternalVCXO, CRG0_VCXI (I).CRG0_VCXI UTXD2/ URCTX2/ Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0.CRG1_PO/ IPDAA19 I/O/Z When CRGEN0 on UART2 muxing isenabled(PINMUX0.CRGMUX = 110),thisGP[40]/ DV DD33 pinisCRGEN0 pulsewidthmodulationoutput,CRG0_PO (O/Z).CRG0_PO (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 61 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.19 UART0

Table3-23.UART0 TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. ActualUART0 pinfunctionsaredeterminedby thePINMUX0 and PINMUX1 registerbitsettings.For more details,see Section4.7.3,Pin Multiplexing. UART0 WITH MODEM CONTROL (PINMUX1.UART0CTL = 00) Thispinismultiplexedbetween UART0 and TSIF1. URXD0 / IPD When UART0 UART functionalmuxing isselected(PINMUX1.UART0CTL = 0x)AB13 ITS1_DIN DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),this pinisUART0 receivedata,URXD0 (I). Thispinismultiplexedbetween UART0 and TSIF1.UTXD0 / IPD When UART0 UART functionalmuxing isselected(PINMUX1.UART0CTL = 0x)URCTX0/ Y13 I/O/Z DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),thisTS1_PSTIN pinisUART0 transmitdata,UTXD0 (O/Z). Thispinismultiplexedbetween UART0 and TSIF1.URTS0 / IPU When UART0 UART functionalmuxing isselected(PINMUX1.UART0CTL = 0x)UIRTX0/ AA13 I/O/Z DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),thisTS1_EN_WAITO pinistheUART0 request-to-sendsignal,URTS0 (O/Z). Thispinismultiplexedbetween UART0 and TSIF1. IPU When UART0 UART functionalmuxing isselected(PINMUX1.UART0CTL = 0x)UCTS0 /USD0 AC12 I/O/Z DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),this pinistheUART0 clear-to-sendsignal,UCTS0 (I). Thispinismultiplexedbetween UART0, TSIF0,and GPIO.UDTR0 / IPU When UART0 UART withmodem functionalmuxing isselectedTS0_ENAO/ Y12 I/O/Z DV DD33 (PINMUX1.UART0CTL = 00)and TSIF0 outputmuxing isnot enabledGP[36] (PINMUX0.PTSOMUX ≠ 1x),thispinisUART0 data-terminal-ready,UDTR0 (O/Z). Thispinismultiplexedbetween UART0, TSIF0,and GPIO.UDSR0 / IPU When UART0 UART withmodem functionalmuxing isselectedTS0_PSTO/ AB11 I/O/Z DV DD33 (PINMUX1.UART0CTL = 00)and TSIF0 outputmuxing isnot enabledGP[37] (PINMUX0.PTSOMUX ≠ 1x),thispinisUART0 data-set-ready,UDSR0 (I). Thispinismultiplexedbetween UART0, TSIF0,and GPIO.UDCD0 / IPU When UART0 UART withmodem functionalmuxing isselectedTS0_WAITIN/ AA11 I/O/Z DV DD33 (PINMUX1.UART0CTL = 00)and TSIF0 outputmuxing isnot enabledGP[38] (PINMUX0.PTSOMUX ≠ 1x),thispinisUART0 data-carrier-detect,UDCD0 (I). Thispinismultiplexedbetween UART0, GPIO, and TSIF1. When UART0 UART withmodem functionalmuxing isselectedURIN0 /GP[8]/ IPDY11 I/O/Z (PINMUX1.UART0CTL = 00)and TSIF1 outputon UART/PWM muxing isnotTS1_WAITIN DV DD33 enabled(PINMUX0.TSSOMUX ≠ 11),thispinistheUART0 ringindicator, URIN0 (I). UART0 WITHOUT MODEM CONTROL (PINMUX1.UART0CTL = 01) Thispinismultiplexedbetween UART0 and TSIF1. URXD0 / IPD When UART0 UART functionalmuxing isselected(PINMUX1.UART0CTL = 0x)AB13 ITS1_DIN DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),this pinisUART0 receivedata,URXD0 (I). Thispinismultiplexedbetween UART0 and TSIF1.UTXD0 / IPD When UART0 UART functionalmuxing isselected(PINMUX1.UART0CTL = 0x)URCTX0/ Y13 I/O/Z DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),thisTS1_PSTIN pinisUART0 transmitdata,UTXD0 (O/Z). Thispinismultiplexedbetween UART0 and TSIF1.URTS0 / IPU When UART0 UART functionalmuxing isselected(PINMUX1.UART0CTL = 0x)UIRTX0/ AA13 I/O/Z DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),thisTS1_EN_WAITO pinisUART0 request-to-sendsignal,URTS0 (O/Z). When UART0 UART functionalmuxing isselected(PINMUX1.UART0CTL = 0x)UCTS0 / IPUAC12 I/O/Z and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),thisUSD0 DV DD33 pinisUART0 clear-to-sendsignal,UCTS0 (I). (1) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (2) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-23.UART0 TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. UART0 IrDA/CIRFUNCTION (PINMUX1.UART0CTL = 1x) Thispinismultiplexedbetween UART0 and TSIF1.URXD0 / IPDAB13 I When TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),TS1_DIN DV DD33 thispinisUART0 IrDA/CIRreceivedata,URXD0 (I). Thispinismultiplexedbetween UART0 and TSIF1.UTXD0/ IPD When UART0 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART0CTL = 1x)URCTX0 / Y13 I/O/Z DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),thisTS1_PSTIN pinisUART0 CIR transmitdata,URCTX0 (O/Z). Thispinismultiplexedbetween UART0 and TSIF1.URTS0/ IPU When UART0 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART0CTL = 1x)UIRTX0 / AA13 I/O/Z DV DD33 and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),thisTS1_EN_WAITO pinisUART0 IrDAtransmitdata,UIRTX0 (O/Z). When UART0 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART0CTL = 1x)UCTS0/ IPUAC12 I/O/Z and TSIF1 inputon UART0 muxing isnot enabled(PINMUX0.TSSIMUX ≠ 01),thisUSD0 DV DD33 pinisUART0 IrDAtransceivercontrol,USD0 (O/Z). Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 63 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.20 UART1

Table3-24.UART1 TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. UART1 WITH FLOW CONTROL (PINMUX1.UART1CTL = 00) ActualUART1 pinfunctionsaredeterminedby thePINMUX0 and PINMUX1 registerbitsettings.For more details,see Section4.7.3,Pin Multiplexing. Thispinismultiplexedbetween UART1, TSIF0,and GPIO.URXD1 / IPD When UART1 UART functionalmuxing isselected(PINMUX1.UART1CTL = 0x)TS0_DIN7/ Y18 I/O/Z DV DD33 and TSIF0 serialinputisnot enabled(PINMUX0.PTSIMUX ≠ 11),thispinisGP[23] UART1 receivedata,URXD1 (I). UTXD1 / Thispinismultiplexedbetween UART1, TSIF0,and GPIO. URCTX1/ IPD When UART1 UART functionalmuxing isselected(PINMUX1.UART1CTL = 0x)AB19 I/O/ZTS0_DOUT7/ DV DD33 and TSIF0 serialoutputisnot enabled(PINMUX0.PTSIMUX ≠ 11),thispinis GP[24] UART1 transmitdata,UTXD1 (O/Z). Thispinismultiplexedbetween UART1, TSIF0,and GPIO.URTS1 /UIRTX1/ IPU When UART1 UART withflowcontrolmuxing isselected(PINMUX1.UART1CTL =TS0_WAITO/ AA18 I/O/Z DV DD33 00)and TSIF0 inputisnot enabled(PINMUX0.PTSIMUX ≠ 0x),thispinisUART1GP[25] request-to-send,URTS1 (O/Z). Thispinismultiplexedbetween UART1, TSIF0,and GPIO.UCTS1 /USD1 IPU When UART1 UART withflowcontrolmuxing isselected(PINMUX1.UART1CTL =TS0_EN_WAITO/ Y17 I/O/Z DV DD33 00)and TSIF0 inputisnot enabled(PINMUX0.PTSIMUX ≠ 0x),thispinisUART1GP[26] clear-to-send,UCTS1 (I). UART1 WITHOUT FLOW CONTROL (PINMUX1.UART1CTL = 01) Thispinismultiplexedbetween UART1, TSIF0,and GPIO.URXD1 / IPD When UART1 UART functionalmuxing isselected(PINMUX1.UART1CTL = 0x)TS0_DIN7/ Y18 I/O/Z DV DD33 and TSIF0 serialinputisnot enabled(PINMUX0.PTSIMUX ≠ 11),thispinisGP[23] UART1 receivedata,URXD1 (I). UTXD1 / Thispinismultiplexedbetween UART1, TSIF0,and GPIO. URCTX1/ IPD When UART1 UART functionalmuxing isselected(PINMUX1.UART1CTL = 0x)AB19 I/O/ZTS0_DOUT7/ DV DD33 and TSIF0 serialoutputisnot enabled(PINMUX0.PTSIMUX ≠ 11),thispinis GP[24] UART1 transmitdata,UTXD1 (O/Z). UART1 IrDA/CIRFUNCTION (PINMUX1.UART1CTL = 10) Thispinismultiplexedbetween UART1, TSIF0,and GPIO.URXD1 / IPD When UART1 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART1CTL = 10)TS0_DIN7/ Y18 I/O/Z DV DD33 and TSIF0 serialinputisnot enabled(PINMUX0.PTSIMUX ≠ 11),thispinisGP[23] UART1 receivedata,URXD1 (I). Thispinismultiplexedbetween UART1, TSIF0,and GPIO.UTXD1/ URCTX1 / IPD When UART1 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART1CTL = 10)TS0_DOUT7/ AB19 I/O/Z DV DD33 and TSIF0 serialoutputisnot enabled(PINMUX0.PTSOMUX ≠ 11),thispinisGP[24] UART1 CIR transmitdata,URCTX1 (O/Z). Thispinismultiplexedbetween UART1, TSIF0,and GPIO.URTS1/ UIRTX1 / IPU When UART1 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART1CTL = 10)TS0_WAITO/ AA18 I/O/Z DV DD33 and TSIF0 inputisnot enabled(PINMUX0.PTSIMUX = 0x),thispinisUART1 IrDAGP[25] transmitdata,UIRTX1 (O/Z). Thispinismultiplexedbetween UART1, TSIF0,and GPIO.UCTS1/ USD1 / IPU When UART1 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART1CTL = 10)TS0_EN_WAITO/ Y17 I/O/Z DV DD33 and TSIF0 inputisnot enabled(PINMUX0.PTSIMUX = 0x),thispinisUART1 IrDAGP[26] tranceivercontrol,USD1 (O/Z). (1) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (2) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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3.7.21 UART2

Table3-25.UART2 TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. UART2 WITH FLOW CONTROL (PINMUX1.UART2CTL = 00) ActualUART2 pinfunctionsaredeterminedby thePINMUX0 and PINMUX1 registerbitsettings.For more details,see Section4.7.3,Pin Multiplexing. URXD2 / Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0. CRG1_VCXI/ IPD When UART2 UART functionalmuxing isselected(PINMUX1.UART2CTL = 0x)AB20 I/O/ZGP[39]/ DV DD33 and CRGEN0/1 arenot enabled(PINMUX0.CRGMUX ≠ x01,110),thispinis CRG0_VCXI UART2 receivedata,URXD2 (I). UTXD2 / Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0.URCTX2/ IPD When UART2 UART functionalmuxing isselected(PINMUX1.UART2CTL = 0x)CRG1_PO/ AA19 I/O/Z DV DD33 and CRGEN0/1 arenot enabled(PINMUX0.CRGMUX ≠ x01,110),thispinisGP[40]/ UART2 transmitdata,UTXD2 (O/Z).CRG0_PO Thispinismultiplexedbetween UART2, TSIF0,and GPIO.URTS2 /UIRTX2/ IPU When UART2 UART withflowcontrolmuxing isselected(PINMUX1.UART2CTL =TS0_PSTIN/ AC20 I/O/Z DV DD33 00)and TSIF0 inputisnot enabled(PINMUX0.PTSIMUX = 0x),thispinisUART2GP[41] request-to-send,URTS2 (O/Z). UCTS2 /USD2/ Thispinismultiplexedbetween UART2, CRGEN0, GPIO, and TSIF1. CRG0_VCXI/ IPU When UART2 UART withflowcontrolmuxing isselected(PINMUX1.UART2CTL =AC21 I/O/ZGP[42]/ DV DD33 00)and TSIF1 outputisnot enabled(PINMUX0.PTSOMUX = 0x),thispinis TS1_PSTO UART2 clear-to-send,UCTS2 (I). UART2 WITHOUT FLOW CONTROL (PINMUX1.UART2CTL = 01) URXD2 / Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0. CRG1_VCXI/ IPD When UART2 UART functionalmuxing isselected(PINMUX1.UART2CTL = 0x)AB20 I/O/ZGP[39]/ DV DD33 and CRGEN0/1 arenot enabled(PINMUX0.CRGMUX ≠ x01,110),thispinis CRG0_VCXI UART2 receivedata,URXD2 (I). UTXD2 / Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0.URCTX2/ IPD When UART2 UART functionalmuxing isselected(PINMUX1.UART2CTL = 0x)CRG1_PO/ AA19 I/O/Z DV DD33 and CRGEN0/1 arenot enabled(PINMUX0.CRGMUX ≠ x01,110),thispinisGP[40]/ UART2 transmitdata,UTXD2 (O/Z).CRG0_PO UART2 IrDA/CIRFUNCTION (PINMUX1.UART2CTL = 10) URXD2 / Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0. CRG1_VCXI/ IPD When UART2 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART2CTL = 10)AB20 I/O/ZGP[39]/ DV DD33 and CRGEN0/1 arenot enabled(PINMUX0.CRGMUX ≠ x01,110),thispinis CRG0_VCXI UART2 receivedata,URXD2 (I). UTXD2/ URCTX2 / Thispinismultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0. CRG1_PO/ IPD When UART2 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART2CTL = 10)AA19 I/O/ZGP[40]/ DV DD33 and CRGEN0/1 arenot enabled(PINMUX0.CRGMUX ≠ x01,110),thispinisthe CRG0_PO UART2 CIR transmitdata,URCTX2 (O/Z). Thispinismultiplexedbetween UART2, TSIF0,and GPIO.URTS2/ UIRTX2 / IPU When UART2 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART2CTL = 10)TS0_PSTIN/ AC20 I/O/Z DV DD33 and TSIF0 inputisnot enabled(PINMUX0.PTSIMUX = 0x),thispinisUART2 IrDAGP[41] transmitdata,UIRTX2 (O/Z). UCTS2/ USD2 / Thispinismultiplexedbetween UART2, CRGEN0, GPIO, and TSIF1. CRG0_VCXI/ IPU When UART2 IrDA/CIRfunctionalmuxing isselected(PINMUX1.UART2CTL = 10)AC21 I/O/ZGP[42]/ DV DD33 and CRGEN0 on TSIF0 outputisnot enabled(PINMUX0.TSSOMUX = 0x),this TS1_PSTO pinisUART2 IrDAtranceivercontrol,USD2 (O/Z). (1) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (2) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 65 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.22 Pulse-WidthModulation(PWM)

Table3-26.PWM TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. PWM0 Thispinismultiplexedbetween PWM0, CRGEN0, and TSIF1.PWM0 / – When not overriddenby CRGEN orTSIF1 outputmuxing (PINMUX0.CRGMUX ≠CRG0_PO/ W17 O/Z DV DD33 10x and PINMUX0.TSSOMUX ≠ 11),thispinisthepulsewidthmodulation0 output,TS1_ENAO PWM0 (O/Z). PWM1 Thispinismultiplexedbetween PWM1 and TSIF1.PWM1 / –W18 O/Z When not overriddenby TSIF1 outputmuxing (PINMUX0.TSSOMUX ≠ 11),thispinTS1_DOUT DV DD33 isthepulsewidthmodulation1 output,PWM1 (O/Z). (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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3.7.23 Timers (Timer0,Timer 1,and Timer 2)

Table3-27.Timer 0,Timer 1,and Timer 2 TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. Timer 0 IPD Timer0lowerinput.ThispinistheTimer0inputfor64-mode operation.For32-bitTINP0L Y7 I/O/Z DV DD33 timeroperation,thispinistheinputfortheTimer0lower32-bitcounter. IPD Timer0upperinput.For32-bittimeroperation,thispinistheinputfortheTimer0TINP0U AA6 I/O/Z DV DD33 upper32-bitcounter.Not used forTimer064-mode operation. IPD Timer0loweroutput.ThispinistheTimer0outputfor64-mode operation.For32-bitTOUT0L W8 I/O/Z DV DD33 timeroperation,thispinistheoutputfortheTimer0lower32-bitcounter. IPD Timer0upperoutput.For32-bittimeroperation,thispinistheoutputfortheTimer0TOUT0U W7 I/O/Z DV DD33 upper32-bitcounter.Not used forTimer064-mode operation. Timer 1 IPD Timer1lowerinput.ThispinistheTimer1inputfor64-mode operation.For32-bitTINP1L Y6 I/O/Z DV DD33 timeroperation,thispinistheinputfortheTimer1lower32-bitcounter. IPD Timer1loweroutput.ThispinistheTimer1outputfor64-mode operation.For32-bitTOUT1L AA5 I/O/Z DV DD33 timeroperation,thispinistheoutputfortheTimer1lower32-bitcounter. IPD Timer1upperoutput.For32-bittimeroperation,thispinistheoutputfortheTimer1TOUT1U AB4 I/O/Z DV DD33 upper32-bitcounter.Not used forTimer164-mode operation. WATCHDOG TIMER (Timer2) IPDTOUT2 Y5 I/O/Z Watchdog timeroutput.DV DD33 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 67 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.24 ATA

Table3-28.ATA TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. ATA PCI,HPI,EMIFA, and ATA PinMuxing. PCI_CBE0/ IPU Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.ATA_CS0 / F4 I/O/Z DV DD33 When ATA isenabled,thispinisATA chipselect0 output,ATA_CS0 (O/Z).GP[33]/EM_A[18] PCI_CBE1/ IPU Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.ATA_CS1 / C2 I/O/Z DV DD33 When ATA isenabled,thispinisATA chipselect1 output,ATA_CS1 (O/Z).GP[32]/EM_A[19] PCI_RSV4/ DIOW / IPU Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.A11 I/O/ZGP[20]/EM_WAIT4 DV DD33 When ATA isenabled,thispinistheATA writestrobeoutput,DIOW (O/Z). PCI_RSV3/ DIOR / IPU Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.E10 I/O/ZGP[19]/EM_WAIT5 DV DD33 When ATA isenabled,thispinistheATA readstrobeoutput,DIOR (O/Z). PCI_RSV5/IORDY / IPU Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.D11 I/O/ZGP[21]/EM_WAIT3 DV DD33 When ATA isenabled,thispinisATA I/Oready,IORDY (I). PCI_RST/ IPD Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.DA2 / C10 I/O/Z DV DD33 When ATA isenabled,thispinisATA addressbit2,DA2 (O/Z).GP[13]/EM_A[22] PCI_RSV0/DA1 / IPD Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.A9 I/O/ZGP[16]/EM_A[21] DV DD33 When ATA isenabled,thispinisATA addressbit1,DA1 (O/Z). PCI_RSV1/DA0 / IPD Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.E9 I/O/ZGP[17]/EM_A[20] DV DD33 When ATA isenabled,thispinisATA addressbit0,DA0 (O/Z). PCI_RSV2/INTRQ / IPD Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.B10 I/O/ZGP[18]/EM_RSV0 DV DD33 When ATA isenabled,thispinistheATA interruptrequestinput,INTRQ (I). PCI_REQ/ IPU Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.DMARQ / B9 I/O/Z DV DD33 When ATA isenabled,thispinistheATA DMA requestinput,DMARQ (I).GP[11]/EM_CS5 PCI_GNT/ Thispinismultiplexedbetween PCI,ATA, GPIO, and EMIFA.IPUDMACK / D10 I/O/Z When ATA isenabled,thispinistheATA DMA acknowledgeoutput,DMACKDV DD33GP[12]/EM_CS4 (O/Z). PCI_IDSEL/ Thispinismultiplexedbetween PCI,ATA, and EMIFA.IPUHDDIR / E8 I/O/Z When ATA isenabled,thispinisthedatadirectionindicatorforexternalbufferDV DD33EM_R/ W control,HDDIR (O/Z). (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-28.ATA TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_AD31/ DD15 / A8 HD31/ EM_A[15] PCI_AD30/ DD14 / C9 HD30/EM_A[14] PCI_AD29/ DD13 / B8 HD29/EM_A[13] PCI_AD28/ DD12 / D9 HD28/EM_A[12] PCI_AD27/ DD11 / A6 HD27/EM_A[11] PCI_AD26/ DD10 / C8 HD26/EM_A[10] PCI_AD25/ DD9 / B6 HD25/EM_A[9] PCI_AD24/ DD8 / D8 These pinsaremultiplexedbetween PCI,ATA, HPI,and EMIFA.HD24/EM_A[8] IPDI/O/Z When ATA isenabled,thesepinsaretheATA 16-bitbidirectionaldatabus,DV DD33PCI_AD23/ DD15:0. DD7 / B5 HD23/EM_A[7] PCI_AD22/ DD6 / C7 HD22/EM_A[6] PCI_AD21/ DD5 / C5 HD21/EM_A[5] PCI_AD20/ DD4 / D7 HD20/EM_A[4] PCI_AD19/ DD3 / A4 HD19/EM_A[3] PCI_AD18/ DD2 / E7 HD18/EM_A[2] PCI_AD17/ DD1 / B4 HD17/EM_A[1] PCI_AD16/ DD0 / C6 HD16/EM_A[0] Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 69 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.25 GeneralPurpose Input/Output(GPIO)

Table3-29.GeneralPurpose Input/Output(GPIO)TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. GPIO The DM6467 devicedoes not supportGP[47:43],GP[35:34],GP[31:27],GP[15:14],and GP[9] signals(notpinned out). GP[7:0]pinshave dedicatedARM926 and DSP interrupts. When PCI isused,GP[19:16]pinsarereserved. IPDGP[0] W5 I/O/Z GP0.Thispinisgeneral-purposeinput/output0.DV DD33 IPDGP[1] V5 I/O/Z GP1.Thispinisgeneral-purposeinput/output1.DV DD33 GP[2]/ IPD Thispinismultiplexedbetween GPIO and theaudioclockselector.AA4 I/O/ZAUDIO_CLK1 DV DD33 When audioclock1 isdisabled(PINMUX0.AUDCK1 = 0),thispinisGP2. GP[3]/ IPD Thispinismultiplexedbetween GPIO and theaudioclockselector.AB3 I/O/ZAUDIO_CLK0 DV DD33 When audioclock0 isdisabled(PINMUX0.AUDCK0 = 0),thispinisGP3. Thispinismultiplexedbetween GPIO and theTSIF clockselector.GP[4]/ IPDAC3 I/O/Z When theSTC sourceclockinputisdisabled(PINMUX0.STCCK = 0),thispinisSTC_CLKIN DV DD33 GP4. IPDGP[5] B11 I/O/Z ThispinisGP5.DV DD33 Thispinismultiplexedbetween GPIO and SmartReflex(VoltageAdjust)Control GP[6]/ IPD Outputs.E11 I/O/ZCVDDADJ0 DV DD33 When thecorevoltageadjustfunctionisdisabled(VP_DOUT7/VADJEN = 0 at reset),thispinisGP6. Thispinismultiplexedbetween GPIO and SmartReflex(VoltageAdjust)Control GP[7]/ IPD Outputs.A12 I/O/ZCVDDADJ1 DV DD33 When thecorevoltageadjustfunctionisdisabled(VP_DOUT7/VADJEN = 0 at reset),thispinisGP7. Thispinismultiplexedbetween UART0, GPIO, and TSIF1. URIN0/GP[8]/ IPD When UART0 UART withmodem functionalmuxing isnot selectedY11 I/O/ZTS1_WAITIN DV DD33 (PINMUX1.UART0CTL = 00)and TSIF1 outputon UART/PWM muxing isnot enabled(PINMUX0.TSSOMUX ≠ 11),thispinisGP8. GP[9] n/a – – GP[9]isnot pinnedouton thisdevice. IPU Thispinismultiplexedbetween PCI and GPIO.PCI_CLK/GP[10] A10 I/O/Z DV DD33 When PCI isdisabled(PINMUX0.PCIEN = 0),thispinisGP10. GP[14:15] n/a – – GP[14:15]arenot pinnedouton thisdevice. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-29.GeneralPurpose Input/Output(GPIO)TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. PCI_RSV0/DA1/ IPDGP[16]/ A9 I/O/Z DV DD33EM_A[21] PCI_RSV1/DA0/ IPDE9 I/O/ZGP[17]/EM_A[20] DV DD33 These pinsaremultiplexedbetween PCI,ATA, GPIO, and EMIFA. When 32-bitHPI mode isenabled(PINMUX0.PCIEN = 0,PINMUX0.HPIEN = 1,PCI_RSV2/ PINMUX0.ATAEN = 0),thesepinsareGP16:19.When PCI mode isenabledINTRQ/ IPDB10 I/O/Z (PINMUX0.PCIEN = 1),thesepinsarereserved.GP[18]/ DV DD33 EM_RSV0 PCI_RSV3/DIOR/ IPUGP[19]/ E10 I/O/Z DV DD33EM_WAIT5 PCI_RSV4/ DIOW/ IPUA11 I/O/ZGP[20]/ DV DD33 These pinsaremultiplexedbetween PCI,ATA, GPIO, and EMIFA.EM_WAIT4 When 32-bitHPI mode isenabled(PINMUX0.PCIEN = 0,PINMUX0.HPIEN = 1, PCI_RSV5/ PINMUX0.ATAEN = 0),thesepinsareGP20:21. IORDY/ IPUD11 I/O/ZGP[21]/ DV DD33 EM_WAIT3 USB_DRVVBUS/ IPD Thispinismultiplexedbetween USB and GPIO.B18 I/O/ZGP[22] DV DD33 When not used forUSB (PINMUX0.VBUSDIS = 1),thispinisGP22. URXD1/ Thispinismultiplexedbetween UART1, TSIF0,and GPIO.IPDTS0_DIN7/ Y18 I/O/Z When UART1 GPIO muxing isselected(PINMUX1.UART1CTL = 11)and TSIF0DV DD33GP[23] serialinputisnot enabled(PINMUX0.PTSIMUX ≠ 11),thispinisGP23. UTXD1/ Thispinismultiplexedbetween UART1, TSIF0,and GPIO.URCTX1/ IPDAB19 I/O/Z When UART1 GPIO muxing isselected(PINMUX1. UART1CTL = 11)and TSIF0TS0_DOUT7/ DV DD33 serialinputisnot enabled(PINMUX0.PTSIMUX ≠ 11),thispinisGP24.GP[24] URTS1/ UIRTX1/ IPDAA18 I/O/ZTS0_WAITO/ DV DD33 These pinsaremultiplexedbetween UART1, TSIF0,and GPIO. GP[25] When UART1 GPIO muxing isselected(PINMUX1.UART1CTL = 11)and TSIF0 inputisnot enabled(PINMUX0.PTSIMUX = 0x),thesepinsareGP25:26.UCTS1/USD1/ IPUTS0_EN_WAITO/ Y17 I/O/Z DV DD33GP[26] GP[27:31] n/a – – GP[27:31]arenot pinnedouton thisdevice. PCI_CBE1/ ATA_CS1/ IPUC2 I/O/ZGP[32]/ DV DD33 These pinsaremultiplexedbetween PCI,ATA, GPIO, and EMIFA.EM_A[19] When 32-bitHPI mode isenabled(PINMUX0.PCIEN = 0,PINMUX0.HPIEN = 1, PCI_CBE0/ PINMUX0.ATAEN = 0),thesepinsareGP32:33. ATA_CS0/ IPUF4 I/O/ZGP[33]/ DV DD33 EM_A[18] GP[34:35] n/a – – GP[34:35]arenot pinnedouton thisdevice. UDTR0/ IPUTS0_ENAO/ Y12 I/O/Z DV DD33GP[36] These pinsaremultiplexedbetween UART0, TSIF0,and GPIO.UDSR0/ IPU When UART0 UART withmodem functionalmuxing isnot selectedTS0_PSTO/ AB11 I/O/Z DV DD33 (PINMUX1.UART0CTL ≠ 00)and TSIF0 outputmuxing isnot enabledGP[37] (PINMUX0.PTSOMUX ≠ 1x),thesepinsareGP36:38. UDCD0/ IPUTS0_WAITIN/ AA11 I/O/Z DV DD33GP[38] Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 71 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-29.GeneralPurpose Input/Output(GPIO)TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. URXD2/ CRG1_VCXI/ IPDAB20 I/O/ZGP[39]/ DV DD33 These pinsaremultiplexedbetween UART2, CRGEN1, GPIO, and CRGEN0. CRG0_VCXI When UART2 UART GPIO muxing isselected(PINMUX1.UART2CTL = 11)and CRGEN0/1 arenot enabled(PINMUX0.CRGMUX ≠ x01,110),thesepinsareUTXD2/URCTX2/ GP39:40.CRG1_PO/ IPDAA19 I/O/ZGP[40]/ DV DD33 CRG0_PO Thispinismultiplexedbetween UART2, TSIF0,and GPIO.URTS2/UIRTX2/ IPU When UART2 UART withoutflowcontrolorGPIO muxing isselectedTS0_PSTIN/ AC20 I/O/Z DV DD33 (PINMUX1.UART2CTL = x1)and TSIF0 inputisnot enabledGP[41] (PINMUX0.PTSIMUX = 0x),thispinisGP41. GP[43:47] n/a – – GP[43:47]arenot pinnedouton thisdevice.

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3.7.26 Reserved

Table3-30.Reserved TerminalFunctions SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. RESERVED RSV1 A1 Reserved.Forproperdeviceoperation,thispinmust be tieddirectlytoVSS . RSV2 A2 Reserved.Forproperdeviceoperation,thispinmust be tieddirectlytoVSS . RSV3 A22 Reserved.Forproperdeviceoperation,thispinmust be tieddirectlytoVSS . RSV4 A23 Reserved.(Leaveunconnected,do not connecttopower orground.) RSV5 D14 Reserved.(Leaveunconnected,do not connecttopower orground.) RSV6 F17 Reserved.Forproperdeviceoperation,thispinmust be tieddirectlytoCV DD . RSV7 G16 Reserved.Forproperdeviceoperation,thispinmust be tieddirectlytoCV DD . (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 73 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.7.27 Supply

Table3-31.Supply TerminalFunctions SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. SUPPLY VOLTAGE PINS F10 F11 F12 F13 F14 F15 F16 3.3-VI/OsupplyvoltageDV DD33 M3 S (seethePower-SupplyDecouplingsectionofthisdatamanual) V17 W10 W11 W12 W13 W14 W15 W16 AA12 B20 E21 G17 G19 H17 1.8-VDDR2 I/OsupplyvoltageDV DDR2 S (seethePower-SupplyDecouplingsectionofthisdatamanual)J17 K17 K21 P21 R17 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-31.Supply TerminalFunctions(continued) SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. R18 T18 T19 1.8-VDDR2 I/OsupplyvoltageDV DDR2 S (seethePower-SupplyDecouplingsectionofthisdatamanual)U19 W21 AA20 G10 G11 G12 G13 G14 G15 H14 H15 H16 J8 1.20-Vcoresupplyvoltage(-594,-594A,-729devices) (seethePower-SupplyDecouplingsectionofthisdatamanual)J9 SmartReflex:when selected(VP_DOUT7/VADJEN = 1 atreset),theJ10 GP[7]/CVDDADJ1 and GP[6]/CVDDADJ0 pinsfunctionas SmartReflexControlJ11 Outputstotheadjustablecorepower supply.Formore detailedinformationon CV DD J13 S SmartReflex,see theSection7.3.6,SmartReflex(VoltageScaling). J14 1.2-Vcoresupplyvoltage(-594V,-594AV only)[GP[7]/CVDDADJ1 andJ15 GP[6]/CVDDADJ0 = 00] J16 1.05-Vcoresupplyvoltage(-594V,-594AV only)[GP[7]/CVDDADJ1 and GP[6]/CVDDADJ0 = 11]K8 K10 K11 K13 K14 K15 K16 P10 P11 P13 P14 P15 Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 75 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-31.Supply TerminalFunctions(continued) SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. R10 R11 R13 R14 R15 T10 1.20-Vcoresupplyvoltage(-594,-594A,-729devices)T11 (seethePower-SupplyDecouplingsectionofthisdatamanual) T13 SmartReflex:when selected(VP_DOUT7/VADJEN = 1 atreset),the T14 GP[7]/CVDDADJ1 and GP[6]/CVDDADJ0 pinsfunctionas SmartReflexControl Outputstotheadjustablecorepower supply.Formore detailedinformationonT15 CV DD S SmartReflex,see theSection7.3.6,SmartReflex(VoltageScaling). U9 1.2-Vcoresupplyvoltage(-594V,-594AV only)[GP[7]/CVDDADJ1 and U10 GP[6]/CVDDADJ0 = 00] 1.05-Vcoresupplyvoltage(-594V,-594AV only)[GP[7]/CVDDADJ1 andU14 GP[6]/CVDDADJ0 = 11] U15 U16 V10 V11 V12 V13 V14 V15 V16

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3.7.28 Ground

Table3-32.Ground TerminalFunctions SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. GROUND PINS A14 A18 A21 B19 B23 C19 D19 E19 E22 F19 G18 H10 VSS GND Ground pins H11 H12 H13 H18 H19 J12 J18 K12 K18 K22 L10 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 77 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table3-32.Ground TerminalFunctions(continued) SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. L11 L12 L13 L14 L15 L16 L17 L18 M10 M11 M12 M13 M14 M15 M16 M17 M18 VSS GND Ground pins N10 N11 N12 N13 N14 N15 N16 N17 N18 P12 P16 P17 P18 P22 R12 R16

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table3-32.Ground TerminalFunctions(continued) SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. T12 T16 T17 U11 U12 U13 U17 U18 V18 VSS GND Ground Pins V19 W19 W22 Y19 AB1 AB12 AB21 AB23 AC1 AC2 AC22 AC23 Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 79 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.8 Device Support

3.8.1 Development Support

TIoffersan extensivelineofdevelopmenttoolsfortheTMS320DM646x DMSoC platform,includingtools to evaluatethe performanceof the processors,generatecode,developalgorithmimplementations,and fullyintegrateand debug softwareand hardware modules. The tool'ssupport documentationis electronicallyavailablewithintheCode Composer Studio™ IntegratedDevelopmentEnvironment(IDE). The followingproductssupportdevelopmentofTMS320DM646x SoC-based applications: SoftwareDevelopment Tools: Code Composer Studio™ IntegratedDevelopmentEnvironment(IDE):includingEditor C/C++/AssemblyCode Generation,and Debug plusadditionaldevelopmenttools Scalable,Real-TimeFoundationSoftware(DSP/BIOS™ ),which providesthe basicrun-timetarget softwareneeded tosupportany SoC application. Hardware Development Tools: ExtendedDevelopmentSystem (XDS ™ )Emulator For a completelistingofdevelopment-supporttoolsfortheTMS320DM644x DMSoC platform,visitthe Texas Instrumentsweb siteon the Worldwide Web at http://www.ti.comuniformresourcelocator (URL).For informationon pricingand availability,contactthenearestTIfieldsalesofficeorauthorized distributor.

3.8.2 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall DSP devicesand supporttools.Each DSP commercialfamilymember has one ofthreeprefixes:TMX, TMP, orTMS (e.g.,TMX320DM6467CCUT7). Texas Instrumentsrecommends two ofthreepossibleprefix designatorsforitssupporttools:TMDX and TMDS. These prefixesrepresentevolutionarystages of product development from engineeringprototypes(TMX/TMDX) through fullyqualifiedproduction devices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatis not necessarilyrepresentativeof the finaldevice'selectrical specifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthas notcompleted qualityand reliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproduct that has not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-supporttoolsare shipped againstthe following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devicesand TMDS development-supporttoolshave been characterizedfully,and the qualityand reliabilityofthedevicehave been demonstratedfully.TI'sstandardwarrantyapplies.

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TMX = Experimental device TMS = Qualified device DEVICE FAMILY 320 = TMS320™ DSP family PACKAGE TYPE (A) C64x+™ DSP: DM6467 DEVICE DEVICE SPEED RANGE ( ) Blank = 594-MHz DSP, 297-MHz ARM9 [Default] 7 = 729-MHz DSP, 364.5-MHz ARM9 , 297-MHz DDR2 , 310.5-MHz DDR2 TEMPERATURE RANGE AC SILICON REVISION V Blank = A = -4 0° C to 85° C, Commercial Temperature 0° C to 105° C, Extended Temperature [-594 MHz only] D = -40° C to 85° C, Industrial Temperature [-729 MHz only] VOLTAGE SCALE ADJUSTMENT Blank = V = SmartReflex [-594 MHz only] SmartReflex Not Supported TMX TMS CUT = 529-pin plastic BGA, with Pb-Free die bump and solder ball Blank = C = Revision 1.1 Revision 3.0 Blank = C = Revision 1.0 A = Revision 1.1 Revision 3.0 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Predictionsshow thatprototypedevices(TMX or TMP) have a greaterfailureratethan the standard productiondevices.Texas Instrumentsrecommends thatthesedevicesnot be used inany production systembecause theirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobe used. TI devicenomenclaturealso includesa suffixwiththe devicefamilyname. This suffixindicatesthe package type (forexample, CUT), the temperaturerange (forexample, "Blank"is the commercial temperaturerange),and thedevicespeed range inmegahertz(forexample,"Blank"isthedefault[594- MHz DSP, 297-MHz ARM9]). Figure3-8 providesa legendforreadingthe completedevicename forany TMS320DM646x DMSoC platformmember. A. BGA = BallGridArray B. Foractualdevicepartnumbers (P/Ns)and orderinginformation,see theTIwebsite(http://www.ti.com). Figure3-8.Device Nomenclature(B) Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 81 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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3.9 Documentation Support

3.9.1 RelatedDocumentation From Texas Instruments

The followingdocuments describetheTMS320DM646x DigitalMedia System-on-Chip(DMSoC). Copies of thesedocuments are availableon the Internetat www.ti.com.Tip:Enterthe literaturenumber inthe searchbox providedatwww.ti.com. The currentdocumentationthatdescribestheDM646x DMSoC, relatedperipherals,and othertechnical collateral,isavailableintheC6000 DSP productfolderat:www.ti.com/c6000. SPRUEP8 TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describesthe digitalsignal processor(DSP) subsystemintheTMS320DM646x DigitalMedia System-on-Chip(DMSoC). SPRUEP9 TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARM subsystem in the TMS320DM646x DigitalMedia System-on-Chip(DMSoC). The ARM subsystem isdesignedto givethe ARM926EJ-S (ARM9) master controlof the device.In general,the ARM isresponsibleforconfigurationand controlof the device;includingthe DSP subsystemand a majorityoftheperipheralsand externalmemories. SPRUEQ0 TMS320DM646x DMSoC PeripheralsOverview Reference Guide. Providesan overview and brieflydescribestheperipheralsavailableon theTMS320DM646x DigitalMedia System- on-Chip(DMSoC). SPRAA84 TMS320C64x to TMS320C64x+ CPU MigrationGuide.DescribesmigratingfromtheTexas InstrumentsTMS320C64x digitalsignalprocessor(DSP) to the TMS320C64x+ DSP. The objectiveofthisdocument istoindicatedifferencesbetween thetwo cores.Functionalityin thedevicesthatisidenticalisnotincluded. SPRU732 TMS320C64x/C64x+ DSP CPU and InstructionSet Reference Guide.DescribestheCPU architecture,pipeline,instructionset,and interruptsfortheTMS320C64x and TMS320C64x+ digitalsignalprocessors(DSPs) of the TMS320C6000 DSP family.The C64x/C64x+ DSP generationcomprisesfixed-pointdevicesintheC6000 DSP platform.The C64x+ DSP isan enhancement oftheC64x DSP withadded functionalityand an expanded instructionset. SPRU871 TMS320C64x+ DSP Megamodule Reference Guide. Describesthe TMS320C64x+ digital signalprocessor(DSP) megamodule. Includedisa discussionon theinternaldirectmemory access (IDMA) controller,the interruptcontroller,the power-down controller,memory protection,bandwidthmanagement, and thememory and cache. SPRAAV0 Understanding TI'sPCB Routing Rule-Based DDR Timing SpecificationApplication Report Thisapplicationreportdescribestheway theDDR high-speedtimingrequirements are now goingto be communicated to system designers.The system designeruses this informationto evaluatewhether timingspecificationsare met and can be expected to operatereliably. SPRAAZ2 EnablingSmartReflexon the TMS320DM6467 ApplicationReport Thisapplicationreport describesthe basicconceptsof SmartReflex™ technologyimplemented in the DM6467 device.The goalforimplementingthistechnologyand the expectedbenefitsare detailed, and a referencedesignoftheSmartReflexfeatureisintroduced.

3.10 Community Resources

The followinglinksconnectto TI community resources.Linkedcontentsare provided"AS IS"by the respectivecontributors.They do notconstituteTI specificationsand do notnecessarilyreflectTI'sviews; see TI'sTerms ofUse. TIE2E Community TI's Engineer-to-Engineer(E2E) Community. Created to fostercollaboration among engineers.Ate2e.ti.com,you can ask questions,shareknowledge,exploreideasand helpsolveproblemswithfellowengineers.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 TIEmbedded Processors Wiki Texas InstrumentsEmbedded Processors Wiki.Establishedto help developersget startedwithEmbedded Processorsfrom Texas Instrumentsand to foster innovationand growthofgeneralknowledge aboutthehardwareand softwaresurrounding thesedevices. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOverview 83 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4 Device Configurations

4.1 System Module Registers

The system module includesstatusand controlregistersforconfigurationofthedevice.Briefdescriptions of the variousregistersare shown in Table 4-1. System Module registersrequiredfor device configurationsarediscussedinthefollowingsections. Table4-1.System Module RegisterMemory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C4 0000 PINMUX0 PinMultiplexingControl0 (seeSection4.7.2.1,PINMUX0 Register). 0x01C4 0004 PINMUX1 PinMultiplexingControl1 (seeSection4.7.2.2,PINMUX1 Register). 0x01C4 0008 DSPBOOTADDR DSP BootAddress.Decoded by bootloadersoftwareforhostboots. (See Section4.4.2.1,DSPBOOTADDR Register.) 0x01C4 000C SUSPSRC EmulatorSuspend Source(seeSection4.7.3.13,EmulationControl). 0x01C4 0010 BOOTSTAT BootStatus(seeSection4.4.2.2,BOOTSTAT Register). 0x01C4 0014 BOOTCFG DeviceBootConfiguration(seeSection4.4.2.3,BOOTCFG Register). 0x01C4 0018 SMTREFLEX SmartReflexStatus(seeFigure7-7,SMTREFLEX StatusRegister). [VoltageScaleAdjustment(V)partsonly] 0x01C4 001C -0x01C4 0020 – Reserved 0x01C4 0024 ARMBOOT ARM926 BootControl(seeSection4.4.2.4,ARMBOOT Register). 0x01C4 0028 JTAGID DeviceID Number [seeSection7.29.1,JTAG ID (JTAGID)Register Description(s)]. 0x01C4 002C – Reserved 0x01C4 0030 HPICTL HPI Control(seeSection4.6.2.1,HPICTL Register). 0x01C4 0034 USBCTL USB Control(seeSection4.6.2.2,USBCTL Register). 0x01C4 0038 VIDCLKCTL VideoClockControl(seeSection4.3.2.1,VideoClockControl). 0x01C4 003C MSTPRI0 Bus MasterPriorityControl0 (seeSection4.6.1,SwitchCentral Resource(SCR) Bus Priorities). 0x01C4 0040 MSTPRI1 Bus MasterPriorityControl1 (seeSection4.6.1,SwitchCentral Resource(SCR) Bus Priorities). 0x01C4 0044 MSTPRI2 Bus MasterPriorityControl2 (seeSection4.6.1,SwitchCentral Resource(SCR) Bus Priorities). 0x01C4 0048 VDD3P3V_PWDN VDD 3.3-VI/OPowerdown Control(seeSection4.2,Power Considerations). 0x01C4 004C – Reserved 0x01C4 0050 TSIFCTL TSIF ControlRegister(seeSection4.3.2.2,TSIF Control). 0x01C4 0054 PWMCTL PWM Control(seeSection4.6.2.3,PWM (TriggerSource)Control Register). 0x01C4 0058 EDMATCCFG EDMA TC Configuration(seeSection4.6.2.4,EDMATCCFG Register). 0x01C4 005C CLKCTL Oscillatorand OutputClockControl(seeSection4.3.3,Clockand OscillatorControl). 0x01C4 0060 DSPINT ARM toDSP InterruptStatus(seeSection4.7.3.12,ARM/DSP CommunicationsInterrupts). 0x01C4 0064 DSPINTSET ARM toDSP InterruptSet(seeSection4.7.3.12,ARM/DSP CommunicationsInterrupts). 0x01C4 0068 DSPINTCLR ARM toDSP InterruptClear(seeSection4.7.3.12,ARM/DSP CommunicationsInterrupts). 0x01C4 006C VSCLKDIS Videoand TSIF ClockDisable(seeSection4.3.2.3,Videoand TSIF ClockDisable). 0x01C4 0070 ARMINT DSP toARM InterruptStatus(seeSection4.7.3.12,ARM/DSP CommunicationsInterrupts). 0x01C4 0074 ARMINTSET DSP toARM InterruptSet(seeSection4.7.3.12,ARM/DSP CommunicationsInterrupts).

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-1.System Module RegisterMemory Map (continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C4 0078 ARMINTCLR DSP toARM InterruptClear(seeSection4.7.3.12,ARM/DSP CommunicationsInterrupts). 0x01C4 007C ARMWAIT ARM Memory WaitStateControl(seeSection4.4.2.5,ARMWAIT Register). 0x01C4 0080 -0x01C4 03FF – Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 85 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.2 Power Considerations

The DM6467 providesseveralmeans ofmanaging power consumption. As describedintheSection7.3.4,DM6467 Power and ClockDomains,theDM6467 has one singlepower domain— the“Always On ”power domain.Withinthispower domain,theDM6467 utilizeslocalclockgating viathePower and Sleep Controller(PSC) toachievepower savings.For more detailson thePSC, see Section7.3.5, Power and Sleep Controller(PSC) and the TMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). Some of the DM6467 peripheralssupportadditionalpower savingfeatures.For more detailson power saving features supported, see the peripheral-specificreference guides [listed/linkedin the TMS320DM646x DMSoC PeripheralsOverviewReferenceGuide (literaturenumber SPRUEQ0 ). Most DM6467 3.3-VI/Oscan be powered-down to reduce power consumption.The VDD3P3V_PWDN registerintheSystem Module (seeFigure4-1)isused toselectivelypower down unused 3.3-VI/Opins. Note:To save power,allotherI/Obuffersarepowered down by default.Beforeusingthesepins,theuser must programtheVDD3P3V_PWDN registertopower up thecorrespondingI/Obuffers. For a listofmultiplexedpinson thedeviceand thepinmux groupeach pinbelongsto,see Section4.7.3, PinMultiplexingDetails. Note: The VDD3P3V_PWDN registeronlycontrolsthe power to the I/Obuffers.The Power and Sleep Controller(PSC) determinestheclock/powerstateoftheperipheral. 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED USBV CLKOUT RSV SPI VLYNQ RESERVED GMII MII MCASP1 MCASP0 PCIHPI1 PCIHPI0 R-000 R/W-1 R/W-0 R-0 R/W-1 R/W-1 R-00 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO WDTIM TIM23 TIM01 PWM1 PWM0 UR2FC UR2DAT UR1FC UR1DAT UR0MDM UR0DF VPIF3 VPIF2 VPIF1 VPIF0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-1.VDD3P3V_PWDN Register[0x01C4 0048]

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-2.VDD3P3V_PWDN RegisterBitDescriptions BIT NAME DESCRIPTION 31:29 RESERVED Reserved.Read returns"0". USB_DRVVBUS Powerdown Control. 0 = I/Ocellspowered up.28 USBV 1 = I/Ocellspowered down. ThisbitcontrolstheUSB_DRVVBUS/GP[22] pin. CLKOUT0 Powerdown Control.27 CLKOUT ThisbitcontrolstheCLKOUT0 pin. 26 RSV Reserved.Read returns"0". SPI Powerdown Control.

25 SPI ThisbitcontrolsthesixSPI interfacepins:SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_SOMI, and

SPI_SIMO. VLYNQ Powerdown Control.

24 VLYNQ ThisbitcontrolsthetenVLYNQ interfacepins:VLYNQ_CLOCK, VLYNQ_SCRUN,

VLYNQ_TXD[3:0],and VLYNQ_RXD[3:0]. 23:22 RESERVED Reserved.Read returns"0". GMII Powerdown Control.

21 GMII Thisbitcontrolsthetenpinsused by GMII (Gigabit)only:RFTCLK, GMTCLK, MTXD[7:4],and

MRXD[7:4]. MIIPowerdown Control.

20 MII Thisbitcontrolsthe17 pinsused by (G)MII(10/100/1000)and MDIO interfaces:MTCLK,

MTXD[3:0],MTXEN, MCOL, MCRS, MRCLK, MRXD[3:0],MRXDV, MRXER, MDCLK, and MDIO. McASP1 Powerdown Control.19 MCASP1 ThisbitcontrolsthethreeMcASP1 pins:ACLKX1, AHCLKX1, and AXR1[0]. McASP0 Powerdown Control.

18 MCASP0 Thisbitcontrolsthe12 McASP0 pins:ACLKR0, AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0,

AXR0[3:0],AMUTE0, and AMUTEIN0. PCI/HPI/EMIFA/ATAPowerdown Control. Thisbitcontrolsthe28 pinsused by theATA orPCI\`,HPI,orEMIFA. These pinsinclude: PCI_RST/DA2/GP[13]/EM_A[22],PCI_IDSEL/HDDIR/EM_R/ W, PCI_REQ/DMARQ/GP[11]/ EM_CS5, PCI_GNT/ DMACK/GP[12]/EM_CS4,

17 PCIHPI1 PCI_CBE1/ATA_CS1/GP[32]/EM_A[19],PCI_CBE0/ATA_CS0/GP[33]/EM_A[18],

DIOW/GP[20]/EM_WAIT4/(RDY4/BSY4),IORDY/GP[21]/EM_WAIT3/(RDY3/BSY3), DIOR/GP[19]/EM_WAIT5/(RDY5/BSY5),DA1/GP[16]/EM_A[21],DA0/GP[17]/EM_A[20], INTRQ/GP[18]/RSV ,PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0] Defaultstopowered up forNOR boot. PCI/HPI/EMIFAPowerdown Control. Thisbitcontrolsthe28 pinsused by PCI,HPI,orEMIFA butnotsharedwithATA. These pins include:PCI_CLK/GP[10],PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/ HINT/EM_BA[0], PCI_IRDY/HRDY/EM_A[17]/(CLE),PCI_TRDY/HHWIL/EM_A[16]/(ALE),16 PCIHPI0 PCI_STOP/HCNTL0/ EM_WE, PCI_SERR/ HDS1/ EM_OE, PCI_PERR/ HCS/ EM_DQM1, PCI_PAR/HAS/EM_DQM0, PCI_INTA/EM_WAIT2/(RDY2/BSY2),PCI_CBE3/HR/ W/EM_CS3, PCI_CBE2/HDS2/ EM_CS2, PCI_AD[15:0]/HD[15:0]/EM_D[15:0] Defaultstopowered up forNOR boot. GPIO Powerdown Control.15 GPIO ThisbitcontrolstheeightGP[7:0]pins.Defaultstopowered up. WD TimerPowerdown Control.14 WDTIM ThisbitcontrolstheWD TimerpinTOUT2. Timer1Powerdown Control.13 TIM23 ThisbitcontrolsthethreeTimer1pinsTINP1L,TOUT1L, and TOUT1U. Timer0Powerdown Control.12 TIM01 ThisbitcontrolsthefourTimer0pinsTINP0L,TINP0U, TOUT0L, and TOUT0U. PWM1 Powerdown Control.11 PWM1 ThisbitcontrolsthePWM1/TS1_DOUT pin. PWM0 Powerdown Control.10 PWM0 ThisbitcontrolsthePWM0/CRG0_PO/TS1_ENAO pin. UART2 Flow ControlPowerdown Control.

9 UR2FC ThisbitcontrolstheURTS2/UIRTX2/TS0_PSTIN/GP[41] and

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table4-2.VDD3P3V_PWDN RegisterBitDescriptions(continued) BIT NAME DESCRIPTION UART2 Data Powerdown Control.

8 UR2DAT ThisbitcontrolstheURXD2/CRG1_VCXI/GP[39]/CRG0_VCXI and

UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO pins. UART1 Flow ControlPowerdown Control.

7 UR1FC ThisbitcontrolstheURTS1/UIRTX1/TS0_WAITO/GP[25] and

UCTS1/USD1/TS0_EN_WAITO/GP[26] pins. UART1 Data Powerdown Control.6 UR1DAT ThisbitcontrolstheURXD1/TS0_DIN7/GP[23] and UTXD1/URCTX1/TS0_DOUT7/GP[24] pins. UART0 Modem ControlPowerdown Control.

5 UR0MDM ThisbitcontrolstheUDTR0/TS0_ENAO/GP[36], UDSR0/TS0_PSTO/GP[37],

UDCD0/TS0_WAITIN/GP[38], and URIN0/GP[8]/TS1_WAITINpins. UART0 Data and Flow ControlPowerdown Control.

4 UR0DF ThisbitcontrolstheURXD0/TS1_DIN, UTXD0/URCTX0/TS1_PSTIN,

URTS0/UIRTX0/TS1_EN_WAITO, and UCTS0/USD0 pins. VPIF MSB OutputPowerdown Control.

3 VPIF3 ThisbitcontrolstheVP_DOUT[15:8]/TS1_xx,VP_CLKIN3/TS1_CLKO, and VP_CLKO3/TS0_CLKO

pins. VPIF LSB OutputPowerdown Control. 2 VPIF2 ThisbitcontrolstheVP_DOUT[7:0],VP_CLKIN2, and VP_CLKO2 pins.(VP_DOUT[7:0]areboot configurationinputs.) VPIF MSB InputPowerdown Control.1 VPIF1 ThisbitcontrolstheVP_DIN[15:8]/TS0_DIN[7:0]and VP_CLKIN1 pins. VPIF LSB InputPowerdown Control.

0 VPIF0 ThisbitcontrolstheVP_DIN[3:0]/TS0_DOUT[3:0],VP_DIN[7:4]/TS0_DOUT[7:4]/TS1_xx,and

VP_CLKIN0 pins.

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4.3 Clock Considerations

Globaldeviceand localperipheralclocksare controlledby thePLL Controllers(PLLC1 and PLLC2) and thePower and SleepController(PSC).Inaddition,theSystem Module VideoClockControl(VIDCLKCTL), TSIF Control(TSIFCTL),and Clockand OscillatorControl(CLKCTL) registersconfiguretheclocksources totheVPIF,TSIF,CRGEN peripherals,and theAuxiliaryOscillator. The selectedVideo,TSIF,and CRGEN module inputclocksaredisabledusingtheSystem Module Video Source Clock Disable(VSCLKDIS) register.Note: To ensure glitch-freeoperation,the clockshouldbe disabledbeforechangingtheclocksourcefrequencyormuxing viatheVIDCLKCTL and TSIFCTL.

4.3.1 Clock ConfigurationsafterDevice Reset

Afterdevicereset,theuserisresponsibleforprogramming thePLL Controllers(PLLC1 and PLLC2) and the Power and Sleep Controller(PSC) to bringthe deviceup to the desiredclockfrequencyand the desiredperipheralclockstate(clockgatingornot). For additionalpower savings,some oftheDM6467 peripheralssupportclockgatingwithintheperipheral boundary.For more detailson clockgatingand power savingfeaturessupportedby a specificperipheral, see the peripheral-specificreference/user'sguides [listed/linkedin the TMS320DM646x DMSoC PeripheralsOverviewReferenceGuide (literaturenumber SPRUEQ0 )].

4.3.1.1 Device Clock Frequency

The DM6467 defaultstoPLL bypass mode. IftheROM bootloaderisselected(BTMODE[3:0] ≠ 0100),the bootloadercode programsPLLC1 and PLLC2. Section4.4.1,BootModes discussesthedifferentbootmodes inmore detail. The usermust adheretothevariousclockrequirementswhen programmingthePLLC1 and PLLC2:

PLL multiplierand frequencyranges.For more detailson PLL multiplierand frequencyranges,see Section7.5.1,PLL1 and PLL2.

4.3.1.2 Module Clock State

The clockand resetstateforeach ofthemodules iscontrolledby thePower and SleepController(PSC). Table4-3 shows thedefaultstateofeach module aftera device-levelglobalreset.The DM6467 device has fourdifferentmodule states— Enable,Disable,SyncReset,orSwRstDisable.For more informationon thedefinitionsofthemodule states,thePSC, and PSC programming,see Section7.3.5,Power and Sleep Controller(PSC) and theTMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 89 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table4-3.DM6467 DefaultModule States DEFAULT MODULE STATELPSC # MODULE NAME [PSC RegisterMDSTATn.STATE]

0 ARM Enable

DSP C64x+ IfDSPBOOT = 0 then,Enableand Module LocalResetisasserted (MDSTATn.LRST = 0).1 IfDSPBOOT = 1 then,Enableand Module LocalResetisdeasserted (MDSTATn.LRST = 1).

2 HDVICP0 SwRstDisable

3 HDVICP1 SwRstDisable

4 EDMACC SwRstDisable

5 EDMATC0 SwRstDisable

6 EDMATC1 SwRstDisable

7 EDMATC2 SwRstDisable

8 EDMATC3 SwRstDisable

9 USB2.0 SwRstDisable

10 ATA SwRstDisable

11 VLYNQ SwRstDisable

12 HPI SwRstDisable

13 PCI SwRstDisable

14 EMAC/MDIO SwRstDisable

15 VDCE SwRstDisable

16 – 17 VideoPort(1) SwRstDisable

18 TSIF0 SwRstDisable

19 TSIF1 SwRstDisable

20 DDR2 Memory Contoller SwRstDisable

IfBTMODE[3:0] ≠ 0100 and DSPBOOT = 0 then,SwRstDisable21 EMIFA IfBTMODE[3:0] = 0100 orDSPBOOT = 1 then,Enable

22 McASP0 SwRstDisable

23 McASP1 SwRstDisable

24 CRGEN0 SwRstDisable

25 CRGEN1 SwRstDisable

26 UART0 SwRstDisable

27 UART1 SwRstDisable

28 UART2 SwRstDisable

29 PWM0 SwRstDisable

30 PWM1 SwRstDisable

31 I2C SwRstDisable

32 SPI SwRstDisable

33 GPIO SwRstDisable

34 TIMER0 SwRstDisable

35 TIMER1 SwRstDisable

36 – 44 Reserved Reserved

45 ARM INTC Enable

(1) The VideoPortModule has a totaloffiveclockinputsthatcan be controlledby theLPSC. One LPSC can supportonlya maximum of fourclocks;therefore,two LPSCs areassignedtotheVideoPort.BothVideoPortLPSCs shouldbe controlledtogetherand shouldbe settothesame state.

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4.3.2 Clock Control

This sectiondescribesthe followingregisters:the VPIF (Video)/TSIFclockcontroland clockdisable registersand theClockand Oscillatorcontrolregister.

4.3.2.1 Video Clock ControlRegister

The Video ClockControl(VIDCLKCTL) registerallowstheusertoselect/controltheclockmuxing forthe videochannels'(i.e.,channels1,2,and 3)outputclocksource. 31 16 RESERVED R-0000 0000 0000 0000 15 14 12 11 10 8 7 5 4 3 0 RSV VCH3CLK RSV VCH2CLK RESERVED VCH1CLK RESERVED R-0 R/W-111 R-0 R/W-110 R-000 R/W-1 R-0000 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-2.VIDCLKCTL Register[0x01C4 0038] Table4-4.VIDCLKCTL RegisterBitDescriptions BIT NAME DESCRIPTION 31:15 RESERVED Reserved.Read returns"0". VideoChannel3 ClockSource. ThisfieldselectstheclocksourcefortheChannel3 outputsourceclock. 000 = CRG0_VCXI (externalpin) 001 = CRG1_VCXI (externalpin) 010 = SYSCLK8 (PLLC1)14:12 VCH3CLK 011 = AUXCLK (PLLC1) 100 = VP_CLKIN0 (externalpin) 101 = STC_CLKIN (externalpin) 110 = VP_CLKIN2 (externalpin) 111 = VP_CLKIN3 (externalpin) 11 RSV Reserved.Read returns"0". VideoChannel2 ClockSource. ThisfieldselectstheclocksourcefortheChannel2 outputsourceclock. 000 = CRG0_VCXI (externalpin) 001 = CRG1_VCXI (externalpin) 010 = SYSCLK8 (PLLC1)10:8 VCH2CLK 011 = AUXCLK (PLLC1) 100 = VP_CLKIN0 (externalpin) 101 = STC_CLKIN (externalpin) 110 = VP_CLKIN2 (externalpin) 111 = Reserved 7:5 RESERVED Reserved.Read returns"0". VideoChannel1 ClockSource. ThisbitselectstheclocksourcefortheChannel1 inputclock.4 VCH1CLK 0 = VP_CLKIN0 (externalpin) 1 = VP_CLKIN1 (externalpin) 3:0 RESERVED Reserved.Read returns"0". Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 91 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.3.2.2 TSIF Control

The TSIF Control(TSIFCTL)registersallowstheusertoselect/controltheclockmuxing forthecounter and serialoutputofTSIF1 andthecounterand parallel/serialoutputforTSIF0. 31 16 RESERVED R-0000 0000 0000 0000 15 14 12 11 8 7 6 4 3 2 0 RSV TSIF1_CNTCLK TSSO_CLK RSV TSIF0_CNTCLK RSV TSPO_CLK R-0 R/W-000 R/W-0000 R-0 R/W-000 R-0 R/W-000 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-3.TSIFCTL Register[0x01C4 0050] Table4-5.TSIFCTL RegisterBitDescriptions BIT NAME DESCRIPTION 31:15 RESERVED Reserved.Read returns"0". TSIF1 CounterClockSource. ThisfieldselectstheclocksourcefortheTSIF1 module'scounter. 000 = CRG1_VCXI (externalpin) 001 = STC_CLKIN (externalpin) 010 = AUXCLK (PLLC1 output– 27 MHz)14:12 TSIF1_CNTCLK 011 = CRG0_VCXI (externalpin) 100 = VP_CLKIN2 (externalpin) 101 = VP_CLKIN3 (externalpin) 110 = Reserved 111 = Reserved TSIF1 SerialOutputClockSource. ThisfieldselectstheclocksourcefortheTSIF1 outputsourceclock. 0000 = CRG1_VCXI (externalpin) 0001 = STC_CLKIN (externalpin) 0010 = SYSCLK6 (PLLC1) 0011 = SYSCLKBP (PLLC1) 11:8 TSSO_CLK 0100 = VP_CLKIN0 (externalpin) 0101 = TS1_CLKIN (externalpin) 0110 = VP_CLKIN2 (externalpin) 0111 = Reserved 1000 = CRG0_VCXI 1001 = Reserved 1xx1 = Reserved 7 RSV Reserved.Read returns"0". TSIF0 CounterClockSource. ThisfieldselectstheclocksourcefortheTSIF0 module'scounter. 000 = CRG0_VCXI (externalpin) 001 = STC_CLKIN (externalpin) 010 = AUXCLK (PLLC1 output– 27 MHz)6:4 TSIF0_CNTCLK 011 = CRG1_VCXI (externalpin) 100 = VP_CLKIN0 (externalpin) 101 = VP_CLKIN1 (externalpin) 110 = Reserved 111 = Reserved 3 RSV Reserved.Read returns"0". TSIF0 Parallel/SerialOutputClockSource. ThisfieldselectstheclocksourcefortheTSIF0 outputsourceclock. 000 = CRG0_VCXI (externalpin) 001 = STC_CLKIN (externalpin) 010 = SYSCLK5 (PLLC1)2:0 TSPO_CLK 011 = SYSCLKBP (PLLC1) 100 = VP_CLKIN0 (externalpin) 101 = VP_CLKIN1 (externalpin) 110 = TS0_CLKIN (externalpin) 111 = CRG1_VCXI (externalpin)

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4.3.2.3 Video and TSIF Clock Disable

The Video Source Clock Disable(VSCLKDIS) registerallowsthe user to disablethe selectedVideo (VPIF),TSIF,and CRGEN module inputclocks. Note: To ensure glitch-freeoperation,the clockshouldbe disabledbeforechangingthe clocksource frequencyormuxing viatheVIDCLKCTL and TSIFCTL. 31 16 RESERVED R-0000 0000 0000 0000 15 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VID3 VID2 VID1 VID0 TSIFCNT1 TSIFCNT0 TSIFTX1 TSIFTX0 TSIFRX1 TSIFRX0 CRG1 CRG0 R-0000 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-4.VSCLKDIS Register[0x01C4 006C] Table4-6.VSCLKDIS RegisterBitDescriptions BIT NAME DESCRIPTION 31:12 RESERVED Reserved.Read returns"0". VPIF Channel3 ClockDisable. 11 VID3 0 = Clockenabled. 1 = Clockdisabled. VPIF Channel2 ClockDisable. 10 VID2 0 = Clockenabled. 1 = Clockdisabled. VPIF Channel1 ClockDisable. 9 VID1 0 = Clockenabled. 1 = Clockdisabled. VPIF Channel0 ClockDisable. 8 VID0 0 = Clockenabled. 1 = Clockdisabled. TSIF1 CounterClockDisable. 7 TSIFCNT1 0 = Clockenabled. 1 = Clockdisabled. TSIF0 CounterClockDisable. 6 TSIFCNT0 0 = Clockenabled. 1 = Clockdisabled. TSIF1 TransmitClockDisable. 5 TSIFTX1 0 = Clockenabled. 1 = Clockdisabled. TSIF0 TransmitClockDisable. 4 TSIFTX0 0 = Clockenabled. 1 = Clockdisabled. TSIF1 ReceiveClockDisable. 3 TSIFRX1 0 = Clockenabled. 1 = Clockdisabled. TSIF0 ReceiveClockDisable. 2 TSIFRX0 0 = Clockenabled. 1 = Clockdisabled. CRGEN1 ClockDisable. 1 CRG1 0 = Clockenabled. 1 = Clockdisabled. CRGEN0 ClockDisable. 0 CRG0 0 = Clockenabled. 1 = Clockdisabled. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 93 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.3.3 Clock and OscillatorControl

The Clockand OscillatorControl(CLKCTL) registerallowstheusertodisabletheOSC pwrdwn and pwr disable 31 26 25 24 23 20 19 16 RESERVED OSCPWRDN OSCDIS RESERVED CLKOUT R-0000 00 R/W-0 R/W-1 R-0000 R/W-1000 15 12 11 8 7 4 3 0 RESERVED AUD_CLK1 RESERVED AUD_CLK0 R-0000 R/W-0000 R-0000 R/W-0000 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-5.CLKCTL Register[0x01C4 005C] Table4-7.CLKCTL RegisterBitDescriptions BIT NAME DESCRIPTION 31:26 RESERVED Reserved.Read returns"0". 25 OSCPWRDN AuxiliaryOscillatorPowerdown. Thisbitcontrolstheinternalbiasresistorconection. 0 = Internalbiasresistorconnected(normaloperation) 1 = Internalbiasresistordisconnected(externalbiasresistorrequiredorclockinputused) 24 OSCDIS AuxiliaryOscillatorDisable. Thisbitdisablestheoscillator. 0 = Oscillatorenabled(normaloperation). 1 = Oscillatordisabled(clockinputused orno Auxiliaryclockrequired). 23:20 RESERVED Reserved.Read returns"0". 19:16 CLKOUT CLKOUT0 Source. ThisfieldselectstheclocksourcefortheCLKOUT0 output. 0000 = Disabled 0001 = PLL1 AUXCLK 0010 = Reserved 0011 = SYSCLK3 (1) 0100 = SYSCLK4 0101 = SYSCLK5 0110 = SYSCLK6 0111 = Reserved 1000 = SYSCLK8 1001 = SYSCLK9 1010 = AUX_MXI 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved 15:12 RESERVED Reserved.Read returns"0". (1) The maximum frequencyallowedfortheCLKOUT0 pinis148.5MHz. Forthe-729MHz device,inPLL mode, do notconfigurethe CLKOUT bitstoSYSCLK3 (0011)because theCLKOUT0 sourcewillexceed themaximum frequencylimitallowedforCLKOUT0 pin. Formore detailson theCLKOUT0 timings,see Table7-15,SwitchingCharacteristicsOver Recommended OperatingConditionsfor CLKOUT0 .

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-7.CLKCTL RegisterBitDescriptions(continued) BIT NAME DESCRIPTION 11:8 AUD_CLK1 AUDIO_CLK1 Source. ThisfieldselectstheclocksourcefortheAUDIO_CLK1 output. 0000 = Disabled 0001 = PLL1 AUXCLK 0010 = CRG0_VCXI 0011 = CRG1_VCXI 0100 = VP_CLKIN0 0101 = VP_CLKIN1 0110 = VP_CLKIN2 0111 = VP_CLKIN3 1000 = AUX_MXI 1001 = STC_CLKIN 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved 7:4 RESERVED Reserved.Read returns"0". 3:0 AUD_CLK0 AUDIO_CLK0 Source. ThisfieldselectstheclocksourcefortheAUDIO_CLK0 output. 0000 = Disabled 0001 = PLL1 AUXCLK 0010 = CRG0_VCXI 0011 = CRG1_VCXI 0100 = VP_CLKIN0 0101 = VP_CLKIN1 0110 = VP_CLKIN2 0111 = VP_CLKIN3 1000 = AUX_MXI 1001 = STC_CLKIN 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 95 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.4 Boot Sequence

The bootsequence isa processby whichthedevice'smemory isloadedwithprogram and datasections, and by whichsome ofthedevice'sinternalregistersareprogrammed withpredeterminedvalues.The boot sequence isstartedautomaticallyaftereach device-levelglobalreset.For more detailson device-level globalresets,see Section7.7,Reset. There areseveralmethods by whichthememory and registerinitializationcan takeplace.Each ofthese methods is referredto as a boot mode. The boot mode to be used is selectedat reset.For more informationon thebootmode selections,see Section4.4.1,BootModes . The deviceisbooted throughmultiplemeans — primarybootloaderswithininternalROM or EMIFA, and secondaryuserbootloadersfrom peripheralsor externalmemories.Boot modes, pinconfigurations,and registerconfigurationsrequiredforbootingthedevice,aredescribedinthefollowingsubsections.

4.4.1 Boot Modes

The DM6467 bootmodes aredeterminedby thesedevicebootand configurationpins.For informationon how thesepinsaresampled atdevicereset,see Section7.7.1.2,LatchingBootand ConfigurationPins.

BTMODE[3:0]
PCIEN
CS2BW
DSPBOOT
VP_DOUT7/VADJEN The TMS320DM646x DMSoC ARM can boot eitherfrom asynchronousEMIF/NOR Flashor from ARM ROM, as determinedby thedevicebootand configurationpinsatreset(BTMODE[3:0] and PCIEN). The PCIEN pinconfigurationisused to selectthe defaultconfigurationof the EMIFA/PCI/HPI pinsat reset. ThisallowstheDM646x DMSoC tobe PCI-compliantatreset.When PCIEN = 1,thePCI module controls themultiplexedpinswiththeappropriatepullup/pulldownconfiguration.For allotherbootmodes (non-PCI bootmodes),thePCIEN must be clearedto"0". For a more detaileddescriptionoftheROM bootmodes supportedby theDM646x DMSoC, see Usingthe TMS320DM646x BootloaderApplicationReport(literaturenumber SPRAAS0 ).

4.4.2 Boot Mode Registers

The DSPBOOTADDR, BOOTCMPLT, BOOTCMD, and BOOTCFG registersareused tocontrolbootand deviceconfigurations.

4.4.2.1 DSPBOOTADDR Register

The DSPBOOTADDR registercontainstheupper22 bitsoftheDSP resetvector. 31 10 9 0 BOOTADDR[21:0] RESERVED R/W-0100 0010 0010 0000 0000 00 R-00 0000 0000 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-6.DSPBOOTADDR Register Table4-8.DSPBOOTADDR RegisterBitDescriptions BIT NAME DESCRIPTION 31:10 BOOTADDR[21:0] Upper 22 bitsoftheC64x+ DSP bootaddress. 9:0 RESERVED Reserved

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4.4.2.2 BOOTSTAT Register

The Boot Status(BOOTSTAT) registerindicatesthestatusofthedevicebootprocess(e.g.,booterror, bootcomplete,orwatchdogtimerreset). 31 30 20 19 16 WDRST RESERVED BOOTERR R/W-0 R-000 0000 0000 R-0000 15 1 0 RESERVED BC R-0000 0000 0000 000 R/W-0 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-7.BOOTSTAT Register Table4-9.BOOTSTAT RegisterBitDescriptions BIT NAME DESCRIPTION Watchdog TimerReset. 0 = Deviceresetwas nota resultofa watchdogtimertimeout. 1 = Deviceresetwas a resultofa watchdogtimertimeout. 31 WDRST Thisisa "sticky"bitthatcan be used todebug WD timeoutconditions.The bitissetwhen a WD timeoutoccurs(TOUT2).Thisbitisreset(to"0")by a POR resetonly;otherwiseitretainsitsvalue. Itisnot clearedby a Warm ResetorSoftReset. The bitmay be clearedby writinga "1". 30:20 RESERVED Reserved.Read returns"0". BootError. 0000 = No booterror[default].19:16 BOOTERR Others= Bootloaderdetectedbooterror. The exactmeaning ofthevariouserrorcodes willbe determinedby thebootloadersoftware. 15:1 RESERVED Reserved.Read returns"0". BootComplete. 0 = Hosthas not completedthebootsequence [default]. 1 = Hosthas completedthebootsequence.0 BC Thisbitmay be optionallysetby a hostbootdevice(suchas PCI orHPI)toindicatethatithas finishedloadingcode.The ARM926 can pollthisbittodeterminewhethertocontinuetheboot process. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 97 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.4.2.3 BOOTCFG Register

The Boot Configuration(BOOTCFG) registerisa read-onlyregisterthatindicatesthevalueofthedevice bootmode and configurationpinslatchedat the end of reset.Duringa hard reset(POR or RESET pin active[low]),thevaluesoftheCFG pins(i.e.,BTMODE[3:0],CS2BW, PCIEN, DSPBOOT) arepropagated throughtheBOOTCFG registertotheBoot Controller.When RESET orPOR isde-asserted,thevalueof thepinsislatched.The BOOTCFG valuedoes notchange as a resultofa softreset,insteadthevalue latchedattheend ofthepreviousglobalresetisretained. 31 18 17 16 RESERVED DSP_BT PCIEN R-0000 0000 0000 00 R-L R-L 15 13 12 11 9 8 7 4 3 0 RESERVED VADJEN RESERVED CS2_BW RESERVED BOOTMODE R-000 R-L R-000 R-L R-0000 R-LLLL LEGEND: R = Read only;L = Latchedpinvalue;-n = valueafterreset Figure4-8.BOOTCFG Register

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-10.BOOTCFG RegisterBitDescriptions BIT NAME DESCRIPTION 31:18 RESERVED Reserved.Read returns"0". DSP Boot.LatchedfromDSPBOOT inputattherisingedge ofRESET orPOR. 0 = ARM bootsC64x+. 1 = C64x+ self-boots.17 DSP_BT Thisbitwillcause theDSP tobe releasedfromresetautomatically.The C64x+ willbootfrom EMIFA (defaultDSPBOOTADDR address0x4220 0000).IfBOOTMODE = 0010 or0011, orPCIEN = 1,thentheC64x+ self-bootwillfailsinceEMIFA willbe disabled. PCI Enable.LatchedfromPCIEN inputattherisingedge ofRESET orPOR. 0 = PCI disabled. 16 PCIEN 1 = PCI enabled. PCIEN = 1 disablestheinternalpullupand pulldownresistorson thePCI pinsand configuresthe pinmuxing forPCI. 15:13 RESERVED Reserved.Read returns"0". VotlageAdjustEnable(SmartReflex).LatchedfromVADJEN inputattherisingedge ofRESET or POR. ThispindetermineswhetherGP[6]/CVDDADJ0 and GP[7]/CVDDADJ1 functionas GPIO pinsoras 12 VADJEN SmartReflexcontroloutputpins. 0 = SmartReflexoutputsdisabled.GP[6]/CVDDADJ0 and GP[7]/CVDDADJ1 pinsfunctionas GPIO. 1 = SmartReflexoutputsenabled.GP[6]/CVDDADJ0 and GP[7]/CVDDADJ1 pinsfunctionas SmartReflexcontroloutputs. 11:9 RESERVED Reserved.Read returns"0". EMIFA EM_CS2 DefaultBus Width.LatchedfromCS2BW inputattherisingedge ofRESET or POR. 0 = Defaultto8-bitoperation.8 CS2_BW 1 = Defaultto16-bitoperation. Thisbitdeterminesthedefaultbus widthoftheEMIFA EM_CS2 memory space.Thisensuresthat bootfromEMIFA (ARM orDSP) willcorrectlyreadtheattachedmemory. 7:4 RESERVED Reserved.Read returns"0". BootMode ConfigurationBits.BitvalueslatchedfromBTMODE[3:0] attherisingedge ofRESET or POR. 0000 = Emulationboot. 0001 = Reserved. 0010 = HPI-16(ifPCIEN = 0). PCI withoutautoinitialization(ifPCIEN = 1). 0011 = HPI-32(ifPCIEN = 0). PCI withautoinitialization(ifPCIEN = 1). 0100 = EMIFA directboot(ROM/NOR) (ifPCIEN = 0;errorifPCIEN = 1 defaultstoUART0). 0101 = Reserved. 3:0 BOOTMODE 0110 = I2C boot. 0111 = NAND Flashboot(ifPCIEN = 0;errorifPCIEN = 1 defaultstoUART0). 1000 = UART0 boot. 1001 = Reserved. 1010 = Reserved. 1011 = Reserved. 1100 = Reserved. 1101 = Reserved. 1110 = SPI boot. 1111 = Reserved. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 99 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.4.2.4 ARMBOOT Register

The ARM Boot Configuration(ARMBOOT) registerisused tocontroltheARM926 boot.The ARMBOOT valuedoes notchange as a resultofa softreset,insteadthelastvaluewrittenisretained. When ROM bootisselected(BTMODE[3:0] ≠ 0100),a jump totheinternalTCM ROM (0x00008000) is forcedintothe firstfetchedinstructionword. The embedded ROM boot loader(RBL) code can then performcertainconfigurationsteps,read theBOOTCFG registertodeterminethedesiredbootmethod, and branchtoan appropriatesecondaryloaderutility. IfEMIFA bootisselected(BTMODE[3:0] = 0100),a jump tothehighestbranchaddress(0x02000000)is forcedintothefirstfetchedinstructionword.Thismust be modifiedtoaddress0x4200 0000 inorderto map totheEMIFA. The ARM willthencontinueexecutingfromexternalmemory usingthedefaultEMIFA timingsuntilmodifiedby software.Note: thateitherNOR Flashor ROM must be connectedtothefirst EMIFA chipselectspace (EM_CS2). The EMIFA does not supportdirectexecutionfromNAND Flash. 31 5 4 3 1 0 RESERVED ADDRMOD RESERVED TRAMBOOT R-0000 0000 0000 0000 0000 0000 000 R/W-C R-000 R/W-0 LEGEND: R/W = Read/Write;R = Read only;C = Clear;-n = valueafterreset Figure4-9.ARMBOOT Register Table4-11.ARMBOOT RegisterBitDescriptions BIT NAME DESCRIPTION 31:5 RESERVED Reserved.Read returns"0". IAHB AddressModification. 0 = No addressmodification. 1 = Addressbit30 istiedhightomodifyIAHB fetchaddresstopointtoEMIFA. The defaultvalueforthisbitisdeterminedby theBOOTMODE configurationbits(BTMODE[3:0]).If BTMODE[3:0] = 0100 [EMIFA directboot(ROM/NOR)] ,thenADDRMOD defaultsto"1"so that 4 ADDRMOD instructionfetchesfromtheARM willpointtoEMIFA CS2 memory space.Forallother BTMODE[3:0] values,ADDRMOD defaultsto"0"because ARM willbootfromitsTCM (ROM or RAM). The ADDRMOD valueisignoredwhen TRAMBOOT isset(1)[addressmodificationisdisabled]. AfterbranchingintotheEMIFA CS2 space,softwareshouldclearthisbitas partoftheresetroutine so thatsubsequentIAHB accessaddressesarenotmodified. 3:1 RESERVED Reserved.Read returns"0". ARM TCM RAM Boot. 0 = Use BTMODE[3:0] selectedbootmode 1 = BootfromITCM RAM 0 TRAMBOOT Thisisa "sticky"bitthatcan be used toforcetheARM926 tobootfromITCM RAM. On POR reset, thisbitwillbe initializedto"0"because TCM RAM isnotinitialized;otherwise,thebitretainsthe value.AfterinitializingITCM RAM, softwarecan setthisbitso thatsubsequentWarm Reset (RESET) orSoftResetwillbootfromtheITCM.

4.4.2.5 ARMWAIT Register

The ARM WaitStateControl(ARMWAIT) registerisused tocontrolARM926 accessestoitsTCM RAM. At normalARM operatingfrequency,a waitstatemust be insertedwhen accessingTCM RAM. When the deviceisoperatedatlow speeds,performancemay be increasedby removingthewaitstate.Note:TCM ROM willalwaysoperatewitha waitstateenabled. 31 1 0 RESERVED RAMWAIT R-0000 0000 0000 0000 0000 0000 0000 000 R/W-1 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-10.ARMWAIT Register

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-12.ARMWAIT RegisterBitDescriptions BIT NAME DESCRIPTION 31:1 RESERVED Reserved.Read returns"0". ARM TCM RAM WaitStateConfiguration. 0 RAMWAIT 0 = TCM RAM waitstatedisabled. 1 = TCM RAM waitstateenabled. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 101 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.5 ConfigurationsAt Reset

Some deviceconfigurationsaredeterminedatreset.The followingsubsectionsgivemore details.

4.5.1 Device and PeripheralConfigurationsatDevice Reset

Table3-5,BOOT TerminalFunctionsliststhedevicebootand configurationpinsthatarelatchedatdevice resetforconfiguringbasicdevicesettingsforproperdeviceoperation.Table4-13,summarizes thedevice bootand configurationpins,and thedevicefunctionsthattheyaffect. Table4-13.DefaultFunctionsAffectedby Device Boot and ConfigurationPins DEVICE BOOT AND BOOT SELECTED PIN MUX CONTROL GLOBAL SETTING PERIPHERAL SETTINGCONFIGURATION PINS BOOTMODE[3:0] BootMode PINMUX0/PINMUX1 I/OPin Power : PSC/Peripherals: Registers: Based on Based on Based on BOOTMODE[3:0], the BOOTMODE[3:0], the BOOTMODE[3:0], the bootloadercode programs bootloadercode programs bootloadercode programs VDD3P3V_PWDN registerthePSC toputboot- PINMUX0 and PINMUX1 topower up theI/Opins relatedperipheral(s)inthe registerstoselectthe requiredforboot. EnableState,and appropriatepinfunctions programstheperipheral(s) requiredforboot. forbootoperation. CS2BW EMIFA DirectBootMode PINMUX0.HPIEN = 0 – The defaultwidthofthe PINMUX0.PCIEN = 0 firstEMIFA chipselect PINMUIX0.ATAEN = 0 space (CS2)is determinedby the CS2BW value.IfCS2BW = 0,thespace defaultsto 8-bitswide.IfCS2BW = 1, itdefaultsto16-bitswide. ThisallowstheARM to make fulluse ofthewidth oftheattachedmemory devicewhen bootingfrom EMIFA. PCIEN (1) Host Boot: PINMUX0.PCIEN : – PSC/Peripheral PCIEN selectsthetypeof setsthisfieldtocontrol (ApplicabletoHostBoot HostBoot thePCI pinmuxing in. only): (HPIBootorPCI Boot) (1)(2) Based on theHostBoot type(PCIorHPI),the bootloadercode programs thePSC toputthe correspondingperipheral intheEnableState,and programstheperipheral forbootoperation. (1) Softwarecan modifyallPINMUX0 and PINMUX1 bitfieldsfromtheirdefaults. (2) Inadditiontopinmux control,PCIEN alsoaffectstheinternalpullup/downresistorsofthePCI capablepins.When PCIEN = 0,internal pullup/downresistorson thePCI capablepinsareenabled.When PCIEN = 1,internalpullup/downresistorson thePCI capablepinsare disabledtobe complianttothePCI LocalBus SpecificationRevision2.3.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-13.DefaultFunctionsAffectedby Device Boot and ConfigurationPins (continued) DEVICE BOOT AND BOOT SELECTED PIN MUX CONTROL GLOBAL SETTING PERIPHERAL SETTINGCONFIGURATION PINS DSPBOOT Bit= 0,DSP isbootedby – – Note:thateitherNOR theARM FlashorROM must be Bit=1,DSP bootsself connectedtothefirst fromEMIFA EMIFA chipselectspace (CS2). The EMIFA does not supportdirectexecution fromNAND Flash.Code withintheEMIFA memory shouldexecutea branch totheactualEMIFA addressand thendisable theInstructionAddress Modificationlogic(by clearingtheADDRMOD bitintheARMBOOT registeroftheSystem Module). VADJEN – Atreset,theinputstateis – – sampled todetermine whethertheSmartReflex ControlOutputsare enbabledordisabled. 0 = SmartReflexoutputs disabled. GP[6]/CVDDADJ0 and GP[7]/CVDDADJ1 pins functionas GPIO. 1 = SmartReflexoutputs enabled. GP[6]/CVDDADJ0 and GP[7]/CVDDADJ1 pins functionas SmartReflex controloutputs. CVDDADJ0 – Once theSmartReflex – CVDDADJ1 ControlOutputsare enabled(VADJEN = 1 at reset),thesepinscontrol theadjustablecorepower supplytooutputtheCV DD voltageforthedevice: 00 = 1.2V (-594V,- 594AV devciesonly) 594AV devciesonly) Allothersettings RESERVED. For properdeviceoperation,externalpullup/pulldownresistorsmay be requiredon thesedevicebootand configurationpins.For discussionsituationswhere externalpullup/pulldownresistorsare required,see Section4.8.1,Pullup/PulldownResistors. Note:AllDM6467 deviceconfigurationinputs(BOOTMODE[3:0], CS2BW, PCIEN, and DSPBOOT) are multiplexedwithotherfunctionalpins.These pinsfunctionas deviceboot and configurationpinsonly duringdevicereset.The usermust takecareofany potentialdatacontentioninthesystem.To helpavoid system data contention,the DM6467 puts these configurationpinsintoa high-impedancestate(Hi-Z) when devicereset(RESET or POR) isasserted,and continuestoholdthem ina high-impedancestate untilthe internalglobalresetisremoved; at which point,the defaultperipheral(VPIF)willnow control thesepins. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 103 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Allof the deviceboot and configurationpinsettingsare capturedinthe correspondingbitfieldsinthe BOOTCFG register(seeSection4.4.2.3). The followingsubsectionsprovidemore detailson thedeviceconfigurationsdeterminedatdevicereset: CS2BW, PCIEN, and DSPBOOT.

4.5.2 EMIFA CS2 Bus Width (CS2BW)

The defaultwidthof the firstEMIFA chipselectspace (CS2) isdeterminedby the CS2BW value.If CS2BW = 0,thespace defaultsto8-bitswide.IfCS2BW = 1,itdefaultsto16-bitswide.Thisallowsthe ARM tomake fulluse ofthewidthoftheattachedmemory devicewhen bootingfromEMIFA. Note:CS2BW only selectsthedefaultbus width.The EMIFA bus widthmay be changed atany timevia softwareby accessingtheappropriateEMIFA controlregister. The defaultwidthaffectsonly thefirstchipselectspace (CS2).Allotherchipselectspaces defaultto8- bitswideand must be modifiedusingtheappropriateEMIFA controlregisterif16-bitoperationisdesired.

4.5.3 PCI Enable (PCIEN)

The PCIEN configurationpin determinesifthe PCI peripheralis used on thisdevice.IfPCIEN = 1 indicatingthe PCI is used, then the PCI multiplexedpins defaultto PCI functions,and the pins’ correspondinginternalpullup/pulldownresistorsaredisabled.IfPCIEN = 0 indicatingthePCI isnotused, thenthePCI muxed pinsdefaulttonon-PCI functions(e.g.,EMIFA or HPI pinfunctions),and thepins’ correspondinginternalpullup/pulldownresistorsareenabled. The PCIEN settingis captured and stored in the BOOTCFG.PCIEN bitfield,and also in the PINMUX0.PCIEN bitfield.

4.5.4 DSPBOOT

The DSPBOOT inputdeterminesDSP operationatreset.For most applications,theARM isthemaster deviceand controlsthe resetand boot of the DSP. Under thisscenario(DSPBOOT = 0),the DSP will remaindisabled(heldinreset)afterreset.The ARM isresponsibleforreleasingDSP from reset.Before releasingDSP fromreset,theARM must transfera validDSP bootimage toprogram memory accessible by theDSP (DSP memory, EMIFA or DDR2), and configuretheDSP bootaddressinDSPBOOTADDR register(inSYSTEM module)fromwhichtheDSP willbeginexecution. When DSPBOOT = 1, the DSP willboot itself.Under thisscenario,DSP willbe releasedfrom reset withoutARM intervention.The DSP boot addressissetto an EMIFA address0x4220 0000h. DSP will beginexecutionwithinstruction(L1P)cache enabled. Note: The DSPBOOT operationisoverriddenwhen ARM HPI or PCI bootisselected(BTMODE[3:0] = 001x).Thisisbecause ARM HPI/PCIbootselectionwillforcetheHPIEN orPCIEN bitinPINMUX0 to‘1’. ThisenablesUHPI/PCI functionson theEMIFA controland datapinsand preventstheDSP from using EMIFA. DSPBOOT istreatedas "0"internallywhen BTMODE[3:0] = 001x,regardlessofthevalueatthe configurationpin(The actualpinvalueshouldstillbe latchedinthe BOOTCFG registerof the System Module).

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4.6 ConfigurationsAfterReset

The followingsectionsprovidedetailson configuringthedeviceafterreset. Multiplexedpinareconfiguredbothatand afterreset.Section4.5.1,Deviceand PeripheralConfigurations atDeviceReset,discussesmultiplexedpincontrolatreset.For more detailson multiplexedpinscontrol afterreset,see Section4.7,MultiplexedPinConfigurations.

4.6.1 Switch CentralResource (SCR) Bus Priorities

PrioritizationwithintheSwitchedCentralResource (SCR) isprogrammableforeach master.The register bitfieldsand defaultprioritylevelsforDM6467 bus mastersareshown inTable4-14,DM6467 DefaultBus MasterPriorities.The prioritylevelsshouldbe tunedtoobtainthebestsystemperformancefora particular application.Lower valuesindicatehigherpriority.For most masters,theirpriorityvaluesareprogrammed at the system levelby configuringthe MSTPRI0, MSTPRI1, and MSTPRI2 registers.Detailson the MSTPRI0/1/2 registersareshown inFigure4-11,Figure4-12,and Figure4-13. Table4-14.DM6467 DefaultBus Master Priorities PriorityBitField Bus Master DefaultPriorityLevel VP0P VPIF Capture 1 (MSTPRI2 Register) VP1P VPIF Display 1 (MSTPRI2 Register) TSIF0P TSIF0 1 (MSTPRI2 Register) TSIF1P TSIF1 1 (MSTPRI2 Register) EDMATC0P EDMATC0 2 (MSTPRI2 Register) EDMATC1P EDMATC1 2 (MSTPRI2 Register) EDMATC2P EDMATC2 2 (MSTPRI2 Register) EDMATC3P EDMATC3 2 (MSTPRI2 Register) HDVICP0P HDVICP0 (CFG)(1) 3 (MSTPRI0 Register) HDVICP1P HDVICP1 (CFG)(1) 3 (MSTPRI0 Register) ARMINSTP ARM926 (INST) 4 (MSTPRI0 Register) ARMDATAP ARM926 (DATA) 4 (MSTPRI0 Register) DSPDMAP C64x+ DSP (DMA) 4 (MSTPRI0 Register) DSPCFGP C64x+ DSP (CFG)(1) 4 (MSTPRI0 Register) VDCEP VDCE 4 (MSTPRI1 Register) EMACP EMAC 5 (MSTPRI1 Register) USBP USB2.0 5 (MSTPRI1 Register) ATAP ATA 5 (MSTPRI1 Register) VLYNQP VLYNQ 5 (MSTPRI1 Register) PCIP PCI 6 (MSTPRI1 Register) HPIP HPI 6 (MSTPRI1 Register) (1) The C64x+ DSP (CFG),HDVICP0 (CFG),and HDVICP1 (CFG) priorityvaluesarenotactuallyused by theDMSoC infrastructure– whichgivesequalweightround-robinprioritytoaccessesfromthesethreemasters.Therefore,theprioritysettingsforthesethree mastersintheMSTPRI0 registerhave no effect. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 105 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 31 23 22 20 19 18 16 RESERVED RSVHDVICP1P (1) HDVICP0P (1) R-0000 0000 0 R/W-011 R-0 R/W-011 15 14 12 11 8 7 6 4 3 2 0 RSV DSPDMAP RSV DSPCFGP (1) RSV ARMDATAP RSV ARMINSTP R-0 R/W-100 R-0 R/W-100 R-0 R/W-100 R-0 R/W-100 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-11.MSTPRI0 Register[0x01C4 003C] (1) The DSPCFGP, HDVICP0P, and HDVICP1P priorityvaluesarenotactuallyused by theinfrastructure,whichgivesequalweightround- robinprioritytoaccessesfromthismaster;therefore,thesettingshave no effect. Table4-15.MSTPRI0 RegisterBitDescriptions BIT NAME DESCRIPTION 31:23 RESERVED Reserved.Read returns"0". 22:20 HDVICP1P (1) HDVICP1 masterportpriorityinSystem Infrastructure.Read returns"011".Writeshave no effect. 19 RSV Reserved.Read returns"0". 18:16 HDVICP0P (1) HDVICP0 masterportpriorityinSystem Infrastructure.Read returns"011".Writeshave no effect. 15 RSV Reserved.Read returns"0". 14:12 DSPDMAP DSPDMA masterportpriorityinSystem Infrastructure. 000 = Priority0 (Highest) 100 = Priority4 [Default] 001 = Priority1 101 = Priority5 010 = Priority2 110 = Priority6 011 = Priority3 111 = Priority7 (Lowest) 11 RSV Reserved.Read returns"0". 10:8 DSPCFGP (1) DSPCFG masterportpriorityinSystem Infrastructure.Read returns"100".Writeshave no effect. 7 RSV Reserved.Read returns"0". 6:4 ARMDATAP ARM DATA masterportpriorityinSystem Infrastructure. 000 = Priority0 (Highest) 100 = Priority4 [Default] 001 = Priority1 101 = Priority5 010 = Priority2 110 = Priority6 011 = Priority3 111 = Priority7 (Lowest) 3 RSV Reserved.Read returns"0". 2:0 ARMINSTP ARM INST masterportpriorityinSystem Infrastructure. 000 = Priority0 (Highest) 100 = Priority4 [Default] 001 = Priority1 101 = Priority5 010 = Priority2 110 = Priority6 011 = Priority3 111 = Priority7 (Lowest) (1) The prioritiesforthesemastersarefixedattheirdefaultvalues.Writingalternatevaluestothesefieldshas no effect..

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 31 30 28 27 26 24 23 22 20 19 18 16 RSV VDCEP RSV PCIP RSV HPIP RSV VLYNQP R-0 R/W-100 R-0 R/W-110 R-0 R/W-110 R-0 R/W-101 15 14 12 11 10 8 7 3 2 0 RSV ATAP RSV USBP RESERVED EMACP R-0 R/W-101 R-0 R/W-101 R-0000 0 R/W-101 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-12.MSTPRI1 Register[0x01C4 0040] Table4-16.MSTPRI1 RegisterBitDescriptions BIT NAME DESCRIPTION 31 RSV Reserved.Read returns"0". 30:28 VDCEP VDCE masterportpriorityinSystem Infrastructure. 000 = Priority0 (Highest) 100 = Priority4 [Default] 001 = Priority1 101 = Priority5 010 = Priority2 110 = Priority6 011 = Priority3 111 = Priority7 (Lowest) 27 RSV Reserved.Read returns"0". 26:24 PCIP PCI masterportpriorityinSystem Infrastructure. 000 = Priority0 (Highest) 100 = Priority4 001 = Priority1 101 = Priority5 010 = Priority2 110 = Priority6 [Default] 011 = Priority3 111 = Priority7 (Lowest) 23 RSV Reserved.Read returns"0". HPI masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.22:20 HPIP "110"= Priority6 [default]. 19 RSV Reserved.Read returns"0". VLYNQ masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.18:16 VLYNQP "110"= Priority6 [default]. 15 RSV Reserved.Read returns"0". ATA masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.14:12 ATAP "101"= Priority5 [default]. 11 RSV Reserved.Read returns"0". USB masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.10:8 USBP "101"= Priority5 [default]. 7:3 RESERVED Reserved.Read returns"0". EMAC masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.2:0 EMACP "101"= Priority5 [default]. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 107 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 31 30 28 27 26 24 23 22 20 19 18 16 RSV TSIF1P RSV TSIF0P RSV VP1P RSV VP0P R-0 R/W-001 R-0 R/W-001 R-0 R/W-001 R-0 R/W-001 15 14 12 11 10 8 7 6 4 3 2 0 RSV EDMATC3P RSV EDMATC2P RSV EDMATC1P RSV EDMATC0P R-0 R/W-010 R-0 R/W-010 R-0 R/W-010 R-0 R/W-010 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-13.MSTPRI2 Register Table4-17.MSTPRI2 RegisterBitDescriptions BIT NAME DESCRIPTION 31 RSV Reserved.Read returns"0". 30:28 TSIF1P TSIF1 masterportpriorityinSystem Infrastructure. 000 = Priority0 (Highest) 100 = Priority4 001 = Priority1 [Default] 101 = Priority5 010 = Priority2 110 = Priority6 011 = Priority3 111 = Priority7 (Lowest) 27 RSV Reserved.Read returns"0". 26:24 TSIF0P TSIF0 masterportpriorityinSystem Infrastructure. 000 = Priority0 (Highest) 100 = Priority4 001 = Priority1 [Default] 101 = Priority5 010 = Priority2 110 = Priority6 011 = Priority3 111 = Priority7 (Lowest) 23 RSV Reserved.Read returns"0". VPIF displaymasterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.22:20 VP1P "001"= Priority1 [default]. 19 RSV Reserved.Read returns"0". VPIF capturemasterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.18:16 VP0P "001"= Priority1 [default]. 15 RSV Reserved.Read returns"0". EDMATC3 masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.14:12 EDMATC3P "010"= Priority2 [default]. 11 RSV Reserved.Read returns"0". EDMATC2 masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.10:8 EDMATC2P "010"= Priority2 [default]. 7 RSV Reserved.Read returns"0". EDMATC1 masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.6:4 EDMATC1P "010"= Priority2 [default]. 3 RSV Reserved.Read returns"0". EDMATC0 masterportpriorityinSystem Infrastructure.Same priority0–7 selectionas above.2:0 EDMATC0P "010"= Priority2 [default].

4.6.2 PeripheralSelectionAfterDevice Reset

Afterdevicereset,most peripheralconfigurationsare done withinthe peripheral’s registers.This sectiondiscussessome additionalperipheralcontrolsin the System Module. For informationon multiplexedpin controlsthatdeterminewhat peripheralpins are brought out to the pins,see Section4.7,MultiplexedPinConfigurations.

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4.6.2.1 HPICTL Register

The HPI controlregister(HPICTL) [0x01C4 0030] controlswriteaccess to HPI controland address registersand determinesthehosttime-outvalue.HPICTL isnotresetby a softresetso thattheHPI width willremaincorrectlyconfigured.Figure4-14and Table4-18describeindetailtheHPICTL register. 31 18 17 16 RESERVED RESERVED R-0000 0000 0000 00 R/W-00 15 14 10 9 8 7 0 WIDTH RESERVED CTLMODE ADDMODE TIMOUT R/W-0 R-000 00 R/W-0 R/W-0 R/W-1000 0000 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-14.HPICTL Register[0x01C4 0030] Table4-18.HPICTL RegisterBitDescriptions BIT NAME DESCRIPTION 31:18 RESERVED Reserved.Read-only,writeshave no effect. 17:16 RESERVED Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothesebits(default). HPI Data Width. 0 = Half-width(16-bit)databus

15 WIDTH 1 = Full-width(32-bit)databus

Thisbitvaluemust be determinedbeforereleasingtheUHPI fromresettoensurecorrectUHPI operation. 14:10 RESERVED Reserved.Read-only,writeshave no effect. HPIC RegisterWriteAccess.

9 CTLMODE 0 = Host

1 = DMSoC (ifADDMODE = 1) HPIA RegisterWriteAccess.

8 ADDMODE 0 = Host

1 = DMSoC HostBurstWriteTimeoutValue. When theHPI time-outcounterreachesthevalueprogrammed here,theHPI writeFIFO contentis7:0 TIMOUT flushed.Formore detailson thetime-outcounterand itsuse inwritebursting,see the TMS320DM646x DMSoC HostPortInterface(HPI)User'sGuide (literaturenumber SPRUES1).

4.6.2.2 USBCTL Register

The USB interfacecontrolregister(USBCTL) [0x01C40034]isdescribedinFigure4-15and Table4-19. 31 19 18 17 16 RESERVED DATAPOL VBUSVAL USBID R-0000 0000 0000 0 R/W-1 R/W-0 R/W-0 15 9 8 7 5 4 3 1 0 PHY PHY PHYRESERVED RESERVED RESERVEDCLKGD PLLON PDWN R-0000 000 R-0 R-000 R/W-0 R-000 R/W-1 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-15.USBCTL Register[0x01C4 0034] Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 109 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table4-19.USBCTL RegisterBitDescriptions BIT NAME DESCRIPTION 31:19 RESERVED Reserved.Read returns"0". USB Data Polarity. 18 DATAPOL 0 = Inverteddata. 1 = Normal datapolarity[default]. VBUS Sense Control. 17 VBUSVAL 0 = Disabled[default]. 1 = Sessionstarts. USB Mode. 16 USBID 0 = Host[default]. 1 = Peripheral. 15:9 RESERVED Reserved.Read returns"0". USB PHY Power and ClockGood. 8 PHYCLKGD 0 = PHY power isnotramped orPLL isnotlocked[default]. 1 = PHY power isgood and PLL islocked. 7:5 RESERVED Reserved.Read returns"0". USB PHY PLL Suspend Override. 4 PHYPLLON 0 = Normal PLL operation[default]. 1 = OverridePLL suspend state. 3:1 RESERVED Reserved.Read returns"0". USB PHY Power-Down Control. 0 PHYPDWN 0 = PHY powered on. 1 = PHY power off[default].

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4.6.2.3 PWMCTL (TriggerSource)ControlRegister

The PWM controlregister(PWMCTL) [0x01C4 0054]chip-levelconnectionsofbothPWM0 and PWM1. Figure4-16and Table4-20describeindetailthePWMCTL register. 31 16 RESERVED R-0000 0000 0000 0000 15 8 7 4 3 0 RESERVED PWM11TRG PWM0TRG R-0000 0000 R/W-1111 R/W-1111 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-16.PWMCTL Register[0x01C4 0054] Table4-20.PWMCTL RegisterBitDescriptions BIT NAME DESCRIPTION 31:8 RESERVED Reserved.Read-only,writeshave no effect. 7:4 PWM1TRG PWM1 TriggerSource 0000 = GP[0] 1000 = VPIF VerticalInterrupt0 0001 = GP[1] 1001 = VPIF VerticalInterrupt1 0010 = GP[2] 1010 = VPIF VerticalInterrupt2 0011 = GP[3] 1011 = VPIF VerticalInterrupt3 0100 = GP[4] 1100 = Reserved 0101 = GP[5] 1101 = Reserved 0110 = GP[6] 1110 = Reserved 0111 = GP[7] 1111 = Reserved PWM0 TriggerSource3:0 PWM0TRG same selectionas above. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 111 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.6.2.4 EDMATCCFG Register

The EDMA TransferControllerDefaultBurstSizeConfigurationRegister(EDMATCCFG) [0x01C4 0058] configuresthe defaultburstsize(DBS) forEDMA TC0, EDMA TC1, EDMA TC2, and EDMA TC3. Figure4-17 and Table 4-21 describeindetailthe EDMATCCFG register.For more informationon the correctusage of DBS, see the TMS320DM646x DMSoC Enhanced DirectMemory Access (EDMA) ControllerUser'sGuide (literaturenumber SPRUEQ5 ). 31 16 RESERVED R-0000 0000 0000 0000 15 8 7 6 5 4 3 2 1 0 RESERVED TC3DBS TC2DBS TC1DBS TC0DBS R-0000 0000 R/W-01 R/W-01 R/W-01 R/W-01 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-17.EDMA TransferControllerDefaultBurstSizeConfigurationRegister(EDMATCCFG) [0x01C4 0058] Table4-21.EDMATCCFG RegisterBitDescriptions BIT NAME DESCRIPTION 31:8 RESERVED Reserved.Read-only,writeshave no effect. EDMA TC3 DefaultBurstSize. 00 = 16 byte 01 = 32 byte[default]7:6 TC3DBS 10 = 64 byte 11 = reserved TC3 FIFO sizeis256 bytes,regardlessofDefaultBurstSizesetting. EDMA TC2 DefaultBurstSize. 00 = 16 byte 01 = 32 byte[default]5:4 TC2DBS 10 = 64 byte 11 = reserved TC2 FIFO sizeis256 bytes,regardlessofDefaultBurstSizesetting. EDMA TC1 DefaultBurstSize. 00 = 16 byte 01 = 32 byte[default]3:2 TC1DBS 10 = 64 byte 11 = reserved TC1 FIFO sizeis256 bytes,regardlessofDefaultBurstSizesetting. EDMA TC0 DefaultBurstSize. 00 = 16 byte 01 = 32 byte[default]1:0 TC0DBS 10 = 64 byte 11 = reserved TC0 FIFO sizeis256 bytes,regardlessofDefaultBurstSizesetting.

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4.7 MultiplexedPin Configurations

DM6467 makes extensiveuse ofpinmultiplexingtoaccommodate a largenumber ofperipheralfunctionin thesmallestpossiblepackage,providingtheultimateflexibilityforend applications. The PinMultiplexRegistersPINMUX0 and PINMUX1 intheSystem Module areresponsiblieforcontrolling allpinmultiplexingfunctionson theDM6467. The defaultsettingofsome ofthePINMUX0 and PINMUX1 bitfieldsare configuredby configurationpinslatchedatreset(seeSection4.5.1,Deviceand Peripheral ConfigurationsatDeviceReset).Afterreset,softwaremay program thePINMUX0 and PINMUX1 registers toswitchpinfunctionalities. The followingperipheralshave multiplexedpins:VPIF,TSIF0,TSIF1,CRGEN0, CRGEN1, EMIFA, PCI, HPI,ATA, PWM0, PWM1, UART0, UART1, UART2, AudioClockSelector,theUSB USB_DRVVBUS pin, and GPIO.

4.7.1 Pin Muxing SelectionAt Reset

Thissectionsummarizespinmux selectionatreset. The configurationpinsCS2BW, PCIEN, and VADJEN, latchedatdevicereset,determinethedefaultpin muxing.Formore detailson thedefaultpinmuxing atreset,see Section4.5,ConfigurationsAtReset.

4.7.2 Pin Muxing SelectionAfterReset

The PINMUX0 and PINMUX1 registersintheSystem Module allowsoftwaretoselectthepinfunctions. Some pin functionsrequirea combinationof PINMUX0/PINMUX1 bitfields.For more detailson the combinationof the PINMUX bitfieldsthatcontroleach muxed pin,see Section4.7.3, Pin Multiplexing Details. This sectiononly providesan overviewof the PINMUX0 and PINMUX1 registers.For more detailed discussionon how toprogrameach PinMux Block,see Section4.7.3,PinMultiplexingDetails.

4.7.2.1 PINMUX0 RegisterDescription

The Pin Multiplexing0 Registercontrolsthe pin functionin the EMIFA/ATA/HPI/PCI,TSIF0, TSIF1, CRGEN, Block.The PINMUX0 registerformatisshown inFigure4-18 and thebitfielddescriptionsare given in Table 4-22. Some muxed pins are controlledby more than one PINMUX bitfield.For the combinationof the PINMUX bitfieldsthatcontroleach muxed pin,see Section4.7.3, Pin Multiplexing Details.For more informationon theblockpinmuxing and pin-by-pinmuxing control,see specificblock muxing section(forexample,forCRGEN PinMux Control,see Section4.7.3.7,CRGEN SignalMuxing). 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 VBUSDIS STCCK AUDCK1 AUDCK0 RSV CRGMUX TSSOMUX TSSIMUX TSPOMUX TSPIMUX R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-000 R/W-00 R/W-00 R/W-00 R/W-00 15 6 5 4 3 2 1 0 RESERVED RSV RESERVED PCIEN HPIEN ATAEN R-0000 0000 00 R/W-0 R-0 R/W-L R/W-0 R/W-0 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-18.PINMUX0 Register[0x01C4 0000] Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 113 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table4-22.PINMUX0 RegisterBitDescriptions BIT NAME DESCRIPTION ThisbitdisablesUSB_DRVVBUS output. 31 VBUSDIS 0 = USB_DRVVBUS functionselected. 1 = GP[22]functionselected. ThisbitenablesSTC SourceClockinput. 30 STCCK 0 = GP[4]functionselected. 1 = STC_CLKIN functionselected. ThisbitenablesAUDIO_CLK1 output. 29 AUDCK1 0 = GP[2]functionselected. 1 = AUDIO_CLK1 functionselected. ThisbitenablesAUDIO_CLK0 output. 28 AUDCK0 0 = GP[3]functionselected. 1 = AUDIO_CLK0 functionselected. 27 RSV Reserved.Read returns"0". CRGEN PinMux Control(seeSection4.7.3.7,CRGEN SignalMuxing). 000 = No CRGEN signalsenabled. 001 = CRGEN1 selectionenabled(muxed withUART2 data). 010 = Reserved(noCRGEN signalsenabled). 26:24 CRGMUX 011 = Reserved(noCRGEN signalsenabled). 100 = CRGEN0 selectionenabled(muxed withUCTS2 and PWM0). 101 = CRGEN0 and CRGEN1 selectionenabled. 110 = CRGEN0 selectionenabled(muxed withUART2 data). 111 = Reserved(noCRGEN signalsenabled). TSIF1 SerialOutputPinMux Control(see(1),TSSO SignalMuxing). 0x = No TS1 outputsignalsenabled.23:22 TSSOMUX 10 = TS1 outputselectionenabled(muxed on VP_DOUT pins). 11 = TS1 outputselectionenabled(muxed on URIN0, UCTS2, PWM0, and PWM1 pins). TSIF1 SerialInputPinMux Control(seeSection4.7.3.5,TSIF1 InputSignalMuxing). 00 = No TS1 inputsignalsenabled. 21:20 TSSIMUX 01 = TS1 inputselectionenabled(muxed on UART0 pins). 10 = TS1 inputselectionenabled(muxed on VP_DOUT pins). 11 = TS1 inputselectionenabled(muxed on VP_DIN pins). TSIF0 Parallel/SerialOutputPinMux Control(seeSection4.7.3.4,TSIF0 OutputSignalMuxing). 0x = No TS0 outputsignalsenabled.19:18 TSPOMUX 10 = TS0 paralleloutputmuxing enabled(muxed withVP_DIN pins). 11 = TS0 serialoutputmuxing enabled(muxed TS0_DOUT7 withUTXD1). TSIF0 Parallel/SerialInputPinMux Control(seeSection4.7.3.3,TSIF0 InputSignalMuxing). 0x = No TS0 signalsenabled.17:16 TSPIMUX 10 = TS0 parallelinputmuxing enabled(muxed withVP_DIN pins). 11 = TS0 serialinputmuxing enabled(muxed TS0_DIN7 withURXD1). 15:6 RESERVED Reserved.Read returns"0". Reserved.Read returns"0".Note:Forproperdeviceoperation,when writingtothisbit,onlya "0"5 RESERVED shouldbe written. 4:3 RESERVED Reserved.Read returns"0". 1 HPIEN HPI FunctionEnable(seeSection4.7.3.1,PCI,HPI,EMIFA and ATA PinMuxing). 0 ATAEN ATA FunctionEnable(seeSection4.7.3.1,PCI,HPI,EMIFA and ATA PinMuxing). (1) IPD = Internalpulldown,IPU = Internalpullup.Formore detailedinformationon pullup/pulldownresistorsand situationswhere external pullup/pulldownresistorsarerequired,see Section4.8.1,Pullup/PulldownResistors.

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4.7.2.2 PINMUX1 RegisterDescription

The PinMultiplexing1 RegistercontrolsthepinfunctionintheUART0, UART1, and UART2 Blocks.The PINMUX1 registerformatisshown inFigure4-19 and thebitfielddescriptionsare giveninTable4-23. Some muxed pinsarecontrolledby more thanone PINMUX bitfield.For thecombinationofthePINMUX bitfieldsthatcontroleach muxed pin,see Section4.7.3, Pin MultiplexingDetails. For the pin-by-pin muxing controlof the UART0, UART1, and UART2 Blocks,see Section4.7.3.8, UART0 Pin Muxing; 31 16 RESERVED R-0000 0000 0000 0000 15 6 5 4 3 2 1 0 RESERVED UART2CTL UART1CTL UART0CTL R-0000 0000 00 R/W-00 R/W-00 R/W-00 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-19.PINMUX1 Register Table4-23.PINMUX1 RegisterBitDescriptions BIT NAME DESCRIPTION 31:6 RESERVED Reserved.Read returns"0". UART2 PinConfiguration(seeSection4.7.3.10,UART2 PinMuxing). 00 = UART functionwithflowcontrol. 01 = UART functionwithoutflowcontrol.5:4 UART2CTL 10 = IrDA/CIRfunction. 11 = GPIO function. (Individualpinfunctionsmay be overriddenby TSPIMUX, CRGEN0, and CRGEN1 values.) UART1 PinConfiguration(seeSection4.7.3.9,UART1 PinMuxing). 00 = UART functionwithflowcontrol. 01 = UART functionwithoutflowcontrol.3:2 UART1CTL 10 = IrDA/CIRfunction. 11 = GPIO function. (Individualpinfunctionsmay be overriddenby TSPIMUX and TSPOMUX values.) UART0 PinConfiguration(seeSection4.7.3.8,UART0 PinMuxing). 00 = UART functionwithmodem control. 1:0 UART0CTL 01 = UART functionwithoutmodem control. 1x = IrDA/CIRfunction. (Individualpinfunctionsmay be overriddenby TSPOMUX value.) Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 115 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.7.3 Pin MultiplexingDetails

Thissectiondiscusseshow toprogram each Pin Mux Registertoselectthedesiredperipheralfunctions and pinmuxing.See theindividualpinmux sectionsforpinmuxing detailsfora specificmuxed pin. Fordetailson PINMUX0 and PINMUX1 registers,see Section4.7.2,PinMuxing SelectionAfterReset.

4.7.3.1 PCI,HPI,EMIFA, and ATA Pin Muxing

The PCI, HPI, EMIFA, and ATA signalmuxing isdeterminedby the valueof the PCIEN, HPIEN, and ATAEN bitfieldsinthePINMUX0 register.For more detailson theactualpinfunctions,see Table4-24 and Table4-25. Table4-24.PCIEN, HPIEN, and ATAEN Encoding PCIEN HPIEN ATAEN PIN FUNCTIONS 0 0 0 EMIFA 0 0 1 EMIFA (NAND) and ATA 0 1 0 HPI (32-bit) 0 1 1 HPI (16-bit)and ATA 1 x x PCI(1) (1) InPCI mode (PCIEN = 1),theinternalpullups/pulldowns(IPUs/IPDs)aredisabledon allPCI pinsand itisrecommended tohave externalpullupresistorson thePCI_RSV[5:0]pins.See Table4-25forthe actualPCI pinfunctionsand any associatedfootnotes. Table4-25.PCI,HPI,EMIFA, and ATA Pin Muxing PIN FUNCTIONS (WITH PCIEN, HPIEN, ATAEN VALUES) 1xx(1) 010 011 000 001 PCI_CLK GP[10] GP[10] GP[10] GP[10] PCI_IDSEL – HDDIR EM_R/ W HDDIR PCI_DEVSEL HCNTL1 HCNTL1 EM_BA[1] EM_BA[1] PCI_FRAME HINT HINT EM_BA[0] EM_BA[0] PCI_IRDY HRDY HRDY EM_A[17] EM_A[17]/(CLE) PCI_TRDY HHWIL HHWIL EM_A[16] EM_A[16]/(ALE) PCI_STOP HCNTL0 HCNTL0 EM_WE EM_WE PCI_SERR HDS1 HDS1 EM_OE EM_OE PCI_PERR HCS HCS EM_DQM1 EM_DQM1 PCI_PAR HAS HAS EM_DQM0 EM_DQM0 PCI_INTA – – EM_WAIT2 EM_WAIT2/(RDY2/ BSY2) PCI_REQ GP[11] DMARQ EM_CS5 DMARQ PCI_GNT GP[12] DACK EM_CS4 DACK PCI_CBE3 HR/W HR/W EM_CS3 EM_CS3 PCI_CBE2 HDS2 HDS2 EM_CS2 EM_CS2 PCI_CBE1 GP[32] ATA_CS1 EM_A[19] ATA_CS1 PCI_CBE0 GP[33] ATA_CS0 EM_A[18] ATA_CS0 PCI_AD31 HD31 DD15 EM_A[15] DD15 PCI_AD30 HD30 DD14 EM_A[14] DD14 PCI_AD29 HD29 DD13 EM_A[13] DD13 PCI_AD28 HD28 DD12 EM_A[12] DD12 PCI_AD27 HD27 DD11 EM_A[11] DD11 (1) InPCI mode (PCIEN = 1),theinternalpullups/pulldowns(IPUs/IPDs)aredisabledon allPCI pinsand itisrecommended tohave externalpullupresistorson thePCI_RSV[5:0]pins.Formore detailedinformationon externalpullup/pulldownresistors,see Section4.8.1,Pullup/PulldownResistors.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-25.PCI,HPI,EMIFA, and ATA Pin Muxing (continued) PIN FUNCTIONS (WITH PCIEN, HPIEN, ATAEN VALUES) 1xx(1) 010 011 000 001 PCI_AD26 HD26 DD10 EM_A[10] DD10 PCI_AD25 HD25 DD9 EM_A[9] DD9 PCI_AD24 HD24 DD8 EM_A[8] DD8 PCI_AD23 HD23 DD7 EM_A[7] DD7 PCI_AD22 HD22 DD6 EM_A[6] DD6 PCI_AD21 HD21 DD5 EM_A[5] DD5 PCI_AD20 HD20 DD4 EM_A[4] DD4 PCI_AD19 HD19 DD3 EM_A[3] DD3 PCI_AD18 HD18 DD2 EM_A[2] DD2 PCI_AD17 HD17 DD1 EM_A[1] DD1 PCI_AD16 HD16 DD0 EM_A[0] DD0 PCI_AD15 HD15 HD15 EM_D15 EM_D15 PCI_AD14 HD14 HD14 EM_D14 EM_D14 PCI_AD13 HD13 HD13 EM_D13 EM_D13 PCI_AD12 HD12 HD12 EM_D12 EM_D12 PCI_AD11 HD11 HD11 EM_D11 EM_D11 PCI_AD10 HD10 HD10 EM_D10 EM_D10 PCI_AD9 HD9 HD9 EM_D9 EM_D9 PCI_AD8 HD8 HD8 EM_D8 EM_D8 PCI_AD7 HD7 HD7 EM_D7 EM_D7 PCI_AD6 HD6 HD6 EM_D6 EM_D6 PCI_AD5 HD5 HD5 EM_D5 EM_D5 PCI_AD4 HD4 HD4 EM_D4 EM_D4 PCI_AD3 HD3 HD3 EM_D3 EM_D3 PCI_AD2 HD2 HD2 EM_D2 EM_D2 PCI_AD1 HD1 HD1 EM_D1 EM_D1 PCI_AD0 HD0 HD0 EM_D0 EM_D0 PCI_RST GP[13] DA2 EM_A[22] DA2 PCI_RSV0 (2) GP[16] DA1 EM_A[21] DA1 PCI_RSV1 (2) GP[17] DA0 EM_A[20] DA0 PCI_RSV2 (2) GP[18] INTRQ EM_RSV0 INTRQ PCI_RSV3 (2) GP[19] DIOR EM_WAIT5/(RDY5/ BSY5) DIOR PCI_RSV4 (2) GP[20] DIOW EM_WAIT4/(RDY4/ BSY4) DIOW PCI_RSV5 (2) GP[21] IORDY EM_WAIT3/(RDY3/ BSY3) IORDY (2) InPCI mode (PCIEN = 1),theinternalpullups/pulldowns(IPUs/IPDs)aredisabledon allPCI pinsand itisrecommended tohave externalpullupresistorson thePCI_RSV[5:0]pins.Formore detailedinformationon externalpullup/pulldownresistors,see Section4.8.1,Pullup/PulldownResistors. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 117 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.7.3.2 PWM SignalMuxing

The two PWM outputswillbe configuredas PWM pinfunctionsby default.The PWM functionsmay be overriddenby thesettingsofvariousPINMUX0 bitfieldsas shown inTable4-26and Table4-27. Table4-26.PWM0 Pin Muxing PIN FUNCTION CRGMUX ≠ 10x CRGMUX = 10x TSSOMUX = 11TSSOMUX ≠ 11 TSSOMUX ≠ 11 PWM0 CRG0_PO TS1_ENAO Table4-27.PWM1 Pin Muxing PIN FUNCTION TSSOMUX ≠ 11 TSSOMUX = 11 PWM1 TS1_DOUT

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4.7.3.3 TSIF0 InputSignalMuxing (Serial/Parallel)

The TSIF 0 (TS0)inputsignalshave muxing optionsforbothparallelorserialoperationas configuredby theTPSIMUX bitsas shown inTable4-28. Table4-28.TSIF0 InputPin Muxing TSPIMUX = 0x TSPIMUX = 10 TSPIMUX = 11 (NO TSIF0 SIGNALS ENABLED) (PARALLEL) (SERIAL) TS0_CLKIN TS0_CLKIN TS0_CLKIN VP_DIN15_VSYNC TS0_DIN7 VP_DIN15_VSYNC VP_DIN14_HSYNC TS0_DIN6 VP_DIN14_HSYNC VP_DIN13_FIELD TS0_DIN5 VP_DIN13_FIELD VP_DIN12 TS0_DIN4 VP_DIN12 VP_DIN11 TS0_DIN3 VP_DIN11 VP_DIN10 TS0_DIN2 VP_DIN10 VP_DIN9 TS0_DIN1 VP_DIN9 VP_DIN8 TS0_DIN0 VP_DIN8 URXD1 (1) URXD1 (1) TS0_DIN7 UTXD1 (1) UTXD1 (1) (seeTable4-22— TSPOMUX bit field) (alsosee Table4-35) URTS1 (1) TS0_WAITO TS0_WAITO UCTS1 (1) TS0_EN_WAITO TS0_EN_WAITO URTS2 (2) TS0_PSTIN TS0_PSTIN (1) Functionisdeterminedby UART1CTL bitfieldvalueinthePINMUX0 register. (2) Functionisdeterminedby UART2CTL bitfieldvalueinthePINMUX0 register. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 119 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.7.3.4 TSIF0 Output SignalMuxing (Serial/Parallel)

The TSIF 0 (TS0)outputsignalshave muxing optionsforbothparallelorserialoperationas configuredby theTPSOMUX bitsas shown inTable4-29. Table4-29.TSIF0 Output Pin Muxing TSPOMUX = 0x TSPOMUX = 10 TSPOMUX = 11 (PARALLEL) (SERIAL)UART0CTL = 00 UART0CTL ≠ 00 VP_CLKO3 VP_CLKO3 TS0_CLKO TS0_CLKO VP_DIN7 (1) VP_DIN7 (1) TS0_DOUT7 (1) VP_DIN7 (1) VP_DIN6 (1) VP_DIN6 (1) TS0_DOUT6 (1) VP_DIN6 (1) VP_DIN5 (1) VP_DIN5 (1) TS0_DOUT5 (1) VP_DIN5 (1) VP_DIN4 (1) VP_DIN4 (1) TS0_DOUT4 (1) VP_DIN4 (1) VP_DIN3 (1) VP_DIN3 (1) TS0_DOUT3 (1) VP_DIN3 (1) VP_DIN2 (1) VP_DIN2 (1) TS0_DOUT2 (1) VP_DIN2 (1) VP_DIN1 (1) VP_DIN1 (1) TS0_DOUT1 (1) VP_DIN1 (1) VP_DIN0 (1) VP_DIN0 (1) TS0_DOUT0 (1) VP_DIN0 (1) UDTR0 GP[36] TS0_ENAO TS0_ENAO UDSR0 GP[37] TS0_PSTO TS0_PSTO UDCD0 GP[38] TS0_WAITIN TS0_WAITIN URIN0 GP[8] GP[8] GP[8] URXD1 (2) URXD1 (2) URXD1 (2) (seeTable4-22— TSPIMUX bit field) (alsosee Table4-35) UTXD1 (2) UTXD1 (2) UTXD1 (2) TS0_DOUT7 (1) Functionwillbe overriddenby TSIF1 signalsifTSSIMUX = 11 (PINMUX0 register). (2) Functionisdeterminedby UART1CTL bitfieldvalueinthePINMUX1 register.

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4.7.3.5 TSIF1 InputSignalMuxing (SerialOnly)

The TSIF 1 (TS1)inputsignalshave threemuxing optionsas configuredby theTSSIMUX bitsas shown inTable 4-30. When TSSIMUX = 11, the TSSI data and controlpinsare muxed onto the VP_DIN[7:4] regardlessofthevalueofTSPOMUX. Table4-30.TSIF1 SerialInputPin Muxing TSSIMUX = 00 TSSIMUX = 01 TSSIMUX = 10 TSSIMUX = 11 TS1_CLKIN TS1_CLKIN TS1_CLKIN TS1_CLKIN VP_DIN7/TS0_DOUT7 (1) VP_DIN7/TS0_DOUT7 (1) VP_DIN7/TS0_DOUT7 (1) TS1_DIN VP_DIN6/TS0_DOUT6 (1) VP_DIN6/TS0_DOUT6 (1) VP_DIN6/TS0_DOUT6 (1) TS1_PSTIN VP_DIN5/TS0_DOUT5 (1) VP_DIN5/TS0_DOUT5 (1) VP_DIN5/TS0_DOUT5 (1) TS1_EN_WAITO VP_DIN4/TS0_DOUT4 (1) VP_DIN4/TS0_DOUT4 (1) VP_DIN4/TS0_DOUT4 (1) TS1_WAITO VP_DIN3/TS0_DOUT3 (1) VP_DIN3/TS0_DOUT3 (1) VP_DIN3/TS0_DOUT3 (1) Hi-Z VP_DIN2/TS0_DOUT2 (1) VP_DIN2/TS0_DOUT2 (1) VP_DIN2/TS0_DOUT2 (1) Hi-Z VP_DIN1/TS0_DOUT1 (1) VP_DIN1/TS0_DOUT1 (1) VP_DIN1/TS0_DOUT1 (1) Hi-Z VP_DIN0/TS0_DOUT0 (1) VP_DIN0/TS0_DOUT0 (1) VP_DIN0/TS0_DOUT0 (1) Hi-Z VP_DOUT15 VP_DOUT15 TS1_DIN VP_DOUT15 VP_DOUT14 VP_DOUT14 TS1_PSTIN VP_DOUT14 VP_DOUT13 VP_DOUT13 TS1_EN_WAITO VP_DOUT13 VP_DOUT12 VP_DOUT12 TS1_WAITO VP_DOUT12 URXD0 (2) TS1_DIN URXD0 (2) URXD0 (2) UTXD0 (2) TS1_PSTIN UTXD0 (2) UTXD0 (2) URTS0 (2) TS1_EN_WAITO URTS0 (2) URTS0 (2) UCTS0 (2) USD0 UCTS0 (2) UCTS0 (2) (1) Functionwillbe determinedby TSPOMUX bitfieldvalueinthePINMUX0 register. (2) Functionisdeterminedby UART0CTL bitfieldvalueinthePINMUX1 register Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 121 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.7.3.6 TSIF1 Output SignalMuxing (SerialOnly)

The TSIF 1 (TS1) outputsignalsare muxed witheitherthe VP_DOUT signalsor UART0, UART2, and PWM signalsas selectedby TSSOMUX (PINMUX0 register).The TS1 outputpinmuxing isshown in Table4-31. Table4-31.TSIF1 SerialOutput Pin Muxing PIN FUNCTION TSSOMUX = 0x TSSOMUX = 10 TSSOMUX = 11 VP_CLKIN3 TS1_CLKO TS1_CLKO VP_DOUT11 TS1_DOUT VP_DOUT11 VP_DOUT10 TS1_PSTO VP_DOUT10 VP_DOUT9 TS1_ENAO VP_DOUT9 VP_DOUT8 TS1_WAITIN VP_DOUT8 URIN0/GP8 URIN0/GP8 TS1_WAITIN UCTS2/GP[42]/CRG0_VCXI (2) UCTS2/GP[42]/CRG0_VCXI (2) TS1_PSTO PWM0/CRG0_PO (3) PWM0/CRG0_PO (3) TS1_ENAO PWM1 PWM1 TS1_DOUT (1) Functionwillbe determinedby UART0CTL bitfieldvalueinthePINMUX1 register. (2) Functionwillbe determinedby UART2CTL and CRGMUX bitfieldvaluesinthePINMUX1 and PINMUX0 registers,respectively. (3) Functionwillbe determinedby CRGMUX bitfieldvalueinthePINMUX0 register.

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4.7.3.7 CRGEN SignalMuxing

The two CRGEN modules sharepinswithUART2 and PWM0. The CRGEN functionisselectedusingthe CRGMUX bitfieldinthePINMUX0 register(seeTable4-32). Table4-32.CRG Pin Muxing PIN FUNCTION CRGMUX = 001 CRGMUX = 100 CRGMUX = 101 CRGMUX = 110 CRGMUX = other PWM0 (1) CRG0_PO (1) CRG0_PO (1) PWM0 (1) PWM0 (1) UCTS2 (2)(3) CRG0_VCXI (3) CRG0_VCXI (3) UCTS2 (2)(3) UCTS2 (2)(3) CRG1_VCXI URXD2 (2) CRG1_VCXI CRG0_VCXI URXD2 (2) CRG1_PO UTXD2 (2) CRG1_PO CRG0_PO UTXD2 (2) (1) Functionwillbe overriddenby TS1_ENAO pinifTSSOMUX = 11 (PINMUX0 register). (2) Functionisdeterminedby UART2CTL bitfieldvalueinthePINMUX1 register. (3) Functionwillbe overriddenby TS1_PSTO ifTSSOMUX = 11 (PINMUX0 register). Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 123 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.7.3.8 UART0 Pin Muxing

The UART0 module can operateas eithera UART or IrDA/CIRinterface.The UART0 pin muxing is controlledby the UART0CTL bitfieldin the PINMUX1 registerand the TSPOMUX, TSSIMUX, and TSSOMUX bitfieldsinthePINMUX0 register.Muxing optionsare shown inTable4-33 and Table4-34. When UART operationisselected,UART0CTL must be settoeither‘00’forUART withmodem signalsor ‘01’forUART withoutmodem signals.When IrDA/CIRoperationisselected,UART0CTL must be setto ‘1x’ to use the IrDA/CIRsignalsand the modem signalbecome GPIOs. A TSPOMUX settingof ‘1x’ overridesthemodem controlmux settings.UART0 can stillbe used as a UART withoutmodem controlor inIrDA/CIRmode based on theUART0CTL bitfieldvalue.A TSSIMUX settingof‘01’overridestheUART dataand flowcontrolsettingsand preventsUART0 frombeingused.The UART0 modem controlpinsmay be used as eitherTSIF 0 outputor GPIO pinsbased on the TSPOMUX and UART0CTL settings.A TSSOMUX settingof‘11’overridestheRIN functionwiththeTS1_WAITIN function. Table4-33.UART0 Pin Muxing — Part1 PIN FUNCTIONS UTXD0/ URTS0 /TSSIMUX[1] TSSIMUX[0] UART0CTL[1] UART0CTL[0] URXD0/ UCTS0 /URCTX0/ UIRTX0/TS1_DIN USD0TS1_PSTIN TS1_EN_WAITO 0 0 0 0 URXD0 UTXD0 URTS0 UCTS0 0 0 0 1 URXD0 UTXD0 URTS0 UCTS0 0 0 1 0 URXD0 URCTX0 UIRTX0 USD0 0 0 1 1 URXD0 URCTX0 UIRTX0 USD0 0 1 0 0 TS1_DIN TS1_PSTIN TS1_EN_WAITO – 0 1 0 1 TS1_DIN TS1_PSTIN TS1_EN_WAITO – 0 1 1 0 TS1_DIN TS1_PSTIN TS1_EN_WAITO – 0 1 1 1 TS1_DIN TS1_PSTIN TS1_EN_WAITO – 1 x 0 0 URXD0 UTXD0 URTS0 UCTS0 1 x 0 1 URXD0 UTXD0 URTS0 UCTS0 1 x 1 0 URXD0 URCTX0 UIRTX0 USD0 1 x 1 1 URXD0 URCTX0 UIRTX0 USD0

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-34.UART0 Pin Muxing — Part2 PIN FUNCTIONS UDTR0 / UDSR0 / UDCD0 / URIN0/TSSOMUX[1] TSSOMUX[0] TSPOMUX[1] TSPOMUX[0] UART0CTL[1] UART0CTL[0] TS0_ENAO/ TS0_PSTO/ TS0_WAITIN/ GP[8]/ GP[36] GP[37] GP[38] TS1_WAITIN 0 x 0 x 0 0 UDTR0 UDSR0 UDCD0 URIN0 0 x 0 x 0 1 GP[36] GP[37] GP[38] GP[8] 0 x 0 x 1 0 GP[36] GP[37] GP[38] GP[8] 0 x 0 x 1 1 GP[36] GP[37] GP[38] GP[8] 0 x 1 x 0 0 TS0_ENAO TS0_PSTO TS0_WAITIN GP[8] 0 x 1 x 0 1 TS0_ENAO TS0_PSTO TS0_WAITIN GP[8] 0 x 1 x 1 0 TS0_ENAO TS0_PSTO TS0_WAITIN GP[8] 0 x 1 x 1 1 TS0_ENAO TS0_PSTO TS0_WAITIN GP[8] 1 0 0 x 0 0 UDTR0 UDSR0 UDCD0 URIN0 1 0 0 x 0 1 GP[36] GP[37] GP[38] GP[8] 1 0 0 x 1 0 GP[36] GP[37] GP[38] GP[8] 1 0 0 x 1 1 GP[36] GP[37] GP[38] GP[8] 1 0 1 x 0 0 TS0_ENAO TS0_PSTO TS0_WAITIN GP[8] 1 0 1 x 0 1 TS0_ENAO TS0_PSTO TS0_WAITIN GP[8] 1 0 1 x 1 0 TS0_ENAO TS0_PSTO TS0_WAITIN GP[8] 1 0 1 x 1 1 TS0_ENAO TS0_PSTO TS0_WAITIN GP[8] 1 1 0 x 0 0 UDTR0 UDSR0 UDCD0 TS1_WAITIN 1 1 0 x 0 1 GP[36] GP[37] GP[38] TS1_WAITIN 1 1 0 x 1 0 GP[36] GP[37] GP[38] TS1_WAITIN 1 1 0 x 1 1 GP[36] GP[37] GP[38] TS1_WAITIN 1 1 1 x 0 0 TS0_ENAO TS0_PSTO TS0_WAITIN TS1_WAITIN 1 1 1 x 0 1 TS0_ENAO TS0_PSTO TS0_WAITIN TS1_WAITIN 1 1 1 x 1 0 TS0_ENAO TS0_PSTO TS0_WAITIN TS1_WAITIN 1 1 1 x 1 1 TS0_ENAO TS0_PSTO TS0_WAITIN TS1_WAITIN Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 125 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.7.3.9 UART1 Pin Muxing

The UART1 module can operateas eithera UART orIrDA/CIRinterface.The UART1 pinmuxing options are shown inTable 4-35. When UART operationisselected,UART1CTL must be setto either‘00’for UART withflowcontrolor‘01’forUART withoutflowcontrolsignals.When IrDA/CIRoperationisselected, UART1CTL must be setto‘10’touse theIrDA/CIRsignals.IfUART1 isunused,thensettingUART1CTL = 11 muxes GPIO functionontoallthepins.The UART1 pinfunctionsmay be overriddenbased on the settingsofTSPIMUX and TSPOMUX Table4-35.UART1 Pin Muxing PIN FUNCTIONS UTXD1/ URTS1 / UCTS1 /URXD1/TSPIMUX[1] TSPIMUX[0] TSPOMUX[1] TSPOMUX[0] UART1CTL[1] UART1CTL[0] URCTX1/ UIRTX1/ USD1/TS0_DIN7/ TS0_DOUT7/ TS0_WAITO/ TS0_EN_WAITO/GP[23] GP[24] GP[25] GP[26] 0 x 0 x 0 0 URXD1 UTXD1 URTS1 UCTS1 0 x 0 x 0 1 URXD1 UTXD1 GP[25] GP[26] 0 x 0 x 1 0 URXD1 URCTX1 UIRTX1 USD1 0 x 0 x 1 1 GP[23] GP[24] GP[25] GP[26] 0 x 1 0 0 0 URXD1 UTXD1 URTS1 UCTS1 0 x 1 0 0 1 URXD1 UTXD1 GP[25] GP[26] 0 x 1 0 1 0 URXD1 URCTX1 UIRTX1 USD1 0 x 1 0 1 1 GP[23] GP[24] GP[25] GP[26] 0 x 1 1 0 0 URXD1 TS0_DOUT7 URTS1 UCTS1 0 x 1 1 0 1 URXD1 TS0_DOUT7 GP[25] GP[26] 0 x 1 1 1 0 URXD1 TS0_DOUT7 UIRTX1 USD1 0 x 1 1 1 1 GP[23] TS0_DOUT7 GP[25] GP[26] 1 0 0 x 0 x URXD1 UTXD1 TS0_WAITO TS0_EN_WAITO 1 0 0 x 1 0 URXD1 URCTX1 TS0_WAITO TS0_EN_WAITO 1 0 0 x 1 1 GP[23] GP[24] TS0_WAITO TS0_EN_WAITO 1 0 1 0 0 x URXD1 UTXD1 TS0_WAITO TS0_EN_WAITO 1 0 1 0 1 0 URXD1 URCTX1 TS0_WAITO TS0_EN_WAITO 1 0 1 0 1 1 GP[23] GP[24] TS0_WAITO TS0_EN_WAITO 1 0 1 1 0 x URXD1 TS0_DOUT7 TS0_WAITO TS0_EN_WAITO 1 0 1 1 1 0 URXD1 TS0_DOUT7 TS0_WAITO TS0_EN_WAITO 1 0 1 1 1 1 GP[23] TS0_DOUT7 TS0_WAITO TS0_EN_WAITO 1 1 0 x 0 x TS0_DIN7 UTXD1 TS0_WAITO TS0_EN_WAITO 1 1 0 x 1 0 TS0_DIN7 URCTX1 TS0_WAITO TS0_EN_WAITO 1 1 0 x 1 1 TS0_DIN7 GP[24] TS0_WAITO TS0_EN_WAITO 1 1 1 0 0 x TS0_DIN7 UTXD1 TS0_WAITO TS0_EN_WAITO 1 1 1 0 1 0 TS0_DIN7 URCTX1 TS0_WAITO TS0_EN_WAITO 1 1 1 0 1 1 TS0_DIN7 GP[24] TS0_WAITO TS0_EN_WAITO 1 1 1 1 x x TS0_DIN7 TS0_DOUT7 TS0_WAITO TS0_EN_WAITO

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 4.7.3.10UART2 Pin Muxing The UART2 module can operateas eithera UART orIrDA/CIRinterface.The UART2 pinmuxing options areshown inTable4-36throughTable4-38.When UART operationisselected,UART2CTL must be set to either‘00’forUART withflowcontrolor ‘01’forUART withoutflowcontrolsignals.When IrDA/CIR operationisselected,UART2CTL must be setto‘10’touse theIrDA/CIRsignals.IfUART2 isunused, thensettingUART2CTL = 11 muxes GPIO functionontoallthepins.The UART2 pinfunctionsmay be overriddenbased on thesettingsofTSPIMUX, CRGMUX, and TSSOMUX. Table4-36.UART2 Data Pin Muxing PIN FUNCTIONS UTXD2/URXD2/ URCTX2/CRGMUX[2] CRGMUX[1] CRGMUX[0] UART2CTL[1] UART2CTL[0] CRG1_VCXI/ CRG1_PO/GP[39]/ GP[40]/CRG0_VCXI CRG0_PO 0 0 0 0 0 URXD2 UTXD2 0 0 0 0 1 URXD2 UTXD2 0 0 0 1 0 URXD2 URCTX2 0 0 0 1 1 GP[39] GP[40] 0 0 1 0 0 CRG1_VCXI CRG1_PO 0 0 1 0 1 CRG1_VCXI CRG1_PO 0 0 1 1 0 CRG1_VCXI CRG1_PO 0 0 1 1 1 CRG1_VCXI CRG1_PO 0 1 0 0 0 URXD2 UTXD2 0 1 0 0 1 URXD2 UTXD2 0 1 0 1 0 URXD2 URCTX2 0 1 0 1 1 GP[39] GP[40] 0 1 1 0 0 URXD2 UTXD2 0 1 1 0 1 URXD2 UTXD2 0 1 1 1 0 URXD2 URCTX2 0 1 1 1 1 GP[39] GP[40] 1 0 0 0 0 URXD2 UTXD2 1 0 0 0 1 URXD2 UTXD2 1 0 0 1 0 URXD2 URCTX2 1 0 0 1 1 GP[39] GP[40] 1 0 1 0 0 CRG1_VCXI CRG1_PO 1 0 1 0 1 CRG1_VCXI CRG1_PO 1 0 1 1 0 CRG1_VCXI CRG1_PO 1 0 1 1 1 CRG1_VCXI CRG1_PO 1 1 0 0 0 CRG0_VCXI CRG0_PO 1 1 0 0 1 CRG0_VCXI CRG0_PO 1 1 0 1 0 CRG0_VCXI CRG0_PO 1 1 0 1 1 CRG0_VCXI CRG0_PO 1 1 1 0 0 URXD2 UTXD2 1 1 1 0 1 URXD2 UTXD2 1 1 1 1 0 URXD2 URCTX2 1 1 1 1 1 GP[39] GP[40] Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 127 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table4-37.UART2 Ready-to-Send(URTS2 )Pin Muxing PIN FUNCTION URTS2 / TSPIMUX[1] TSPIMUX[0] UART2CTL[1] UART2CTL[0] UIRTX2/ TS0_PSTIN/ GP[41] 0 x 0 0 URTS2 0 x 0 1 GP[41] 0 x 1 0 UIRTX2 0 x 1 1 GP[41] 1 x x x TS0_PSTIN Table4-38.UART2 Clear-to-Send(UCTS2 )Pin Muxing PIN PINTSSOMUX ≠ 11 TSSOMUX = 11FUNCTION FUNCTION UCTS2 / UCTS2 / USD2/ USD2/ CRGMUX[2] CRGMUX[1] CRGMUX[0] UART2CTL[1] UART2CTL[0] CRG0_VCXI/ CRGMUX[2] CRGMUX[1] CRGMUX[0] UART2CTL[1] UART2CTL[0] CRG0_VCXI/ GP[42]/ GP[42]/ TS1_PSTO TS1_PSTO 0 0 0 0 0 UCTS2 0 0 0 0 0 TS1_PSTO 0 0 0 0 1 GP[42] 0 0 0 0 1 TS1_PSTO 0 0 0 1 0 USD2 0 0 0 1 0 TS1_PSTO 0 0 0 1 1 GP[42] 0 0 0 1 1 TS1_PSTO 0 0 1 0 0 UCTS2 0 0 1 0 0 TS1_PSTO 0 0 1 0 1 GP[42] 0 0 1 0 1 TS1_PSTO 0 0 1 1 0 USD2 0 0 1 1 0 TS1_PSTO 0 0 1 1 1 GP[42] 0 0 1 1 1 TS1_PSTO 0 1 0 0 0 UCTS2 0 1 0 0 0 TS1_PSTO 0 1 0 0 1 GP[42] 0 1 0 0 1 TS1_PSTO 0 1 0 1 0 USD2 0 1 0 1 0 TS1_PSTO 0 1 0 1 1 GP[42] 0 1 0 1 1 TS1_PSTO 0 1 1 0 0 UCTS2 0 1 1 0 0 TS1_PSTO 0 1 1 0 1 GP[42] 0 1 1 0 1 TS1_PSTO 0 1 1 1 0 USD2 0 1 1 1 0 TS1_PSTO 0 1 1 1 1 GP[42] 0 1 1 1 1 TS1_PSTO 1 0 0 0 0 CRG0_VCXI 1 0 0 0 0 TS1_PSTO 1 0 0 0 1 CRG0_VCXI 1 0 0 0 1 TS1_PSTO 1 0 0 1 0 CRG0_VCXI 1 0 0 1 0 TS1_PSTO 1 0 0 1 1 CRG0_VCXI 1 0 0 1 1 TS1_PSTO 1 0 1 0 0 CRG0_VCXI 1 0 1 0 0 TS1_PSTO 1 0 1 0 1 CRG0_VCXI 1 0 1 0 1 TS1_PSTO 1 0 1 1 0 CRG0_VCXI 1 0 1 1 0 TS1_PSTO 1 0 1 1 1 CRG0_VCXI 1 0 1 1 1 TS1_PSTO 1 1 0 0 0 UCTS2 1 1 0 0 0 TS1_PSTO 1 1 0 0 1 GP[42] 1 1 0 0 1 TS1_PSTO 1 1 0 1 0 USD2 1 1 0 1 0 TS1_PSTO 1 1 0 1 1 GP[42] 1 1 0 1 1 TS1_PSTO 1 1 1 0 0 UCTS2 1 1 1 0 0 TS1_PSTO 1 1 1 0 1 GP[42] 1 1 1 0 1 TS1_PSTO 1 1 1 1 0 USD2 1 1 1 1 0 TS1_PSTO 1 1 1 1 1 GP[42] 1 1 1 1 1 TS1_PSTO

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 4.7.3.11SmartReflexand GPIO Pin Muxing The SmartReflexand GPIO signalmuxing isdeterminedby thevalueoftheVADJEN pin(AB7)atreset. For more detailson the actualpin functions,see Table 4-39. For more detailedinformationon SmartReflex,see Section7.3.6,SmartReflex(VoltageScaling). Table4-39.SmartReflexand GPIO Pin Muxing PIN FUNCTION VADJEN = 0 VADJEN = 1 SmartReflexDisabled. SmartReflexControlOutputs Enabled GP[7]and GP[6] CVDDADJ[1:0] 00 = deviceoperatesat1.2V corepower supplyonly(-594V,-594AV devciesonly) 11 = devicecan operateat1.05V corepower supply(-594V,-594AV devciesonly) AllothersettingsRESERVED. The valueofthesepinsisalsostoredintheSmartReflexStatusRegister(SMTREFLEX) [seeFigure7- 7]. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 129 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 4.7.3.12ARM/DSP Communications Interrupts The systemmodule includesregistersforgeneratinginterruptsbetween theARM and DSP. The DSPINT registershows the statusof the ARM-to-DSP interrupts.The DSPINT registerformatis shown inFigure4-20.Table4-40describestheregisterbitfields.The ARM may generatean interruptto the DSP by settingone of the fourINTDSP[3:0]bitsor by settingthe INTNMI bitinthe DSPINTSET pseudo-register(see Figure 4-21). The interruptset bit then self-clearsand the corresponding INTDSP[3:0]or INTNMI bitintheDSPINT statusregister(seeFigure4-20)isautomaticallysettoindicate thattheinterruptwas generated.Afterservicingtheinterrupt,theDSP clearsthestatusbitby writing‘1’to thecorrespondingbitintheDSPINTCLR register(seeFigure4-22).The ARM may pollthestatusbitto determinewhen theDSP has completedtheinterruptservice. The DSP may generatean interruptto the ARM in the same manner using the ARMINTSET and ARMINTCLR registersshown/describedin Figure 4-24, Table 4-44, and Figure 4-25, Table 4-45, respectively.The DSP can then view the statusof the DSP-to-ARM interruptsviathe ARMINT register shown/describedinFigure4-23and Table4-43. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTNMI Reserved INTDSP3 INTDSP2 INTDSP1 INTDSP0 R-0000 000 R-0 R-0000 R-0 R-0 R-0 R-0 LEGEND: R = Read only,n = Valueatreset Figure4-20.DSPINT StatusRegister[0x01C4 0060] Table4-40.DSPINT StatusRegisterBitDescriptions(1) BIT NAME DESCRIPTION 31:9 Reserved Reserved.A readreturns0.

8 INTNMI DSP NMI Status

7:4 Reserved Reserved.A readreturns0.

3 INTDSP3 ARM-to-DSP Int3Status

2 INTDSP2 ARM-to-DSP Int2Status

1 INTDSP1 ARM-to-DSP Int1Status

0 INTDSP0 ARM-to-DSP Int0Status

(1) Read only,writeshave no effect.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTNMI Reserved INTDSP3 INTDSP2 INTDSP1 INTDSP0 R-0000 000 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write,n = Valueatreset Figure4-21.DSPINTSET Register[0x01C4 0064] Table4-41.DSPINTSET RegisterBitDescriptions BIT NAME DESCRIPTION 31:9 Reserved Reserved.A readreturns0.

8 INTNMI DSP NMI Set(1)

7:4 Reserved Reserved.A readreturns0.

3 INTDSP3 ARM-to-DSP Int3Set(1)

2 INTDSP2 ARM-to-DSP Int2Set(1)

1 INTDSP1 ARM-to-DSP Int1Set(1)

0 INTDSP0 ARM-to-DSP Int0Set(1)

(1) Writinga '1'generatestheinterruptand setsthecorrespondingbitintheDSPINT statusregister.The registerbitautomaticallyclearsto a valueof'0'.Writinga '0'has no effect.Thisregisteralwaysreadsas '0'. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTNMI Reserved INTDSP3 INTDSP2 INTDSP1 INTDSP0 R-0000 000 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write,n = Valueatreset Figure4-22.DSPINTCLR Register[0x01C4 0068] Table4-42.DSPINTCLR RegisterBitDescriptions BIT NAME DESCRIPTION 31:9 Reserved Reserved.A readreturns0.

8 INTNMI DSP NMI Clear(1)

7:4 Reserved Reserved.A readreturns0.

3 INTDSP3 ARM-to-DSP Int3Clear(1)

2 INTDSP2 ARM-to-DSP Int2Clear(1)

1 INTDSP1 ARM-to-DSP Int1Clear(1)

0 INTDSP0 ARM-to-DSP Int0Clear(1)

(1) Writinga '1'clearsthecorrespondingbitintheDSPINT statusregister.The registerbitautomaticallyclearstoa valueof'0'.Writinga '0' has no effect.Thisregisteralwaysreadsas '0'. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 131 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTARM0 R-0000 0000 0000 000 R-0 LEGEND: R = Read only,n = Valueatreset Figure4-23.ARMINT StatusRegister[0x01C4 0070] Table4-43.ARMINT StatusRegisterBitDescriptions(1) BIT NAME DESCRIPTION 31:1 Reserved Reserved.A readreturns0.

0 INTARM0 DSP-to-ARM Int0Status

(1) Read only,writeshave no effect. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTARM0 R-0000 0000 0000 000 R/W-0 LEGEND: R = Read, W = Write,n = Valueatreset Figure4-24.ARMINTSET Register[0x01C4 0074] Table4-44.ARMINTSET RegisterBitDescriptions BIT NAME DESCRIPTION 31:1 Reserved Reserved.A readreturns0.

0 INTARM0 DSP-to-ARM Int0Set(1)

(1) Writinga '1'generatestheinterruptand setsthecorrespondingbitintheARMINT statusregister.The registerbitautomaticallyclearsto a valueof'0'.Writinga '0'has no effect.Thisregisteralwaysreadsas '0'.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTARM0 R-0000 0000 0000 000 R/W-0 LEGEND: R = Read, W = Write,n = Valueatreset Figure4-25.ARMINTCLR Register[0x01C4 0078] Table4-45.ARMINTCLR RegisterBitDescriptions BIT NAME DESCRIPTION 31:1 Reserved Reserved.A readreturns0.

0 INTARM0 DSP-to-ARM Int0Clear(1)

(1) Writinga '1'clearsthecorrespondingbitintheARMINT statusregister.The registerbitautomaticallyclearstoa valueof'0'.Writinga '0' has no effect.Thisregisteralwaysreadsas '0'. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 133 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 4.7.3.13EmulationControl The flexibilityof the DM646x DMSoC architectureallowseitherthe ARM or DSP to controlthe various peripherals(setupregisters,serviceinterrupts,etc.).Whilethisassignmentispurelya matterofsoftware convention,duringan emulationhaltitis necessary forthe device to know which peripheralsare associatedwiththehaltingprocessorso thatonlythosemodules receivethesuspend signal.Thisallows peripheralsassociatedwiththeother(unhalted)processortocontinuenormaloperation.The SUSPSRC registerindicatestheemulationsuspend sourceforthoseperipheralswhichsupportemulationsuspend. The SUSPSRC registerformatisshown inFigure4-26.Briefdetailson theperipheralswhichcorrespond to the registerbitsare listedinTable 4-46. When the associatedSUSPSRC bitis‘0’, the peripheral’s emulationsuspend signaliscontrolledby theARM emulatorand when setto‘1’itiscontrolledby theDSP emulator. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRGEN1 CRGEN0 TIMR2 TIMR1 TIMR0 GPIO PWM1 PWM0 SPI UART2 UART1 UART0 I2C MCASP1 MCASP0RSVSRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 13 12 11 10 9 8 7 6 5 4 3 0 HPI EMAC USB VDCE TSIF1 TSIF0 VPIFRESERVED RSV RSV RESERVEDSRC SRC SRC SRC SRC SRC SRC R-000 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R-0000 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Figure4-26.SUSPSRC Register Table4-46.SUSPSRC RegisterBitDescriptions BIT NAME DESCRIPTION ClockRecoveryGenerator1 EmulationSuspend Source. 31 CRGEN1SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. ClockRecoveryGenerator0 EmulationSuspend Source. 30 CRGEN0SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. Timer2(WD Timer)EmulationSuspend Source. 29 TIMR2SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. Timer1EmulationSuspend Source. 28 TIMR1SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. Timer0EmulationSuspend Source. 27 TIMR0SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. GPIO EmulationSuspend Source. 26 GPIOSRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. 25 RSV Reserved.Read returns"0". PWM1 EmulationSuspend Source. 24 PWM1SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. PWM0 EmulationSuspend Source. 23 PWM0SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. SPI EmulationSuspend Source. 22 SPISRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. UART2 EmulationSuspend Source. 21 UART2SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table4-46.SUSPSRC RegisterBitDescriptions(continued) BIT NAME DESCRIPTION UART1 EmulationSuspend Source. 20 UART1SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. UART0 EmulationSuspend Source. 19 UART0SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. I2C EmulationSuspend Source. 18 I2CSRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. McASP1 EmulationSuspend Source. 17 MCASP1SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. McASP0 EmulationSuspend Source. 16 MCASP0SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. 15:13 RESERVED Reserved.Read returns"0". HPI EmulationSuspend Source. 12 HPISRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. 11 RSV Reserved.Read returns"0". EthernetMAC EmulationSuspend Source. 10 EMACSRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. USB EmulationSuspend Source. 9 USBSRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. VDCE EmulationSuspend Source. 8 VDCESRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. TSIF1 EmulationSuspend Source. 7 TSIF1SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. TSIF0 EmulationSuspend Source. 6 TSIF0SRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. 5 RSV Reserved.Read returns"0". VideoPortEmulationSuspend Source. 4 VPIFSRC 0 = ARM emulationsuspend. 1 = DSP emulationsuspend. 3:0 RESERVED Reserved.Read returns"0". Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceConfigurations 135 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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4.8 Debugging Considerations

4.8.1 Pullup/PulldownResistors

ProperboarddesignshouldensurethatinputpinstotheTMS320DM646x DMSoC devicealwaysbe ata validlogicleveland notfloating.Thismay be achievedviapullup/pulldownresistors.The TMS320DM646x DMSoC featuresinternalpullup(IPU)and internalpulldown(IPD)resistorson most pinstoeliminatethe need,unlessotherwisenoted,forexternalpullup/pulldownresistors. An externalpullup/pulldownresistorneeds tobe used inthefollowingsituations:

Boot and ConfigurationPins: Ifthe pin is both routedout and 3-stated(notdriven),an external pullup/pulldownresistoris strongly recommended , even ifthe IPU/IPD matches the desired value/state.
Other Input Pins: If the IPU/IPD does not match the desired value/state,use an external pullup/pulldownresistortopullthesignaltotheoppositerail. For thebootand configurationpins(listedinTable3-5,Boot TerminalFunctions),iftheyarebothrouted out and 3-stated(notdriven),itisstronglyrecommended thatan externalpullup/pulldownresistorbe implemented.Although,internalpullup/pulldownresistorsexiston thesepinsand theymay match the desiredconfigurationvalue,providingexternalconnectivitycan help ensure thatvalidlogiclevelsare latchedon these device boot and configurationpins.In addition,applyingexternalpullup/pulldown resistorson thebootand configurationpinsadds conveniencetotheuserindebuggingand flexibilityin switchingoperatingmodes. Tipsforchoosingan externalpullup/pulldownresistor:
Considerthetotalamount ofcurrentthatmay pass throughthepulluporpulldownresistor.Make sure toincludetheleakagecurrentsofallthedevicesconnectedtothenet,as wellas any internalpullupor pulldownresistors.
Decidea targetvalueforthenet.For a pulldownresistor,thisshouldbe below thelowestVIL levelof allinputsconnectedtothenet.For a pullupresistor,thisshouldbe above thehighestVIH levelofall inputson thenet.A reasonablechoicewould be totargettheVOL orVOH levelsforthelogicfamilyof thelimitingdevice;which,by definition,have margintotheVIL and VIH levels.
Selecta pullup/pulldownresistorwiththelargestpossiblevalue;but,whichcan stillensurethatthenet willreachthetargetpulledvaluewhen maximum currentfromalldeviceson thenetisflowingthrough the resistor.The currentto be consideredincludesleakage currentplus,any otherinternaland externalpullup/pulldownresistorson thenet.
For bidirectionalnets,thereisan additionalconsiderationwhich setsa lowerlimiton the resistance valueoftheexternalresistor.Verifythattheresistanceissmallenough thattheweakestoutputbuffer can drivethenettotheoppositelogiclevel(includingmargin).
Remember toincludetoleranceswhen selectingtheresistorvalue.
Forpullupresistors,alsoremember toincludetoleranceson theDV DD rail. For most systems,a 1-kΩ resistorcan be used tooppose theIPU/IPDwhilemeetingtheabove criteria. Usersshouldconfirmthisresistorvalueiscorrectfortheirspecificapplication. For most systems,a 20-kΩ resistorcan be used tocomplimenttheIPU/IPDon thebootand configuration pinswhilemeetingtheabove criteria.Users shouldconfirmthisresistorvalueiscorrectfortheirspecific application. For most systems,a 20-kΩ resistorcan also be used as an externalPU/PD on the pins thathave IPUs/IPDsdisabledand requirean externalPU/PD resistorwhilestillmeetingthe above criteria.Users shouldconfirmthisresistorvalueiscorrectfortheirspecificapplication. For more detailedinformationon inputcurrent(II),and thelow-/high-levelinputvoltages(VIL and VIH)for theDM6467 DMSoC, see Section6.3,ElectricalCharacteristicsOver Recommended Ranges ofSupply Voltageand OperatingTemperature.

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5 System Interconnect

On the DM6467 device,the C64x+ megamodule, the ARM subsystem,the EDMA3 transfercontrollers, and the system peripheralsare interconnectedthrougha switchfabricarchitecture.The switchfabricis composed ofmultipleswitchedcentralresources(SCRs) and multiplebridges. For more detailedinformationon the DMSoC System InterconnectArchitecture,includingthe device- specificSCRs, bridges,and thesystem connectionmatrix,see theTMS320DM6467 SoC Architectureand ThroughputOverviewApplicationReport(literaturenumber SPRAAW4).

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6 Device OperatingConditions

6.1 AbsoluteMaximum RatingsOver OperatingCase Temperature Range (Unless

OtherwiseNoted)(1) Supplyvoltageranges: Core (CVDD ,DEV_CV DD ,AUX_CV DD )(2) –0.5V to1.5V I/O,3.3V(DVDD33 ,USB_V DDA3P3 )(2) –0.3V to3.8V I/O,1.8V(DVDDR2 ,PLL1V DD18 ,PLL2V DD18 ,DEV_DV DD18 ,AUX_DV DD18 , –0.3V to2.6V USB_V DD1P8 )(2) Inputand Outputvoltageranges: –0.3V to3.8V V I/O,3.3-Vpins(exceptPCI-capablepins) –0.3V toDV DD33 + 0.3V –0.5V to4.2V V I/O,3.3-VpinsPCI-capablepins –0.5V toDV DD33 + 0.5V –0.3V to2.6V V I/O,1.8V –0.3V toDV DD18 + 0.3V Operatingcase temperature (default)[-594,-729] 0°C to85°C ranges,Tc: (A version)ExtendedTemperature[-594A,-594AV only] -40°C to105°C (D version)IndustrialTemperature[-729Donly] -40°C to85°C Storagetemperaturerange,Tstg (default) –55°C to150°C ElectrostaticDischarge(ESD) ESD-HBM (Human Body Model)(3) ± 2000 V Performance: ESD-CDM (Charged-DeviceModel)DDR2 (SiliconRevision1.1and ± 150 V Pins(4) 1.0) (SiliconRevision3.0) ± 500 V ESD-CDM (Charged-DeviceModel)– allpinsexceptDDR2 pins(4) ± 500 V (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagevaluesarewithrespecttoVSS. (3) Based on JEDEC JESD22-A114E (ElectrostaticDischarge(ESD) SensitivityTestingHuman Body Model (HBM)). (4) Based on JEDEC JESD22-C101C (Field-InducedCharged-DeviceModel TestMethod forElectrostatic-Discharge-WithstandThresholds ofMicroelectronicComponents). Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOperatingConditions 139 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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6.2 Recommended OperatingConditions

NORM 1.14 1.2 1.26 V SmartReflex 1.14 1.2 1.26 VSupplyvoltage,Core (CVDD ,DEV_CV DD ,CV DD [-594V,-594AVAUX_CV DD ) (1) only] 1.00 1.05 1.1 V [seeTable4-39] Supplyvoltage,I/O,3.3V(DVDD33 ,USB_V DDA3P3 ) 3.14 3.3 3.46 V DV DD Supplyvoltage,I/O,1.8V(DVDDR2 ,PLL1V DD18 ,PLL2V DD18 , 1.71 1.8 1.89 VDEV_DV DD18 ,AUX_DV DD18 ,USB_V DD1P8 (2)) Supplyground(VSS ,PLL1V SS ,PLL2V SS ,DEV_V SS (3),AUX_V SSVSS 0 0 0 V(3),USB_V SSREF ) DDR_VREF DDR2 referencevoltage(4) 0.49DVDDR2 0.5DVDDR2 0.51DVDDR2 V DDR2 impedance control,connectedvia50-Ω (±5% tolerance)DDR_ZP VSS VresistortoVSS DDR2 impedance control,connectedvia50-Ω (±5% tolerance)DDR_ZN DV DDR2 VresistortoDV DDR2 High-levelinputvoltage,3.3V (exceptJTAG[TCK],PCI-capable, 2 Vand I2C pins) High-levelinputvoltage,JTAG [TCK] 2.5 V VIH High-levelinputvoltage,PCI 0.5DVDD33 V High-levelinputvoltage,I2C 0.7DVDD33 V High-levelinputvoltage,non-DDR I/O,1.8V 0.65DVDD18 V Low-levelinputvoltage,3.3V (exceptPCI-capableand I2C pins) 0.8 V Low-levelinputvoltage,PCI 0.3DVDD33 V VIL Low-levelinputvoltage,I2C 0 0.3DVDD33 V Low-levelinputvoltage,non-DDR I/O,1.8V 0.35DVDD18 V Default 0 85 Tc Operatingcase temperature (A version) -40 105 °C (D version) -40 85 -594 20 594 MHz FSYSCLK1 DSP OperatingFrequency(SYSCLK1) -729 20 729 MHz (1) FuturevariantsofTISoC devicesmay operateatvoltagesrangingfrom0.9V to1.4V toprovidea rangeofsystempower/performance 1.1V,1.14V,1.2V,1.26V with± 3% tolerances)by implementingsimpleboardchanges such as referenceresistorvaluesorinputpin configurationmodifications.Not incorporatinga flexiblesupplymay limitthesystem's abilitytoeasilyadapttofutureversionsofTISoC devices. (2) Oscillator1.8V power supply(DEV_DV DD18 )can be connectedtothesame 1.8V power supplyas DV DDR2 . (3) Oscillatorground(DEV_V SS and AUX_V SS )must be keptseparatefromothergroundsand connecteddirectlytothecrystalload capacitorground. (4) DDR_VREF isexpectedtoequal0.5DVDDR2 ofthetransmittingdeviceand totrackvariationsintheDV DDR2 .

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6.3 ElectricalCharacteristicsOver Recommended Ranges ofSupply Voltageand

OperatingTemperature (UnlessOtherwiseNoted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Low/fullspeed:USB_DN and USB_DP 2.8 USB_V DDA3P3 V Highspeed:USB_DN and USB_DP 360 440 mV High-leveloutputvoltage(3.3VI/OexceptVOH DV DD33 = MIN, IOH = MAX 2.4 VPCI-capableand I2C pins) High-leveloutputvoltage(3.3VI/OPCI- IOH = –0.5mA, DV DD33 = 3.3V 0.9DVDD33 (2) Vcapablepins) Low/fullspeed:USB_DN and USB_DP 0.0 0.3 V Highspeed:USB_DN and USB_DP –10 10 mV Low-leveloutputvoltage(3.3VI/Oexcept DV DD33 = MIN, IOL = MAX 0.4 VPCI-capableand I2C pins)VOL Low-leveloutputvoltage(3.3VI/OPCI- IOL = 1.5mA, DV DD33 = 3.3V 0.1DVDD33 (2) Vcapablepins) Low-leveloutputvoltage(3.3VI/OI2C IO = 3 mA 0 0.4 Vpins) VLDO USB_V DDA1P2LDO outputvoltage 1.14 1.2 1.26 V VI= VSS toDV DD33 withoutopposing ±20 μAinternalresistor Inputcurrent[DC](exceptI2C and PCI- VI = VSS toDV DD33 withopposinginternal 50 100 250 μAcapablepins) pullupresistor(4) VI = VSS toDV DD33 withopposinginternal –250 –100 –50 μApulldownresistor(4) II (3) InputcurrentDC VI = VSS toDV DD33 ±20 μA 0 < VI< DV DD33 = 3.3V withoutopposing ±50 μAinternalresistor 0 < VI< DV DD33 = 3.3V withopposingInputcurrent(PCI-capablepins)[DC] 50 250 μAinternalpullupresistor(4) 0 < VI< DV DD33 = 3.3V withopposing –250 –50 μAinternalpulldownresistor(4) GMTCLK, MTXD[7:0],MTXEN –8 mA DDR2; VOH = DV DDR2 – 0.4V –8 mA IOH High-leveloutputcurrent[DC] PCI-capablepins –0.5(2) mA(PCIpinfunctiononly) Allotherperipherals –4 mA GMTCLK, MTXD[7:0],MTXEN 8 mA DDR2; VOL = 0.4V 8 mA IOL Low-leveloutputcurrent[DC] PCI-capablepins 1.5(2) mA(PCIpinfunctiononly) Allotherperipherals 4 mA VO = DV DD33 orVSS ;internalpulldisabled ±20 μA IOZ (5) I/OOff-stateoutputcurrent VO = DV DD33 orVSS ;internalpullenabled ±100 μA (1) Fortestconditionsshown as MIN, MAX, orTYP, use theappropriatevaluespecifiedintherecommended operatingconditionstable. (2) These ratednumbers arefromthePCI LocalBus SpecificationRevision2.3.The DC specificationsand AC specificationsaredefinedin Table4-3(DC Specificationsfor3.3VSignaling)and Table4-4(AC Specificationsfor3.3VSignaling),respectively. (3) IIappliestoinput-onlypinsand bi-directionalpins.Forinput-onlypins,IIindicatestheinputleakagecurrent.Forbi-directionalpins,II indicatestheinputleakagecurrentand off-state(Hi-Z)outputleakagecurrent. (4) Appliesonlytopinswithan internalpullup(IPU)orpulldown(IPD)resistor. (5) IOZ appliestooutput-onlypins,indicatingoff-state(Hi-Z)outputleakagecurrent. Copyright© 2007–2012,Texas InstrumentsIncorporated DeviceOperatingConditions 141 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

Transmission□Line 4.0□pF 1.85□pF Z0□=□50 (see□Note) Ω Tester□Pin□Electronics Data□Sheet□Timing□Reference□Point Output Under Test NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only . It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. 42 Ω 3.5□nH Device□Pin (see□Note) TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com ElectricalCharacteristicsOver Recommended Ranges ofSupply Voltageand OperatingTemperature (UnlessOtherwiseNoted)(continued) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT CV DD = 1.2V,DSP clock= 594 MHz ARM Clock= 297 MHz, DDR Clock= 297 1318.58 mA MHz CV DD = 1.05V,DSP clock= 594 MHz ARM Clock= 297 MHz, DDR Clock= 297 814.00 mA MHz (SmartReflexV parts)Core (CVDD ,DEV_CV DD ,AUX_CV DD )ICDD supplycurrent(6) CV DD = 1.2V,DSP clock= 594 MHz ARM Clock= 297 MHz, DDR Clock= 297 915.39 mA MHz (SmartReflexV parts) CV DD = 1.2V,DSP clock= 729 MHz ARM Clock= 364.5MHz, DDR Clock= 1622.09 mA 310.5MHz DV DD = 3.3V,DSP clock= 594 MHz ARM Clock= 297 MHz, DDR Clock= 297 25.32 mA MHz3.3VI/O(DVDD33 ,USB_V DDA3P3 )supplyIDDD current(6) DV DD = 3.3V,DSP clock= 729 MHz ARM Clock= 364.5MHz, DDR Clock= 26.17 mA 310.5MHz DV DD = 1.8V,DSP clock= 594 MHz ARM Clock= 297 MHz, DDR Clock= 297 255.15 mA 1.8VI/O(DVDDR2 ,PLL1V PRW18 , MHz IDDD PLL2V PRW18 ,DEV_DV DD18 ,AUX_DV DD18 , DV DD = 1.8V,DSP clock= 729 MHzUSB_V DD1P8 )supplycurrent(6) ARM Clock= 364.5MHz, DDR Clock= 260.42 mA 310.5MHz C I Inputcapacitance 4 pF C o Outputcapacitance 4 pF (6) Measured underthefollowingconditions:60% DSP CPU utilization;ARM doingtypicalactivity(peripheralconfigurations,other housekeepingactivities);DDR2 Memory Controllerat50% utilization,50% writes,32 bits,50% bitswitchingatroom temperature(25 °C).The actualcurrentdraw variesacrossmanufacturingprocessesand ishighlyapplication-dependent.Formore detailson coreand I/Oactivity,as wellas informationrelevanttoboardpower supplydesign,see theTMS320DM646x Power ConsumptionSummary

7 PeripheralInformationand ElectricalSpecifications

7.1 Parameter Information

Figure7-1.TestLoad CircuitforAC Timing Measurements The loadcapacitancevaluestatedisonlyforcharacterizationand measurement ofAC timingsignals.This loadcapacitancevaluedoes notindicatethemaximum loadthedeviceiscapableofdriving.

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V =□V MAX□(or□V MAX)ref IL OL V =□V MIN□(or□V MIN)ref IH OH Vref TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Allinputand outputtimingparametersarereferencedtoVrefforboth"0"and "1"logiclevels.For3.3-VI/O, Figure7-2.Inputand Output VoltageReferenceLevelsforAC Timing Measurements Allriseand falltransitiontimingparametersarereferencedtoVIL MAX and VIH MIN forinputclocks,VOL MAX and VOH MIN foroutputclocks. Figure7-3.Rise and FallTransitionTime VoltageReferenceLevels 7.1.2 3.3-VSignalTransitionRates Alltimingsaretestedwithan inputedge rateof4 voltspernanosecond (4V/ns).

7.1.3 Timing Parameters and Board Routing Analysis

The timingparametervaluesspecifiedinthisdatamanual do notincludedelaysby board routings.As a good board designpractice,such delaysmust always be taken intoaccount.Timing valuesmay be adjustedby increasing/decreasingsuch delays.TI recommends utilizingthe availableI/O buffer informationspecification(IBIS)models toanalyzethetimingcharacteristicscorrectly.To properlyuse IBIS models to attainaccuratetiminganalysisfora givensystem,see the Using IBIS Models forTiming Analysisapplicationreport(literaturenumber SPRA839). Ifneeded, externallogichardware such as buffersmay be used tocompensate any timingdifferences. For theDDR2 memory controllerinterface,itisnotnecessarytouse theIBISmodels toanalyzetiming characteristics.Section7.10.2,DDR2 Interface,providesa PCB routingrulessolutionthatdescribesthe routingrulestoensuretheDDR2 memory controllerinterfacetimingsaremet.

7.2 Recommended Clock and ControlSignalTransitionBehavior

Allclocksand controlsignalsmust transitionbetween VIH and VIL (orbetween VIL and VIH)ina monotonic manner. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 143 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.3 Power Supplies

For more informationregardingTI'spower management productsand suggesteddevicesto power TI DSPs, visitwww.ti.com/processorpower.

7.3.1 Power-Supply Sequencing

The DM6467 includesone core supply(CVDD ),and two I/Osupplies— DV DD33 and DV DDR2 . To ensure properdeviceoperation,a specificpower-upsequence must be followed.Some TIpower-supplydevices includefeaturesthat facilitatepower sequencing— for example, Auto-Trackand Slow-Start/Enable features.Formore informationon TIpower suppliesand theirfeatures,visitwww.ti.com/processorpower. Here isa summary ofthepower sequencingrequirements:

The power ramp ordermust be CV DD beforeDV DDR2 , and DV DDR2 beforeDV DD33 — meaning during power up,thevoltageattheDV DDR2 railshouldneverexceed thevoltageattheCV DD rail.Similarly, thevoltageattheDV DDD33 railshouldneverexceed thevoltageattheDV DDR2 rail.
From the timethatpower ramp begins,allpower supplies(CVDD , DV DDR2 , DV DD33 ) must be stable within200 ms. The term "stable"means reachingthe recommended operatingcondition(see Section6.2,Recommended OperatingConditionstable).

7.3.2 Power-Supply Design Considerations

Core and I/Osupplyvoltageregulatorsshouldbe locatedclosetotheDSP (orDSP array)tominimize inductanceand resistanceinthepower deliverypath.Additionally,when designingforhigh-performance applicationsutilizingthe DM6467 device,the PC board shouldincludeseparatepower planesforcore, I/O,and ground;allbypassedwithhigh-qualitylow-ESL/ESR capacitors.

7.3.3 Power-Supply Decoupling

Inordertoproperlydecouplethesupplyplanesfrom system noise,placeas many capacitors(caps)as possibleclosetotheDM6467. These caps need tobe closetotheDM6467 power pins,no more than 1.25cm maximum distancetobe effective.Physicallysmallercaps,such as 0402,arebetterbutneed to be evaluatedfroma yield/manufacturingpoint-of-view.Parasiticinductancelimitstheeffectivenessofthe decouplingcapacitors,thereforephysicallysmallercapacitorsshouldbe used whilemaintainingthelargest availablecapacitancevalue. Largercaps foreach supplycan be placedfurtheraway forbulkdecoupling.Largebulkcaps (ontheorder of100 μF) shouldbe furthestaway, butstillas closeas possible.Large caps foreach supplyshouldbe placedoutsideoftheBGA footprint. As withtheselectionofany component,verificationofcapacitoravailabilityovertheproduct'sproduction lifetimeshouldbe considered. For more detailson capacitorusage and placement,see the ImplementingDDR2 PCB Layouton the TMS320DM646x DMSoC ApplicationReport(literaturenumber SPRAAM1A ).

7.3.4 DM6467 Power and Clock Domains

The DM6467 includesone singlepower domain — the "AlwaysOn" power domain.The "AlwaysOn" power domain isalwayson when thechipison.The "AlwaysOn" domain ispowered by theCV DD pinsof theDM6467. AllDM6467 modules liewithinthe"AlwaysOn" power domain.Table7-1providesa listingof theDM6467 clockdomains. Two primaryreferenceclocksare requiredfortheDM6467 device.These can eitherbe crystalinputsor drivenby externaloscillators.A 27-MHz crystalisrecommended forthesystem PLLs,whichgeneratethe internalclocksfortheARM926, DSP, HDVICPs, peripherals,and theEDMA3. A 24-or48-MHz crystalis alsorequiredifthe USB (24-MHz only)or UART (either24- or 48-MHz) peripheralsare to be used.In addition,the24-or48-MHz inputclockcan be used tosourcetheMcASPs' clocks.For furtherdescription oftheDM6467 clockdomains,see Table7-2and Figure7-4.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 The DM6467 architectureisdividedintothe power and clockdomains shown inTable 7-1. Table 7-2 furtherdiscussestheclockdomains and theirratios.Figure7-4shows theClockDomain BlockDiagram. Table7-1.DM6467 Power and Clock Domains POWER DOMAIN CLOCK DOMAIN PERIPHERAL/MODULE AlwaysOn SYSCLK3 UART0 AlwaysOn SYSCLK3 UART1 AlwaysOn SYSCLK3 UART2 AlwaysOn SYSCLK3 I2C AlwaysOn SYSCLK3 Timer0 AlwaysOn SYSCLK3 Timer1 AlwaysOn SYSCLK3 Timer2 AlwaysOn SYSCLK3 PWM0 AlwaysOn SYSCLK3 PWM1 AlwaysOn SYSCLK2 DDR2 AlwaysOn SYSCLK2 VPIF AlwaysOn SYSCLK2 TSIF0 AlwaysOn SYSCLK2 TSIF1 AlwaysOn SYSCLK2 VDCE AlwaysOn SYSCLK2 HDVICP0 AlwaysOn SYSCLK2 HDVICP1 AlwaysOn SYSCLK2 EDMA3 AlwaysOn SYSCLK2 PCI AlwaysOn SYSCLK2 SCR AlwaysOn SYSCLK3 GPSC AlwaysOn SYSCLK3 LPSCs AlwaysOn SYSCLK3 PLLC1 AlwaysOn SYSCLK3 PLLC2 AlwaysOn SYSCLK3 IcePick AlwaysOn SYSCLK3 EMIFA AlwaysOn SYSCLK3 USB AlwaysOn SYSCLK3 HPI AlwaysOn SYSCLK3 VLYNQ AlwaysOn SYSCLK3 EMAC/MDIO AlwaysOn SYSCLK3 SPI AlwaysOn SYSCLK3 McASP0 AlwaysOn SYSCLK3 McASP1 AlwaysOn SYSCLK3 CRGEN0 AlwaysOn SYSCLK3 CRGEN1 AlwaysOn SYSCLK4 ATA AlwaysOn SYSCLK3 GPIO AlwaysOn SYSCLK1 C64x+ CPU AlwaysOn SYSCLK2 ARM926 Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 145 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-2.DM6467 Clock Domains DOMAIN FIXED RATIO vs.CLOCK CLOCK SYSCLK1 CLOCK MODES FREQUENCY (MHz)DOMAIN SOURCE FREQUENCYSUBSYSTEM PLL MODE (- PLL MODE (-BYPASS MODE 594)(1) 729)(2) DSP Subsystem PLLC1 1:1PLLDIV1 27 MHz 594 MHz 729 MHzSYSCLK1 ARM926 Subsystem, 1:2 EDMA3, HDVICP, PCI, PLLC1PLLDIV2 13.5MHz 297 MHz 364.5MHzVDCE, VPIF,TSIFs, SYSCLK2 DDR2 Mem Ctlr Peripherals(GPIO, 1:4 Timers,I2C,PWMs, HPI, EMAC, EMIFA, VLYNQ, PLLC1PLLDIV3 6.75MHz 148.5MHz 182.25MHzSPI,ARM INTC,USB2.0, SYSCLK3 UARTs, McASPs, CRGENs, SYSTEM) ATA PLLC1 1:6(-594)default PLLDIV4 4.5MHz 99 MHz 104.14MHzSYSCLK4 1:7(-729)(3) TSIF0(4) PLLC1 1:8(-594)default PLLDIV5 3.38MHz 74.25MHz 72.9MHzSYSCLK5 1:10(-729)(3) TSIF1(4) PLLC1 1:8(-594)default PLLDIV6 3.38MHz 74.25MHz 72.9MHzSYSCLK6 1:10(-729)(3) VPIF(4) PLLC1 1:6(-594)default PLLDIV8 3.38MHz 99 MHz 104.14MHz (5) SYSCLK8 1:7(-729)(3) VLYNQ PLLC1 1:6(-594)default PLLDIV9 4.5MHz 99 MHz 104.14MHzSYSCLK9 1:7(-729)(3) DDR2 PHY PLLC2 1:1PLLDIV1 27 MHz 594 MHz 621 MHzSYSCLK1 (1) These tablevaluesassume a DEV_MXI/DEV_CLKIN of27 MHz and a PLL1 multiplierequalto22. (2) These tablevaluesassume a DEV_MXI/DEV_CLKIN of27 MHz and a PLL1 multiplierequalto27. (3) The defaultSYSCLKx ratiosapplytothe-594MHz deviceonly.Forthe-729MHz devicetoachievethequotedfrequencines,the PLLC1 SYSCLKx (forSYSCLK4, SYSCLK5, SYSCLK6, SYSCLK8, SYSCLK9) defaultdividervaluesmust be changed.Forthestepsto change thePLLC1 SYSCLKx dividervalues,see theTMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). (4) These domain clocksources,alongwithVP_CLKIN[3:0],STC_CLKIN, CRG0_VCXI, and CRG1_VCXI clocksignals,go throughthe clockselectlogictodeterminetheclocksourceenabledas theinputtotheVPIF and TSIF peripherals. (5) Forthe-729device,use an externalclocksourceforthe54-/74.25-/108-MHzVPIF clock.

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PLLDIV1□(/1□Fixed) PLLDIV2□(/2□Fixed) PLLDIV3□(/4□Fixed) PLLDIV4□(/6□Prog) PLLDIV5□(/8□Prog) PLLDIV6□(/8□Prog) PLLDIV8□(/8□Prog) PLLDIV9□(/6□Prog) BPDIV□(/1□Prog) SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK8 SYSCLK9 SYSCLKBP AUXCLK PLLEN PLL CLKMODE PLLM CLKIN OSCIN PLLOUT PLL Controller□1 PLLDIV1□(/1□Fixed) SYSCLK1 PLLDIV2□(/2□Fixed) SYSCLK2 PLLDIV3□(/4□Fixed) SYSCLK3 PLLDIV4□(/6□Prog) SYSCLK4 PLLDIV9□(/6□Prog) SYSCLK9 PLLDIV5□(/8□Prog) SYSCLK5 PLLDIV6□(/8□Prog) SYSCLK6 PLLDIV8□(/8□Prog) SYSCLK8 BPDIV□(/1□Prog) SYSCLKBP AUXCLK DEV_MXI/ DEV_CLKIN (27□MHz) DSP Subsystem PCI VDCE HDVICP0 HDVICP1 EDMA3 Crossbar/SCR ARM□Subsystem GPIO Timer□0 Timer□1 Timer□2□(WD) I2C PWM□(x2) HPI EMAC/MDIO EMIFA VLYNQ SPI ARM□INTC ATA TINP0L TINP0U TINP1L USB□2.0 60□MHz USB□PHY UART0 McASP0 McASP1 AUX_MXI/ AUX_CLKIN (24/48□MHz) Clock□Select Logic TSIF0 TSIF1 Video□Port I/F CLKOUT0 AUDIO_CLK0 AUDIO_CLK1 CRGEN0 CRGEN1 DDR2□Mem□Cltr UART1 UART2 VP_CLKIN0 VP_CLKIN1 VP_CLKIN2 VP_CLKIN3 STC_CLKIN CRG0_VCXI CRG1_VCXI PLLDIV1□(/1□Prog) PLL Controller□2 PLL2_SYSCLK1 PLLM PLLM TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-4.PLL1 and PLL2 Clock Domain Block Diagram For furtherdetailon PLL1 and PLL2, see thestructureblockdiagramsshown inFigure7-5and Figure7- 6,respectively. Figure7-5.PLL1 StructureBlock Diagram Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 147 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

PLLDIV1□(/1□Prog) PLL2_SYSCLK1 (DDR2_PHY) PLLEN PLL PLLM CLKIN/OSCIN(A) (A) As□selected□by□the□PLL2□PLLCTL register PLLOUT TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-6.PLL2 StructureBlock Diagram

7.3.5 Power and Sleep Controller(PSC)

The Power and Sleep Controller(PSC) controlsdevice power by gatingoffclocksto individual peripherals/modules.The PSC consistsofa GlobalPSC (GPSC) and a setofLocalPSCs (LPSCs).The GPSC containsmemory mapped registers,PSC interruptcontrol,and a statemachine for each peripheral/module.An LPSC isassociatedwitheach peripheral/moduleand providesclockand reset control.The GPSC controlsalloftheDM6467's LPSCs. The ARM Subsystem does nothave an LPSC module. ARM sleep mode is accomplishedthroughthe waitforinterruptinstruction.The LPSCs for DM6467 areshown inTable7-3.The PSC Registermemory map isgiveninTable7-4.For more details on the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literaturenumber SPRUEP9 ). Table7-3.DM6467 LPSC Assignments LPSC PERIPHERAL/MODULE LPSC PERIPHERAL/MODULE LPSC PERIPHERAL/MODULE NUMBER NUMBER NUMBER

0 Reserved 16 VideoPort 32 SPI

1 C64x+ CPU 17 VideoPort 33 GPIO

2 HDVICP0 18 TSIF0 34 TIMER0

3 HDVICP1 19 TSIF1 35 TIMER1

4 EDMA CC 20 DDR2 Memory Controller 36 Reserved

5 EDMA TC0 21 EMIFA 37 Reserved

6 EDMA TC1 22 McASP0 38 Reserved

7 EDMA TC2 23 McASP1 39 Reserved

8 EDMA TC3 24 CRGEN0 40 Reserved

9 USB2.0 25 CRGEN1 41 Reserved

10 ATA 26 UART0 42 Reserved

11 VLYNQ 27 UART1 43 Reserved

12 HPI 28 UART2 44 Reserved

13 PCI 29 PWM0 45 ARM INTC

14 EMAC/MDIO 30 PWM1

15 VDCE 31 I2C

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-4.PSC Registers REGISTERHEX ADDRESS RANGE DESCRIPTIONACRONYM 0x01C4 1000 PID PeripheralRevisionand ClassInformationRegister 0x01C4 1004 -0x01C4 1017 – Reserved 0x01C4 1018 INTEVAL InterruptEvaluationRegister 0x01C4 101C -0x01C4 1039 – Reserved 0x01C4 1040 MERRPR0 Module ErrorPending0 (mod 0-31)Register 0x01C4 1044 MERRPR1 Module ErrorPending1 (mod 32-63)Register 0x01C4 1048 -0x01C4 1049 – Reserved 0x01C4 1050 MERRCR0 Module ErrorClear0 (mod 0 -31)Register 0x01C4 1054 MERRCR1 Module ErrorClear1 (mod 32 -63)Register 0x01C4 1058 -0x01C4 111F Reserved 0x01C4 1120 PTCMD Power Domain TransitionCommand Register 0x01C4 1124 -0x01C4 1127 – Reserved 0x01C4 1128 PTSTAT Power Domain TransitionStatusRegister 0x01C4 112C -0x01C4 11FF – Reserved 0x01C4 1200 PDSTAT0 Power Domain Status0 Register(AlwaysOn) 0x01C4 1204 -0x01C4 12FF – Reserved 0x01C4 1300 PDCTL0 Power Domain Control0 Register(AlwaysOn) 0x01C4 1304 -0x01C4 17FF – Reserved 0x01C4 1800 -0x01C4 1803 – Reserved 0x01C4 1804 MDSTAT1 Module Status1 Register(C64x+ CPU) 0x01C4 1808 MDSTAT2 Module Status2 Register(HDVICP0) 0x01C4 180C MDSTAT3 Module Status3 Register(HDVICP1) 0x01C4 1810 MDSTAT4 Module Status4 Register(EDMA CC) 0x01C4 1814 MDSTAT5 Module Status5 Register(EDMA TC0) 0x01C4 1818 MDSTAT6 Module Status6 Register(EDMA TC1) 0x01C4 181C MDSTAT7 Module Status7 Register(EDMA TC2) 0x01C4 1820 MDSTAT8 Module Status8 Register(EDMA TC3) 0x01C4 1824 MDSTAT9 Module Status9 Register(USB) 0x01C4 1828 MDSTAT10 Module Status10 Register(ATA) 0x01C4 182C MDSTAT11 Module Status11 Register(VLYNQ) 0x01C4 1830 MDSTAT12 Module Status12 Register(HPI) 0x01C4 1834 MDSTAT13 Module Status13 Register(PCI) 0x01C4 1838 MDSTAT14 Module Status14 Register(EMAC) 0x01C4 183C MDSTAT15 Module Status15 Register(VDCE) 0x01C4 1840 MDSTAT16 Module Status16 Register(VdieoPort) 0x01C4 1844 MDSTAT17 Module Status17 Register(VideoPort) 0x01C4 1848 MDSTAT18 Module Status18 Register(TSIF0) 0x01C4 184C MDSTAT19 Module Status19 Register(TSIF1) 0x01C4 1850 MDSTAT20 Module Status20 Register(DDR2 Mem Ctlr) 0x01C4 1854 MDSTAT21 Module Status21 Register(EMIFA) 0x01C4 1858 MDSTAT22 Module Status22 Register(McASP0) 0x01C4 185C MDSTAT23 Module Status23 Register(McASP1) 0x01C4 1860 MDSTAT24 Module Status24 Register(CRGEN0) 0x01C4 1864 MDSTAT25 Module Status25 Register(CRGEN1) 0x01C4 1868 MDSTAT26 Module Status26 Register(UART0) 0x01C4 186C MDSTAT27 Module Status27 Register(UART1) 0x01C4 1870 MDSTAT28 Module Status28 Register(UART2) Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 149 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-4.PSC Registers(continued) REGISTERHEX ADDRESS RANGE DESCRIPTIONACRONYM 0x01C4 1874 MDSTAT29 Module Status29 Register(PWM0) 0x01C4 1878 MDSTAT30 Module Status30 Register(PWM1) 0x01C4 187C MDSTAT31 Module Status31 Register(I2C) 0x01C4 1880 MDSTAT32 Module Status32 Register(SPI) 0x01C4 1884 MDSTAT33 Module Status33 Register(GPIO) 0x01C4 1888 MDSTAT34 Module Status34 Register(TIMER0) 0x01C4 188C MDSTAT35 Module Status35 Register(TIMER1) 0x01C4 1890 -0x01C4 18B3 – Reserved 0x01C4 18B4 MDSTAT45 Module Status45 Register(ARM INTC) 0x01C4 18B8 -0x01C4 19FF – Reserved 0x01C4 1A00 -0x01C4 1A03 – Reserved 0x01C4 1A04 MDCTL1 Module Control1 Register(C64x+ CPU) 0x01C4 1A08 MDCTL2 Module Control2 Register(HDVICP0) 0x01C4 1A0C MDCTL3 Module Control3 Register(HDVICP1) 0x01C4 1A10 MDCTL4 Module Control4 Register(EDMA CC) 0x01C4 1A14 MDCTL5 Module Control5 Register(EDMA TC0) 0x01C4 1A18 MDCTL6 Module Control6 Register(EDMA TC1) 0x01C4 1A1C MDCTL7 Module Control7 Register(EDMA TC2) 0x01C4 1A20 MDCTL8 Module Control8 Register(EDMA TC3) 0x01C4 1A24 MDCTL9 Module Control9 Register(USB) 0x01C4 1A28 MDCTL10 Module Control10 Register(ATA) 0x01C4 1A2C MDCTL11 Module Control11 Register(VLYNQ) 0x01C4 1A30 MDCTL12 Module Control12 Register(HPI) 0x01C4 1A34 MDCTL13 Module Control13 Register(PCI) 0x01C4 1A38 MDCTL14 Module Control14 Register(EMAC) 0x01C4 1A3C MDCTL15 Module Control15 Register(VDCE) 0x01C4 1A40 MDCTL16 Module Control16 Register(VideoPort) 0x01C4 1A44 MDCTL17 Module Control17 Register(VideoPort) 0x01C4 1A48 MDCTL18 Module Control18 Register(TSIF0) 0x01C4 1A4C MDCTL19 Module Control19 Register(TSIF1) 0x01C4 1A50 MDCTL20 Module Control20 Register(DDR2 Mem Ctlr) 0x01C4 1A54 MDCTL21 Module Control21 Register(EMIFA) 0x01C4 1A58 MDCTL22 Module Control22 Register(McASP0) 0x01C4 1A5C MDCTL23 Module Control23 Register(McASP1) 0x01C4 1A60 MDCTL24 Module Control24 Register(CRGEN0) 0x01C4 1A64 MDCTL25 Module Control25 Register(CRGEN1) 0x01C4 1A68 MDCTL26 Module Control26 Register(UART0) 0x01C4 1A6C MDCTL27 Module Control27 Register(UART1) 0x01C4 1A70 MDCTL28 Module Control28 Register(UART2) 0x01C4 1A74 MDCTL29 Module Control29 Register(PWM0) 0x01C4 1A78 MDCTL30 Module Control30 Register(PWM1) 0x01C4 1A7C MDCTL31 Module Control31 Register(I2C) 0x01C4 1A80 MDCTL32 Module Control32 Register(SPI) 0x01C4 1A84 MDCTL33 Module Control33 Register(GPIO) 0x01C4 1A88 MDCTL34 Module Control34 Register(TIMER0) 0x01C4 1A8C MDCTL35 Module Control35 Register(TIMER1) 0x01C4 1A90 -0x01C4 1AB3 – Reserved

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-4.PSC Registers(continued) REGISTERHEX ADDRESS RANGE DESCRIPTIONACRONYM 0x01C4 1AB4 MDCTL45 Module Control45 Register(ARM INTC) 0x01C4 1AB8 -0x01C4 1FFF – Reserved

7.3.6 SmartReflex(VoltageScaling)

Increasingthe device complexityincreasesitspower consumption and with the smallertransistor structuresresponsibleforhigherachievableclockratesand increasedperformance,comes an inevitable penalty,increasingtheleakagecurrents.Leakage currentsarepresentinany activecircuit,independently ofclockratesand usage scenarios.Thisstaticpower consumptionismainlydeterminedby transistortype and process technology.Higher clock ratesalso increasedynamic power, the power used when transistorsswitch.The dynamic power depends mainlyon a specificusage scenario,clockrates,and I/O activity. Texas Instruments'SmartReflex™ technologyis used to decrease both staticand dynamic power consumptionwhilemaintainingthe deviceperformance.SmartReflexin the TMS320DM6467 DMSoC device(-594Vpartsonly) isa featurethatallowsthecorevoltagetobe optimizedbased on theprocess cornerofthedevice.Thisrequiresan adjustablepower supplydesignwitha voltageregulator. On the DM6467, deviceswithdifferentstrengthsare partitionedintotwo groups:Weak and Strong. "Weak" devicesshouldrunat1.2-Vcorepower supplywhere as "Strong"devicescan runat1.05-Vcore toreducepower consumption.Duringmanufacturingtest,thedevicecharacterizationinformationisstored permanentlyon theDM6467 device. On theDM6467 device,theSmartReflexfeatureisdisabledby default.Itcan be enabledby pullingthe configurationpinVADJEN (AB7)highbeforereleasingthedeviceout-of-reset.The VADJEN inputvalueis latchedintoBOOTCFG register(VADJEN bit)attherisingedge ofRESET orPOR. Once SmartReflexis enabled,thepinsGP[7]/CVDDADJ1 (A12)and GP[6]/CVDDADJ0 (E11)functionas SmartReflexcontrol outputsto the adjustablecore power supplyand the GPIO functionalityisdisabled.For more detailed informationon theSmartReflexand GPIO pinmuxing,see Section4.7.3.11,SmartReflexand GPIO Pin Muxing. The read-onlySMTREFELX register[bits1:0]reflectsthestatusoftheCVDDADJ[1:0] pins(seeFigure7- 7, SMTREFLEX Register[0x01C4 0018]).For additionalinformationon SmartReflex,see the Enabling SmartReflexon theTMS320DM6467 ApplicationReport(LiteratureNumber SPRAAZ2 ). 31 16 RESERVED R-0000 0000 0000 0000 15 2 1 0 RESERVED SMTREFLEX R-0000 0000 0000 00 R-PP LEGEND: R = Read only;P = Pinvalue Figure7-7.SMTREFLEX StatusRegister[0x01C4 0018](VoltageScaleAdjustment (V)PartsOnly) Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 151 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-5.SMTREFLEX StatusRegisterBitDescriptions BIT NAME DESCRIPTION 31:2 RESERVED Reserved.Read returns"0". When SmartReflexControlOutputsareenabled(VADJEN = 1),thesebitsreflectthestatusofthe CVDDADJ[1:0] pins. 00 = 1.2V coresupplyvoltage 1:0 SMTREFLEX 11 = 1.05V coresupplyvoltage Formore detailedinformationon theSmartReflexand GPIO pinmuxing,see Section4.7.3.11, SmartReflexand GPIO PinMuxing.

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/c40 /c41 C C1 2CL C C1 2 /c61 /c43 DEV_MXI/ DEV_CLKIN DEV_MXO C1 C2 Crystal DEV_VSS 27□MHz 1.8□V DEV_DVDD18 1.2□V DEV_CVDDDEV_DVSS TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012

7.4 ExternalClock InputFrom DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins

The DM6467 deviceincludestwo optionsto providean externalclockinputforboth the system and auxiliaryoscillators:

Use an on-chiposcillatorwithexternalcrystal(fundamentalparallelresonantmode only,no overtone support).
Use an external1.8-VLVCMOS-compatible clockinput. The optimalexternalclock inputfrequencyfor the crystalsare 27 MHz for the system oscillator (DEV_MXI/DEV_CLKIN) and 24 MHz fortheauxiliaryoscillator.Section7.4.1.1providesmore detailson Option1,usingan on-chiposcillatorwithexternalcrystalforthe27-MHz system oscillator.Section7.4.1.2 providesmore detailson Option1,usingan on-chiposcillatorwithexternalcrystalforthe24-MHz auxiliary inputforthe27-MHz system oscillator.Section7.4.2providesdetailson Option2,usingan external1.8-V LVCMOS-compatible clockinputforthe24-MHz auxiliaryoscillator.

7.4.1 Clock InputOption 1— Crystal

7.4.1.1 27-MHz forSystem OscillatorClock InputOption 1— Crystal Inthisoption,a crystalisused as theexternalclockinputtotheDM6467 systemoscillator. The 27-MHz oscillatorprovidesthereferenceclockforallDM6467 subsystemsand peripherals.The on- chiposcillatorrequiresan external27-MHz crystalconnectedacrosstheDEV_MXI and DEV_MXO pins, alongwithtwo loadcapacitors,as shown inFigure7-8. The externalcrystalloadcapacitorsmust be connectedonlytothe27-MHz oscillatorground pin(DEV_V SS ).Do not connecttoboard ground (VSS ). The DEV_DV DD18 pincan be connectedtothesame 1.8V power supplyas DV DDR2 . A. The DEV_CV DD corevoltagevalueisdevicedependent(e.g.,when usingSmartReflex,DEV_CV DD can be either1.2 V or1.05V). Figure7-8.27-MHz System Oscillator(A) The loadcapacitors,C1 and C2, shouldbe chosen such thattheequationissatisfied(typicalvaluesare C1 = C2 = 10 pF).C L in the equationisthe load specifiedby the crystalmanufacturer.Alldiscrete components used to implement the oscillatorcircuitshould be placed as close as possibleto the associatedoscillatorpins(DEV_MXI and DEV_MXO) and totheDEV_V SS pin. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 153 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

/c40 /c41 C C1 2CL C C1 2 /c61 /c43 AUX_MXI/ AUX_CLKIN AUX_MXO C1 C2 Crystal AUX_VSS 24□MHz 1.8□V AUX_DVDD18 1.2□V AUX_CVDDAUX_DVSS TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-6.InputRequirements forCrystalon the27-MHz System Oscillator PARAMETER MIN NOM MAX UNIT Start-uptime(frompower up untiloscillatingatstablefrequencyof 4 ms27 MHz) Oscillationfrequency 27 MHz ESR 60 Ω 7.4.1.2 24-MHz AuxiliaryOscillatorClock InputOption 1— Crystal Inthisoption,a crystalisused as theexternalclockinputtotheDM6467 auxiliaryoscillator. The 24-MHz oscillatorprovidesthereferenceclockforUSB and UART peripheralsand theinternalclock sourcefortheMcASP peripherals.The on-chiposcillatorrequiresan external24-MHz crystalconnected acrosstheAUX_MXI and AUX_MXO pins,alongwithtwo loadcapacitors,as shown inFigure7-9.The externalcrystalloadcapacitorsmust be connectedonlytothe24-MHz oscillatorground pin(AUX_V SS ). Do not connecttoboardground(VSS ).The AUX_DV DD18 pincan be connectedtothesame 1.8V power supplyas DV DDR2 . A. The AUX_CV DD corevoltagevalueisdevicedependent(e.g.,when usingSmartReflex,AUX_CV DD can be either1.2 V or1.05V). Figure7-9.24-MHz AuxiliaryOscillator(A) The loadcapacitors,C1 and C2, shouldbe chosen such thattheequationissatisfied(typicalvaluesare C1 = C2 = 10 pF).C L in the equationisthe load specifiedby the crystalmanufacturer.Alldiscrete components used to implement the oscillatorcircuitshould be placed as close as possibleto the associatedoscillatorpins(AUX_MXI and AUX_MXO) and totheAUX_V SS pin. Table7-7.InputRequirements forCrystalon the24-MHz AuxiliaryOscillator PARAMETER MIN NOM MAX UNIT Start-uptime(frompower up untiloscillatingatstablefrequencyof 4 ms24 MHz) Oscillationfrequency 24 MHz ESR 60 Ω (1) Frequencystability ±50 ppm (1) IftheUSB isused,a 24-MHz, 50-ppm crystalisrecommended.

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AUX_MXI/ AUX_CLKIN AUX_MXO NC AUX_VSS 1.8□V AUX_DVDD18 AUX_DVSS 1.2□V AUX_CVDD DEV_MXI/ DEV_CLKIN DEV_MXO NC DEV_VSS 1.8□V DEV_DVDD18 DEV_DVSS 1.2□V DEV_CVDD TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 7.4.2 Clock InputOption 2— 1.8-VLVCMOS-Compatible Clock Input 7.4.2.1 27-MHz System OscillatorClock InputOption 2— 1.8-VLVCMOS-Compatible Clock Input Inthisoption,a 1.8-VLVCMOS-Compatible ClockInputisused as theexternalclockinputtothesystem oscillator.The externalconnectionsare shown in Figure 7-10. The DEV_MXI/DEV_CLKIN pin is connectedtothe1.8-VLVCMOS-Compatible clocksource.The DEV_MXO pinisleftunconnected.The DEV_V SS pinisconnectedtoboard ground (VSS ).The DEV_DV DD18 pincan be connectedtothesame 1.8-Vpower supplyas DV DDR2 . A. The DEV_CV DD corevoltagevalueisdevicedependent(e.g.,when usingSmartReflex,DEV_CV DD can be either1.2 V or1.05V). Figure7-10.1.8-VLVCMOS-Compatible Clock Input(A) The clocksourcemust meet theDEV_MXI/DEV_CLKIN timingrequirementsinSection7.5.5,ClockPLL ElectricalData/Timing(Inputand OutputClocks). 7.4.2.2 24-MHz AuxiliaryOscillatorClock InputOption 2— 1.8-VLVCMOS-Compatible Clock Input Inthisoption,a 1.8-VLVCMOS-Compatible ClockInputisused as theexternalclockinputtotheauxiliary oscillator.The externalconnectionsare shown in Figure 7-11. The AUX_MXI/AUX_CLKIN pin is connectedtothe1.8-VLVCMOS-Compatible clocksource.The AUX_MXO pinisleftunconnected.The AUX_V SS pinisconnectedtoboard ground (VSS ).The AUX_DV DD18 pincan be connectedtothesame 1.8-Vpower supplyas DV DDR2 . A. The AUX_CV DD corevoltagevalueisdevicedependent(e.g.,when usingSmartReflex,AUX_CV DD can be either1.2 V or1.05V). Figure7-11.1.8-VLVCMOS-Compatible Clock Input(A) The clocksourcemust meet theAUX_MXI/AUX_CLKIN timingrequirementsinSection7.5.5,ClockPLL ElectricalData/Timing(Inputand OutputClocks). Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 155 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

EMI□Filter +1.8□V

0.01 F μ

0.1 F μ

EMI□Filter +1.8□V SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com

7.5 Clock PLLs

Therearetwo independentlycontrolledPLLs on DM6467. PLL1 generatesthefrequenciesrequiredforthe ARM, DSP, HDVICP0/1, EDMA, and peripherals.PLL2 generatesthefrequenciesrequiredfortheDDR2 interface.The recommended referenceclockforbothPLLs isthe27-MHz crystalinput.The DM6467 has a thirdPLL thatisembedded withinthe USB2.0 PHY and the 24-MHz oscillatorisitsreferenceclock source.This particularPLL is only usable for USB operation,and is discussed furtherin the TMS320DM646x DMSoC UniversalSerialBus (USB) ControllerUser's Guide (literaturenumber SPRUER7 ).

7.5.1 PLL1 and PLL2

Both PLL1 and PLL2 power aresuppliedexternallyviathe1.8-VPLL power-supplypins(PLL1VDD18 and PLL2V DD18 ).An externalEMI filtercircuitmust be added to PLL1V DD18 and PLL2V DD18 , as shown in Figure7-12.The 1.8-VsupplyoftheEMI filtersmust be fromthesame 1.8-Vpower planesupplyingthe device’s 1.8-V I/O power-supplypins (DVDDR2 ).TI recommends EMI filtermanufacturerMurata,part number NFM18CC222R1C3. AllPLL externalcomponents (C1,C2, C3, C4, and theEMI Filters)must be placedas closetothedevice as possible.For the bestperformance,TI recommends thatallthe PLL externalcomponents be on a singlesideoftheboardwithoutjumpers,switches,orcomponents otherthantheones shown inFigure7- 12. For reduced PLL jitter,maximize the spacing between switchingsignalsand the PLL external components (C1,C2, C3, C4, and theEMI Filters). Figure7-12.PLL1 and PLL2 ExternalConnection The minimum CLKIN riseand falltimesshouldalsobe observed.For theinputclocktimingrequirements, see Section7.5.5,ClockPLL ElectricalData/Timing(Inputand OutputClocks). There isan allowablerange forPLL multiplier(PLLM). There isa minimum and maximum operating frequency for DEV_MXI/DEV_CLKIN, PLLOUT, AUX_MXI/AUX_CLKIN, and the device clocks (SYSCLKs). The PLL Controllersmust be configurednottoexceed any oftheseconstraintsdocumented in thissection(certaincombinationsof externalclockinputs,internaldividers,and PLL multiplyratios mightnotbe supported).Fortheseconstraints(ranges),see Table7-8throughTable7-10.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-8.PLL1 and PLL2 MultiplierRanges -594 -729PLL MULTIPLIER (PLLM) MIN MAX MIN MAX PLL1 Multiplier x14 x22 x14 x27 PLL2 Multiplier x14 x22 x14 x23 Table7-9.PLLC1 Clock Frequency Ranges -594 -729 CLOCK SIGNAL NAME UNIT MIN MAX MIN MAX DEV_MXI/DEV_CLKIN (1) 20 30 20 30 MHz PLLOUT 400 594 400 729 MHz SYSCLK1 (PLLDIV1 Domain) 594 729 MHz (1) DEV_MXI/DEV_CLKIN inputclockisused forbothPLL Controllers(PLLC1 and PLLC2). Table7-10.PLLC2 Clock Frequency Ranges -594 -729 CLOCK SIGNAL NAME UNIT MIN MAX MIN MAX DEV_MXI/DEV_CLKIN (1) 20 30 20 30 MHz PLLOUT 400 594 400 621 MHz PLL2_SYSCLK1 (toDDR2 PHY) 594 621 MHz (1) DEV_MXI/DEV_CLKIN inputclockisused forbothPLL Controllers(PLLC1 and PLLC2). BothPLL1 and PLL2 have stabilization,lock,and resettimingrequirementsthatmust be followed. The PLL stabilizationtimeistheamount oftimethatmust be allottedfortheinternalPLL regulatorsto become stableafterthe PLL ispowered up (afterthe PLLCTL.PLLPWRDN bitgoes througha 1-to-0 transition).The PLL shouldnotbe operateduntilthisstabilizationtimehas expired.Thisstabilizationstep must be appliedafterthese resets— a Power-on Reset, a Warm Reset, or a Max Reset, as the PLLCTL.PLLPWRDN bitresetstoa "1".ForthePLL stabliziationtimevalue,see Table7-11. The PLL resettimeistheamount ofwaittimeneeded forthePLL toproperlyreset(writingPLLRST = 1) beforebringingthePLL outofreset(writingPLLRST = 0).ForthePLL resettimevalue,see Table7-11. The PLL locktimeistheamount oftimeneeded from when thePLL istakenoutofreset(PLLRST = 0 withPLLEN = 0)towhen towhen thePLL controllercan be switchedtoPLL mode (PLLEN = 1).For the PLL locktimevalue,see Table7-11. Table7-11.PLL1 and PLL2 Stabilization,Lock,and Reset Times PLL STABILIZATION/ MIN NOM MAX UNITLOCK/RESET TIME PLL StabilizationTime 150 μs PLL Lock Time 2000C (1) ns PLL ResetTime 128C (1) ns (1) C = CLKIN cycletimeinns.Forexample,when DEV_MXI/DEV_CLKIN orAUX_MXI/AUX_CLKIN frequencyis27 MHz, use C = 37.037 ns. Fordetailson thePLL initializationsoftwaresequence,see theTMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). For more informationon theclockdomains and theirclockratiorestrictions,see Section7.3.4,DM6467 Power and ClockDomains. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 157 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.5.2 PLL ControllerRegisterDescription(s)

A summary of the PLL controllerregistersis shown in Table 7-12. For more details,see the TMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). Table7-12.PLL and Reset ControllerRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME PLL1 ControllerRegisters 0x01C4 0800 PID PeripheralID Register 0x01C4 08E4 RSTYPE ResetType Register 0x01C4 0900 PLLCTL PLL Controller1 PLL ControlRegister 0x01C4 0910 PLLM PLL Controller1 PLL MultiplierControlRegister 0x01C4 0918 PLLDIV1 PLL Controller1 Divider1 Register(SYSCLK1) 0x01C4 091C PLLDIV2 PLL Controller1 Divider2 Register(SYSCLK2) 0x01C4 0920 PLLDIV3 PLL Controller1 Divider3 Register(SYSCLK3) 0x01C4 0928 – Reserved 0x01C4 092C BPDIV PLL Controller1 Bypass Control-DividerRegister(SYSCLKBP) 0x01C4 0938 PLLCMD PLL Controller1 Command Register 0x01C4 093C PLLSTAT PLL Controller1 StatusRegister(Shows PLLC1 PLLCTL Status) PLL Controller1 ClockAlignControlRegister0x01C4 0940 ALNCTL (IndicatesWhich SYSCLKs Need tobe AlignedforProperDeviceOperation) PLL Controller1 PLLDIV DividerRatioChange StatusRegister0x01C4 0944 DCHANGE (IndicatesifSYSCLK DivideRatiohas been modified) 0x01C4 0948 CKEN PLL Controller1 ClockEnableControlRegister 0x01C4 094C CKSTAT PLL Controller1 ClockStatusRegister(ForAllClocksExceptSYSCLKx) 0x01C4 0950 SYSTAT PLL Controller1 SYSCLK StatusRegister(IndicatesSYSCLK on/offStatus) 0x01C4 0960 PLLDIV4 PLL Controller1 Divider4 Register(SYSCLK4) 0x01C4 0964 PLLDIV5 PLL Controller1 Divider5 Register(SYSCLK5) 0x01C4 0968 PLLDIV6 PLL Controller1 Divider6 Register(SYSCLK6) 0x01C4 096C – Reserved 0x01C4 0970 PLLDIV8 PLL Controller1 Divider8 Register(SYSCLK8) 0x01C4 0974 PLLDIV9 PLL Controller1 Divider9 Register(SYSCLK9) PLL2 ControllerRegisters 0x01C4 0C00 PID PeripheralID Register 0x01C4 0D00 PLLCTL PLL Controller2 PLL ControlRegister 0x01C4 0D10 PLLM PLL Controller2 PLL MultiplierControlRegister 0x01C4 0D18 PLLDIV1 PLL Controller2 Divider1 Register(PLL2_SYSCLK1 DDR2 PHY) 0x01C4 0D28 – Reserved 0x01C4 0D38 PLLCMD PLL Controller2 Command Register 0x01C4 0D3C PLLSTAT PLL Controller2 StatusRegister(Shows PLLC2 PLLCTL Status) PLL Controller2 ClockAlignControlRegister0x01C4 0D40 ALNCTL (IndicatesWhich SYSCLKs Need tobe AlignedforProperDeviceOperation) PLL Controller2 PLLDIV DividerRatioChange StatusRegister0x01C4 0D44 DCHANGE (IndicatesifSYSCLK DivideRatiohas been modified) 0x01C4 0D48 CKEN PLL Controller2 ClockEnableControlRegister 0x01C4 0D4C CKSTAT PLL Controller2 ClockStatusRegister(ForAllClocksExceptSYSCLKx) 0x01C4 0D50 SYSTAT PLL Controller2 SYSCLK StatusRegister(IndicatesSYSCLK on/offStatus) 0x01C4 0D54 -0x01C4 0FFF – Reserved

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PLL Controller□1 0101 0100 0001 0011 1010 1001 0110 1000 0000 CLKCTL.CLKOUT AUX_MXI/AUX_CLKIN DEV_MXI/DEV_CLKIN CLKOUT0 PLLDIV9□(/6□Prog) AUX_MXI SYSCLK9 SYSCLK8 PLLDIV8□(/8□Prog) SYSCLK6PLLDIV6□(/8□Prog) SYSCLK5PLLDIV5□(/8□Prog) PLLDIV4□(/6□Prog) SYSCLK4 SYSCLK3 PLLDIV3□(/4□Fixed) AUXCLK TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012

7.5.3 Clock PLL ConsiderationsWith ExternalClock Sources

Iftheinternaloscillatorisbypassed,tominimizetheclockjittera singlecleanpower supplyshouldpower boththeDM6467 deviceand theexternalclockoscillatorcircuit.The minimum CLKIN riseand falltimes shouldalsobe observed.For theinputclocktimingrequirements,see Section7.5.5,ClockPLL Electrical Data/Timing(Inputand OutputClocks). Rise/falltimes,duty cycles(high/lowpulsedurations),and the load capacitanceof the externalclock sourcemust meet thedevicerequirementsinthisdatamanual (seeSection6.3,ElectricalCharacteristics Over Recommended Ranges of Supply Voltageand OperatingTemperature, and Section7.5.5, Clock PLL ElectricalData/Timing(Inputand OutputClocks).

7.5.4 Output Clocks (CLKOUT0, AUDIO_CLK1, AUDIO_CLK0) -Clock SelectLogic

The DM6467 includesa selectablegeneral-purposeclockoutput(CLKOUT0) [seeFigure7-13]and two selectableaudiooutputclocks(AUDIO_CLK0 and AUDIO_CLK1) forsynchronizingexternalaudiodevices withtheon-chipsystem or videoclocks[seeFigure7-14 and Figure7-15].The sourcefortheseoutput clocksiscontrolledby theCLKCTL register(0x01C4 005C).Formore detailedinformationon theCLKCTL register,see Section4.3.3,Clockand OscillatorControl. Figure7-13.CLKOUT0 Source Selection Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 159 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

CLKCTL.AUD_CLK1 GP[4]/STC_CLKIN AUX_MXI/AUX_CLKIN AUDIO_CLK1 STC_CLKIN AUX_MXI VP0_CLKIN3 VP0_CLKIN2 VP0_CLKIN1 VP0_CLKIN0 CRG0_VCXI

0 GP[2]

URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x 10xUCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 0001AUXCLKPLL Controller□1 PINMUX0.AUDCK1 PINMUX0.CRGMUX 0011 CRG1_VCXI VP_CLKIN3/TS1_CLKO VP_CLKIN2 VP_CLKIN1 VP_CLKIN0 URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI DEV_MXI/DEV_CLKIN 0110 0101 0010 0100 1001 0111 1000 0000 CLKCTL.AUD_CLK0 GP[4]/STC_CLKIN AUX_MXI/AUX_CLKIN AUDIO_CLK0 STC_CLKIN AUX_MXI VP0_CLKIN3 VP0_CLKIN2 VP0_CLKIN1 VP0_CLKIN0 CRG0_VCXI

0 GP[3]

URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x 10xUCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 0001AUXCLKPLL Controller□1 PINMUX0.AUDCK0 PINMUX0.CRGMUX 0011 CRG1_VCXI VP_CLKIN3/TS1_CLKO VP_CLKIN2 VP_CLKIN1 VP_CLKIN0 URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI DEV_MXI/DEV_CLKIN TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-14.AUDIO_CLK0 Source Selection Figure7-15.AUDIO_CLK1 Source Selection

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7.5.5 Clock PLL ElectricalData/Timing(Inputand Output Clocks)

Table7-13.Timing Requirements forDEV_MXI/DEV_CLKIN (1)(2)(3)(4)(seeFigure7-16) -594,-729 NO. UNIT MIN NOM MAX 1 tc(DMXI) Cycletime,DEV_MXI/DEV_CLKIN 33.33 37.037 50 ns 2 tw(DMXIH) Pulseduration,DEV_MXI/DEV_CLKIN high 0.45C 0.55C ns 3 tw(DMXIL) Pulseduration,DEV_MXI/DEV_CLKIN low 0.45C 0.55C ns 4 tt(DMXI) Transitiontime,DEV_MXI/DEV_CLKIN 7 ns 5 tJ(DMXI) Periodjitter,DEV_MXI/DEV_CLKIN 0.02C ns (1) The DEV_MXI/DEV_CLKIN frequencyand PLL multiplyfactorshouldbe chosen such thattheresultingclockfrequencyiswithinthe specificrangeforCPU operatingfrequency.Forexample,fora -594speed devicewitha 27-MHz DEV_CLKIN frequency,thePLL multiplyfactorshouldbe ≤ 22 and fora -729speed devicewitha 27-MHz DEV_CLKIN frequency,thePLL multiplyfactorshouldbe ≤ 27. (2) The referencepointsfortheriseand falltransitionsaremeasured atVILMAX and VIH MIN. (3) Formore detailson thePLL multiplierfactors,see theTMS320DM646x DMSoC ARM Subsystem ReferenceGuide (LiteratureNumber SPRUEP9 ). (4) C = DEV_CLKIN cycletimeinns.Forexample,when DEV_MXI/DEV_CLKIN frequencyis27 MHz, use C = 37.037 ns. Figure7-16.DEV_MXI/DEV_CLKIN Timing Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 161 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

AUX_MXI/ AUX_CLKIN 5 1 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-14.Timing Requirements forAUX_MXI/AUX_CLKIN (1)(2)(3)(seeFigure7-17) -594,-729 NO. UNIT MIN NOM MAX 1 tc(AMXI) Cycletime,AUX_MXI/AUX_CLKIN 41.6 or20.83 (4) ns 2 tw(AMXIH) Pulseduration,AUX_MXI/AUX_CLKIN high 0.45C 0.55C ns 3 tw(AMXIL) Pulseduration,AUX_MXI/AUX_CLKIN low 0.45C 0.55C ns 4 tt(AMXI) Transitiontime,AUX_MXI/AUX_CLKIN 7 ns 5 tJ(AMXI) Periodjitter,AUX_MXI/AUX_CLKIN 0.02C ns

6 Sf Frequencystability,AUX_MXI/AUX_CLKIN (4) ± 50 ppm

(1) The referencepointsfortheriseand falltransitionsaremeasured atVILMAX and VIH MIN. (2) Formore detailson thePLL,see theTMS320DM646x DMSoC UniversalSerialBus (USB) ControllerUser's Guide (LiteratureNumber SPRUER7 ). (3) C = DEV_CLKIN cycletimeinns.Forexample,when AUX_MXI/AUX_CLKIN frequencyis24 MHz, use C = 41.6 ns and when AUX_MXI/AUX_CLKIN frequencyis48 MHz, use C = 20.83 ns. (4) IftheUSB isused,a 24-MHz, 50-ppm crystalisrecommended. Figure7-17.AUX_MXI/AUX_CLKIN Timing

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(Divide-by-1) TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-15.SwitchingCharacteristicsOver Recommended OperatingConditionsforCLKOUT0 (1)(2) (seeFigure7-18) -594,-729 NO. PARAMETER UNIT MIN MAX 1 tc(CLKOUT0) Cycletime,CLKOUT0 6.734 296.296 ns 2 tw(CLKOUT0H) Pulseduration,CLKOUT0 high 0.4P 0.6P ns 3 tw(CLKOUT0L) Pulseduration,CLKOUT0 low 0.4P 0.6P ns 4 tt(CLKOUT0) Transitiontime,CLKOUT0 0.05P ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVOL MAX and VOH MIN. (2) P = 1/CLKOUT0 clockfrequencyinnanoseconds(ns).Forexample,when CLKOUT0 frequencyis27 MHz, use P = 37.037 ns. Figure7-18.CLKOUT0 Timing Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 163 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.6 Enhanced DirectMemory Access (EDMA3) Controller

The EDMA controllerhandlesalldatatransfersbetween memories and thedeviceslaveperipheralson the DM6467 device.These data transfersincludecache servicing,non-cacheablememory accesses, user-programmeddatatransfers,and hostaccesses.These aresummarized as follows:

Transferto/fromon-chipmemories – ARM926 TCM – DSP L1D memory – DSP L2 memory
Transferto/fromexternalstorage – DDR2 SDRAM – NAND flash – AsynchronousEMIF (EMIFA) – ATA
Transferto/fromperipherals/hosts – VLYNQ – HPI – McASP0/1 – SPI – I2C – PWM0/1 – UART0/1/2 – PCI The EDMA supportstwo addressingmodes: constantaddressingand incrementaddressing.On the DM6467, constantaddressingmode isnot supportedby any peripheralor internalmemory. For more informationon thesetwo addressingmodes, see theTMS320DM646x DMSoC Enhanced DirectMemory Access (EDMA) ControllerUser’s Guide (literaturenumber SPRUEQ5 ). The DM6467 devicesupportsa programmable defaultburstsizefeature.The defaultburstsizeofeach EDMA3 TransferController(TC) is configuredvia the EDMA TransferControllerDefaultBurstSize Configurationregister(EDMATCCFG). For more detailedinformationon theEDMATCCFG register,see Section4.6.2,PeripheralSelectionAfterDeviceReset.

7.6.1 EDMA3 Channel SynchronizationEvents

The EDMA supportsup to 64 EDMA channelswhich serviceperipheraldevicesand externalmemory. Table7-16 liststhesourceofEDMA synchronizationeventsassociatedwitheach oftheprogrammable EDMA channels.For theDM6467 device,theassociationofan eventtoa channelisfixed;each ofthe EDMA channelshas one specificevent associatedwithit.These specificeventsare capturedin the EDMA eventregisters(ER, ERH) even ifthe eventsare disabledby the EDMA eventenableregisters (EER, EERH). For more detailedinformationon theEDMA module and how EDMA eventsare enabled, captured,processed,linked,chained,and cleared,etc.,see the TMS320DM646x DMSoC Enhanced DirectMemory Access (EDMA) ControllerUser’s Guide (literaturenumber SPRUEQ5 ) Table7-16.DM6467 EDMA Channel SynchronizationEvents(1) EDMA EVENT NAME EVENT DESCRIPTIONCHANNEL 0-3 – Reserved (1) Inadditiontotheeventsshown inthistable,each ofthe64 channelscan alsobe synchronizedwith thetransfercompletionoralternatetransfercompletionevents.Formore detailedinformationon EDMA event-transferchaining,see theTMS320DM646x DMSoC Enhanced DirectMemory Access (EDMA) ControllerUser's Guide (literaturenumber SPRUEQ5 ).

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-16.DM6467 EDMA Channel SynchronizationEvents(1) (continued) EDMA EVENT NAME EVENT DESCRIPTIONCHANNEL

4 AXEVTE0 McASP0 TransmitEventEven

5 AXEVTO0 McASP0 TransmitEventOdd

6 AXEVT0 McASP0 TransmitEvent

7 AREVTE0 McASP0 ReceiveEventEven

8 AREVTO0 McASP0 ReceiveEventOdd

9 AREVT0 McASP0 ReceiveEvent

10 AXEVTE1 McASP1 TransmitEventEven

11 AXEVTO1 McASP1 TransmitEventOdd

12 AXEVT1 McASP1 TransmitEvent

13-15 – Reserved

16 SPIXEVT SPI TransmitEvent

17 SPIREVT SPI ReceiveEvent

18 URXEVT0 UART 0 ReceiveEvent

19 UTXEVT0 UART 0 TransmitEvent

20 URXEVT1 UART 1 ReceiveEvent

21 UTXEVT1 UART 1 TransmitEvent

22 URXEVT2 UART 2 ReceiveEvent

23 UTXEVT2 UART 2 TransmitEvent

24-27 – Reserved

28 ICREVT I2C ReceiveEvent

29 ICXEVT I2C TransmitEvent

30-31 – Reserved[Unused]

32 GPINT0 GPIO 0 InterruptEvent

33 GPINT1 GPIO 1 InterruptEvent

34 GPINT2 GPIO 2 InterruptEvent

35 GPINT3 GPIO 3 InterruptEvent

36 GPINT4 GPIO 4 InterruptEvent

37 GPINT5 GPIO 5 InterruptEvent

38 GPINT6 GPIO 6 InterruptEvent

39 GPINT7 GPIO 7 InterruptEvent

40 GPBNKINT0 GPIO Bank 0 InterruptEvent

41 GPBNKINT1 GPIO Bank 1 InterruptEvent

42 GPBNKINT2 GPIO Bank 2 InterruptEvent

43 CP_ECDCMP1 HDVICP1 ECDCMP InterruptEvent

44 CP_MC1 HDVICP1 MC InterruptEvent

45 CP_BS1 HDVICP1 BS InterruptEvent

46 CP_CALC1 HDVICP1 CALC InterruptEvent

47 CP_LPF1 HDVICP1 LPF InterruptEvent

48 TEVTL0 Timer0 EventLow Interrupt

49 TEVTH0 Timer0 EventHighInterrupt

50 TEVTL1 Timer1 EventLow Interrupt

51 TEVTH1 Timer1 EventHighInterrupt

52 PWM0 PWM 0 InterruptEvent

53 PWM1 PWM 1 InterruptEvent

54-56 – Reserved

57 CP_ME0 HDVICP0 ME InterruptEvent

58 CP_IPE0 HDVICP0 IPE InterruptEvent

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-16.DM6467 EDMA Channel SynchronizationEvents(1) (continued) EDMA EVENT NAME EVENT DESCRIPTIONCHANNEL

59 CP_ECDCMP0 HDVICP0 ECDCMP InterruptEvent

60 CP_MC0 HDVICP0 MC InterruptEvent

61 CP_BS0 HDVICP0 BS InterruptEvent

62 CP_CALC0 HDVICP0 CALC InterruptEvent

63 CP_LPF0 HDVICP0 LPF InterruptEvent

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7.6.2 EDMA PeripheralRegisterDescription(s)

Table 7-17 liststhe EDMA registers,theircorrespondingacronyms, and DM6467 device memory locations. Table7-17.DM6467 EDMA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME Channel ControllerRegisters 0x01C0 0000 PID PeripheralIdentificationRegister 0x01C0 0004 CCCFG EDMA3CC ConfigurationRegister 0x01C0 0008 -0x01C0 00FF – Reserved GlobalRegisters 0x01C0 0100 DCHMAP0 DMA Channel0 Mapping toPaRAM Register 0x01C0 0104 DCHMAP1 DMA Channel1 Mapping toPaRAM Register 0x01C0 0108 DCHMAP2 DMA Channel2 Mapping toPaRAM Register 0x01C0 010C DCHMAP3 DMA Channel3 Mapping toPaRAM Register 0x01C0 0110 DCHMAP4 DMA Channel4 Mapping toPaRAM Register 0x01C0 0114 DCHMAP5 DMA Channel5 Mapping toPaRAM Register 0x01C0 0118 DCHMAP6 DMA Channel6 Mapping toPaRAM Register 0x01C0 011C DCHMAP7 DMA Channel7 Mapping toPaRAM Register 0x01C0 0120 DCHMAP8 DMA Channel8 Mapping toPaRAM Register 0x01C0 0124 DCHMAP9 DMA Channel9 Mapping toPaRAM Register 0x01C0 0128 DCHMAP10 DMA Channel10 Mapping toPaRAM Register 0x01C0 012C DCHMAP11 DMA Channel11 Mapping toPaRAM Register 0x01C0 0130 DCHMAP12 DMA Channel12 Mapping toPaRAM Register 0x01C0 0134 DCHMAP13 DMA Channel13 Mapping toPaRAM Register 0x01C0 0138 DCHMAP14 DMA Channel14 Mapping toPaRAM Register 0x01C0 013C DCHMAP15 DMA Channel15 Mapping toPaRAM Register 0x01C0 0140 DCHMAP16 DMA Channel16 Mapping toPaRAM Register 0x01C0 0144 DCHMAP17 DMA Channel17 Mapping toPaRAM Register 0x01C0 0148 DCHMAP18 DMA Channel18 Mapping toPaRAM Register 0x01C0 014C DCHMAP19 DMA Channel19 Mapping toPaRAM Register 0x01C0 0150 DCHMAP20 DMA Channel20 Mapping toPaRAM Register 0x01C0 0154 DCHMAP21 DMA Channel21 Mapping toPaRAM Register 0x01C0 0158 DCHMAP22 DMA Channel22 Mapping toPaRAM Register 0x01C0 015C DCHMAP23 DMA Channel23 Mapping toPaRAM Register 0x01C0 0160 DCHMAP24 DMA Channel24 Mapping toPaRAM Register 0x01C0 0164 DCHMAP25 DMA Channel25 Mapping toPaRAM Register 0x01C0 0168 DCHMAP26 DMA Channel26 Mapping toPaRAM Register 0x01C0 016C DCHMAP27 DMA Channel27 Mapping toPaRAM Register 0x01C0 0170 DCHMAP28 DMA Channel28 Mapping toPaRAM Register 0x01C0 0174 DCHMAP29 DMA Channel29 Mapping toPaRAM Register 0x01C0 0178 DCHMAP30 DMA Channel30 Mapping toPaRAM Register 0x01C0 017C DCHMAP31 DMA Channel31 Mapping toPaRAM Register 0x01C0 0180 DCHMAP32 DMA Channel32 Mapping toPaRAM Register 0x01C0 0184 DCHMAP33 DMA Channel33 Mapping toPaRAM Register 0x01C0 0188 DCHMAP34 DMA Channel34 Mapping toPaRAM Register 0x01C0 018C DCHMAP35 DMA Channel35 Mapping toPaRAM Register 0x01C0 0190 DCHMAP36 DMA Channel36 Mapping toPaRAM Register 0x01C0 0194 DCHMAP37 DMA Channel37 Mapping toPaRAM Register Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 167 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 0198 DCHMAP38 DMA Channel38 Mapping toPaRAM Register 0x01C0 019C DCHMAP39 DMA Channel39 Mapping toPaRAM Register 0x01C0 01A0 DCHMAP40 DMA Channel40 Mapping toPaRAM Register 0x01C0 01A4 DCHMAP41 DMA Channel41 Mapping toPaRAM Register 0x01C0 01A8 DCHMAP42 DMA Channel42 Mapping toPaRAM Register 0x01C0 01AC DCHMAP43 DMA Channel43 Mapping toPaRAM Register 0x01C0 01B0 DCHMAP44 DMA Channel44 Mapping toPaRAM Register 0x01C0 01B4 DCHMAP45 DMA Channel45 Mapping toPaRAM Register 0x01C0 01B8 DCHMAP46 DMA Channel46 Mapping toPaRAM Register 0x01C0 01BC DCHMAP47 DMA Channel47 Mapping toPaRAM Register 0x01C0 01C0 DCHMAP48 DMA Channel48 Mapping toPaRAM Register 0x01C0 01C4 DCHMAP49 DMA Channel49 Mapping toPaRAM Register 0x01C0 01C8 DCHMAP50 DMA Channel50 Mapping toPaRAM Register 0x01C0 01CC DCHMAP51 DMA Channel51 Mapping toPaRAM Register 0x01C0 01D0 DCHMAP52 DMA Channel52 Mapping toPaRAM Register 0x01C0 01D4 DCHMAP53 DMA Channel53 Mapping toPaRAM Register 0x01C0 01D8 DCHMAP54 DMA Channel54 Mapping toPaRAM Register 0x01C0 01DC DCHMAP55 DMA Channel55 Mapping toPaRAM Register 0x01C0 01E0 DCHMAP56 DMA Channel56 Mapping toPaRAM Register 0x01C0 01E4 DCHMAP57 DMA Channel57 Mapping toPaRAM Register 0x01C0 01E8 DCHMAP58 DMA Channel58 Mapping toPaRAM Register 0x01C0 01EC DCHMAP59 DMA Channel59 Mapping toPaRAM Register 0x01C0 01F0 DCHMAP60 DMA Channel60 Mapping toPaRAM Register 0x01C0 01F4 DCHMAP61 DMA Channel61 Mapping toPaRAM Register 0x01C0 01F8 DCHMAP62 DMA Channel62 Mapping toPaRAM Register 0x01C0 01FC DCHMAP63 DMA Channel63 Mapping toPaRAM Register 0x01C0 0200 QCHMAP0 QDMA Channel0 Mapping toPaRAM Register 0x01C0 0204 QCHMAP1 QDMA Channel1 Mapping toPaRAM Register 0x01C0 0208 QCHMAP2 QDMA Channel2 Mapping toPaRAM Register 0x01C0 020C QCHMAP3 QDMA Channel3 Mapping toPaRAM Register 0x01C0 0210 QCHMAP4 QDMA Channel4 Mapping toPaRAM Register 0x01C0 0214 QCHMAP5 QDMA Channel5 Mapping toPaRAM Register 0x01C0 0218 QCHMAP6 QDMA Channel6 Mapping toPaRAM Register 0x01C0 021C QCHMAP7 QDMA Channel7 Mapping toPaRAM Register 0x01C0 0220 -0x01C0 023F – Reserved 0x01C0 0240 DMAQNUM0 DMA Queue Number Register0 (Channels00 to07) 0x01C0 0244 DMAQNUM1 DMA Queue Number Register1 (Channels08 to15) 0x01C0 0248 DMAQNUM2 DMA Queue Number Register2 (Channels16 to23) 0x01C0 024C DMAQNUM3 DMA Queue Number Register3 (Channels24 to31) 0x01C0 0250 DMAQNUM4 DMA Queue Number Register4 (Channels32 to39) 0x01C0 0254 DMAQNUM5 DMA Queue Number Register5 (Channels40 to47) 0x01C0 0258 DMAQNUM6 DMA Queue Number Register6 (Channels48 to55) 0x01C0 025C DMAQNUM7 DMA Queue Number Register7 (Channels56 to63) 0x01C0 0260 QDMAQNUM CC QDMA Queue Number 0x01C0 0264 -0x01C0 0283 – Reserved 0x01C0 0284 QUEPRI Queue PriorityRegister 0x01C0 0288 -0x01C0 02FF – Reserved

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 0300 EMR EventMissedRegister 0x01C0 0304 EMRH EventMissedRegisterHigh 0x01C0 0308 EMCR EventMissedClearRegister 0x01C0 030C EMCRH EventMissedClearRegisterHigh 0x01C0 0310 QEMR QDMA EventMissedRegister 0x01C0 0314 QEMCR QDMA EventMissedClearRegister 0x01C0 0318 CCERR EDMA3CC ErrorRegister 0x01C0 031C CCERRCLR EDMA3CC ErrorClearRegister 0x01C0 0320 EEVAL ErrorEvaluateRegister 0x01C0 0324 -0x01C0 033F – Reserved 0x01C0 0340 DRAE0 DMA RegionAccess EnableRegisterforRegion0 0x01C0 0344 DRAEH0 DMA RegionAccess EnableRegisterHighforRegion0 0x01C0 0348 DRAE1 DMA RegionAccess EnableRegisterforRegion1 0x01C0 034C DRAEH1 DMA RegionAccess EnableRegisterHighforRegion1 0x01C0 0350-0x01C0 035F – Reserved 0x01C0 0360 DRAE4 DMA RegionAccess EnableRegisterforRegion4 0x01C0 0364 DRAEH4 DMA RegionAccess EnableRegisterHighforRegion4 0x01C0 0368 DRAE5 DMA RegionAccess EnableRegisterforRegion5 0x01C0 036C DRAEH5 DMA RegionAccess EnableRegisterHighforRegion5 0x01C0 0370 DRAE6 DMA RegionAccess EnableRegisterforRegion6 0x01C0 0374 DRAEH6 DMA RegionAccess EnableRegisterHighforRegion6 0x01C0 0378 DRAE7 DMA RegionAccess EnableRegisterforRegion7 0x01C0 037C DRAEH7 DMA RegionAccess EnableRegisterHighforRegion7 0x01C0 0380 QRAE0 QDMA RegionAccess EnableRegisterforRegion0 0x01C0 0384 QRAE1 QDMA RegionAccess EnableRegisterforRegion1 0x01C0 0388 -0x01C0 038F – Reserved 0x01C0 0390 QRAE4 QDMA RegionAccess EnableRegisterforRegion4 0x01C0 0394 QRAE5 QDMA RegionAccess EnableRegisterforRegion5 0x01C0 0398 QRAE6 QDMA RegionAccess EnableRegisterforRegion6 0x01C0 039C QRAE7 QDMA RegionAccess EnableRegisterforRegion7 0x01C0 03A0 -0x01C0 03FF – Reserved 0x01C0 0400 Q0E0 EventQ0 Entry0 Register 0x01C0 0404 Q0E1 EventQ0 Entry1 Register 0x01C0 0408 Q0E2 EventQ0 Entry2 Register 0x01C0 040C Q0E3 EventQ0 Entry3 Register 0x01C0 0410 Q0E4 EventQ0 Entry4 Register 0x01C0 0414 Q0E5 EventQ0 Entry5 Register 0x01C0 0418 Q0E6 EventQ0 Entry6 Register 0x01C0 041C Q0E7 EventQ0 Entry7 Register 0x01C0 0420 Q0E8 EventQ0 Entry8 Register 0x01C0 0424 Q0E9 EventQ0 Entry9 Register 0x01C0 0428 Q0E10 EventQ0 Entry10 Register 0x01C0 042C Q0E11 EventQ0 Entry11 Register 0x01C0 0430 Q0E12 EventQ0 Entry12 Register 0x01C0 0434 Q0E13 EventQ0 Entry13 Register 0x01C0 0438 Q0E14 EventQ0 Entry14 Register 0x01C0 043C Q0E15 EventQ0 Entry15 Register Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 169 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 0440 Q1E0 EventQ1 Entry0 Register 0x01C0 0444 Q1E1 EventQ1 Entry1 Register 0x01C0 0448 Q1E2 EventQ1 Entry2 Register 0x01C0 044C Q1E3 EventQ1 Entry3 Register 0x01C0 0450 Q1E4 EventQ1 Entry4 Register 0x01C0 0454 Q1E5 EventQ1 Entry5 Register 0x01C0 0458 Q1E6 EventQ1 Entry6 Register 0x01C0 045C Q1E7 EventQ1 Entry7 Register 0x01C0 0460 Q1E8 EventQ1 Entry8 Register 0x01C0 0464 Q1E9 EventQ1 Entry9 Register 0x01C0 0468 Q1E10 EventQ1 Entry10 Register 0x01C0 046C Q1E11 EventQ1 Entry11 Register 0x01C0 0470 Q1E12 EventQ1 Entry12 Register 0x01C0 0474 Q1E13 EventQ1 Entry13 Register 0x01C0 0478 Q1E14 EventQ1 Entry14 Register 0x01C0 047C Q1E15 EventQ1 Entry15 Register 0x01C0 0480 Q2E0 EventQ2 Entry0 Register 0x01C0 0484 Q2E1 EventQ2 Entry1 Register 0x01C0 0488 Q2E2 EventQ2 Entry2 Register 0x01C0 048C Q2E3 EventQ2 Entry3 Register 0x01C0 0490 Q2E4 EventQ2 Entry4 Register 0x01C0 0494 Q2E5 EventQ2 Entry5 Register 0x01C0 0498 Q2E6 EventQ2 Entry6 Register 0x01C0 049C Q2E7 EventQ2 Entry7 Register 0x01C0 04A0 Q2E8 EventQ2 Entry8 Register 0x01C0 04A4 Q2E9 EventQ2 Entry9 Register 0x01C0 04A8 Q2E10 EventQ2 Entry10 Register 0x01C0 04AC Q2E11 EventQ2 Entry11 Register 0x01C0 04B0 Q2E12 EventQ2 Entry12 Register 0x01C0 04B4 Q2E13 EventQ2 Entry13 Register 0x01C0 04B8 Q2E14 EventQ2 Entry14 Register 0x01C0 04BC Q2E15 EventQ2 Entry15 Register 0x01C0 04C0 Q3E0 EventQ3 Entry0 Register 0x01C0 04C4 Q3E1 EventQ3 Entry1 Register 0x01C0 04C8 Q3E2 EventQ3 Entry2 Register 0x01C0 04CC Q3E3 EventQ3 Entry3 Register 0x01C0 04D0 Q3E4 EventQ3 Entry4 Register 0x01C0 04D4 Q3E5 EventQ3 Entry5 Register 0x01C0 04D8 Q3E6 EventQ3 Entry6 Register 0x01C0 04DC Q3E7 EventQ3 Entry7 Register 0x01C0 04E0 Q3E8 EventQ3 Entry8 Register 0x01C0 04E4 Q3E9 EventQ3 Entry9 Register 0x01C0 04E8 Q3E10 EventQ3 Entry10 Register 0x01C0 04EC Q3E11 EventQ3 Entry11 Register 0x01C0 04F0 Q3E12 EventQ3 Entry12 Register 0x01C0 04F4 Q3E13 EventQ3 Entry13 Register 0x01C0 04F8 Q3E14 EventQ3 Entry14 Register

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 04FC Q3E15 EventQ3 Entry15 Register 0x01C0 0500 -0x01C0 05FF – Reserved 0x01C0 0600 QSTAT0 Queue 0 StatusRegister 0x01C0 0604 QSTAT1 Queue 1 StatusRegister 0x01C0 0608 QSTAT2 Queue 2 StatusRegister 0x01C0 060C QSTAT3 Queue 3 StatusRegister 0x01C0 0610 -0x01C0 061F – Reserved 0x01C0 0620 QWMTHRA Queue Watermark ThresholdA RegisterforQ[3:0] 0x01C0 0624 -0x01C0 063F – Reserved 0x01C0 0640 CCSTAT EDMA3CC StatusRegister 0x01C0 0644 -0x01C0 0FFF – Reserved GlobalChannel Registers 0x01C0 1000 ER EventRegister 0x01C0 1004 ERH EventRegisterHigh 0x01C0 1008 ECR EventClearRegister 0x01C0 100C ECRH EventClearRegisterHigh 0x01C0 1010 ESR EventSetRegister 0x01C0 1014 ESRH EventSetRegisterHigh 0x01C0 1018 CER ChainedEventRegister 0x01C0 101C CERH ChainedEventRegisterHigh 0x01C0 1020 EER EventEnableRegister 0x01C0 1024 EERH EventEnableRegisterHigh 0x01C0 1028 EECR EventEnableClearRegister 0x01C0 102C EECRH EventEnableClearRegisterHigh 0x01C0 1030 EESR EventEnableSetRegister 0x01C0 1034 EESRH EventEnableSetRegisterHigh 0x01C0 1038 SER SecondaryEventRegister 0x01C0 103C SERH SecondaryEventRegisterHigh 0x01C0 1040 SECR SecondaryEventClearRegister 0x01C0 1044 SECRH SecondaryEventClearRegisterHigh 0x01C0 1048 -0x01C0 104F – Reserved 0x01C0 1050 IER InterruptEnableRegister 0x01C0 1054 IERH InterruptEnableRegisterHigh 0x01C0 1058 IECR InterruptEnableClearRegister 0x01C0 105C IECRH InterruptEnableClearRegisterHigh 0x01C0 1060 IESR InterruptEnableSetRegister 0x01C0 1064 IESRH InterruptEnableSetRegisterHigh 0x01C0 1068 IPR InterruptPendingRegister 0x01C0 106C IPRH InterruptPendingRegisterHigh 0x01C0 1070 ICR InterruptClearRegister 0x01C0 1074 ICRH InterruptClearRegisterHigh 0x01C0 1078 IEVAL InterruptEvaluateRegister 0x01C0 107C -0x01C0 107F – Reserved 0x01C0 1080 QER QDMA EventRegister 0x01C0 1084 QEER QDMA EventEnableRegister 0x01C0 1088 QEECR QDMA EventEnableClearRegister 0x01C0 108C QEESR QDMA EventEnableSetRegister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 171 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 1090 QSER QDMA SecondaryEventRegister 0x01C0 1094 QSECR QDMA SecondaryEventClearRegister 0x01C0 1098 -0x01C0 1FFF – Reserved Shadow Region 0 Channel Registers 0x01C0 2000 ER EventRegister 0x01C0 2004 ERH EventRegisterHigh 0x01C0 2008 ECR EventClearRegister 0x01C0 200C ECRH EventClearRegisterHigh 0x01C0 2010 ESR EventSetRegister 0x01C0 2014 ESRH EventSetRegisterHigh 0x01C0 2018 CER ChainedEventRegister 0x01C0 201C CERH ChainedEventRegisterHigh 0x01C0 2020 EER EventEnableRegister 0x01C0 2024 EERH EventEnableRegisterHigh 0x01C0 2028 EECR EventEnableClearRegister 0x01C0 202C EECRH EventEnableClearRegisterHigh 0x01C0 2030 EESR EventEnableSetRegister 0x01C0 2034 EESRH EventEnableSetRegisterHigh 0x01C0 2038 SER SecondaryEventRegister 0x01C0 203C SERH SecondaryEventRegisterHigh 0x01C0 2040 SECR SecondaryEventClearRegister 0x01C0 2044 SECRH SecondaryEventClearRegisterHigh 0x01C0 2048 -0x01C0 204F – Reserved 0x01C0 2050 IER InterruptEnableRegister 0x01C0 2054 IERH InterruptEnableRegisterHigh 0x01C0 2058 IECR InterruptEnableClearRegister 0x01C0 205C IECRH InterruptEnableClearRegisterHigh 0x01C0 2060 IESR InterruptEnableSetRegister 0x01C0 2064 IESRH InterruptEnableSetRegisterHigh 0x01C0 2068 IPR InterruptPendingRegister 0x01C0 206C IPRH InterruptPendingRegisterHigh 0x01C0 2070 ICR InterruptClearRegister 0x01C0 2074 ICRH InterruptClearRegisterHigh 0x01C0 2078 IEVAL InterruptEvaluateRegister 0x01C0 207C -0x01C0 207F – Reserved 0x01C0 2080 QER QDMA EventRegister 0x01C0 2084 QEER QDMA EventEnableRegister 0x01C0 2088 QEECR QDMA EventEnableClearRegister 0x01C0 208C QEESR QDMA EventEnableSetRegister 0x01C0 2090 QSER QDMA SecondaryEventRegister 0x01C0 2094 QSECR QDMA SecondaryEventClearRegister 0x01C0 2098 -0x01C0 21FF – Reserved Shadow Region 1 Channel Registers 0x01C0 2200 ER EventRegister 0x01C0 2204 ERH EventRegisterHigh 0x01C0 2208 ECR EventClearRegister 0x01C0 220C ECRH EventClearRegisterHigh

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 2210 ESR EventSetRegister 0x01C0 2214 ESRH EventSetRegisterHigh 0x01C0 2218 CER ChainedEventRegister 0x01C0 221C CERH ChainedEventRegisterHigh 0x01C0 2220 EER EventEnableRegister 0x01C0 2224 EERH EventEnableRegisterHigh 0x01C0 2228 EECR EventEnableClearRegister 0x01C0 222C EECRH EventEnableClearRegisterHigh 0x01C0 2230 EESR EventEnableSetRegister 0x01C0 2234 EESRH EventEnableSetRegisterHigh 0x01C0 2238 SER SecondaryEventRegister 0x01C0 223C SERH SecondaryEventRegisterHigh 0x01C0 2240 SECR SecondaryEventClearRegister 0x01C0 2244 SECRH SecondaryEventClearRegisterHigh 0x01C0 2248 -0x01C0 224F – Reserved 0x01C0 2250 IER InterruptEnableRegister 0x01C0 2254 IERH InterruptEnableRegisterHigh 0x01C0 2258 IECR InterruptEnableClearRegister 0x01C0 225C IECRH InterruptEnableClearRegisterHigh 0x01C0 2260 IESR InterruptEnableSetRegister 0x01C0 2264 IESRH InterruptEnableSetRegisterHigh 0x01C0 2268 IPR InterruptPendingRegister 0x01C0 226C IPRH InterruptPendingRegisterHigh 0x01C0 2270 ICR InterruptClearRegister 0x01C0 2274 ICRH InterruptClearRegisterHigh 0x01C0 2278 IEVAL InterruptEvaluateRegister 0x01C0 227C -0x01C0 227F – Reserved 0x01C0 2280 QER QDMA EventRegister 0x01C0 2284 QEER QDMA EventEnableRegister 0x01C0 2288 QEECR QDMA EventEnableClearRegister 0x01C0 228C QEESR QDMA EventEnableSetRegister 0x01C0 2290 QSER QDMA SecondaryEventRegister 0x01C0 2294 QSECR QDMA SecondaryEventClearRegister 0x01C0 2298 -0x01C0 23FF – Reserved 0x01C0 2400 -0x01C0 25FF – Reserved 0x01C0 2600 -0x01C0 27FF – Reserved Shadow Region 4 Channel Registers 0x01C0 2800 ER EventRegister 0x01C0 2804 ERH EventRegisterHigh 0x01C0 2808 ECR EventClearRegister 0x01C0 280C ECRH EventClearRegisterHigh 0x01C0 2810 ESR EventSetRegister 0x01C0 2814 ESRH EventSetRegisterHigh 0x01C0 2818 CER ChainedEventRegister 0x01C0 281C CERH ChainedEventRegisterHigh 0x01C0 2820 EER EventEnableRegister 0x01C0 2824 EERH EventEnableRegisterHigh Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 173 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 2828 EECR EventEnableClearRegister 0x01C0 282C EECRH EventEnableClearRegisterHigh 0x01C0 2830 EESR EventEnableSetRegister 0x01C0 2834 EESRH EventEnableSetRegisterHigh 0x01C0 2838 SER SecondaryEventRegister 0x01C0 283C SERH SecondaryEventRegisterHigh 0x01C0 2840 SECR SecondaryEventClearRegister 0x01C0 2844 SECRH SecondaryEventClearRegisterHigh 0x01C0 2848 -0x01C0 284F – Reserved 0x01C0 2850 IER InterruptEnableRegister 0x01C0 2854 IERH InterruptEnableRegisterHigh 0x01C0 2858 IECR InterruptEnableClearRegister 0x01C0 285C IECRH InterruptEnableClearRegisterHigh 0x01C0 2860 IESR InterruptEnableSetRegister 0x01C0 2864 IESRH InterruptEnableSetRegisterHigh 0x01C0 2868 IPR InterruptPendingRegister 0x01C0 286C IPRH InterruptPendingRegisterHigh 0x01C0 2870 ICR InterruptClearRegister 0x01C0 2874 ICRH InterruptClearRegisterHigh 0x01C0 2878 IEVAL InterruptEvaluateRegister 0x01C0 287C -0x01C0 287F – Reserved 0x01C0 2880 QER QDMA EventRegister 0x01C0 2884 QEER QDMA EventEnableRegister 0x01C0 2888 QEECR QDMA EventEnableClearRegister 0x01C0 288C QEESR QDMA EventEnableSetRegister 0x01C0 2890 QSER QDMA SecondaryEventRegister 0x01C0 2894 QSECR QDMA SecondaryEventClearRegister 0x01C0 2898 -0x01C0 29FF – Reserved Shadow Region 5 Channel Registers 0x01C0 2A00 ER EventRegister 0x01C0 2A04 ERH EventRegisterHigh 0x01C0 2A08 ECR EventClearRegister 0x01C0 2A0C ECRH EventClearRegisterHigh 0x01C0 2A10 ESR EventSetRegister 0x01C0 2A14 ESRH EventSetRegisterHigh 0x01C0 2A18 CER ChainedEventRegister 0x01C0 2A1C CERH ChainedEventRegisterHigh 0x01C0 2A20 EER EventEnableRegister 0x01C0 2A24 EERH EventEnableRegisterHigh 0x01C0 2A28 EECR EventEnableClearRegister 0x01C0 2A2C EECRH EventEnableClearRegisterHigh 0x01C0 2A30 EESR EventEnableSetRegister 0x01C0 2A34 EESRH EventEnableSetRegisterHigh 0x01C0 2A38 SER SecondaryEventRegister 0x01C0 2A3C SERH SecondaryEventRegisterHigh 0x01C0 2A40 SECR SecondaryEventClearRegister 0x01C0 2A44 SECRH SecondaryEventClearRegisterHigh

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 2A48 -0x01C0 2A4F – Reserved 0x01C0 2A50 IER InterruptEnableRegister 0x01C0 2A54 IERH InterruptEnableRegisterHigh 0x01C0 2A58 IECR InterruptEnableClearRegister 0x01C0 2A5C IECRH InterruptEnableClearRegisterHigh 0x01C0 2A60 IESR InterruptEnableSetRegister 0x01C0 2A64 IESRH InterruptEnableSetRegisterHigh 0x01C0 2A68 IPR InterruptPendingRegister 0x01C0 2A6C IPRH InterruptPendingRegisterHigh 0x01C0 2A70 ICR InterruptClearRegister 0x01C0 2A74 ICRH InterruptClearRegisterHigh 0x01C0 2A78 IEVAL InterruptEvaluateRegister 0x01C0 2A7C -0x01C0 2A7F – Reserved 0x01C0 2A80 QER QDMA EventRegister 0x01C0 2A84 QEER QDMA EventEnableRegister 0x01C0 2A88 QEECR QDMA EventEnableClearRegister 0x01C0 2A8C QEESR QDMA EventEnableSetRegister 0x01C0 2A90 QSER QDMA SecondaryEventRegister 0x01C0 2A94 QSECR QDMA SecondaryEventClearRegister 0x01C0 2A98 -0x01C0 2BFF – Reserved Shadow Region 6 Channel Registers 0x01C0 2C00 ER EventRegister 0x01C0 2C04 ERH EventRegisterHigh 0x01C0 2C08 ECR EventClearRegister 0x01C0 2C0C ECRH EventClearRegisterHigh 0x01C0 2C10 ESR EventSetRegister 0x01C0 2C14 ESRH EventSetRegisterHigh 0x01C0 2C18 CER ChainedEventRegister 0x01C0 2C1C CERH ChainedEventRegisterHigh 0x01C0 2C20 EER EventEnableRegister 0x01C0 2C24 EERH EventEnableRegisterHigh 0x01C0 2C28 EECR EventEnableClearRegister 0x01C0 2C2C EECRH EventEnableClearRegisterHigh 0x01C0 2C30 EESR EventEnableSetRegister 0x01C0 2C34 EESRH EventEnableSetRegisterHigh 0x01C0 2C38 SER SecondaryEventRegister 0x01C0 2C3C SERH SecondaryEventRegisterHigh 0x01C0 2C40 SECR SecondaryEventClearRegister 0x01C0 2C44 SECRH SecondaryEventClearRegisterHigh 0x01C0 2C48 -0x01C0 2C4F – Reserved 0x01C0 2C50 IER InterruptEnableRegister 0x01C0 2C54 IERH InterruptEnableRegisterHigh 0x01C0 2C58 IECR InterruptEnableClearRegister 0x01C0 2C5C IECRH InterruptEnableClearRegisterHigh 0x01C0 2C60 IESR InterruptEnableSetRegister 0x01C0 2C64 IESRH InterruptEnableSetRegisterHigh 0x01C0 2C68 IPR InterruptPendingRegister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 175 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 2C6C IPRH InterruptPendingRegisterHigh 0x01C0 2C70 ICR InterruptClearRegister 0x01C0 2C74 ICRH InterruptClearRegisterHigh 0x01C0 2C78 IEVAL InterruptEvaluateRegister 0x01C0 2C7C -0x01C0 2C7F – Reserved 0x01C0 2C80 QER QDMA EventRegister 0x01C0 2C84 QEER QDMA EventEnableRegister 0x01C0 2C88 QEECR QDMA EventEnableClearRegister 0x01C0 2C8C QEESR QDMA EventEnableSetRegister 0x01C0 2C90 QSER QDMA SecondaryEventRegister 0x01C0 2C94 QSECR QDMA SecondaryEventClearRegister 0x01C0 2C98 -0x01C0 2DFF – Reserved Shadow Region 7 Channel Registers 0x01C0 2E00 ER EventRegister 0x01C0 2E04 ERH EventRegisterHigh 0x01C0 2E08 ECR EventClearRegister 0x01C0 2E0C ECRH EventClearRegisterHigh 0x01C0 2E10 ESR EventSetRegister 0x01C0 2E14 ESRH EventSetRegisterHigh 0x01C0 2E18 CER ChainedEventRegister 0x01C0 2E1C CERH ChainedEventRegisterHigh 0x01C0 2E20 EER EventEnableRegister 0x01C0 2E24 EERH EventEnableRegisterHigh 0x01C0 2E28 EECR EventEnableClearRegister 0x01C0 2E2C EECRH EventEnableClearRegisterHigh 0x01C0 2E30 EESR EventEnableSetRegister 0x01C0 2E34 EESRH EventEnableSetRegisterHigh 0x01C0 2E38 SER SecondaryEventRegister 0x01C0 2E3C SERH SecondaryEventRegisterHigh 0x01C0 2E40 SECR SecondaryEventClearRegister 0x01C0 2E44 SECRH SecondaryEventClearRegisterHigh 0x01C0 2E48 -0x01C0 2E4F – Reserved 0x01C0 2E50 IER InterruptEnableRegister 0x01C0 2E54 IERH InterruptEnableRegisterHigh 0x01C0 2E58 IECR InterruptEnableClearRegister 0x01C0 2E5C IECRH InterruptEnableClearRegisterHigh 0x01C0 2E60 IESR InterruptEnableSetRegister 0x01C0 2E64 IESRH InterruptEnableSetRegisterHigh 0x01C0 2E68 IPR InterruptPendingRegister 0x01C0 2E6C IPRH InterruptPendingRegisterHigh 0x01C0 2E70 ICR InterruptClearRegister 0x01C0 2E74 ICRH InterruptClearRegisterHigh 0x01C0 2E78 IEVAL InterruptEvaluateRegister 0x01C0 2E7C -0x01C0 2E7F – Reserved 0x01C0 2E80 QER QDMA EventRegister 0x01C0 2E84 QEER QDMA EventEnableRegister 0x01C0 2E88 QEECR QDMA EventEnableClearRegister

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C0 2E8C QEESR QDMA EventEnableSetRegister 0x01C0 2E90 QSER QDMA SecondaryEventRegister 0x01C0 2E94 QSECR QDMA SecondaryEventClearRegister 0x01C0 2E98 -0x01C0 2FFF – Reserved 0x01C0 3000 -0x01C0 3FFF – Reserved 0x01C0 4000 -0x01C0 7FFF – ParameterSetRAM (seeTable7-18) 0x01C0 8000 -0x01C0 FFFF – Reserved TransferController0 Registers 0x01C1 0000 PID PeripheralIdentificationRegister 0x01C1 0004 TCCFG EDMA3 TC0 ConfigurationRegister 0x01C1 0008 -0x01C1 00FF – Reserved 0x01C1 0100 TCSTAT EDMA3 TC0 ChannelStatusRegister 0x01C1 0104 -0x01C1 0113 – Reserved 0x01C1 0114 -0x01C1 011F – Reserved 0x01C1 0120 ERRSTAT EDMA3 TC0 ErrorStatusRegister 0x01C1 0124 ERREN EDMA3 TC0 ErrorEnableRegister 0x01C1 0128 ERRCLR EDMA3 TC0 ErrorClearRegister 0x01C1 012C ERRDET EDMA3 TC0 ErrorDetailsRegister 0x01C1 0130 ERRCMD EDMA3 TC0 ErrorInterruptCommand Register 0x01C1 0134 -0x01C1 013F – Reserved 0x01C1 0140 RDRATE EDMA3 TC0 Read Command Rate Register 0x01C1 0144 -0x01C1 01FF – Reserved 0x01C1 0200 -0x01C1 023F – Reserved 0x01C1 0240 SAOPT EDMA3 TC0 SourceActiveOptionsRegister 0x01C1 0244 SASRC EDMA3 TC0 SourceActiveSourceAddressRegister 0x01C1 0248 SACNT EDMA3 TC0 SourceActiveCount Register 0x01C1 024C SADST EDMA3 TC0 SourceActiveDestinationAddressRegister 0x01C1 0250 SABIDX EDMA3 TC0 SourceActiveB-IndexRegister 0x01C1 0254 SAMPPRXY EDMA3 TC0 SourceActiveMemory ProtectionProxyRegister 0x01C1 0258 SACNTRLD EDMA3 TC0 SourceActiveCount ReloadRegister 0x01C1 025C SASRCBREF EDMA3 TC0 SourceActiveSourceAddressB-ReferenceRegister 0x01C1 0260 SADSTBREF EDMA3 TC0 SourceActiveDestinationAddressB-ReferenceRegister 0x01C1 0264 -0x01C1 027F – Reserved 0x01C1 0280 DFCNTRLD EDMA3 TC0 DestinationFIFO SetCount ReloadRegister 0x01C1 0284 DFSRCBREF EDMA3 TC0 DestinationFIFO SetSourceAddressB-ReferenceRegister EDMA3 TC0 DestinationFIFO SetDestinationAddressB-Reference0x01C1 0288 DFDSTBREF Register 0x01C1 028C -0x01C1 02FF – Reserved 0x01C1 0300 DFOPT0 EDMA3 TC0 DestinationFIFO OptionsRegister0 0x01C1 0304 DFSRC0 EDMA3 TC0 DestinationFIFO SourceAddressRegister0 0x01C1 0308 DFCNT0 EDMA3 TC0 DestinationFIFO Count Register0 0x01C1 030C DFDST0 EDMA3 TC0 DestinationFIFO DestinationAddressRegister0 0x01C1 0310 DFBIDX0 EDMA3 TC0 DestinationFIFO B-IndexRegister0 0x01C1 0314 DFMPPRXY0 EDMA3 TC0 DestinationFIFO Memory ProtectionProxyRegister0 0x01C1 0318 -0x01C1 033F – Reserved 0x01C1 0340 DFOPT1 EDMA3 TC0 DestinationFIFO OptionsRegister1 0x01C1 0344 DFSRC1 EDMA3 TC0 DestinationFIFO SourceAddressRegister1 0x01C1 0348 DFCNT1 EDMA3 TC0 DestinationFIFO Count Register1 Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 177 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 034C DFDST1 EDMA3 TC0 DestinationFIFO DestinationAddressRegister1 0x01C1 0350 DFBIDX1 EDMA3 TC0 DestinationFIFO B-IndexRegister1 0x01C1 0354 DFMPPRXY1 EDMA3 TC0 DestinationFIFO Memory ProtectionProxyRegister1 0x01C1 0358 -0x01C1 037F – Reserved 0x01C1 0380 DFOPT2 EDMA3 TC0 DestinationFIFO OptionsRegister2 0x01C1 0384 DFSRC2 EDMA3 TC0 DestinationFIFO SourceAddressRegister2 0x01C1 0388 DFCNT2 EDMA3 TC0 DestinationFIFO Count Register2 0x01C1 038C DFDST2 EDMA3 TC0 DestinationFIFO DestinationAddressRegister2 0x01C1 0390 DFBIDX2 EDMA3 TC0 DestinationFIFO B-IndexRegister2 0x01C1 0394 DFMPPRXY2 EDMA3 TC0 DestinationFIFO Memory ProtectionProxyRegister2 0x01C1 0398 -0x01C1 03BF – Reserved 0x01C1 03C0 DFOPT3 EDMA3 TC0 DestinationFIFO OptionsRegister3 0x01C1 03C4 DFSRC3 EDMA3 TC0 DestinationFIFO SourceAddressRegister3 0x01C1 03C8 DFCNT3 EDMA3 TC0 DestinationFIFO Count Register3 0x01C1 03CC DFDST3 EDMA3 TC0 DestinationFIFO DestinationAddressRegister3 0x01C1 03D0 DFBIDX3 EDMA3 TC0 DestinationFIFO B-IndexRegister3 0x01C1 03D4 DFMPPRXY3 EDMA3 TC0 DestinationFIFO Memory ProtectionProxyRegister3 0x01C1 03D8 -0x01C1 03FF – Reserved TransferController1 Registers 0x01C1 0400 PID PeripheralIdentificationRegister 0x01C1 0404 TCCFG EDMA3 TC1 ConfigurationRegister 0x01C1 0408 -0x01C1 04FF – Reserved 0x01C1 0500 TCSTAT EDMA3 TC1 ChannelStatusRegister 0x01C1 0504 -0x01C1 0513 – Reserved 0x01C1 0514 -0x01C1 051F – Reserved 0x01C1 0520 ERRSTAT EDMA3 TC1 ErrorStatusRegister 0x01C1 0524 ERREN EDMA3 TC1 ErrorEnableRegister 0x01C1 0528 ERRCLR EDMA3 TC1 ErrorClearRegister 0x01C1 052C ERRDET EDMA3 TC1 ErrorDetailsRegister 0x01C1 0530 ERRCMD EDMA3 TC1 ErrorInterruptCommand Register 0x01C1 0534 -0x01C1 053F – Reserved 0x01C1 0540 RDRATE EDMA3 TC1 Read Command Rate Register 0x01C1 0544 -0x01C1 05FF – Reserved 0x01C1 0600 -0x01C1 063F – Reserved 0x01C1 0640 SAOPT EDMA3 TC1 SourceActiveOptionsRegister 0x01C1 0644 SASRC EDMA3 TC1 SourceActiveSourceAddressRegister 0x01C1 0648 SACNT EDMA3 TC1 SourceActiveCount Register 0x01C1 064C SADST EDMA3 TC1 SourceActiveDestinationAddressRegister 0x01C1 0650 SABIDX EDMA3 TC1 SourceActiveB-IndexRegister 0x01C1 0654 SAMPPRXY EDMA3 TC1 SourceActiveMemory ProtectionProxyRegister 0x01C1 0658 SACNTRLD EDMA3 TC1 SourceActiveCount ReloadRegister 0x01C1 065C SASRCBREF EDMA3 TC1 SourceActiveSourceAddressB-ReferenceRegister 0x01C1 0660 SADSTBREF EDMA3 TC1 SourceActiveDestinationAddressB-ReferenceRegister 0x01C1 0664 -0x01C1 067F – Reserved 0x01C1 0680 DFCNTRLD EDMA3 TC1 DestinationFIFO SetCount ReloadRegister 0x01C1 0684 DFSRCBREF EDMA3 TC1 DestinationFIFO SetSourceAddressB-ReferenceRegister EDMA3 TC1 DestinationFIFO SetDestinationAddressB-Reference0x01C1 0688 DFDSTBREF Register

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 068C -0x01C1 06FF – Reserved 0x01C1 0700 DFOPT0 EDMA3 TC1 DestinationFIFO OptionsRegister0 0x01C1 0704 DFSRC0 EDMA3 TC1 DestinationFIFO SourceAddressRegister0 0x01C1 0708 DFCNT0 EDMA3 TC1 DestinationFIFO Count Register0 0x01C1 070C DFDST0 EDMA3 TC1 DestinationFIFO DestinationAddressRegister0 0x01C1 0710 DFBIDX0 EDMA3 TC1 DestinationFIFO B-IndexRegister0 0x01C1 0714 DFMPPRXY0 EDMA3 TC1 DestinationFIFO Memory ProtectionProxyRegister0 0x01C1 0718 -0x01C1 073F – Reserved 0x01C1 0740 DFOPT1 EDMA3 TC1 DestinationFIFO OptionsRegister1 0x01C1 0744 DFSRC1 EDMA3 TC1 DestinationFIFO SourceAddressRegister1 0x01C1 0748 DFCNT1 EDMA3 TC1 DestinationFIFO Count Register1 0x01C1 074C DFDST1 EDMA3 TC1 DestinationFIFO DestinationAddressRegister1 0x01C1 0750 DFBIDX1 EDMA3 TC1 DestinationFIFO B-IndexRegister1 0x01C1 0754 DFMPPRXY1 EDMA3 TC1 DestinationFIFO Memory ProtectionProxyRegister1 0x01C1 0758 -0x01C1 077F – Reserved 0x01C1 0780 DFOPT2 EDMA3 TC1 DestinationFIFO OptionsRegister2 0x01C1 0784 DFSRC2 EDMA3 TC1 DestinationFIFO SourceAddressRegister2 0x01C1 0788 DFCNT2 EDMA3 TC1 DestinationFIFO Count Register2 0x01C1 078C DFDST2 EDMA3 TC1 DestinationFIFO DestinationAddressRegister2 0x01C1 0790 DFBIDX2 EDMA3 TC1 DestinationFIFO B-IndexRegister2 0x01C1 0794 DFMPPRXY2 EDMA3 TC1 DestinationFIFO Memory ProtectionProxyRegister2 0x01C1 0798 -0x01C1 07BF – Reserved 0x01C1 07C0 DFOPT3 EDMA3 TC1 DestinationFIFO OptionsRegister3 0x01C1 07C4 DFSRC3 EDMA3 TC1 DestinationFIFO SourceAddressRegister3 0x01C1 07C8 DFCNT3 EDMA3 TC1 DestinationFIFO Count Register3 0x01C1 07CC DFDST3 EDMA3 TC1 DestinationFIFO DestinationAddressRegister3 0x01C1 07D0 DFBIDX3 EDMA3 TC1 DestinationFIFO B-IndexRegister3 0x01C1 07D4 DFMPPRXY3 EDMA3 TC1 DestinationFIFO Memory ProtectionProxyRegister3 0x01C1 07D8 -0x01C1 07FF – Reserved TransferController2 Registers 0x01C1 0800 PID PeripheralIdentificationRegister 0x01C1 0804 TCCFG EDMA3 TC2 ConfigurationRegister 0x01C1 0808 -0x01C1 08FF – Reserved 0x01C1 0900 TCSTAT EDMA3 TC2 ChannelStatusRegister 0x01C1 0904 -0x01C1 0913 – Reserved 0x01C1 0914 -0x01C1 091F – Reserved 0x01C1 0920 ERRSTAT EDMA3 TC2 ErrorStatusRegister 0x01C1 0924 ERREN EDMA3 TC2 ErrorEnableRegister 0x01C1 0928 ERRCLR EDMA3 TC2 ErrorClearRegister 0x01C1 092C ERRDET EDMA3 TC2 ErrorDetailsRegister 0x01C1 0930 ERRCMD EDMA3 TC2 ErrorInterruptCommand Register 0x01C1 0934 -0x01C1 093F – Reserved 0x01C1 0940 RDRATE EDMA3 TC2 Read Command Rate Register 0x01C1 0944 -0x01C1 09FF – Reserved 0x01C1 0A00 -0x01C1 0A3F – Reserved 0x01C1 0A40 SAOPT EDMA3 TC2 SourceActiveOptionsRegister 0x01C1 0A44 SASRC EDMA3 TC2 SourceActiveSourceAddressRegister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 179 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 0A48 SACNT EDMA3 TC2 SourceActiveCount Register 0x01C1 0A4C SADST EDMA3 TC2 SourceActiveDestinationAddressRegister 0x01C1 0A50 SABIDX EDMA3 TC2 SourceActiveB-IndexRegister 0x01C1 0A54 SAMPPRXY EDMA3 TC2 SourceActiveMemory ProtectionProxyRegister 0x01C1 0A58 SACNTRLD EDMA3 TC2 SourceActiveCount ReloadRegister 0x01C1 0A5C SASRCBREF EDMA3 TC2 SourceActiveSourceAddressB-ReferenceRegister 0x01C1 0A60 SADSTBREF EDMA3 TC2 SourceActiveDestinationAddressB-ReferenceRegister 0x01C1 0A64 -0x01C1 0A7F – Reserved 0x01C1 0A80 DFCNTRLD EDMA3 TC2 DestinationFIFO SetCount ReloadRegister 0x01C1 0A84 DFSRCBREF EDMA3 TC2 DestinationFIFO SetSourceAddressB-ReferenceRegister EDMA3 TC2 DestinationFIFO SetDestinationAddressB-Reference0x01C1 0A88 DFDSTBREF Register 0x01C1 0A8C -0x01C1 0AFF – Reserved 0x01C1 0B00 DFOPT0 EDMA3 TC2 DestinationFIFO OptionsRegister0 0x01C1 0B04 DFSRC0 EDMA3 TC2 DestinationFIFO SourceAddressRegister0 0x01C1 0B08 DFCNT0 EDMA3 TC2 DestinationFIFO Count Register0 0x01C1 0B0C DFDST0 EDMA3 TC2 DestinationFIFO DestinationAddressRegister0 0x01C1 0B10 DFBIDX0 EDMA3 TC2 DestinationFIFO B-IndexRegister0 0x01C1 0B14 DFMPPRXY0 EDMA3 TC2 DestinationFIFO Memory ProtectionProxyRegister0 0x01C1 0B18 -0x01C1 0B3F – Reserved 0x01C1 0B40 DFOPT1 EDMA3 TC2 DestinationFIFO OptionsRegister1 0x01C1 0B44 DFSRC1 EDMA3 TC2 DestinationFIFO SourceAddressRegister1 0x01C1 0B48 DFCNT1 EDMA3 TC2 DestinationFIFO Count Register1 0x01C1 0B4C DFDST1 EDMA3 TC2 DestinationFIFO DestinationAddressRegister1 0x01C1 0B50 DFBIDX1 EDMA3 TC2 DestinationFIFO B-IndexRegister1 0x01C1 0B54 DFMPPRXY1 EDMA3 TC2 DestinationFIFO Memory ProtectionProxyRegister1 0x01C1 0B58 -0x01C1 0B7F – Reserved 0x01C1 0B80 DFOPT2 EDMA3 TC2 DestinationFIFO OptionsRegister2 0x01C1 0B84 DFSRC2 EDMA3 TC2 DestinationFIFO SourceAddressRegister2 0x01C1 0B88 DFCNT2 EDMA3 TC2 DestinationFIFO Count Register2 0x01C1 0B8C DFDST2 EDMA3 TC2 DestinationFIFO DestinationAddressRegister2 0x01C1 0B90 DFBIDX2 EDMA3 TC2 DestinationFIFO B-IndexRegister2 0x01C1 0B94 DFMPPRXY2 EDMA3 TC2 DestinationFIFO Memory ProtectionProxyRegister2 0x01C1 0B98 -0x01C1 0BBF – Reserved 0x01C1 0BC0 DFOPT3 EDMA3 TC2 DestinationFIFO OptionsRegister3 0x01C1 0BC4 DFSRC3 EDMA3 TC2 DestinationFIFO SourceAddressRegister3 0x01C1 0BC8 DFCNT3 EDMA3 TC2 DestinationFIFO Count Register3 0x01C1 0BCC DFDST3 EDMA3 TC2 DestinationFIFO DestinationAddressRegister3 0x01C1 0BD0 DFBIDX3 EDMA3 TC2 DestinationFIFO B-IndexRegister3 0x01C1 0BD4 DFMPPRXY3 EDMA3 TC2 DestinationFIFO Memory ProtectionProxyRegister3 0x01C1 0BD8 -0x01C1 0BFF – Reserved TransferController3 Registers 0x01C1 0C00 PID PeripheralIdentificationRegister 0x01C1 0C04 TCCFG EDMA3 TC3 ConfigurationRegister 0x01C1 0C08 -0x01C1 0CFF – Reserved 0x01C1 0D00 TCSTAT EDMA3 TC3 ChannelStatusRegister 0x01C1 0D04 -0x01C1 0D1F – Reserved 0x01C1 0D20 ERRSTAT EDMA3 TC3 ErrorStatusRegister

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 0D24 ERREN EDMA3 TC3 ErrorEnableRegister 0x01C1 0D28 ERRCLR EDMA3 TC3 ErrorClearRegister 0x01C1 0D2C ERRDET EDMA3 TC3 ErrorDetailsRegister 0x01C1 0D30 ERRCMD EDMA3 TC3 ErrorInterruptCommand Register 0x01C1 0D34 -0x01C1 0D3F – Reserved 0x01C1 0D40 RDRATE EDMA3 TC3 Read Command Rate Register 0x01C1 0D44 -0x01C1 0E3F – Reserved 0x01C1 0E40 SAOPT EDMA3 TC3 SourceActiveOptionsRegister 0x01C1 0E44 SASRC EDMA3 TC3 SourceActiveSourceAddressRegister 0x01C1 0E48 SACNT EDMA3 TC3 SourceActiveCount Register 0x01C1 0E4C SADST EDMA3 TC3 SourceActiveDestinationAddressRegister 0x01C1 0E50 SABIDX EDMA3 TC3 SourceActiveB-IndexRegister 0x01C1 0E54 SAMPPRXY EDMA3 TC3 SourceActiveMemory ProtectionProxyRegister 0x01C1 0E58 SACNTRLD EDMA3 TC3 SourceActiveCount ReloadRegister 0x01C1 0E5C SASRCBREF EDMA3 TC3 SourceActiveSourceAddressB-ReferenceRegister 0x01C1 0E60 SADSTBREF EDMA3 TC3 SourceActiveDestinationAddressB-ReferenceRegister 0x01C1 0E64 -0x01C1 0E7F – Reserved 0x01C1 0E80 DFCNTRLD EDMA3 TC3 DestinationFIFO SetCount ReloadRegister 0x01C1 0E84 DFSRCBREF EDMA3 TC3 DestinationFIFO SetSourceAddressB-ReferenceRegister EDMA3 TC3 DestinationFIFO SetDestinationAddressB-Reference0x01C1 0E88 DFDSTBREF Register 0x01C1 0E8C -0x01C1 0EFF – Reserved 0x01C1 0F00 DFOPT0 EDMA3 TC3 DestinationFIFO OptionsRegister0 0x01C1 0F04 DFSRC0 EDMA3 TC3 DestinationFIFO SourceAddressRegister0 0x01C1 0F08 DFCNT0 EDMA3 TC3 DestinationFIFO Count Register0 0x01C1 0F0C DFDST0 EDMA3 TC3 DestinationFIFO DestinationAddressRegister0 0x01C1 0F10 DFBIDX0 EDMA3 TC3 DestinationFIFO B-IndexRegister0 0x01C1 0F14 DFMPPRXY0 EDMA3 TC3 DestinationFIFO Memory ProtectionProxyRegister0 0x01C1 0F18 -0x01C1 0F3F – Reserved 0x01C1 0F40 DFOPT1 EDMA3 TC3 DestinationFIFO OptionsRegister1 0x01C1 0F44 DFSRC1 EDMA3 TC3 DestinationFIFO SourceAddressRegister1 0x01C1 0F48 DFCNT1 EDMA3 TC3 DestinationFIFO Count Register1 0x01C1 0F4C DFDST1 EDMA3 TC3 DestinationFIFO DestinationAddressRegister1 0x01C1 0F50 DFBIDX1 EDMA3 TC3 DestinationFIFO B-IndexRegister1 0x01C1 0F54 DFMPPRXY1 EDMA3 TC3 DestinationFIFO Memory ProtectionProxyRegister1 0x01C1 0F58 -0x01C1 0F7F – Reserved 0x01C1 0F80 DFOPT2 EDMA3 TC3 DestinationFIFO OptionsRegister2 0x01C1 0F84 DFSRC2 EDMA3 TC3 DestinationFIFO SourceAddressRegister2 0x01C1 0F88 DFCNT2 EDMA3 TC3 DestinationFIFO Count Register2 0x01C1 0F8C DFDST2 EDMA3 TC3 DestinationFIFO DestinationAddressRegister2 0x01C1 0F90 DFBIDX2 EDMA3 TC3 DestinationFIFO B-IndexRegister2 0x01C1 0F94 DFMPPRXY2 EDMA3 TC3 DestinationFIFO Memory ProtectionProxyRegister2 0x01C1 0F98 -0x01C1 0FBF – Reserved 0x01C1 0FC0 DFOPT3 EDMA3 TC3 DestinationFIFO OptionsRegister3 0x01C1 0FC4 DFSRC3 EDMA3 TC3 DestinationFIFO SourceAddressRegister3 0x01C1 0FC8 DFCNT3 EDMA3 TC3 DestinationFIFO Count Register3 0x01C1 0FCC DFDST3 EDMA3 TC3 DestinationFIFO DestinationAddressRegister3 0x01C1 0FD0 DFBIDX3 EDMA3 TC3 DestinationFIFO B-IndexRegister3 Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 181 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-17.DM6467 EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 0FD4 DFMPPRXY3 EDMA3 TC3 DestinationFIFO Memory ProtectionProxyRegister3 0x01C1 0FD8 -0x01C1 0FFF – Reserved Table7-18shows an abbreviationofthesetofregisterswhichmake up theparametersetforeach of512 EDMA events.Each oftheparameterregistersetsconsistof8 32-bitword entries.Table7-19shows the parametersetentryregisterswithrelativememory addresslocationswithineach oftheparametersets.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-18.EDMA Parameter Set RAM HEX ADDRESS RANGE DESCRIPTION 0x01C0 4000 -0x01C0 401F ParametersSet0 (832-bitwords) 0x01C0 4020 -0x01C0 403F ParametersSet1 (832-bitwords) 0x01C0 4040 -0x01C0 405F ParametersSet2 (832-bitwords) 0x01C0 4060 -0x01C0 407F ParametersSet3 (832-bitwords) 0x01C0 4080 -0x01C0 409F ParametersSet4 (832-bitwords) 0x01C0 40A0 -0x01C0 40BF ParametersSet5 (832-bitwords) 0x01C0 7FC0 -0x01C0 7FDF ParametersSet510 (832-bitwords) 0x01C0 7FE0 -0x01C0 7FFF ParametersSet511 (832-bitwords) Table7-19.Parameter Set Entries HEX OFFSET ADDRESS ACRONYM PARAMETER ENTRYWITHIN THE PARAMETER SET 0x0000 OPT Option 0x0004 SRC SourceAddress 0x0008 A_B_CNT A Count,B Count 0x000C DST DestinationAddress 0x0010 SRC_DST_BIDX SourceB Index,DestinationB Index 0x0014 LINK_BCNTRLD LinkAddress,B Count Reload 0x0018 SRC_DST_CIDX SourceC Index,DestinationC Index 0x001C CCNT C Count Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 183 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.7 Reset

The resetcontrollerdetectsthedifferenttypeofresetssupportedon theDM6467 deviceand manages the distributionofthoseresetsthroughoutthedevice. The DM6467 devicehas severaltypesof device-levelglobalresets— power-on reset,warm reset,max reset,and systemreset.Table7-20explainsfurtherthetypesofreset,theresetinitiator,and theeffectsof each reseton the chip.See Section7.7.9, Reset ElectricalData/Timing, formore informationon the effectsofeach reseton thePLL controllersand theirclocks. Table7-20.Device-LevelGlobalReset Types TYPE INITIATOR EFFECT(S) POR pin Globalchipreset(Coldreset).ActivatesthePOR signalon chip, whichresetstheentirechipincludingtheemulationlogic.Power-onReset The power-onreset(POR) pinmust be drivenlowduringpower(POR) ramp ofthedevice. Devicebootand configurationpinsarelatched. Resetseverythingexceptfortheemulationlogic.Emulatorstays Warm Reset RESET pin aliveduringWarm Reset. Devicebootand configurationpinsarelatched. Same as a Warm Reset,excepttheDM6467 devicebootandMax Reset Emulator,WD Timer(Timer2) configurationpinsarenot re-latched. A systemresetmaintainsmemory contentsand does notresetthe System Reset Emulator testand emulationcircuitry.The devicebootand configurationpins arealsonot re-latched. MMR controlstheC64x+ resetinput.Thisisused forcontrolofC64x+ LocalReset Software(registerbit) C64x+ resetby theARM. The C64x+ SlaveDMA portisstillalive(DSP Reset) when inlocalreset. In additionto device-levelglobalresets,the PSC providesthe capabilityto cause localresetsto peripheralsand/ortheC64x+ DSP.

7.7.1 Power-on Reset (POR Pin)

Power-on Reset (POR) isinitiatedby thePOR pinand isused toresettheentirechip,includingthetest and emulationlogic.Power-on Reset isalsoreferredto as a coldresetsincethe deviceusuallygoes througha power-upcycle.Duringpower-up,thePOR pinmust be asserted(drivenlow)untilthepower supplieshave reachedtheirnormaloperatingconditions.Ifan external27-MHz oscillatorisused on the DEV_MXI/DEV_CLKIN pin,thesourceclockshouldalsobe runningatthecorrectfrequencypriortode- assertingthePOR pin.Note:A devicepower-upcycleisnotrequiredtoinitiatea Power-onReset. The followingsequence must be followedduringa Power-onReset. 1. Waitforthepower suppliestoreachnormaloperatingconditionswhilekeepingthePOR pinasserted (drivenlow). 2. Waitfortheinputclocksourcetobe stablewhilekeepingthePOR pinasserted(low). 3. Once thepower suppliesand theinputclocksourcearestable,thePOR pinmust remainasserted (low)fora minimum of12 DEV_MXI cycles. WithinthelowperiodofthePOR pin,thefollowinghappens: – The resetsignalsflowtotheentirechip(includingthetestand emulationlogic),resettingthe modules on chip. – The PLL ControllerclocksstartatthefrequencyoftheDEV_MXI clock.The clocksarepropagated throughoutthechiptoresetthechipsynchronously.By default,bothPLL1 and PLL2 areinreset and unlocked.The PLL ControllersdefaulttoPLL Bypass Mode. 4. The POR pinmay now be deasserted(drivenhigh).

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 When thePOR pinisdeasserted(high),theconfigurationpinvaluesarelatchedand thePLL Controllerschanged theirsystemclockstotheirdefaultdivide-downvalues.BothPLL Controllersare stillinPLL Bypass Mode. Otherdeviceinitializationalsobegins. 5. Afterdeviceinitializationiscomplete,thePLL Controllerspause thesystemclocksfor10 cycles. Atthispoint: – The I/Opinsarecontrolledby thedefaultperipherals(defaultperipheralsaredeterminedby PINMUX0 and PINMUX1 registers). – The clockand resetofeach peripheralisdeterminedby thedefaultsettingsofthePower and Sleep Controller(PSC). – The PLL ControllersareoperatinginPLL Bypass Mode. – The ARM926 beginsexecutingfromthedefaultaddress(eitherARM bootROM orEMIFA). Aftertheresetsequence,thebootsequence begins.Formore detailson thebootsequence,see the UsingtheTMS320DM646x BootloaderApplicationReport(literaturenumber SPRAAS0 ).

7.7.1.1 Usage ofPOR versus RESET Pins

POR and RESET areindependentresets. Ifthedeviceneeds togo througha power-upcycle,POR (notRESET) must be used tofullyresetthe device. Infunctionalend-system,emulation/debuggerlogicistypicallynotneeded;therefore,therecommendation forfunctionalend-systemistouse thePOR pinforfulldevicereset.IfRESET pinisnotneeded,itcan be pulledinactive(high)viaan externalpullupresistor. Ina debug system,itistypicallydesirabletoallowtheresetofthedevicewithoutcrashingan emulation session.Inthiscase,theusercan use thePOR pintoachievefulldeviceresetand use theRESET pinto achievea debug reset— whichresetstheentiredeviceexcepttestand emulationlogic.

7.7.1.2 LatchingBoot and ConfigurationPins

Internaltothechip,thetwo deviceresetpinsRESET and POR arelogicallyAND ’ed togetheronlyforthe purposeoflatchingdevicebootand configurationpins.The valueson alldeviceand bootconfiguration pinsare latchedintotheBOOTCFG registerwhen thelogicalAND ofRESET and POR transitionsfrom lowtohigh.

7.7.2 Warm Reset (RESET Pin)

A Warm Reset isactivatedby drivingthe RESET pinactive-low.Thisresetseverythinginthe device exceptthetestoremulationlogic.An emulatorsessionwillstayaliveduringwarm reset. For more informationon POR vs.RESET usage,see Section7.7.1.1,Usage ofPOR versusRESET Pins and Section7.7.1.2,LatchingBootand ConfigurationPins. The followingsequence must be followedduringa Warm Reset: 1. Power suppliesand inputclocksourceshouldalreadybe stable. 2. The RESET pinmust be asserted(low)fora minimum of12 DEV_MXI cycles. WithinthelowperiodoftheRESET pin,thefollowinghappens: – The resetsignalsflowtotheentirechipresettingallthemodules on chip,exceptthetestand emulationlogic. – The PLL Controllersareresetthereby,switchingback toPLL Bypass Mode and resettingalltheir registerstodefaultvalues.BothPLL1 and PLL2 areplacedinresetand loselock. 3. The RESET pinmay now be deasserted(drivenhigh). When theRESET pinisdeasserted(high),theconfigurationpinvaluesarelatchedand thePLL Controllerschanged theirsystemclockstotheirdefaultdivide-downvalues.BothPLL Controllersare stillinPLL Bypass Mode. Otherdeviceinitializationalsobegins. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 185 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 4. Afterdeviceinitializationiscomplete,thePLL Controllerspause thesystemclocksfor10 cycles. Atthispoint: – The I/Opinsarecontrolledby thedefaultperipherals(defaultperipheralsaredeterminedby PINMUX0 and PINMUX1 registers). – The clockand resetofeach peripheralisdeterminedby thedefaultsettingsofthePower and Sleep Controller(PSC). – The PLL ControllersareoperatinginPLL Bypass Mode. – The ARM926 beginsexecutingfromthedefaultaddress(eitherARM bootROM, TCM RAM, or EMIFA). Afterthe resetsequence,the boot sequence begins.For more detailson the boot sequence,see the UsingtheTMS320DM646x BootloaderApplicationReport(literaturenumber SPRAAS0 ).

7.7.3 Maximum Reset

A Maximum (Max)Reset isinitiatedby theemulatororthewatchdog timer(Timer2).The effectsarethe same as a warm reset,exceptthe deviceboot and configurationpinsare not re-latched.The emulator initiatesa maximum resetviatheICEPICK module.ThisICEPICK-initiatedresetisnon-maskable.When thewatchdogtimercounterreacheszero,thiswillalsoinitiatea maximum resettorecoverfroma runaway condition. To invokethemaximum resetviatheICEPICK module,theusercan performthefollowingfromtheCode Composer Studio™ IDE menu: Debug →Advanced Resets→System Reset ThisistheMax Resetsequence: 1. Max Resetisinitiatedby theemulatororthewatchdogtimer. Duringthistime,thefollowinghappens: – The resetsignalsflowtotheentirechip,resettingallthemodules on chipexceptthetestand emulationlogic. – The PLL Controllersarereset— thereby,switchingback toPLL Bypass Mode and resettingalltheir registerstodefaultvalues.BothPLL1 and PLL2 areplacedinresetand loselock. 2. Afterdeviceinitializationiscomplete,thePLL Controllerspause thesystemclocksfor10 cycles. Atthispoint: – The I/Opinsarecontrolledby thedefaultperipherals(defaultperipheralsaredeterminedby PINMUX0 and PINMUX1 registers). – The clockand resetofeach peripheralisdeterminedby thedefaultsettingsofthePower and Sleep Controller(PSC). – The PLL ControllersareoperatinginPLL Bypass Mode. – The ARM926 beginsexecutingfromthedefaultaddress(eitherARM bootROM, TCM RAM, or EMIFA). Aftertheresetsequence,thebootsequence begins.Sincethebootand configurationpinsarenotlatched witha Max Reset,thepreviousvalues(asshown intheBOOTCFG register)are used toselecttheboot mode. For more detailson thebootsequence,see theUsingtheTMS320DM646x BootloaderApplication Report(literaturenumber SPRAAS0 ).

7.7.4 System Reset

A System Resetisinitiatedby theemulator.The followingmemory contentsaremaintained:

L1/L2 RAM: The C64x+ L1/L2 RAM contentisretained.The L1/L2 cache contentisnot retained because taginformationisreset.
DDR2 Memory Controller:The DDR2 Memory Controllerregistersarenot reset.Inaddition,theDDR2 SDRAM memory contentisretainediftheuserplacestheDDR2 SDRAM inself-refreshmode before invokingtheSystem Reset.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Test,emulation,clock,and power controllogicareunaffected.The emulatorinitiatesa System Reset via theC64x+ emulationlogic.Thisresetcan be masked by theemulator. ThisistheSystem Resetsequence: 1. The System Resetisinitiatedby theemulator. Duringthistime,thefollowinghappens: – The resetsignalsflowtotheentirechipresettingallthemodules on chip,exceptthetestand emulationlogic. – The PLL Controllersarenot reset.Internalsystemclocksareunaffected.IfPLL1/PLL2 were locked beforetheSystem Reset,theyremainlocked. 2. Afterdeviceinitializationiscomplete,thePLL Controllerspause thesystemclocksfor10 cycles. Atthispoint: – The I/Opinsarecontrolledby thedefaultperipherals(defaultperipheralsaredeterminedby PINMUX0 and PINMUX1 registers). – The clockand resetofeach peripheral(excepttheDDR2 Memory Controller)isdeterminedby the defaultsettingsofthePower and SleepController(PSC). – The DDR2 Memory Controllerregistersretaintheirpreviousvalues.OnlytheDDR2 Memory Controllerstatemachinesareresetby theSystem Reset. – The PLL Controllersareoperatinginthemode priortoSystem Reset.The System clocksare unaffected. – The ARM926 beginsexecutingfromthedefaultaddress(eitherARM bootROM, TCM RAM, or EMIFA). Aftertheresetsequence,thebootsequence begins.Sincethebootand configurationpinsarenotlatched witha System Reset,the previousvalues(as shown inthe BOOTCFG register)are used to selectthe boot mode. For more detailson the boot sequence, see the Using the TMS320DM646x Bootloader

7.7.5 C64x+ LocalReset (DSP LocalReset)

WithaccesstothePSC registers,theARM can performtwo typesofDSP reset:DSP localresetand DSP module reset.When DSP localresetisasserted,theDSP ’s internalmemories (L1P,L1D, and L2)arestill accessible.The localresetonlyresetstheDSP CPU core,nottherestoftheDSP subsystem,as theDSP module resetwould.Localresetisusefulwhen theDSP module isintheenablestateor inthedisable state.The DSP module resettakesprecedenceoverlocalreset.The ARM uses localresettoresetthe DSP toinitiatetheDSP bootprocess.The intentofmodule resetistocompletelyresettheDSP (likehard reset).For more detailedinformationon DSP localresetand DSP module reset,see the ARM-DSP IntegrationChapterintheTMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). For informationon peripheralselectionat the risingedge of POR or RESET, see Section4, Device Configurationsofthisdatamanual.

7.7.6 PeripheralLocalReset

The user can configurethe localresetand clockstateof a peripheralthroughprogramming the PSC. Table 7-3, DM6467 LPSC Assignments,identifiesthe LPSC numbers and the peripheralscapableof beinglocallyresetby thePSC. For more detailedinformationon theprogrammingoftheseperipheralsby the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literaturenumber SPRUEP9 ).

7.7.7 Reset Priority

Ifany oftheabove resetsourcesoccursimultaneously,thePLLC onlyprocessesthehighest-priorityreset request.The resetrequestpriorities,fromhightolow,areas follows:

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Maximum Reset
Warm Reset
System Reset

7.7.7.1 Reset Type Status(RSTYPE) Register

The Reset Type Status(RSTYPE) register(0x01C4 08E4) istheonlyregisterfortheresetcontroller.This registerfallsinthe same memory range as the PLL1 controllerregisters(see Table 7-12 forthe PLL1 ControllerRegisters(IncludingReset Controller)).For more detailson the RSTYPE registerand itsbit descriptions,see Figure7-19and Table7-21. 31 16 RESERVED R-0000 0000 0000 0000 15 4 3 2 1 0 RESERVED SRST MRST WRST POR R-0000 0000 0000 R-0/1 R-0/1 R-0/1 R-0/1 LEGEND: R = Read only;-n = valueafterreset Figure7-19.Reset Type Status(RSTYPE) Register[0x01C4 08E4] Table7-21.RSTYPE RegisterBitDescriptions BIT NAME DESCRIPTION 30:4 RESERVED Reserved.Read returns"0".Writeshave no effect. System Reset. 3 SRST 0 = System Resetwas not thelastresettooccur. 1 = System Resetwas thelastresettooccur. Max Reset. 2 MRST 0 = Max Resetwas not thelastresettooccur. 1 = Max Resetwas thelastresettooccur. Warm Reset. 1 WRST 0 = Warm Resetwas not thelastresettooccur. 1 = Warm Resetwas thelastresettooccur. Power-onReset. 0 POR 0 = Power-onResetwas not thelastresettooccur. 1 = Power-onResetwas thelastresettooccur.

7.7.8 Pin BehaviorsatReset

Duringnormal operations,pinsare controlledby the respectiveperipheralselectedinthe PINMUX0 or PINMUX1 register.Duringdevicelevelglobalreset,thepinbehaves as follows: MultiplexedBoot and ConfigurationPins These pins are forced3-statedwhen the deviceis in reset.This is to ensure the properboot and configurationvaluescan be latchedon thesemultiplexedpins.Thisisparticularlyusefulinthecase where thebootand configurationvaluesaredrivenby an externalcontroldevice.Once thedeviceisoutofreset, thesepinsarecontrolledby theirrespectivedefaultperipheral.

Boot and Configuration Pins Group: VP_DOUT6/DSPBOOT, VP_DOUT5/PCIEN, VP_DOUT4/CS2BW, VP_DOUT3/BTMODE3, VP_DOUT2/BTMODE2, VP_DOUT1/BTMODE1, and VP_DOUT0/BTMODE0. For informationon whether externalpullup/pulldownresistorsshould be used on the boot and configurationpins,see Section4.8.1,Pullup/PulldownResistors.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 DefaultPower Down Pins As discussedinSection4.2,Power Considerations,theVDD3P3V_PWDN registercontrolspower tothe 3.3-Vpins.The VDD3P3V_PWDN registerdefaultstopoweringdown some 3.3-Vpinstosave power.For more detailson theVDD3P3V_PWDN registerand which3.3-Vpinsdefaulttopower up orpower down, see Section4.2, Power Considerations. The pinsthatdefaultto power down, are both resetto power down and high-impedance.They remaininthatstateuntilconfiguredotherwiseby VDD3P3_PWDN and PINMUX0/PINMUX1 programming.

DefaultPower Down Pin Group: USB_DRVVBUS/GP[22], CLKOUT0, SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_MISO, SPI_MOSI, VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_TXD[3:0], VLYNQ_RXD[3:0], RFTCLK, GMTCLK, MTXD[7:4],MRXD[7:4],MTCLK, MTXD[3:0],MTXEN, MCOL, MCRS, MRCLK, MRXD[3:0], MRXDV, MRXER, MDCLK, MDIO, ACLKX1, AHCLKX1, AXR1[0], ACLKR0, AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0, AXR0[3:0],AMUTE0, AMUTEIN0, PCI_CLK/GP[10], PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/ HINT/EM_BA[0], PCI_IRDY/HRDY/EM_A[17], PCI_TRDY/HHWIL/EM_A[16], PCI_STOP/HCNTL0/ EM_WE, PCI_SERR/ HDS1/ EM_OE, PCI_PERR/ HCS/ EM_DQM1, PCI_PAR/HAS/EM_DQM0, PCI_INTA/EM_WAIT2, PCI_CBE3/HR/ W/EM_CS3, PCI_CBE2/HDS2/ EM_CS2, PCI_AD[15:0]/HD[15:0]/EM_D[15:0],PCI_RST/DA2/GP[13]/EM_A[22],PCI_IDSEL/HDDIR/EM_R/ W, PCI_REQ/DMARQ/GP[11]/ EM_CS5, PCI_GNT/ DMACK/GP[12]/EM_CS4, PCI_CBE1/ATA_CS1/GP[32]/EM_A[19], PCI_CBE0/ATA_CS0/GP[33]/EM_A[18], DIOW/GP[20]/EM_WAIT4, IORDY/GP[21]/EM_WAIT3, DIOR/GP[19]/EM_WAIT5, DA1/GP[16]/EM_A[21], DA0/GP[17]/EM_A[20], INTRQ/GP[18]/RSV , PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0],GP[7]/CVDDADJ1, GP[6]/CVDDADJ0, GP[5], GP[4]/STC_CLKIN, GP[3]/AUDIO_CLK0, GP[2]/AUDIO_CLK1, GP[1], GP[0], TOUT2, TINP1L, TOUT1L, TOUT1U, TINP0L, TINP0U, TOUT0L, TOUT0U, PWM1/TS1_DOUT, PWM0/CRG0_PO/TS1_ENAO, URTS2/UIRTX2/TS0_PSTIN/GP[41], UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO, URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI, UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO, URTS1/UIRTX1/TS0_WAITO/GP[25], UCTS1/USD1/TS0_EN_WAITO/GP[26], URXD1/TS0_DIN7/GP[23], UTXD1/URCTX1/TS0_DOUT7/GP[24], UDTR0/TS0_ENAO/GP[36], UDSR0/TS0_PSTO/GP[37], UDCD0/TS0_WAITIN/GP[38], URIN0/GP[8]/TS1_WAITIN, URXD0/TS1_DIN, UTXD0/URCTX0/TS1_PSTIN, URTS0/UIRTX0/TS1_EN_WAITO, UCTS0/USD0, VP_DOUT15/TS1_DIN, VP_DOUT14/TS1_PSTIN, VP_DOUT13/TS1_EN_WAITO, VP_DOUT12/TS1_WAITO, VP_DOUT11/TS1_DOUT, VP_DOUT10/TS1_PSTO, VP_DOUT9/TS1_ENAO, VP_DOUT8/TS1_WAITIN, VP_CLKIN3/TS1_CLKO, VP_CLKO3/TS0_CLKO, VP_DOUT7/VADJEN, VP_DOUT6/DSPBOOT, VP_DOUT5/PCIEN, VP_DOUT4/CS2BW, VP_DOUT3/BTMODE3, VP_DOUT2/BTMODE2, VP_DOUT1/BTMODE1, VP_DOUT0/BTMODE0, VP_CLKIN2, VP_CLKO2, VP_DIN15_VSYNC/TS0_DIN7, VP_DIN14_HSYNC/TS0_DIN6, VP_DIN13_FIELD/TS0_DIN5, VP_DIN12/TS0_DIN4, VP_DIN11/TS0_DIN3, VP_DIN10/TS0_DIN2, VP_DIN9/TS0_DIN1, VP_DIN8/TS0_DIN0, VP_CLKIN1, VP_DIN7/TS0_DOUT7/TS1_DIN, VP_DIN6/TS0_DOUT6/TS1_PSTIN, VP_DIN5/TS0_DOUT5/TS1_EN_WAITO, VP_DIN4/TS0_DOUT4/TS1_WAITO, VP_DIN3/TS0_DOUT3, VP_DIN2/TS0_DOUT2, VP_DIN1/TS0_DOUT1, VP_DIN0/TS0_DOUT0, VP_CLKIN0. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 189 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com AllOther Pins During devicereset,allotherpins are controlledby the defaultperipheral.The defaultperipheralis determinedby thedefaultsettingsofthePINMUX0 orPINMUX1 registers. Some of the PINMUX0/PINMUX1 settingsare determinedby configurationpins latchedat reset.To determinetheresetbehaviorofthesepins,see Section4.7,MultiplexedPinConfigurationsand readthe restofthethissubsectiontounderstandhow thatdefaultperipheralcontrolsthepin. The resetbehaviorsforalltheseotherpinsduringallbootmodes, except PCI Boot,are categorizedas follows(alsosee Figure7-20and Figure7-21inSection7.7.9,ResetElectricalData/Timing):

DDR2 Z Group: DDR_DQS[3:0], DDR_DQS[3:0], DDR_D[31:0],DDR_DQGATE1, DDR_DQGATE3
DDR2 Low Group: DDR_CLK, DDR_CKE, DDR_ODT0, DDR_A[14:0], DDR_DQGATE0, DDR_DQGATE2
DDR2 High Group: DDR_CLK, DDR_CS, DDR_WE, DDR_RAS, DDR_CAS
DDR2 Z/HighGroup: DDR_DQM[3:0]
DDR2 Low/High Group: DDR_BA[2:0]
Z Group: These pin are 3-statedby default,and these pins remain 3-statedthroughoutPOR or RESET assertion.When POR or RESET isdeasserted,thesepinsremain 3-stateduntilconfigured otherwise by their respectiveperipheral(afterthe peripheralis enabled by the PSC). PCI_CLK/GP[10], PCI_INTA/EM_WAIT2, DIOW/GP[20]/EM_WAIT4, IORDY/GP[21]/EM_WAIT3, PCI_AD[15:0]/HD[15:0]/EM_D[15:0],RFTCLK, GMTCLK, MTCLK, MTXD[7:0],MTXEN, MCOL, MCRS, MRCLK, MRXD[7:0], MRXDV, MRXER, MDCLK, MDIO, URXD0/TS1_DIN, UTXD0/URCTX0/TS1_PSTIN, URTS0/UIRTX0/TS1_EN_WAITO, UCTS0/USD0, UDTR0/TS0_ENAO/GP[36], UDSR0/TS0_PSTO/GP[37], UDCD0/TS0_WAITIN/GP[38], URIN0/GP[8]/TS1_WAITIN, URXD1/TS0_DIN7/GP[23], UTXD1/URCTX1/TS0_DOUT7/GP[24], URTS1/UIRTX1/TS0_WAITO/GP[25], UCTS1/USD1/TS0_EN_WAITO/GP[26], URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI, UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO, URTS2/UIRTX2/TS0_PSTIN/GP[41], UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO, ACLKR0, AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0, AXR0[3:0],AMUTE0, AMUTEIN0, ACLKX1, AHCLKX1, AXR1[0], SCL, SDA, SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_MISO, SPI_MOSI, PWM0/CRG0_PO/TS1_ENAO, PWM1/TS1_DOUT, VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_TXD[3:0], VLYNQ_RXD[3:0], USB_DRVVBUS/GP[22], TINP0L, TINP0U, TOUT0L, TOUT0U, TINP1L, TOUT1L, TOUT1U, TOUT2, TS0_CLKIN, TS1_CLKIN, VP_CLKIN0, VP_CLKIN1, VP_DIN15_VSYNC/TS0_DIN7, VP_DIN14_HSYNC/TS0_DIN6, VP_DIN13_FIELD/TS0_DIN5, VP_DIN12/TS0_DIN4, VP_DIN11/TS0_DIN3, VP_DIN10/TS0_DIN2, VP_DIN9/TS0_DIN1, VP_DIN8/TS0_DIN0, VP_DIN7/TS0_DOUT7/TS1_DIN, VP_DIN6/TS0_DOUT6/TS1_PSTIN, VP_DIN5/TS0_DOUT5/TS1_EN_WAITO, VP_DIN4/TS0_DOUT4/TS1_WAITO, VP_DIN3/TS0_DOUT3, VP_DIN2/TS0_DOUT2, VP_DIN1/TS0_DOUT1, VP_DIN0/TS0_DOUT0, VP_CLKIN2, VP_CLKIN3/TS1_CLKO, VP_CLKO2, VP_CLKO3/TS0_CLKO, VP_DOUT15/TS1_DIN, VP_DOUT14/TS1_PSTIN, VP_DOUT13/TS1_EN_WAITO, VP_DOUT12/TS1_WAITO, VP_DOUT11/TS1_DOUT, VP_DOUT10/TS1_PSTO, VP_DOUT9/TS1_ENAO, VP_DOUT8/TS1_WAITIN, VP_DOUT7/VADJEN, GP[0], GP[1], GP[2]/AUDIO_CLK1, GP[3]/AUDIO_CLK0, GP[4]/STC_CLKIN, GP[5],GP[6]/CVDDADJ0, GP[7]/CVDDADJ1, TIMS, TDO, TDI,TCK, TRST, EMU1, EMU0, DEV_MXI/DEV_CLKIN, AUX_MXI/AUX_CLKIN
Low Group: These pins are low by default,and remain low untilconfiguredotherwiseby their respective peripheral (after the peripheral is enabled by the PSC). PCI_RST/DA2/GP[13]/EM_A[22], PCI_IDSEL/HDDIR/EM_R/ W, PCI_IRDY/HRDY/EM_A[17], PCI_TRDY/HHWIL/EM_A[16], PCI_CBE1/ATA_CS1/GP[32]/EM_A[19], PCI_CBE0/ATA_CS0/GP[33]/EM_A[18], PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0],CLKOUT0, RTCLK,

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High Group: These pinsare high by default,and remain high untilconfiguredotherwiseby their respective peripheral (after the peripheral is enabled by the PSC). PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/ HINT/EM_BA[0], PCI_STOP/HCNTL0/ EM_WE, PCI_SERR/ HDS1/ EM_OE, PCI_PERR/ HCS/ EM_DQM1, PCI_PAR/HAS/EM_DQM0, PCI_REQ/DMARQ/GP[11]/ EM_CS5, PCI_GNT/ DMACK/GP[12]/EM_CS4, PCI_CBE3/HR/ W/EM_CS3, PCI_CBE2/HDS2/ EM_CS2, NOTE: ForPCI boot mode ,allPCI pinsnow behave accordingtoZ Group. For more informationon thepinbehaviorsduringdevice-levelglobalreset,see Figure7-20and Figure7- 21 inSection7.7.9,ResetElectricalData/Timing. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 191 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.7.9 Reset ElectricalData/Timing

Note: Ifa configurationpinmust be routedout from the device,the internalpullup/pulldown(IPU/IPD) resistorshouldnot be reliedupon;TIrecommends theuse ofan externalpullup/pulldownresistor. Table7-22.Timing Requirements forReset (seeFigure7-20and Figure7-21) -594,-729 NO. UNIT MIN MAX 1 tw(RESET) Pulseduration,POR loworRESET low 12C (1) ns Setuptime,bootand configurationpinsvalidbeforePOR highorRESET2 tsu(CONFIG) 12C (1) nshigh(2) Holdtime,bootand configurationpinsvalidafterPOR highorRESET3 th(CONFIG) 0 nshigh(2) (1) C = 1/DEV_MXI clockfrequencyinns.The deviceclocksourcemust be stableand ata validfrequencypriortomeetingthetw(RESET) requirement. (2) Forthelistofbootand configurationpins,see Table3-5,BootTerminalFunctions. Table7-23.SwitchingCharacteristicsOver Recommended OperatingConditionsDuring Reset(1) (seeFigure7-21) -594,-729 NO. PARAMETER UNIT MIN MAX 4 tw(PAUSE) Pulseduration,SYSCLKs paused (low) 10C 10C ns 23 td(RSTH-PAUSE) Delaytime,RESET highorPOR hightoSYSCLKs paused (low) 1990C ns 5 td(RSTL-BOOTZ) Delaytime,RESET lowtoBootConfigurationGroup highimpedance 0 20 ns 6 td(RSTL-DDRZZ) Delaytime,RESET lowtoDDR2 Z Group highimpedance 0 7P + 20 ns 7 td(RSTL-DDRLL) Delaytime,RESET lowtoDDR2 Low Group low 0 3P + 20 ns 8 td(RSTL-DDRHH) Delaytime,RESET lowtoDDR2 HighGroup high 0 20 ns 13 td(RSTL-DDRZHZ) Delaytime,RESET lowtoDDR2 Z/HighGroup highimpedance 0 7P + 20 ns 14 td(RSTL-DDRLHL) Delaytime,RESET lowtoDDR2 Low/HighGroup low 0 20 ns 17 td(RSTL-ZZ) Delaytime,RESET lowtoZ Group highimpedance 0 20 ns 18 td(RSTL-LOWL) Delaytime,RESET lowtoLow Group low 0 20 ns 19 td(RSTL-HIGHH) Delaytime,RESET lowtoHighGroup high 0 20 ns 9 td(RSTL-BOOTV) Delaytime,RESET hightoBootConfigurationGroup valid (2) ns 10 td(RSTH-DDRZV) Delaytime,RESET hightoDDR2 Z Group valid (2) ns 11 td(RSTH-DDRLV) Delaytime,RESET hightoDDR2 Low Group valid (2) ns 12 td(RSTH-DDRHV) Delaytime,RESET hightoDDR2 HighGroup valid (2) ns 15 td(RSTH-DDRZHV) Delaytime,RESET hightoDDR2 Z/HighGroup validhigh (2) ns 16 td(RSTH-DDRLHV) Delaytime,RESET hightoDDR2 Low/HighGroup validhigh (2) ns 20 td(RSTH-ZV) Delaytime,RESET hightoZ Group valid (2) ns 21 td(RSTH-LOWV) Delaytime,RESET hightoLow Group valid (2) ns 22 td(RSTH-HIGHV) Delaytime,RESET hightoHighGroup valid (2) ns (1) C = 1/DEV_CLKIN clockfrequencyinns. (2) FollowingRESET highorPOR high,thissignalgroupmaintainsthestatethepins(s)achievedwhileRESET orPOR was drivenlowuntil theperipheralisenabledviathePSC. Forexample,theDDR2 Z Group goes highimpedance followingRESET loworPOR lowand remainsinthehigh-impedancestatefollowingRESET highorPOR highuntiltheDDR2 controllerisenabledviathePSC. Figure7-20shows thePower-Up Timing.Figure7-21shows theWarm Reset(RESET) Timing.Max Reset TimingisidenticaltoWarm Reset Timing,exceptthebootand configurationpinsare not relatchedand theBOOTCFG registerretainsitspreviousvaluelatchedbeforetheMax Resetwas initiated.

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DEV_MXI(A) POR RESET SYSCLKREFCLK (PLLC1) SYSCLKx CLKOUT0 Boot□and Configuration□Pins DDR2□Z□Group DDR2□Low□Group DDR2□Z/High□Group Power Supplies Ramping Power□Supplies□Stable Hi-Z Hi-Z Clock□Source□Stable 2 3 DDR2□High□Group DDR2□Low/High□Group Z□Group Hi-Z Low□Group High□Group Config Hi-Z 23 4 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 A. Power suppliesand DEV_MXI must be stablebeforethestartoftW(RESET). . B. Pin resetbehaviordepends on whichperipheraldefaultstocontrollingthemultiplexedpin.For more detailson what Reset. Figure7-20.Power-Up Timing Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 193 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

DEV_MXI POR RESET SYSCLKREFCLK (PLLC1) SYSCLKx CLKOUT0 Boot□and Configuration□Pins DDR2□Z□Group DDR2□Low□Group DDR2□Z/High□Group Power□Supplies□Stable Hi-Z Hi-Z 2 3 DDR2□High□Group DDR2□Low/High□Group Z□Group Hi-Z Low□Group High□Group Config Hi-Z PLL1□CLOCK DIVx□CLOCK TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com A. Pin resetbehaviordepends on whichperipheraldefaultstocontrollingthemultiplexedpin.For more detailson what Reset. Figure7-21.Warm Reset (RESET )Timing

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7.8 Interrupts

The DM6467 devicehas a largenumber of interruptsto servicethe needs of itsmany peripheralsand subsystems.Both the ARM and C64x+ are capable of servicingthese interrupts.Allof the device interruptsare routedtotheARM interruptcontrollerwithonlya limitedsetroutedtotheC64x+ interrupt controller.The interruptscan be selectivelyenabled or disabledin eitherof the controllers.In typical applications,the ARM handles most of the peripheralinterruptsand grantscontrolto the C64x+ for interruptsthatarerelevanttoDSP algorithms.Also,theARM and DSP can communicate witheach other throughinterrupts.

7.8.1 ARM CPU Interrupts

The ARM926 CPU coresupports2 directinterrupts:FIQ and IRQ. The DM6467 ARM interruptcontroller prioritizesup to 64 interruptrequestsfrom variousperipheralsand subsystems,which are listedin Table 7-24, and interruptsthe ARM CPU. Each interruptisprogrammable forup to 8 levelsof priority. There are6 levelsforIRQ and 2 levelsforFIQ.Interruptsatthesame prioritylevelareservicedinorder by theARM InterruptNumber, withthelowestnumber havingthehighestpriority.Table7-25 shows the ARM interruptcontrollerregistersand memory locations.For more detailson ARM interruptcontrol,see theTMS320DM646x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUEP9 ). Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 195 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-24.DM6467 ARM Interrupts ARM ARM INTERRUPT ACRONYM SOURCE INTERRUPT ACRONYM SOURCE NUMBER NUMBER

0 VP_VERTINT0 VPIF 32 TINTL0 Timer0 lower– TINT12

1 VP_VERTINT1 VPIF 33 TINTH0 Timer0 upper– TINT34

2 VP_VERTINT2 VPIF 34 TINTL1 Timer1 lower– TINT12

3 VP_VERTINT3 VPIF 35 TINTH1 Timer1 upper– TINT34

4 VP_ERRINT VPIF 36 PWMINT0 PWM 0

5 - Reserved 37 PWMINT1 PWM 1 6 - Reserved 38 VLQINT VLYNQ WDINT WD Timer(TIMER 2)– I2CINT I2C7 39TINT12

8 CRGENINT0 CRGEN 0 40 UARTINT0 UART 0

9 CRGENINT1 CRGEN 1 41 UARTINT1 UART 1

10 TSINT0 TSIF 0 42 UARTINT2 UART 2

11 TSINT1 TSIF 1 43 SPINT0 SPI

12 VDCEINT VDCE 44 SPINT1 SPI

13 USBINT USB 45 DSP2ARM0 DSP ControllertoARM

14 USBDMAINT USB DMA 46 - Reserved

15 PCIINT PCI 47 PSCINT Power and SleepController

16 CCINT0 EDMA CC Region0 48 GPIO0 GPIO

17 CCERRINT EDMA CC Error 49 GPIO1 GPIO

18 TCERRINT0 EDMA TC 0 Error 50 GPIO2 GPIO

19 TCERRINT1 EDMA TC 1 Error 51 GPIO3 GPIO

20 TCERRINT2 EDMA TC 2 Error 52 GPIO4 GPIO

21 TCERRINT3 EDMA TC 3 Error 53 GPIO5 GPIO

22 IDEINT ATA 54 GPIO6 GPIO

23 HPIINT HPI 55 GPIO7 GPIO

24 MAC_RXTH EMAC RX Threshold 56 GPIOBNK0 GPIO Bank 0

25 MAC_RX EMAC Receive 57 GPIOBNK1 GPIO Bank 1

26 MAC_TX EMAC Transmit 58 GPIOBNK2 GPIO Bank 2

27 MAC_MISC EMAC Miscellaneous 59 DDRINT DDR2 Memory Controller

28 AXINT0 McASP0 Transmit 60 EMIFAINT EMIFA

29 ARINT0 McASP0 Receive 61 COMMTX ARMSS

30 AXINT1 McASP1 Transmit 62 COMMRX ARMSS

31 - Reserved 63 EMUINT E2ICE

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-25.ARM InterruptControllerRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C4 8000 FIQ0 FIQ InterruptStatus0 [InterruptStatusofINT[31:0](IfMapped toFIQ)] 0x01C4 8004 FIQ1 FIQ InterruptStatus1 [InterruptStatusofINT[63:32](IfMapped toFIQ)] 0x01C4 8008 IRQ0 IRQ InterruptStatus0 [InterruptStatusofINT[31:0](IfMapped toIRQ)] 0x01C4 800C IRQ1 IRQ InterruptStatus1 [InterruptStatusofINT[63:32](IfMapped toIRQ)] 0x01C4 8010 FIQENTRY EntryAddress[28:0]forValidFIQ Interrupt 0x01C4 8014 IRQENTRY EntryAddress[28:0]forValidIRQ Interrupt 0x01C4 8018 EINT0 InterruptEnableRegister0 0x01C4 801C EINT1 InterruptEnableRegister1 0x01C4 8020 INCTL InterruptOperationControlRegister 0x01C4 8024 EABASE InterruptEntryTableBase AddressRegister 0x01C4 8028 -0x01C4 802F - Reserved 0x01C4 8030 INTPRI0 Interrupt0-7PrioritySelect 0x01C4 8034 INTPRI1 Interrupt8-15PrioritySelect 0x01C4 8038 INTPRI2 Interrupt16-23PrioritySelect 0x01C4 803C INTPRI3 Interrupt24-31PrioritySelect 0x01C4 8040 INTPRI4 Interrupt32-39PrioritySelect 0x01C4 8044 INTPRI5 Interrupt40-47PrioritySelect 0x01C4 8048 INTPRI6 Interrupt48-55PrioritySelect 0x01C4 804C INTPRI7 Interrupt56-63PrioritySelect 0x01C4 8050 -0x01C4 83FF - Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 197 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.8.2 DSP Interrupts

The C64x+ DSP interruptcontrollercombines deviceeventsinto12 prioritizedinterrupts.The sourcefor each of the 12 CPU interruptsis user-programmableand is listedin Table 7-26. Also,the interrupt controllercontrolsthe generationof the CPU exception,NMI, and emulationinterrupts.Table 7-27 summarizes the C64x+ interruptcontrollerregistersand memory locations.For more detailson DSP interruptcontrol,see theTMS320DM646x DMSoC DSP Subsystem ReferenceGuide (literaturenumber SPRUEP8 ). Table7-26.DM6467 DSP Interrupts DSP DSP INTERRUPT ACRONYM SOURCE INTERRUPT ACRONYM SOURCE NUMBER NUMBER

0 EVT0 C64x+ IntCtl0 64 GPIO0 GPIO

1 EVT1 C64x+ IntCtl1 65 GPIO1 GPIO

2 EVT2 C64x+ IntCtl2 66 GPIO2 GPIO

3 EVT3 C64x+ IntCtl3 67 GPIO3 GPIO

4 TINTL0 Timer0 lower– TINT12 68 GPIO4 GPIO

5 TINTH0 Timer0 upper– TINT34 69 GPIO5 GPIO

6 TINTL1 Timer1 lower– TINT12 70 GPIO6 GPIO

7 TINTH1 Timer1 upper– TINT34 71 GPIO7 GPIO

8 – Reserved 72 – Reserved

9 EMU_DTDMA C64x+ EMC 73 – Reserved

10 – Reserved 74 – Reserved

11 EMU_RTDXRX C64x+ RTDX 75 – Reserved

12 EMU_RTDXTX C64x+ RTDX 76 – Reserved

13 IDMAINT0 C64x+ EMC 0 77 – Reserved

14 IDMAINT1 C64x+ EMC 1 78 – Reserved

15 – Reserved 79 – Reserved

16 ARM2DSP0 ARM toDSP Controller0 80 – Reserved

17 ARM2DSP1 ARM toDSP Controller1 81 – Reserved

18 ARM2DSP2 ARM toDSP Controller2 82 – Reserved

19 ARM2DSP3 ARM toDSP Controller3 83 – Reserved

20 – Reserved 84 CCINT1 EDMA CC Region1 21 – Reserved 85 CCERRINT EDMA CC Error 22 – Reserved 86 TCERRINT0 EDMA TC0 Error 23 – Reserved 87 TCERRINT1 EDMA TC1 Error 24 – Reserved 88 TCERRINT2 EDMA TC2 Error 25 – Reserved 89 TCERRINT3 EDMA TC3 Error 26 – Reserved 90 IDEINT ATA 27 – Reserved 91 – Reserved 28 – Reserved 92 – Reserved 29 – Reserved 93 – Reserved 30 – Reserved 94 – Reserved 31 – Reserved 95 – Reserved – Reserved INTERR C64x+ InterruptController32 96 Dropped CPU InterruptEvent – Reserved EMC_IDMAERR C64x+ EMC InvalidIDMA33 97 Parameters 34 – Reserved 98 – Reserved 35 – Reserved 99 – Reserved 36 – Reserved 100 – Reserved

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-26.DM6467 DSP Interrupts(continued) DSP DSP INTERRUPT ACRONYM SOURCE INTERRUPT ACRONYM SOURCE NUMBER NUMBER 37 – Reserved 101 – Reserved 38 – Reserved 102 – Reserved 39 – Reserved 103 – Reserved 40 – Reserved 104 – Reserved 41 – Reserved 105 – Reserved 42 – Reserved 106 – Reserved 43 – Reserved 107 – Reserved 44 – Reserved 108 – Reserved 45 – Reserved 109 – Reserved 46 – Reserved 110 – Reserved 47 – Reserved 111 – Reserved 48 – Reserved 112 – Reserved 49 – Reserved 113 PMC_ED C64x+ PMC 50 – Reserved 114 – Reserved 51 – Reserved 115 – Reserved 52 – Reserved 116 UMCED1 C64x+ UMC 1 53 – Reserved 117 UMCED2 C64x+ UMC 2

54 AXINT0 McASP 0 Transmit 118 PDCINT C64x+ PDC

55 ARINT0 McASP 0 Receive 119 SYSCMPA C64x+ SYS

56 AXINT1 McASP 1 Transmit 120 PMCCMPA C64x+ PMC

57 – Reserved 121 PMCDMPA C64x+ PMC 58 – Reserved 122 DMCCMPA C64x+ DMC 59 – Reserved 123 DMCDMPA C64x+ DMC 60 – Reserved 124 UMCCMPA C64x+ UMC 61 – Reserved 125 UMCDMPA C64x+ UMC 62 – Reserved 126 EMCCMPA C64x+ EMC 63 – Reserved 127 EMCBUSERR C64x+ EMC Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 199 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-27.C64x+ InterruptControllerRegisters HEX ADDRESS ACRONYM REGISTER NAMERANGE 0x0180 0000 EVTFLAG0 Eventflagregister0 0x0180 0004 EVTFLAG1 Eventflagregister1 0x0180 0008 EVTFLAG2 Eventflagregister2 0x0180 000C EVTFLAG3 Eventflagregister3 0x0180 0020 EVTSET0 Eventsetregister0 0x0180 0024 EVTSET1 Eventsetregister1 0x0180 0028 EVTSET2 Eventsetregister2 0x0180 002C EVTSET3 Eventsetregister3 0x0180 0040 EVTCLR0 Eventclearregister0 0x0180 0044 EVTCLR1 Eventclearregister1 0x0180 0048 EVTCLR2 Eventclearregister2 0x0180 004C EVTCLR3 Eventclearregister3 0x0180 0080 EVTMASK0 Eventmask register0 0x0180 0084 EVTMASK1 Eventmask register1 0x0180 0088 EVTMASK2 Eventmask register2 0x0180 008C EVTMASK3 Eventmask register3 0x0180 00A0 MEVTFLAG0 Masked eventflagregister0 0x0180 00A4 MEVTFLAG1 Masked eventflagregister1 0x0180 00A8 MEVTFLAG2 Masked eventflagregister2 0x0180 00AC MEVTFLAG3 Masked eventflagregister3 0x0180 00C0 EXPMASK0 Exceptionmask register0 0x0180 00C4 EXPMASK1 Exceptionmask register1 0x0180 00C8 EXPMASK2 Exceptionmask register2 0x0180 00CC EXPMASK3 Exceptionmask register3 0x0180 00E0 MEXPFLAG0 Masked exceptionflagregister0 0x0180 00E4 MEXPFLAG1 Masked exceptionflagregister1 0x0180 00E8 MEXPFLAG2 Masked exceptionflagregister2 0x0180 00EC MEXPFLAG3 Masked exceptionflagregister3 0x0180 0104 INTMUX1 Interruptmux register1 0x0180 0108 INTMUX2 Interruptmux register2 0x0180 010C INTMUX3 Interruptmux register3 0x0180 0180 INTXSTAT Interruptexceptionstatus 0x0180 0184 INTXCLR Interruptexceptionclear 0x0180 0188 INTDMASK Dropped interruptmask register

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7.9 ExternalMemory Interface(EMIF)

DM6467 supportsseveralmemory and externaldeviceinterfaces,including:

AsynchronousEMIF (EMIFA)forinterfacingtoNOR Flash,SRAM, etc.
NAND Flash
ATA (seeSection7.20,ATA Controller)

7.9.1 Asynchronous EMIF (EMIFA)

The DM6467 AsynchronousEMIF (EMIFA) providesan 8-bitor16-bitdatabus,an addressbus widthup to24 bits,and 4 chipselects,alongwithmemory controlsignals.These signalsaremultiplexedbetween theseperipherals:

EMIFA and NAND interfaces
ATA interface
Host-PortInterface(HPI)
PCI
GPIO

7.9.2 NAND (NAND, SmartMedia/SSFDC, xD)

The EMIFA interfaceprovidesboththeasynchronousEMIF and NAND interfaces.Four chipselectsare providedand each are individuallyconfigurableto provideeitherEMIFA or NAND support.The NAND featuressupportedareas follows.

NAND flashon up to4 asynchronouschipselects
8-or16-bitdatabus width
Programmable cycletimings
PerformsECC calculation
NAND Mode alsosupportsSmartMedia/SSFDC (SolidStateFloppyDiskController)and xD memory cards
ARM ROM supportsbootingoftheDM6467 ARM926 processorfromNAND flashlocatedatCS2 The memory map forEMIFA and NAND registersisshown inTable7-28.For more detailson theEMIFA and NAND interfaces,the TMS320DM646x DMSoC Asynchronous ExternalMemory Interface(EMIF) User'sGuide (literaturenumber SPRUEQ7 ).

7.9.3 EMIFA PeripheralRegisterDescription(s)

Table7-28shows theEMIFA/NAND registers. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 201 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-28.EMIFA/NAND Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x2000 8000 RCSR RevisionCode and StatusRegister 0x2000 8004 AWCCR AsynchronousWaitCycleConfigurationRegister 0x2000 8008 -0x2000 800F – Reserved 0x2000 8010 A1CR Asynchronous1 ConfigurationRegister(CS2 Space) 0x2000 8014 A2CR Asynchronous2 ConfigurationRegister(CS3 Space) 0x2000 8018 A3CR Asynchronous3 ConfigurationRegister(CS4 Space) 0x2000 801C A4CR Asynchronous4 ConfigurationRegister(CS5 Space) 0x2000 8020 -0x2000 803F – Reserved 0x2000 8040 EIRR EMIF InterruptRaw Register 0x2000 8044 EIMR EMIF InterruptMask Register 0x2000 8048 EIMSR EMIF InterruptMask SetRegister 0x2000 804C EIMCR EMIF InterruptMask ClearRegister 0x2000 8050 -0x2000 805F – Reserved 0x2000 8060 NANDFCR NAND FlashControlRegister 0x2000 8064 NANDFSR NAND FlashStatusRegister 0x2000 8070 NANDF1ECC NAND Flash1 ECC Register(CS2 Space) 0x2000 8074 NANDF2ECC NAND Flash2 ECC Register(CS3 Space) 0x2000 8078 NANDF3ECC NAND Flash3 ECC Register(CS4 Space) 0x2000 807C NANDF4ECC NAND Flash4 ECC Register(CS5 Space) 0x2000 8080 -0x2000 8FFF – Reserved

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7.9.4 EMIFA ElectricalData/Timing

Table7-29.Timing Requirements forAsynchronous Memory Cycles forEMIFA Module (1) (seeFigure7-22and Figure7-23) -594,-729 NO. UNIT MIN MAX READS and WRITES 2 tw(EM_WAIT) Pulseduration,EM_WAITx assertionand deassertion 2E ns READS 12 tsu(EMDV-EMOEH) Setuptime,EM_D[15:0]validbeforeEM_OE high 5 ns 13 th(EMOEH-EMDIV) Holdtime,EM_D[15:0]validafterEM_OE high 0 ns 14 tsu (EMWAIT-EMOEH) Setuptime,EM_WAITx assertedbeforeEM_OE high(2) 4E + 3 ns WRITES 28 tsu(EMWAIT-EMWEH) Setuptime,EM_WAITx assertedbeforeEM_WE high(2) 4E + 3 ns (1) E = SYSCLK3 periodinns forEMIFA. Forexample,when runningtheDSP CPU at594 MHz, use E = 6.734ns. (2) Setupbeforeend ofSTROBE phase (ifno extendedwaitstatesareinserted)by whichEM_WAITx must be assertedtoadd extended waitstates.Figure7-24and Figure7-25describeEMIF transactionsthatincludeextendedwaitstatesinsertedduringtheSTROBE phase.However,cyclesinsertedas partofthisextendedwaitperiodshouldnotbe counted;the4E requirementistothestartofwhere theHOLD phase wouldbeginiftherewere no extendedwaitcycles. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 203 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-30.SwitchingCharacteristicsOver Recommended OperatingConditionsforAsynchronous Memory Cycles forEMIFA Module (1)(2)(seeFigure7-22and Figure7-23) -594,-729 NO. PARAMETER UNIT MIN MAX READS and WRITES 1 td(TURNAROUND) Turnaroundtime (TA + 1)*E -3 (TA + 1)*E + 3 ns READS (RS + RST + RH + (RS + RST + RH + TA +EMIF readcycletime(EW = 0) nsTA + 4)*E -3 4)*E + 3 3 tc(EMRCYCLE) (RS + RST + RH +EMIF readcycletime(EW = 1) 4184 *E + 3 nsTA + 4)*E -3 Outputsetuptime,EM_CS[5:2]lowtoEM_OE low (RS + 1)*E -3 (RS + 1)*E + 3 ns(SS = 0) 4 tsu(EMCSL-EMOEL) Outputsetuptime,EM_CS[5:2]lowtoEM_OE low 3 ns(SS = 1) Outputholdtime,EM_OE hightoEM_CS[5:2]high (RH + 1)*E -3 (RH + 1)*E + 3 ns(SS = 0) 5 th(EMOEH-EMCSH) Outputholdtime,EM_OE hightoEM_CS[5:2]high 3 ns(SS = 1) 6 tsu(EMBAV-EMOEL) Outputsetuptime,EM_BA[1:0]validtoEM_OE low (RS + 1)*E -3 (RS + 1)*E + 3 ns 7 th(EMOEH-EMBAIV) Outputholdtime,EM_OE hightoEM_BA[1:0]invalid (RH + 1)*E -3 (RH + 1)*E + 3 ns 8 tsu(EMBAV-EMOEL) Outputsetuptime,EM_A[22:0]validtoEM_OE low (RS + 1)*E -3 (RS + 1)*E + 3 ns 9 th(EMOEH-EMBAIV) Outputholdtime,EM_OE hightoEM_A[22:0]invalid (RH + 1)*E -3 (RH + 1)*E + 3 ns EM_OE activelowwidth(EW = 0) (RST + 1)*E -3 (RST + 1)*E + 3 ns 10 tw(EMOEL) EM_OE activelowwidth(EW = 1) (RST + 1)*E -3 (RST + 4097)*E + 3 ns 11 td(EMWAITH-EMOEH) DelaytimefromEM_WAITx deassertedtoEM_OE high 4E + 3 ns WRITES (WS + WST + WH (WS + WST + WH + TAEMIF writecycletime(EW = 0) ns+ TA + 4)*E -3 + 4)*E + 3 15 tc(EMWCYCLE) (WS + WST + WHEMIF writecycletime(EW = 1) 4184 *E + 3 ns+ TA + 4)*E -3 Outputsetuptime,EM_CS[5:2]lowtoEM_WE low (WS + 1)*E -3 (WS + 1)*E + 3 ns(SS = 0) 16 tsu(EMCSL-EMWEL) Outputsetuptime,EM_CS[5:2]lowtoEM_WE low 3 ns(SS = 1) Outputholdtime,EM_WE hightoEM_CS[5:2]high (WH + 1)*E -3 (WH + 1)*E + 3 ns(SS = 0) 17 th(EMWEH-EMCSH) Outputholdtime,EM_WE hightoEM_CS[5:2]high 3 ns(SS = 1) 18 tsu(EMRNW-EMWEL) Outputsetuptime,EM_R/ W validtoEM_WE low (WS + 1)*E -3 (WS + 1)*E + 3 ns 19 th(EMWEH-EMRNW) Outputholdtime,EM_WE hightoEM_R/ W invalid (WH + 1)*E -3 (WH + 1)*E + 3 ns 20 tsu(EMBAV-EMWEL) Outputsetuptime,EM_BA[1:0]validtoEM_WE low (WS + 1)*E -3 (WS + 1)*E + 3 ns 21 th(EMWEH-EMBAIV) Outputholdtime,EM_WE hightoEM_BA[1:0]invalid (WH + 1)*E -3 (WH + 1)*E + 3 ns 22 tsu(EMAV-EMWEL) Outputsetuptime,EM_A[22:0]validtoEM_WE low (WS + 1)*E -3 (WS + 1)*E + 3 ns 23 th(EMWEH-EMAIV) Outputholdtime,EM_WE hightoEM_A[22:0]invalid (WH + 1)*E -3 (WH + 1)*E + 3 ns EM_WE activelowwidth(EW = 0) (WST + 1)*E -3 (WST + 1)*E + 3 ns 24 tw(EMWEL) EM_WE activelowwidth(EW = 1) (WST + 1)*E -3 (WST + 4097)*E + 3 ns 25 td(EMWAITH-EMWEH) DelaytimefromEM_WAITx deassertedtoEM_WE high 4E + 3 ns 26 tsu(EMDV-EMWEL) Outputsetuptime,EM_D[15:0]validtoEM_WE low (WS + 1)*E -3 (WS + 1)*E + 3 ns (1) RS = Read setup,RST = Read Strobe,RH = Read Hold,WS = WriteSetup,WST = WriteStrobe,WH = WriteHold,TA = TurnAround, EW = ExtendWaitmode, SS = SelectStrobemode. These parametersareprogrammed viatheAsynchronousn Configurationand the AsynchronousWaitCycleConfigurationregistersand supportthefollowingrangeofvalues:TA[0–3],RS[0–15],RST[0–63],RH[0–7], WS[0 –15],WST[0 –63],WH[0 –7],EW[0 –1],and MEWC[0 –255].Formore information,see theTMS320DM646x DMSoC Asynchronous ExternalMemory Interface(EMIF)User's Guide (literaturenumber SPRUEQ7 ). (2) E = SYSCLK3 periodinns forEMIFA. Forexample,when runningtheDSP CPU at594 MHz, use E = 6.734ns.

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EM_CS[5:2] EM_BA[1:0] EM_A[22:0] EM_OE EM_D[15:0] EM_WE EM_R/W TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-30.SwitchingCharacteristicsOver Recommended OperatingConditionsforAsynchronous Memory Cycles forEMIFA Module (1)(2)(seeFigure7-22and Figure7-23)(continued) -594,-729 NO. PARAMETER UNIT MIN MAX 27 th(EMWEH-EMDIV) Outputholdtime,EM_WE hightoEM_D[15:0]invalid (WH + 1)*E -3 (WH + 1)*E + 3 ns Figure7-22.Asynchronous Memory Read Timing forEMIF Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 205 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

EM_CS[5:2] Asserted Deasserted EM_BA[1:0] EM_A[22:0] EM_D[15:0] EM_OE EM_WAIT[5:2] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_DQM[1:0] EM_CS[5:2] EM_BA[1:0] EM_A[22:0] EM_WE EM_D[15:0] EM_OE EM_R/W TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-23.Asynchronous Memory WriteTiming forEMIF Figure7-24.EM_WAITx Read Timing Requirements

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EM_CS[5:2] Asserted Deasserted EM_BA[1:0] EM_A[22:0] EM_D[15:0] EM_WE EM_WAIT[5:2] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_DQM[1:0] TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-25.EM_WAITx WriteTiming Requirements Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 207 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.10 DDR2 Memory Controller

The DDR2 Memory Controlleris a dedicatedinterfaceto DDR2 SDRAM. ItsupportsJESD79D-2A standardcompliantDDR2 SDRAM devicesand can interfaceto either16-bitor 32-bitDDR2 SDRAM devices.For detailson the DDR2 Memory Controller,see theTMS320DM646x DMSoC DDR2 Memory ControllerUser'sGuide (literaturenumber SPRUEQ4 ). A memory map oftheDDR2 Memory Controllerregistersisshown inTable7-31. Table7-31.DDR2 Memory ControllerRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C4 004C – Reserved 0x01C4 2038 – Reserved 0x2000 0000 -0x2000 0003 – Reserved 0x2000 0004 SDRSTAT SDRAM StatusRegister 0x2000 0008 SDBCR SDRAM Bank ConfigurationRegister 0x2000 000C SDRCR SDRAM RefreshControlRegister 0x2000 0010 SDTIMR SDRAM TimingRegister1 0x2000 0014 SDTIMR2 SDRAM TimingRegister2 0x2000 0018 -0x2000 001F – Reserved 0x2000 0020 PBBPR PeripheralBus BurstPriorityRegister 0x2000 0024 -0x2000 00BF – Reserved 0x2000 00C0 IRR InterruptRaw Register 0x2000 00C4 IMR InterruptMasked Register 0x2000 00C8 IMSR InterruptMask SetRegister 0x2000 00CC IMCR InterruptMask ClearRegister 0x2000 00D0 -0x2000 00E3 – Reserved 0x2000 00E4 DDRPHYCR DDR2 PHY ControlRegister 0x2000 00E8 -0x2000 00EF – Reserved 0x2000 00F0 VTPIOCR DDR2 VTP IO ControlRegister 0x2000 00F4 -0x2000 7FFF – Reserved

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7.10.1 DDR2 Memory ControllerElectricalData/Timing

TIonlysupportsboarddesignsthatfollowtheguidelinesoutlinedinthisdocument. Table7-32.SwitchingCharacteristicsOver Recommended OperatingConditionsforDDR2 Memory Controller(1)(2)(seeFigure7-26) -594 -729 NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(DDR_CLK) Cycletime,DDR_CLK 3.367 8 3.220 8 ns 2 f(DDR_CLK) Frequency,DDR_CLK 125 297 125 310.5 MHz (1) DDR_CLK cycletime= 2 x PLL2 _SYSCLK1 cycletime. (2) The PLL2 Controllermust be programmed such thattheresultingDDR_CLK clockfrequencyiswithinthespecifiedrange. Figure7-26.DDR2 Memory ControllerClock Timing

7.10.2 DDR2 Interface

ThissectionprovidesthetimingspecificationfortheDDR2 interfaceas a PCB designand manufacturing specification.The designrulesconstrainPCB tracelength,PCB traceskew, signalintegrity,cross-talk, and signaltiming.These rules,when followed,resultina reliableDDR2 memory system withouttheneed fora complex timingclosureprocess.For more informationregardingtheguidelinesforusingthisDDR2 specification,see UnderstandingTI’s PCB RoutingRule-Based DDR2 Timing SpecificationApplication Report(SPRAAV0 ). 7.10.2.1DDR2 InterfaceSchematic Figure7-27shows theDDR2 interfaceschematicfora x32 DDR2 memory system.The x16 DDR2 system schematicis identicalexcept thatthe high word DDR2 deviceis deleted,see Figure7-28. The pin numbers fortheDM6467 can be obtainedfromtheSection3.6,PinAssignmentsofthisdocument. 7.10.2.2Compatible JEDEC DDR2 Devices Table 7-33 shows the parametersof the JEDEC DDR2 devicesthatare compatiblewiththisinterface. Generally,theDDR2 interfaceiscompatiblewithx16 DDR2-667 speed gradeDDR2 devices. Table7-33.Compatible JEDEC DDR2 Devices No. Parameter Min Max Unit

1 JEDEC DDR2 DeviceSpeed Grade(1) DDR2-667

2 JEDEC DDR2 DeviceBitWidth x16 x16 Bits

3 JEDEC DDR2 DeviceCount(2) 1 2 Devices

4 JEDEC DDR2 DeviceBallCount(3) 84 92 Balls

(1) HigherDDR2 speed gradesaresupporteddue toinherentJEDEC DDR2 backwardscompatibility. (2) 1 DDR2 deviceisused for16 bitDDR2 memory system.2 DDR2 devicesareused for32 bitDDR2 memory system. (3) 92 balldevicesretainedforlegacysupport.New designswillmigrateto84 ballDDR2 devices.Electrricallythe92 and 84 ballDDR2 devicesarethesame. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 209 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 7.10.2.3PCB Stackup The minimum stackuprequiredforroutingthe DM6467 isa sixlayerstackas shown in Table 7-34. Additionallayersmay be added tothePCB stackup toaccommodate othercircuityortoreducethesize ofthePCB footprint. Table7-34.DM6467 Minimum PCB Stack Up Layer Type Description

1 Signal Top RoutingMostlyHorizontal

2 Plane Ground

3 Plane Power

4 Signal InternalRouting

5 Plane Ground

6 Signal BottomRoutingMostlyVertical

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DDR_D0 DDR_D7 DDR_DQM0 DDR_DQS0 DDR_DQS0 DDR_D8 DDR_D15 DDR_DQM1 DDR_DQS1 DDR_DQS1 DQ0 DQ7 LDM LDQS LDQS DQ8 DQ15 UDM UDQS UDQS BA0 BA2 A14 CS CAS RAS WE CKE CK CK VREF DQ0 DQ7 LDM LDQS LDQS DQ8 DQ15 UDM UDQS UDQS BA0 BA2 A14 CS CAS RAS WE CKE CK CK VREF DDR_D16 DDR_D23 DDR_DQM2 DDR_DQS2 DDR_DQS2 DDR_D24 DDR_D31 DDR_DQM3 DDR_DQS3 DDR_DQS3 DDR_BA0 DDR_BA2 DDR_A0 DDR_A14 DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_CKE DDR_CLK DDR_CLK ODT DDR_VREF

1 K Ω 1%

Vio 1.8 (A) DDR2 DDR2 DDR_DQGATE0 DDR_DQGATE1 DDR_DQGATE2 DDR_DQGATE3 VREF Terminator, if desired. See terminator comments. A Vio1.8 is the power supply for the DDR2 memories and DM646x DDR2 interface. B One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T 0.1 µF VREF VREF 0.1 µF 1 K Ω 1%0.1 µF (B)0.1 µF (B) DDR_ODT0 NC ODT DM646x 50 Ω (±5%) 50 Ω (±5%) T T T DDR_ZN DDR_ZP 0.1 µF (B) DVDDR2 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Completestackup specificationsareprovidedinTable7-35. Figure7-27.DM6467 32-BitDDR2 High LevelSchematic Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 211 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

DDR_D0 DDR_D7 DDR_DQM0 DDR_DQS0 DDR_DQS0 DDR_D8 DDR_D15 DDR_DQM1 DDR_DQS1 DDR_DQS1 DQ0 DQ7 LDM LDQS LDQS DQ8 DQ15 UDM UDQS UDQS BA0 BA2 A14 CS CAS RAS WE CKE CK CK VREF DDR_D16 DDR_D23 DDR_DQM2 DDR_DQS2 DDR_DQS2 DDR_D24 DDR_D31 DDR_DQM3 DDR_DQS3 DDR_DQS3 DDR_BA0 DDR_BA2 DDR_A0 DDR_A14 DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_CKE DDR_CLK DDR_CLK DDR_VREF Vio 1.8 (A) DDR2 DDR_DQGATE0 DDR_DQGATE1 DDR_DQGATE2 DDR_DQGATE3 VREF Terminator, if desired. See terminator comments. A Vio1.8 is the power supply for the DDR2 memories and DM646x DDR2 interface. B One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. T T T T T T T T T T T T T T T T T T T T T 0.1 µF VREF 0.1 µF 1 K Ω 1% 0.1 µF (B) 0.1 µF (B) DDR_ODT0 NC ODT DM646x NC NC NC NC 1 KΩ NC NC 1 KΩ 1 KΩ 1 KΩ T T T DDR_ZP DDR_ZN 50 ( 5%)Ω ± 50 ( 5%)Ω ± Vio 1.8 (A) Vio 1.8 (A) DVDDR2 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-28.DM6467 16-BitDDR2 High LevelSchematic Table7-35.PCB Stack Up Specifications No. Parameter Min Typ Max Unit

1 PCB Routing/PlaneLayers 6

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X Y OFFSET Recommended□DDR2□Device Orientation Y Y OFFSET DDR2 Device DDR2 ControllerDM646x TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-35.PCB Stack Up Specifications(continued) No. Parameter Min Typ Max Unit

2 SignalRoutingLayers 3

3 FullgroundlayersunderDDR2 routingRegion 2

4 Number ofgroundplanecutsallowedwithinDDR routingregion 0

5 Number ofgroundreferenceplanesrequiredforeach DDR2 routinglayer 1

6 Number oflayersbetween DDR2 routinglayerand referencegroundplane 0

7 PCB RoutingFeatureSize 4 Mils

8 PCB TraceWidthw 4 Mils

8 PCB BGA escape viapad size 18 Mils

9 PCB BGA escape viaholesize 8 Mils

10 DSP DeviceBGA pad size(1)

11 DDR2 DeviceBGA pad size(2)

12 SingleEnded Impedance,Zo 50 75 Ω

13 Impedance Control(3) Z-5 Z Z+5 Ω

(1) See theFlipChipBallGridArrayPackage ReferenceGuide (SPRU811 )forDSP deviceBGA pad size. (2) See theDDR2 devicemanufacturerdocumenationfortheDDR2 deviceBGA pad size. (3) Z isthenominalsingledended impedance selectedforthePCB specifiedby item12. 7.10.2.4Placement Figure7-29 shows the requiredplacementforthe DM6467 deviceas wellas the DDR2 devices.The dimensionsforFigure7-29aredefinedinTable7-36.The placementdoes notrestrictthesideofthePCB thatthe devicesare mounted on. The ultimatepurpose of the placementisto limitthe maximum trace lengthsand allowforproperroutingspace.For a 16 bitDDR memory systems,the highword DDR2 deviceisomittedfromtheplacement. Figure7-29.DM6467 and DDR2 Device Placement Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 213 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

DDR2□Controller DDR2□Device TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-36.Placement Specifications No. Parameter Min Max Unit

1 X (1)(2) 1660 Mils

2 Y (1)(2) 1280 Mils

3 Y Offset(1)(2)(3) 650 Mils

4 DDR2 KeepoutRegion(4)

5 Clearancefromnon-DDR2 signaltoDDR2 KeepoutRegion(5) 4 w

(1) See Figure7-27fordimensiondefintions. (2) Measurements fromcenterofDSP devicetocenterofDDR2 device. (3) For16 bitmemory systemsitisrecommended thatY Offsetbe as smallas possible. (4) DDR2 Keepoutregiontoencompass entireDDR2 routingarea (5) Non-DDR2 signalsallowedwithinDDR2 keepoutregionprovidedtheyareseparatedfromDDR2 routinglayersby a groundplane. 7.10.2.5DDR2 Keep Out Region The regionofthePCB used fortheDDR2 circuitrymust be isolatedfrom othersignals.The DDR2 keep outregionisdefinedforthispurposeand isshown inFigure7-30.The sizeofthisregionvarieswiththe placementand DDR routing.Additionalclearancesrequiredforthekeep outregionareshown inTable7- 36. Figure7-30.DDR2 Keepout Region NOTE The regionshown in Figure7-30 should encompass allthe DDR2 circuitryand varies dependingon placement.Non-DDR2 signalsshouldnotbe routedon theDDR signallayers withintheDDR2 keep outregion.Non-DDR2 signalsmay be routedintheregionprovided theyare routedon layersseparatedfrom DDR2 signallayersby a ground layer.No breaks shouldbe allowedinthereferencegroundlayersinthisregion.Inaddition,the1.8-Vpower planeshouldcovertheentirekeep outregion.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 7.10.2.6Bulk Bypass Capacitors Bulk bypass capacitorsare requiredformoderate speed bypassingof the DDR2 and othercircuitry. Table7-37containstheminimum numbers and capacitancerequiredforthebulkbypass capacitors.Note thatthistableonlycoversthe bypass needs of the DSP and DDR2 interfaces.Additionalbulkbypass capacitancemay be needed forothercircuitry. Table7-37.Bulk Bypass Capacitors No. Parameter Min Max Unit

1 DV DD18 BulkBypass CapacitorCount(1) 3 Devices

2 DV DD18 BulkBypass TotalCapacitance 30 μF

3 DDR#1 BulkBypass CapacitorCount(1) 1 Devices

4 DDR#1 BulkBypass TotalCapacitance(1) 10 μF

5 DDR#2 BulkBypass CapacitorCount(2) 1 Devices

6 DDR#2 BulkBypass TotalCapacitance(1)(2) 10 μF

(1) These devicesshouldbe placednearthedevicetheyarebypassing,butpreferenceshouldbe giventotheplacementofthehigh-speed (HS)bypasscaps. (2) Onlyused on 32-bitwideDDR2 memory systems 7.10.2.7High-Speed Bypass Capacitors High-Speed (HS) bypass capacitorsare criticalforproperDDR2 interfaceoperation.Itis particularly importantto minimizethe parasiticseriesinductanceof the HS bypass cap, DSP/DDR power, and DSP/DDR groundconnections.Table7-38containsthespecificationfortheHS bypass capacitorsas well as forthepower connectionson thePCB. 7.10.2.8Net Classes Table7-39liststheclocknetclassesfortheDDR2 interface.Table7-40liststhesignalnetclasses,and associatedclocknetclasses,forthesignalsintheDDR2 interface.These netclassesare used forthe terminationand routingrulesthatfollow. Table7-38.High-Speed Bypass Capacitors No. Parameter Min Max Unit

1 HS Bypass CapacitorPackage Size(1) 0402 10 Mils

2 DistancefromHS bypasscapacitortodevicebeingbypassed 250 Mils

3 Number ofconnectionviasforeach HS bypasscapacitor(2) 2 Vias

4 Tracelengthfrombypasscapacitorcontacttoconnectionvia 1 30 Mils

5 Number ofconnectionviasforeach DSP devicepower orgroundballs 1 Vias

6 TracelengthfromDSP devicepower balltoconnectionvia 35 Mils

7 Number ofconnectionviasforeach DDR2 devicepower orgroundballs 1 Vias

8 TracelengthfromDDR2 devicepower balltoconnectionvia 35 Mils

9 DV DD18 HS Bypass CapacitorCount(3) 20 Devices

10 DV DD18 HS Bypass CapacitorTotalCapacitance 1.2 μF

11 DDR#1 HS Bypass CapacitorCount(3) 8 Devices

12 DDR#1 HS Bypass CapacitorTotalCapacitance 0.4 μF

13 DDR#2 HS Bypass CapacitorCount(3)(4) 8 Devices

14 DDR#2 HS Bypass CapacitorTotalCapacitance(4) 0.4 μF (1) LxW, 10 milunits,i.e.,a 0402 isa 40x20 milsurfacemount capacitor (2) An additionalHS bypasscapacitorcan sharetheconnectionviasonlyifitismounted on theoppositesideoftheboard. (3) These devicesshouldbe placedas closeas possibletothedevicebeingbypassed. (4) Onlyused on 32-bitwideDDR2 memory systems Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 215 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-39.Clock Net Class Definitions Clock Net Class DSP Pin Names CK DDR_CLK/ DDR_CLK DQS0 DDR_DQS0/ DDR_DQS0 DQS1 DDR_DQS1/ DDR_DQS1 DQS2 (1) DDR_DQS2/ DDR_DQS2 DQS3 (1) DDR_DQS3/ DDR_DQS3 (1) Onlyused on 32-bitwideDDR2 memory systems. Table7-40.SignalNet Class Definitions AssociatedClock Net Clock Net Class Class DSP Pin Names ADDR_CTRL CK DDR_BA[2:0],DDR_A[14:0],DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE DQ0 DQS0 DDR_DQ[7:0],DDR_DQM0 DQ1 DQS1 DDR_DQ[15:8],DDR_DQM1 DQ2 (1) DQS2 DDR_DQ[23:16],DDR_DQM2 DQ3 (1) DQS3 DDR_DQ[31:24],DDR_DQM3 DQGATEL CK, DQS0, DQS1 DDR_DQGATE0, DDR_DQGATE1 DQGATEH (1) CK, DQS2, DQS3 DDR_DQGATE2, DDR_DQGATE3 (1) Onlyused on 32-bitwideDDR2 memory systems. 7.10.2.9DDR2 SignalTermination No terminationsof any kindare requiredinorderto meet signalintegrityand overshootrequirements. Serialterminatorsare permitted,ifdesired,toreduceEMI risk;however,serialterminationsare theonly typepermitted.Table7-41shows thespecificationsfortheseriesterminators. Table7-41.DDR2 SignalTerminations No. Parameter Min Typ Max Unit

1 CK Net Class(1) 0 10 Ω

2 ADDR_CTRL Net Class(1)(2)(3) 0 22 Zo Ω

3 Data ByteNet Classes(DQS0-DQS3, DQ0-DQ3) (1)(2)(3)(4) 0 22 Zo Ω

4 DQGATE Net Classes(DQGATEL, DQGATEH) (1)(2)(3) 0 10 Zo Ω

(1) Onlyseriesterminationispermitted,parallelorSST specificallydisallowed. (2) Terminatorvalueslargerthantypicalonlyrecommended toaddressEMI issues. (3) Terminationvalueshouldbe uniformacrossnetclass. (4) When no terminationisused on datalines(0Ωs),theDDR2 devicesmust be programmed tooperatein60% strengthmode.

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A T DDR2 Controller DM646x DM646x Device DDR2□Device VREF□Nominal□Minimum Trace□Width□is□20□Mils VREF□Bypass□Capacitor Neck□down□to□minimum□in□BGA escape regions□is□acceptable.□Narrowing□to accomodate□via□congestion□for□short distances□is□also□acceptable.□Best performance□is□obtained□if□the□width of□VREF□is□maximized. TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 7.10.2.10VREF Routing VREF isused as a referenceby theinputbuffersoftheDDR2 memories as wellas theDM6467 ’s.VREF isintendedtobe 1/2theDDR2 power supplyvoltageand shouldbe createdusinga resistivedivideras shown inFigure7-28. Other methods of creatingVREF are not recommended. Figure7-31 shows the layoutguidelinesforVREF. Figure7-31.VREF Routing and Topology 7.10.2.11DDR2 CK and ADDR_CTRL Routing Figure7-32 shows thetopologyoftheroutingfortheCK and ADDR_CTRL netclasses.The routeisa balancedT as itisintendedthatthelengthofsegments B and C be equal.Inaddition,thelengthofA shouldbe maximized. Figure7-32.CK and ADDR_CTRL Routing and Topology Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 217 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

T T DM646x T DDR2 Controller T TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-42.CK and ADDR_CTRL Routing Specification(1) No Parameter Min Typ Max Unit

1 CentertocenterCK-CK spacing 2w

2 CK A toB/A toC Skew LengthMismatch(1) 25 Mils

3 CK B toC Skew LengthMismatch 25 Mils

4 CentertocenterCK tootherDDR2 tracespacing(2) 4w

5 CK/ADDR_CTRL nominaltracelength(3) CACLM-50 CACLM CACLM+50 Mils

6 ADDR_CTRL toCK Skew LengthMismatch 100 Mils

7 ADDR_CTRL toADDR_CTRL Skew LengthMismatch 100 Mils

8 CentertocenterADDR_CTRL tootherDDR2 tracespacing(2) 4w

9 CentertocenterADDR_CTRL tootherADDR_CTRL tracespacing(2) 3w

10 ADDR_CTRL A toB/A toC Skew LengthMismatch(1) 100 Mils

11 ADDR_CTRL B toC Skew LengthMismatch 100 Mils

(1) Seriesterminator,ifused,shouldbe locatedclosesttoDSP. (2) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (3) CACLM isthelongestManhattandistanceoftheCK and ADDR_CTRL netclasses. Figure7-33shows thetopologyand routingfortheDQS and DQ netclasses;theroutesarepointtopoint. Skew matchingacrossbytesisnotneeded norrecommended. Figure7-33.DQS and DQ Routing and Toplogy

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T T FH FL DDR2 Controller DM646x TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-43.DQS and DQ Routing Specification(1) No. Parameter Min Typ Max Unit

1 CentertocenterDQS- DQS spacing 2w

2 DQS E Skew LengthMismatch 25 Mils

3 CentertocenterDQS tootherDDR2 tracespacing(2) 4w

4 DQS/DQ nominaltracelength(1)(3)(4)(5) DQLM-50 DQLM DQLM+50 Mils

5 DQ toDQS Skew LengthMismatch(3)(4)(5) 100 Mils

6 DQ toDQ Skew LengthMismatch(3)(4)(5) 100 Mils

7 CentertocenterDQ tootherDDR2 tracespacing(2)(6) 4w

8 CentertocenterDQ tootherDQ tracespacing(2)(7)(8) 3w

9 DQ/DQS E Skew LengthMismatch(3)(4)(5) 100 Mils

(1) Seriesterminator,ifused,shouldbe locatedclosesttoDDR. (2) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (3) A 16 bitDDR memory systemwillhave two setsofdatanetclasses,one fordatabyte0,and one fordatabyte1,each withan associatedDQS (2DQS 's). (4) A 32 bitDDR memory systemwillhave foursetsofdatanetclasses,one each fordatabytes0 through3,and each associatedwitha DQS (4DQS 's). (5) Thereisno need and itisnotrecommended toskew match acrossdatabytes,iefromDQS0 and databyte0 toDQS1 and databyte1. (6) DQ 's fromotherDQS domains areconsideredotherDDR2 trace. (7) DQ 's fromotherdatabytesareconsideredotherDDR2 trace. (8) DQLM isthelongestManhattandistanceofeach oftheDQS and DQ netclasses. Figure7-34shows theroutingfortheDQGATE netclasses.Table7-44containstheroutingspecification. Figure7-34.DQGATE Routing Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 219 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-44.DQGATE Routing Specification No. Parameter Min Typ Max Unit

1 DQGATEL LengthF (1) CKB0B1

2 DQGATEH LengthF (2)(3) CKB2B3

3 CentertocenterDQGATE toany othertracespacing 4w

4 DQS/DQ nominaltracelength DQLM-50 DQLM DQLM+50 Mils

5 DQGATEL Skew (4) 100 Mils

6 DQGATEH Skew (3)(5) 100 Mils

(1) CKB0B1 isthesum ofthelengthoftheCK netplustheaveragelengthoftheDQS0 and DQS1 nets. (2) CKB2B3 isthesum ofthelengthoftheCK netplustheaveragelengthoftheDQS2 and DQS3 nets. (3) Onlyused in32-bitwideDDR2 memory systems. (4) Skew fromCKB0B1 (5) Skew fromCKB2B3

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VP_CLKIN0 VPIF Channel□0 Input□Clock□Source VP_CLKIN0 VSCLKDIS.VID0 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012

7.11 Video PortInterface(VPIF)

The DM6467 VideoPortInterface(VPIF)allowsthecaptureand displayofdigitalvideostreams.Features include:

99-MHz VPIF (-594DevicesOnly)and 108-MHz VPIF (-729DevicesOnly)
Up to2 VideoCaptureChannels(Channel0 and Channel1) – Two 8-bitStandard-Definition(SD)Videowithembedded timingcodes (BT.656) – Single16-bitHigh-Definition(HD) Videowithembedded timingcodes (BT.1120) – SingleRaw Video(8-/10-/12-bit)
Up to2 VideoDisplayChannels(Channel2 and Channel3) – Two 8-bitSD VideoDisplaywithembedded timingcodes (BT.656) – Single16-bitHD VideoDisplaywithembedded timingcodes (BT.1120) The VPIF capturechannelinputdataformatisselectablebased on thesettingsofthespecificChannel ControlRegister(Channels0–3).The VPIF Raw Videodata-buswidthisselectablebased on thesettings of the Channel 0 ControlRegister.For more detailedinformationon these specificChannel Control Registers,see theTMS320DM646x DMSoC VideoPortInterface(VPIF)User'sGuide (LiteratureNumber SPRUER9 ).

7.11.1 VPIF Bus Master Memory Map

The VPIF peripheralincludesa bus masterinterfacethataccessestheDM6467 system bus totransfer video-captureand video-displaydata.Table7-45shows thememory map fortheVPIF masterinterface. Table7-45.VPIF Master Memory Map START END SIZE VPIF MASTER INTERFACEADDRESS ADDRESS (BYTES) 0x0000 0000 0x7FFF FFFF 2G Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved

7.11.2 VPIF Clock Control(Captureand Display)

The sourceclocksforthe VPIF data channelsare selectablebased on the settingsof the VIDCLKCTL register(0x01C4 0038) (Forthe VIDCLKCTL registerdetails,see Section4.3.2.1, Video Clock Control Register).The VSCLKDIS register(0x01C4 006C) isused todisabletheclockinputswhen changingthe clocksource to ensure glitch-freeoperation.(Forthe VSCLKDIS registerdetails,see Section4.3.2.3, Videoand TSIF ClockDisable). For boththeVPIF dual8-bitor16-bitvideo-capturemodes, Channel 0 isalwaysclockedby VP_CLKIN0 (seeFigure7-35). Figure7-35.VPIF Capture Channel 0 Source Clock Video-CaptureChannel 1 isclockedby the VP_CLKIN1 signal,when the dual 8-bitcapturemode is enabled.When the16-bitcapturemode or8-/10-/12-bitraw-capturemode isused,VP_CLKIN0 must be selectedas theclocksource(VIDCLKCTL.VCH1CLK = 0)[seeFigure7-36]. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 221 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

VIDCLKCTL.VCH2CLK VP_CLKIN2 GP[4]/STC_CLKIN VPIF Channel□2 Output□Clock□Source VP_CLKIN2 STC_CLKIN VP_CLKIN0 CRG0_VCXIURXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x 10x 010 SYSCLK8(B)PLL Controller□1 VSCLKDIS.VID2 PINMUX0.CRGMUX 001 CRG1_VCXI VP_CLKIN0 URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI DEV_MXI/DEV_CLKIN (27□MHz) UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 011 AUXCLK 111(A) VIDCLKCTL.VCH1CLK VP_CLKIN1 VP_CLKIN0 VPIF Channel□1 Input□Clock□Source VP_CLKIN1 VP_CLKIN0 VSCLKDIS.VID1 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-36.VPIF Capture Channel 1 Source Clock Selection For boththedual8-bitor16-bitdisplaymodes, theVPIF DisplayChannel 2 outputsdatasynchronousto VP_CLKO2. The sourceclockforthe VP_CLKO2 outputisselectablefrom a number of externalclock inputsoron-chipclocksources(seeFigure7-37). (A)111 = Reserved. (B)Forthe-729devices,use an externalclocksourceforthe54-/74.25-/108-MHzVPIF clock. Figure7-37.VPIF DisplayChannel 2 Source Clock Selection For the dual8-bitdisplaymode, the VPIF DisplayChannel 3 outputsdata synchronousto VP_CLKO3. The sourceclockfortheVP_CLKO3 outputisselectablefroma number ofexternalclockinputsoron-chip clocksources(seeFigure7-38).When the16-bitdisplaymode forChannel 3 isselected,theclocksource must match thatofChannel2 (VIDCLKCTL.VCH3CLK = VCH2CLK).

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VIDCLKCTL.VCH3CLK VP_CLKIN2 GP[4]/STC_CLKIN VPIF Channel□3 Output□Clock□Source VP_CLKIN2 STC_CLKIN VP_CLKIN0 CRG0_VCXIURXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x 10x 011 AUXCLK PLL Controller□1 VSCLKDIS.VID3 PINMUX0.CRGMUX 001 CRG1_VCXI VP_CLKIN0 URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI DEV_MXI/DEV_CLKIN (27□MHz) UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 111VP_CLKIN3/TS1_CLKO VP_CLKIN3 010 SYSCLK8(A) TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 (A)Forthe-729devices,use an externalclocksourceforthe54-/74.25-/108-MHzVPIF clock. Figure7-38.VPIF DisplayChannel 3 Source Clock Selection Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 223 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.11.3 VPIF RegisterDescriptions

Table7-46shows theVPIF registers. Table7-46.Video PortInterface(VPIF)Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 2000 PID Peripheralidentificationregister 0x01C1 2004 CH0_CTRL Channel0 controlregister 0x01C1 2008 CH1_CTRL Channel1 controlregister 0x01C1 200C CH2_CTRL Channel2 controlregister 0x01C1 2010 CH3_CTRL Channel3 controlregister 0x01C1 2014 -0x01C1 201F - Reserved 0x01C1 2020 INTEN Interruptenable 0x01C1 2024 INTENSET Interruptenableset 0x01C1 2028 INTENCLR Interruptenableclear 0x01C1 202C INTSTAT Interruptstatus 0x01C1 2030 INTSTATCLR Interruptstatusclear 0x01C1 2034 EMU_CTRL Emulationcontrol 0x01C1 2038 DMA_SIZE DMA sizecontrol 0x01C1 203C -0x01C1 203F - Reserved CAPTURE CHANNEL 0 REGISTERS 0x01C1 2040 CH0_TY_STRTADR Channel0 Top Fieldluma bufferstartaddress 0x01C1 2044 CH0_BY_STRTADR Channel0 BottomFieldluma bufferstartaddress 0x01C1 2048 CH0_TC_STRTADR Channel0 Top Fieldchroma bufferstartaddress 0x01C1 204C CH0_BC_STRTADR Channel0 BottomFieldchroma bufferstartaddress 0x01C1 2050 CH0_THA_STRTADR Channel0 Top Fieldhorizontalancillarydatabufferstartaddress 0x01C1 2054 CH0_BHA_STRTADR Channel0 BottomFieldhorizontalancillarydatabufferstartaddress 0x01C1 2058 CH0_TVA_STRTADR Channel0 Top Fieldverticalancillarydatabufferstartaddress 0x01C1 205C CH0_BVA_STRTADR Channel0 BottomFieldverticalancillarydatabufferstartaddress 0x01C1 2060 CH0_SUBPIC_CFG Channel0 sub-pictureconfiguration 0x01C1 2064 CH0_IMG_ADD_OFST Channel0 image dataaddressoffset 0x01C1 2068 CH0_HA_ADD_OFST Channel0 horizontalancillarydataaddressoffset 0x01C1 206C CH0_HSIZE_CFG Channel0 horizontaldatasizeconfiguration 0x01C1 2070 CH0_VSIZE_CFG0 Channel0 verticaldatasizeconfiguration(0) 0x01C1 2074 CH0_VSIZE_CFG1 Channel0 verticaldatasizeconfiguration(1) 0x01C1 2078 CH0_VSIZE_CFG2 Channel0 verticaldatasizeconfiguration(2) 0x01C1 207C CH0_VSIZE Channel0 verticalimage size CAPTURE CHANNEL 1 REGISTERS 0x01C1 2080 CH1_TY_STRTADR Channel1 Top Fieldluma bufferstartaddress 0x01C1 2084 CH1_BY_STRTADR Channel1 BottomFieldluma bufferstartaddress 0x01C1 2088 CH1_TC_STRTADR Channel1 Top Fieldchroma bufferstartaddress 0x01C1 208C CH1_BC_STRTADR Channel1 BottomFieldchroma bufferstartaddress 0x01C1 2090 CH1_THA_STRTADR Channel1 Top Fieldhorizontalancillarydatabufferstartaddress 0x01C1 2094 CH1_BHA_STRTADR Channel1 BottomFieldhorizontalancillarydatabufferstartaddress 0x01C1 2098 CH1_TVA_STRTADR Channel1 Top Fieldverticalancillarydatabufferstartaddress 0x01C1 209C CH1_BVA_STRTADR Channel1 BottomFieldverticalancillarydatabufferstartaddress 0x01C1 20A0 CH1_SUBPIC_CFG Channel1 sub-pictureconfiguration 0x01C1 20A4 CH1_IMG_ADD_OFST Channel1 image dataaddressoffset 0x01C1 20A8 CH1_HA_ADD_OFST Channel1 horizontalancillarydataaddressoffset 0x01C1 20AC CH1_HSIZE_CFG Channel1 horizontaldatasizeconfiguration

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-46.Video PortInterface(VPIF)Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 20B0 CH1_VSIZE_CFG0 Channel1 verticaldatasizeconfiguration(0) 0x01C1 20B4 CH1_VSIZE_CFG1 Channel1 verticaldatasizeconfiguration(1) 0x01C1 20B8 CH1_VSIZE_CFG2 Channel1 verticaldatasizeconfiguration(2) 0x01C1 20BC CH1_VSIZE Channel1 verticalimage size DISPLAY CHANNEL 2 REGISTERS 0x01C1 20C0 CH2_TY_STRTADR Channel2 Top Fieldluma bufferstartaddress 0x01C1 20C4 CH2_BY_STRTADR Channel2 BottomFieldluma bufferstartaddress 0x01C1 20C8 CH2_TC_STRTADR Channel2 Top Fieldchroma bufferstartaddress 0x01C1 20CC CH2_BC_STRTADR Channel2 BottomFieldchroma bufferstartaddress 0x01C1 20D0 CH2_THA_STRTADR Channel2 Top Fieldhorizontalancillarydatabufferstartaddress 0x01C1 20D4 CH2_BHA_STRTADR Channel2 BottomFieldhorizontalancillarydatabufferstartaddress 0x01C1 20D8 CH2_TVA_STRTADR Channel2 Top Fieldverticalancillarydatabufferstartaddress 0x01C1 20DC CH2_BVA_STRTADR Channel2 BottomFieldverticalancillarydatabufferstartaddress 0x01C1 20E0 CH2_SUBPIC_CFG Channel2 sub-pictureconfiguration 0x01C1 20E4 CH2_IMG_ADD_OFST Channel2 image dataaddressoffset 0x01C1 20E8 CH2_HA_ADD_OFST Channel2 horizontalancillarydataaddressoffset 0x01C1 20EC CH2_HSIZE_CFG Channel2 horizontaldatasizeconfiguration 0x01C1 20F0 CH2_VSIZE_CFG0 Channel2 verticaldatasizeconfiguration(0) 0x01C1 20F4 CH2_VSIZE_CFG1 Channel2 verticaldatasizeconfiguration(1) 0x01C1 20F8 CH2_VSIZE_CFG2 Channel2 verticaldatasizeconfiguration(2) 0x01C1 20FC CH2_VSIZE Channel2 verticalimage size 0x01C1 2100 CH2_THA_STRTPOS Channel2 Top Fieldhorizontalancillarydatainsertionstartposition 0x01C1 2104 CH2_THA_SIZE Channel2 Top Fieldhorizontalancillarydatasize 0x01C1 2108 CH2_BHA_STRTPOS Channel2 BottomFieldhorizontalancillarydatainsertionstartposition 0x01C1 210C CH2_BHA_SIZE Channel2 BottomFieldhorizontalancillarydatasize 0x01C1 2110 CH2_TVA_STRTPOS Channel2 Top Fieldverticalancillarydatainsertionstartposition 0x01C1 2114 CH2_TVA_SIZE Channel2 Top Fieldverticalancillarydatasize 0x01C1 2118 CH2_BVA_STRTPOS Channel2 BottomFieldverticalancillarydatainsertionstartposition 0x01C1 211C CH2_BVA_SIZE Channel2 BottomFieldverticalancillarydatasize 0x01C1 2120 -0x01C1 213F - Reserved DISPLAY CHANNEL 3 REGISTERS 0x01C1 2140 CH3_TY_STRTADR Channel3 Field0 luma bufferstartaddress 0x01C1 2144 CH3_BY_STRTADR Channel3 Field1 luma bufferstartaddress 0x01C1 2148 CH3_TC_STRTADR Channel3 Field0 chroma bufferstartaddress 0x01C1 214C CH3_BC_STRTADR Channel3 Field1 chroma bufferstartaddress 0x01C1 2150 CH3_THA_STRTADR Channel3 Field0 horizontalancillarydatabufferstartaddress 0x01C1 2154 CH3_BHA_STRTADR Channel3 Field1 horizontalancillarydatabufferstartaddress 0x01C1 2158 CH3_TVA_STRTADR Channel3 Field0 verticalancillarydatabufferstartaddress 0x01C1 215C CH3_BVA_STRTADR Channel3 Field1 verticalancillarydatabufferstartaddress 0x01C1 2160 CH3_SUBPIC_CFG Channel3 sub-pictureconfiguration 0x01C1 2164 CH3_IMG_ADD_OFST Channel3 image dataaddressoffset 0x01C1 2168 CH3_HA_ADD_OFST Channel3 horizontalancillarydataaddressoffset 0x01C1 216C CH3_HSIZE_CFG Channel3 horizontaldatasizeconfiguration 0x01C1 2170 CH3_VSIZE_CFG0 Channel3 verticaldatasizeconfiguration(0) 0x01C1 2174 CH3_VSIZE_CFG1 Channel3 verticaldatasizeconfiguration(1) 0x01C1 2178 CH3_VSIZE_CFG2 Channel3 verticaldatasizeconfiguration(2) 0x01C1 217C CH3_VSIZE Channel3 verticalimage size Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 225 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-46.Video PortInterface(VPIF)Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 2180 CH3_THA_STRTPOS Channel3 Top Fieldhorizontalancillarydatainsertionstartposition 0x01C1 2184 CH3_THA_SIZE Channel3 Top Fieldhorizontalancillarydatasize 0x01C1 2188 CH3_BHA_STRTPOS Channel3 BottomFieldhorizontalancillarydatainsertionstartposition 0x01C1 218C CH3_BHA_SIZE Channel3 BottomFieldhorizontalancillarydatasize 0x01C1 2190 CH3_TVA_STRTPOS Channel3 Top Fieldverticalancillarydatainsertionstartposition 0x01C1 2194 CH3_TVA_SIZE Channel3 Top Fieldverticalancillarydatasize 0x01C1 2198 CH3_BVA_STRTPOS Channel3 BottomFieldverticalancillarydatainsertionstartposition 0x01C1 219C CH3_BVA_SIZE Channel3 BottomFieldverticalancillarydatasize 0x01C1 21A0 -0x01C1 21FF - Reserved

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7.11.4 VPIF ElectricalData/Timing

Table7-47.Timing Requirements forVPIF VP_CLKINx Inputs(1)(seeFigure7-39) -594 -729 NO. UNIT MIN MAX MIN MAX 1 tc(VKI) Cycletime,VP_CLKIN0/1/2/3 10.1 9.25 ns 2 tw(VKIH) Pulseduration,VP_CLKINx high 0.4C 0.4C ns 3 tw(VKIL) Pulseduration,VP_CLKINx low 0.4C 0.4C ns 4 tt(VKI) Transitiontime,VP_CLKINx 5 5 ns (1) C = VP_CLKINx periodinns. Figure7-39.Video PortCapture VP_CLKINx Timing Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 227 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

VP_CLKOx (Positive Edge Clocking) VP_CLKOx (Negative Edge Clocking) VP_DOUTx 11 12 VP_CLKIN0/1 VP_DINx/FIELD/ HSYNC/VSYNC TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-48.Timing Requirements forVPIF Channels 0/1Video Capture Data and ControlInputs (seeFigure7-40) -594 -729 NO. UNIT MIN MAX MIN MAX 1 tsu(VDINV-VKIH) Setuptime,VP_DINx validbeforeVP_CLKIN0/1 high 3.3 2.55 ns 2 th(VKIH-VDINV) Holdtime,VP_DINx validafterVP_CLKIN0/1 high 0 0 ns Figure7-40.VPIF Channels 0/1Video Capture Data and ControlInputTiming Table7-49.SwitchingCharacteristicsOver Recommended OperatingConditionsforVideo Data Shown With Respect toVP_CLKO2/3 (1) (seeFigure7-41) -594 -729 NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(VKO) Cycletime,VP_CLKO2/3 10.1 9.25 ns 2 tw(VKOH) Pulseduration,VP_CLKO2/3 high 0.4C 0.4C ns 3 tw(VKOL) Pulseduration,VP_CLKO2/3 low 0.4C 0.4C ns 4 tt(VKO) Transitiontime,VP_CLKO2/3 5 5 ns td(VKOH-11 Delaytime,VP_CLKO2/3 hightoVP_DOUTx valid 6.8 6.5 ns VPDOUTV) td(VCLKOH-12 Delaytime,VP_CLKO2/3 hightoVP_DOUTx invalid 1.5 1.5 ns VPDOUTIV) (1) C = VP_CLKO2/3 periodinns. Figure7-41.VPIF Channels 2/3Video DisplayData Output Timing With Respect toVP_CLKO2/3

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7.12 TransportStream Interface(TSIF)

The DM6467 deviceincludestwo independentTransportStream Interfaces(TSIF0 and TSIF1) with correspondingClockReferenceGenerator(CRGEN) Modules forSystem Time-ClockRecovery.The TSIF peripheralsupportsthefollowingfeatures:

1-bitSerialand 8-bitParallelindependentreceiveand transmitinterfaceswithbothsynchronousand asynchronousmodes. (TSIF1 supportsSerialmode only.)
Stream input/output(I/O)speed rateconfigurableby theI/Oclockspeed
ATS (absolutetimestamp)detection,correction,and additionmodes
AutomaticallydetectsPAT and PMT and reflectsassignmenttotheinternalPacketIdentification(PID) table(supportedforpartialTransferStream [TS]mode only;streamtypeand PID shouldbe one-to- one mapping)
PID filterwith7 PID filtertablesand streamtypeassignments
BYPASS mode implemented so thatnot only TS data,but any otherdata can be receivedor transmittedby theTSIF module
Ringbuffercontrolforbothwrites(8channels)and reads(1channel)to/frommemory
Supports“SpecificPacket”,indicatingboundaryofpluralprogramon TS
SupportsFull-TSinonlyone mode –Semi-Automatic-Amode, allowingcommunicationto the C64x+ CPU.
Supports Partial-TSin these modes –Semi-Automatic-Bmode and Full-Automaticmode (provided streamtypeand PID areone-to-onemapping) For more detailedinformationon the CRGEN peripheral,see the TMS320DM646x DMSoC Clock ReferenceGeneratorUser'sGuide (literaturenumber SPRUEQ1 ).

7.12.1 TSIF Bus Master

The TSIF peripheralseach includea bus master interfacethataccesses the DM646x system bus to transferstream receiveand transmitdata.Table 7-50 shows the memory map forthe TSIF master interfaces. Table7-50.TSIF0/1Master Memory Map SIZESTART ADDRESS END ADDRESS TSIF0/1ACCESS(BYTES) 0x0000 0000 0x0FFF FFFF 256M Reserved 0x1000 0000 0x1000 FFFF 64K Reserved 0x1001 0000 0x1001 3FFF 16K ARM RAM 0 (Data) 0x1001 4000 0x1001 7FFF 16K ARM RAM 1 (Data) 0x1001 8000 0x1001 FFFF 32K ARM ROM (Data) 0x1002 0000 0x10FF FFFF 16256K Reserved 0x1100 0000 0x41FF FFFF 784M 0x4200 0000 0x43FF FFFF 32M EMIFA Data (CS2) 0x4400 0000 0x45FF FFFF 32M EMIFA Data (CS3) 0x4600 0000 0x47FF FFFF 32M EMIFA Data (CS4) 0x4800 0000 0x49FF FFFF 32M EMIFA Data (CS5) 0x4A00 0000 0x4BFF FFFF 32M Reserved 0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) 0x5000 0000 0x7FFF FFFF 768M Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 229 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

TSIFCTL.PTSO_CLK TSIF0 Output□Clock□Source STC_CLKIN 011 SYSCLKBP PLL Controller□1 VSCLKDIS.TSIFTX0 100 VP_CLKIN0 GP[4]/STC_CLKIN VP_CLKIN0 DEV_MXI/DEV_CLKIN (27□MHz) 000 CRG0_VCXI URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x 10x PINMUX0.CRGMUX UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 110 101 TS0_CLKIN VP_CLKIN1 TS0_CLKIN VP_CLKIN1 111URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI CRG1_VCXI 010 SYSCLK5 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com

7.12.2 TSIF Clock Control

The sourceclocksfortheTSIF countersand outputchannelsareselectablebased on thesettingsofthe TSIFCTL register(0x01C4 0050). (For more detailedinformationon the TSIFCTL register,see Section4.3.2.2,TSIF Control.)The VSCLKDIS register(0x01C4 006C) isused todisabletheclockinputs when changingthe clocksourceto ensure glitch-freeoperation.(Formore detailedinformaitonon the VSCLKDIS register,see Section4.3.2.3,Videoand TSIF ClockDisable.) TSIF0 outputsdatasynchronoustoTS0_CLKO. The sourceclockfortheTS0_CLKO outputisselectable fromamong a number ofexternalclockinputsoron-chipclocksources(seeFigure7-42). Figure7-42.TSIF0 Output Clock Source Selection The TSIF0 system timecountermay be clockedfrom a number ofexternalclockinputsor on-chipclock sources(seeFigure7-43).

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TSIFCTL.TSSO_CLK TS1_CLKIN VP_CLKIN0 TSIF1 Output□Clock□Source TS1_CLKIN VP_CLKIN0 CRG1_VCXI CRG0_VCXI URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x 10x 0011 SYSCLKBP PLL Controller□1 VSCLKDIS.TSIFTX1 PINMUX0.CRGMUX 0001 STC_CLKIN URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI GP[4]/STC_CLKIN DEV_MXI/DEV_CLKIN (27□MHz) UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 0110VP_CLKIN2 VP_CLKIN2 0010 SYSCLK6 (A) 01 1 1, 1001–1xx1 = Reserved. 001 TSIFCTL.TSIF0_CNTCLK TSIF0 Counter□Clock STC_CLKIN 010AUXCLKPLL Controller□1 VSCLKDIS.TSIFCNT0 GP[4]/STC_CLKIN DEV_MXI/DEV_CLKIN (27□MHz) 000 CRG0_VCXIURXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x 10x PINMUX0.CRGMUX UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 100 011 VP_CLKIN0 VP_CLKIN0 CRG1_VCXI 101VP_CLKIN1 VP_CLKIN1 (A)□□110,□111□=□Reserved. URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-43.TSIF0 Counter Clock Selection TSIF1 outputsdatasynchronoustoTS1_CLKO. The sourceclockfortheTS1_CLKO outputisselectable fromamong a number ofexternalclockinputsoron-chipclocksources(seeFigure7-44). Figure7-44.TSIF1 Output Clock Source Selection The TSIF1 system timecountermay be clockedfrom a number ofexternalclockinputsor on-chipclock sources(seeFigure7-45). Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 231 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

TSIFCTL.TSIF1_CNTCLK TSIF1 Counter□Clock STC_CLKIN 010AUXCLKPLL Controller□1 VSCLKDIS.TSIFCNT1 GP[4]/STC_CLKIN DEV_MXI/DEV_CLKIN (27□MHz) 011 CRG0_VCXIURXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x 10x PINMUX0.CRGMUX UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 100 000 VP_CLKIN2 VP_CLKIN2 CRG1_VCXI 101VP_CLKIN3/TS1_CLKO VP_CLKIN3 (A)□□110,□111□=□Reserved. URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-45.TSIF1 Counter Clock Selection

7.12.3 TSIF PeripheralRegisterDescription(s)

The TSIF0 and TSIF1 registersareshown inTable7-51and Table7-52,respectively. Table7-51.TSIF0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 3000 PID TSIF0 peripheralidentification(PID)register 0x01C1 3004 CTRL0 Controlregister0 register 0x01C1 3008 CTRL1 Controlregister1 register 0x01C1 300C INTEN Interruptenableregister 0x01C1 3010 INTEN_SET Interruptenablesetregister 0x01C1 3014 INTEN_CLR Interruptenableclearregister 0x01C1 3018 INTSTAT Interruptstatusregister 0x01C1 301C INTSTAT_CLR Interruptstatusclearregister 0x01C1 3020 EMU_CTRL Emulationcontrolregister 0x01C1 3024 ASYNC_TX_WAIT Asynchronoustransmitwaittimeregister 0x01C1 3028 PAT_SEN_CFG Program associationtable(PAT)sense configurationregister 0x01C1 302C PAT_STR_ADDR PAT storeaddressregister 0x01C1 3030 PMT_SEN_CFG Program map table(PMT) sense configurationregister 0x01C1 3034 PMT_STR_ADDR PMT storeaddressregister 0x01C1 3038 BSP_IN Boundarysensingpacket(BSP) inregister 0x01C1 303C BSP_STORE_ADDR BSP instoreaddressregister 0x01C1 3040 PCR_SENSE_CFG Program clockreference(PCR) sense configurationregister 0x01C1 3044 PID0_FILT_CFG PacketIdentifier(PID)0 (PID0)filterconfigurationregister 0x01C1 3048 PID1_FILT_CFG PID1 filterconfigurationregister 0x01C1 304C PID2_FILT_CFG PID2 filterconfigurationregister 0x01C1 3050 PID3_FILT_CFG PID3 filterconfigurationregister 0x01C1 3054 PID4_FILT_CFG PID4 filterconfigurationregister

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-51.TSIF0 Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 3058 PID5_FILT_CFG PID5 filterconfigurationregister 0x01C1 305C PID6_FILT_CFG PID6 filterconfigurationregister 0x01C1 3060 BYPASS_CFG Bypass mode configurationregister 0x01C1 3064 TX_ATS_INIT TransmitArrivalTime Stamp (ATS)initializationregister 0x01C1 3068 TX_ATS_MON TransmitATS monitorregister 0x01C1 306C – Reserved 0x01C1 3070 RX_PKT_STAT Receivepacketstatusregister 0x01C1 3074 -0x01C1 307F – Reserved 0x01C1 3080 STC_INIT_CTRL System Time Clock(STC) initializationcontrolregister 0x01C1 3084 STC_INIT_VAL STC initializationvalueregister 0x01C1 3088 STC_INT0 STC interruptentry0 register 0x01C1 308C STC_INT1 STC interruptentry1 register 0x01C1 3090 STC_INT2 STC interruptentry2 register 0x01C1 3094 STC_INT3 STC interruptentry3 register 0x01C1 3098 STC_INT4 STC interruptentry4 register 0x01C1 309C STC_INT5 STC interruptentry5 register 0x01C1 30A0 STC_INT6 STC interruptentry6 register 0x01C1 30A4 STC_INT7 STC interruptentry7 register 0x01C1 30A8 -0x01C1 30BF – Reserved 0x01C1 30C0 WRB_CTRL Writeringbufferchannelcontrolregister 0x01C1 30C4 WRB0_STRT_ADDR Writeringbufferchannel0 startaddressregister 0x01C1 30C8 WRB0_END_ADDR Writeringbufferchannel0 end addressregister 0x01C1 30CC WRB0_RDPTR Writeringbufferchannel0 readpointerregister 0x01C1 30D0 WRB0_SUB Writeringbufferchannel0 subtractionregister 0x01C1 30D4 WRB0_WRPTR Writeringbufferchannel0 writepointerregister 0x01C1 30D8 -0x01C1 30DF – Reserved 0x01C1 30E0 WRB1_STRT_ADDR Writeringbufferchannel1 startaddressregister 0x01C1 30E4 WRB1_END_ADDR Writeringbufferchannel1 end addressregister 0x01C1 30E8 WRB1_RDPTR Writeringbufferchannel1 readpointerregister 0x01C1 30EC WRB1_SUB Writeringbufferchannel1 subtractionregister 0x01C1 30F0 WRB1_WRPTR Writeringbufferchannel1 writepointerregister 0x01C1 30F4 -0x01C1 30FF – Reserved 0x01C1 3100 WRB2_STRT_ADDR Writeringbufferchannel2 startaddressregister 0x01C1 3104 WRB2_END_ADDR Writeringbufferchannel2 end addressregister 0x01C1 3108 WRB2_RDPTR Writeringbufferchannel2 readpointerregister 0x01C1 310C WRB2_SUB Writeringbufferchannel2 subtractionregister 0x01C1 3110 WRB2_WRPTR Writeringbufferchannel2 writepointerregister 0x01C1 3114 -0x01C1 311F – Reserved 0x01C1 3120 WRB3_STRT_ADDR Writeringbufferchannel3 startaddressregister 0x01C1 3124 WRB3_END_ADDR Writeringbufferchannel3 end addressregister 0x01C1 3128 WRB3_RDPTR Writeringbufferchannel3 readpointerregister 0x01C1 312C WRB3_SUB Writeringbufferchannel3 subtractionregister 0x01C1 3130 WRB3_WRPTR Writeringbufferchannel3 writepointerregister 0x01C1 3134 -0x01C1 313F – Reserved 0x01C1 3140 WRB4_STRT_ADDR Writeringbufferchannel4 startaddressregister 0x01C1 3144 WRB4_END_ADDR Writeringbufferchannel4 end addressregister 0x01C1 3148 WRB4_RDPTR Writeringbufferchannel4 readpointerregister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 233 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-51.TSIF0 Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 314C WRB4_SUB Writeringbufferchannel4 subtractionregister 0x01C1 3150 WRB4_WRPTR Writeringbufferchannel4 writepointerregister 0x01C1 3154 -0x01C1 315F – Reserved 0x01C1 3160 WRB5_STRT_ADDR Writeringbufferchannel5 startaddressregister 0x01C1 3164 WRB5_END_ADDR Writeringbufferchannel5 end addressregister 0x01C1 3168 WRB5_RDPTR Writeringbufferchannel5 readpointerregister 0x01C1 316C WRB5_SUB Writeringbufferchannel5 subtractionregister 0x01C1 3170 WRB5_WRPTR Writeringbufferchannel5 writepointerregister 0x01C1 3174 -0x01C1 317F – Reserved 0x01C1 3180 WRB6_STRT_ADDR Writeringbufferchannel6 startaddressregister 0x01C1 3184 WRB6_END_ADDR Writeringbufferchannel6 end addressregister 0x01C1 3188 WRB6_RDPTR Writeringbufferchannel6 readpointerregister 0x01C1 318C WRB6_SUB Writeringbufferchannel6 subtractionregister 0x01C1 3190 WRB6_WRPTR Writeringbufferchannel6 writepointerregister 0x01C1 3194 -0x01C1 319F – Reserved 0x01C1 31A0 WRB7_STRT_ADDR Writeringbufferchannel7 startaddressregister 0x01C1 31A4 WRB7_END_ADDR Writeringbufferchannel7 end addressregister 0x01C1 31A8 WRB7_RDPTR Writeringbufferchannel7 readpointerregister 0x01C1 31AC WRB7_SUB Writeringbufferchannel7 subtractionregister 0x01C1 31B0 WRB7_WRPTR Writeringbufferchannel7 writepointerregister 0x01C1 31B4 -0x01C1 31BF – Reserved 0x01C1 31C0 RRB_CTRL Read ringbufferchannelcontrolregister 0x01C1 31C4 RRB_STRT_ADDR Read ringbufferchannelstartaddressregister 0x01C1 31C8 RRB_END_ADDR Read ringbufferchannelend addressregister 0x01C1 31CC RRB_WRPTR Read ringbufferchannelwritepointerregister 0x01C1 31D0 RRB_SUB Read ringbufferchannelsubtractionregister 0x01C1 31D4 RRB_RDPTR Read ringbufferchannelreadpointerregister 0x01C1 31D8 PKT_CNT Packetcountervalueregister 0x01C1 31DC -0x01C1 31FF – Reserved Table7-52.TSIF1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 3400 PID TSIF1 peripheralidentification(PID)register 0x01C1 3404 CTRL0 Controlregister0 register 0x01C1 3408 CTRL1 Controlregister1 register 0x01C1 340C INTEN Interruptenableregister 0x01C1 3410 INTEN_SET Interruptenablesetregister 0x01C1 3414 INTEN_CLR Interruptenableclearregister 0x01C1 3418 INTSTAT Interruptstatusregister 0x01C1 341C INTSTAT_CLR Interruptstatusclearregister 0x01C1 3420 EMU_CTRL Emulationcontrolregister 0x01C1 3424 ASYNC_TX_WAIT Asynchronoustransmitwaittimeregister 0x01C1 3428 PAT_SEN_CFG Program associationtable(PAT)sense configurationregister 0x01C1 342C PAT_STR_ADDR PAT storeaddressregister 0x01C1 3430 PMT_SEN_CFG Program map table(PMT) sense configurationregister 0x01C1 3434 PMT_STR_ADDR PMT storeaddressregister 0x01C1 3438 BSP_IN Boundarysensingpacket(BSP) inregister

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-52.TSIF1 Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 343C BSP_STORE_ADDR BSP instoreaddressregister 0x01C1 3440 PCR_SENSE_CFG Program clockreference(PCR) sense configurationregister 0x01C1 3444 PID0_FILT_CFG PacketIdentifier(PID)0 (PID0)filterconfigurationregister 0x01C1 3448 PID1_FILT_CFG PID1 filterconfigurationregister 0x01C1 344C PID2_FILT_CFG PID2 filterconfigurationregister 0x01C1 3450 PID3_FILT_CFG PID3 filterconfigurationregister 0x01C1 3454 PID4_FILT_CFG PID4 filterconfigurationregister 0x01C1 3458 PID5_FILT_CFG PID5 filterconfigurationregister 0x01C1 345C PID6_FILT_CFG PID6 filterconfigurationregister 0x01C1 3460 BYPASS_CFG Bypass mode configurationregister 0x01C1 3064 TX_ATS_INIT TransmitArrivalTime Stamp (ATS)initializationregister 0x01C1 3468 TX_ATS_MON TransmitATS monitorregister 0x01C1 346C – Reserved 0x01C1 3470 RX_PKT_STAT Receivepacketstatusregister 0x01C1 3474 -0x01C1 347F – Reserved 0x01C1 3480 STC_INIT_CTRL System Time Clock(STC) initializationcontrolregister 0x01C1 3484 STC_INIT_VAL STC initializationvalueregister 0x01C1 3488 STC_INT0 STC interruptentry0 register 0x01C1 348C STC_INT1 STC interruptentry1 register 0x01C1 3490 STC_INT2 STC interruptentry2 register 0x01C1 3494 STC_INT3 STC interruptentry3 register 0x01C1 3498 STC_INT4 STC interruptentry4 register 0x01C1 349C STC_INT5 STC interruptentry5 register 0x01C1 34A0 STC_INT6 STC interruptentry6 register 0x01C1 34A4 STC_INT7 STC interruptentry7 register 0x01C1 34A8 -0x01C1 34BF – Reserved 0x01C1 34C0 WRB_CTRL Writeringbufferchannelcontrolregister 0x01C1 34C4 WRB0_STRT_ADDR Writeringbufferchannel0 startaddressregister 0x01C1 34C8 WRB0_END_ADDR Writeringbufferchannel0 end addressregister 0x01C1 34CC WRB0_RDPTR Writeringbufferchannel0 readpointerregister 0x01C1 34D0 WRB0_SUB Writeringbufferchannel0 subtractionregister 0x01C1 34D4 WRB0_WRPTR Writeringbufferchannel0 writepointerregister 0x01C1 34D8 -0x01C1 34DF – Reserved 0x01C1 34E0 WRB1_STRT_ADDR Writeringbufferchannel1 startaddressregister 0x01C1 34E4 WRB1_END_ADDR Writeringbufferchannel1 end addressregister 0x01C1 34E8 WRB1_RDPTR Writeringbufferchannel1 readpointerregister 0x01C1 34EC WRB1_SUB Writeringbufferchannel1 subtractionregister 0x01C1 34F0 WRB1_WRPTR Writeringbufferchannel1 writepointerregister 0x01C1 34F4 -0x01C1 34FF – Reserved 0x01C1 3500 WRB2_STRT_ADDR Writeringbufferchannel2 startaddressregister 0x01C1 3504 WRB2_END_ADDR Writeringbufferchannel2 end addressregister 0x01C1 3508 WRB2_RDPTR Writeringbufferchannel2 readpointerregister 0x01C1 350C WRB2_SUB Writeringbufferchannel2 subtractionregister 0x01C1 3510 WRB2_WRPTR Writeringbufferchannel2 writepointerregister 0x01C1 3514 -0x01C1 351F – Reserved 0x01C1 3520 WRB3_STRT_ADDR Writeringbufferchannel3 startaddressregister 0x01C1 3524 WRB3_END_ADDR Writeringbufferchannel3 end addressregister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 235 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-52.TSIF1 Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 3528 WRB3_RDPTR Writeringbufferchannel3 readpointerregister 0x01C1 352C WRB3_SUB Writeringbufferchannel3 subtractionregister 0x01C1 3530 WRB3_WRPTR Writeringbufferchannel3 writepointerregister 0x01C1 3534 -0x01C1 353F – Reserved 0x01C1 3540 WRB4_STRT_ADDR Writeringbufferchannel4 startaddressregister 0x01C1 3544 WRB4_END_ADDR Writeringbufferchannel4 end addressregister 0x01C1 3548 WRB4_RDPTR Writeringbufferchannel4 readpointerregister 0x01C1 354C WRB4_SUB Writeringbufferchannel4 subtractionregister 0x01C1 3550 WRB4_WRPTR Writeringbufferchannel4 writepointerregister 0x01C1 3554 -0x01C1 355F – Reserved 0x01C1 3560 WRB5_STRT_ADDR Writeringbufferchannel5 startaddressregister 0x01C1 3564 WRB5_END_ADDR Writeringbufferchannel5 end addressregister 0x01C1 3568 WRB5_RDPTR Writeringbufferchannel5 readpointerregister 0x01C1 356C WRB5_SUB Writeringbufferchannel5 subtractionregister 0x01C1 3570 WRB5_WRPTR Writeringbufferchannel5 writepointerregister 0x01C1 3574 -0x01C1 357F – Reserved 0x01C1 3580 WRB6_STRT_ADDR Writeringbufferchannel6 startaddressregister 0x01C1 3584 WRB6_END_ADDR Writeringbufferchannel6 end addressregister 0x01C1 3588 WRB6_RDPTR Writeringbufferchannel6 readpointerregister 0x01C1 358C WRB6_SUB Writeringbufferchannel6 subtractionregister 0x01C1 3590 WRB6_WRPTR Writeringbufferchannel6 writepointerregister 0x01C1 3594 -0x01C1 359F – Reserved 0x01C1 35A0 WRB7_STRT_ADDR Writeringbufferchannel7 startaddressregister 0x01C1 35A4 WRB7_END_ADDR Writeringbufferchannel7 end addressregister 0x01C1 35A8 WRB7_RDPTR Writeringbufferchannel7 readpointerregister 0x01C1 35AC WRB7_SUB Writeringbufferchannel7 subtractionregister 0x01C1 35B0 WRB7_WRPTR Writeringbufferchannel7 writepointerregister 0x01C1 35B4 -0x01C1 35BF – Reserved 0x01C1 35C0 RRB_CTRL Read ringbufferchannelcontrolregister 0x01C1 35C4 RRB_STRT_ADDR Read ringbufferchannelstartaddressregister 0x01C1 35C8 RRB_END_ADDR Read ringbufferchannelend addressregister 0x01C1 35CC RRB_WRPTR Read ringbufferchannelwritepointerregister 0x01C1 35D0 RRB_SUB Read ringbufferchannelsubtractionregister 0x01C1 35D4 RRB_RDPTR Read ringbufferchannelreadpointerregister 0x01C1 35D8 PKT_CNT Packetcountervalueregister 0x01C1 35DC -0x01C1 35FF – Reserved

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TSx_CLKIN (Positive□Edge□Clocking) TSx_CTL/ TSx_DATA(A) 3 3 TSx_CLKIN (Negative□Edge□Clocking) TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012

7.12.4 TransportStream Interface(TSIF)ElectricalData/Timing

Table7-53.Timing Requirements forTSIF Input(seeFigure7-46) -594,-729 SERIAL PARALLELNO. UNITINPUT INPUT (1) MIN MAX MIN MAX 1 tc(TSCLKIN) Cycletime,TSx_CLKIN 10 16.7 ns 2 tw(TSCLKIN) Pulseduration,TSx_CLKIN high/low(2) 0.4C 0.4C ns 3 tt(TSCLKIN) Transitiontime,TSx_CLKIN 3(3) 3(3) ns AllOthers 4 4 ns Setuptime,TSx_CTL/TSx_DATA (4)inputvalid4 tsu(TSDATAIN-TSCLKINV) TSx_WAITbeforeTSx_CLKIN edge 13 13 nsIN Holdtime,TSx_CTL/TSx_DATA (4)inputvalidafter5 th(TSCLKINV-TSDATAIN) 0 0 nsTSx_CLKIN edge (1) TSIF1 supportsSERIAL INPUT mode only. (2) C = TSx_CLKIN period(cycletime)inns. (3) Fora 4-inchtransmissionlinewith4-pFloadcapacitanceatthedevicepin. (4) TSx_CTL/TSx_DATA inputincludes:TS0_EN_WAITO, TS0_WAITIN, TS0_PSTIN, and TS0_DIN[7:0]fora parallelinput.Fora serial input,TSx_CTL/TSx_DATA inputincludes:TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and TS0_DIN7 orTS1_DIN. A. TSx_CTL/TSx_DATA inputincludes:TS0_EN_WAITO, TS0_WAITIN, TS0_PSTIN, and TS0_DIN[7:0]fora parallel input.For a serialinput,TSx_CTL/TSx_DATA inputincludes:TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and TS0_DIN7 orTS1_DIN. Figure7-46.TSIF InputTiming Table7-54.SwitchingCharacteristicsOver Recommended OperatingConditionsforTSIF Output (seeFigure7-47) -594,-729 SERIAL PARALLELNO. UNITOUTPUT OUTPUT (1) MIN MAX MIN MAX 6 tc(TSCLKO) Cycletime,TSx_CLKO 10 16.7 ns 7 tw(TSCLKO) Pulseduration,TSx_CLKO high/low(2) 0.4C 0.4C ns 8 tt(TSCLKO) Transitiontime,TSx_CLKO 3(3) 3(3) ns (1) TSIF1 supportsSERIAL OUTPUT mode only. (2) C = TSx_CLKO period(cycletime)inns. (3) Fora 4-inchtransmissionlinewith4-pFloadcapacitanceatthedevicepin. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 237 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

TSx_CLKO (Positive□Edge□Clocking) TSx_CTL/ TSx_DATA(A) TSx_CLKO (Negative□Edge□Clocking) 8 8 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-54.SwitchingCharacteristicsOver Recommended OperatingConditionsforTSIF Output (seeFigure7-47)(continued) -594,-729 SERIAL PARALLELNO. UNITOUTPUT OUTPUT (1) MIN MAX MIN MAX AllOthers 1 7.5 1 7.5 ns Delaytime,TSx_CLKO edge to9 td(TSCLKOV-TSDATAO) TS0_WAITO,TSx_CTL/TSx_DATA (4)outputvalid 1 16.5 1 16.5 nsTSx_EN_WAITO (4) TSx_CTL/TSx_DATA outputincludes:TS0_ENAO, TS0_WAITO, TS0_PSTO, and TS0_DOUT[7:0] fora paralleloutput.Fora serial output,TSx_CTL/TSx_DATA outputincludes:TSx_ENAO, TSx_EN_WAITO, TSx_PSTO, and TS0_DOUT7 orTS1_DOUT. A. TSx_CTL/TSx_DATA outputincludes:TS0_ENAO, TS0_WAITO, TS0_PSTO, and TS0_DOUT[7:0] fora parallel output.For a serialoutput,TSx_CTL/TSx_DATA outputincludes:TSx_ENAO, TSx_EN_WAITO, TSx_PSTO, and TS0_DOUT7 orTS1_DOUT. Figure7-47.TSIF Output Timing

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7.13 Clock Recovery Generator(CRGEN)

Each TSIF module has an associatedCRGEN module whichcan adjustthelocalsystemtimeclockbased upon thereceivedProgram ClockReference(PCR) packets.CRGEN0 may onlybe used withTSIF 0 and CRGEN 1 may onlybe used withTSIF 1. Each CRGEN module features:

AutomaticloadofreceivedPCR packetvaluesfromassociatedTSIF module
LocalSystem Time Clock(STC) counter
PCR/STC differencegenerator(subtractor)
Loop Filter(LPF)
1-bitsigma/deltamodulatordigital-to-analogconverter(DAC) outputforexternalVCXO control

7.13.1 CRGEN PeripheralRegisterDescription(s)

The CRGEN0 and CRGEN1 registersareshown inTable7-55and Table7-56,respectively. Table7-55.CRGEN0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 6000 PID CRGEN PeripheralIdentificationRegister 0x01C2 6004 CONTROL CRGEN controlregister 0x01C2 6008 STC_HI System Time Clock(STC) currentvalue(upper17 bits) 0x01C2 600C STC_LO STC currentvalue(lower16 bitsplusextension) 0x01C2 6010 STC_VAL_HI STC value(upper17 bits)on TSIF0 PCR packetdetection STC value(lower16 bitsplusextension)on TSIF0 PCR packet0x01C2 6014 STC_VAL_LO detection Program ClockReference(PCR) value(upper17 bits)from0x01C2 6018 PCR_HI TSIF0 Receivepacket PCR value(lower16 bitsplusextension)fromTSIF0 Receive0x01C2 601C PCR_LO packet 0x01C2 6020 PCR_PKT_STAT PCR packetstatus 0x01C2 6024 LOOP_FILTER Loop filter(LPF)interface OffsetvalueoftheSTC counterforthehigher(upper)17 bits. 0x01C2 6028 STC_OFFSET_HI ThisvalueisdetectedintheSTC counterwiththefirstPCR loadingpulsesignal. OffsetvalueoftheSTC counterforthelower16 bits.The role0x01C2 602C STC_OFFSET_LO ofthisregisterissame as theSTC_LO register0x01C2 600C. 0x01C2 6030 -0x01C2 603F - Reserved 0x01C2 6040 INTEN Interruptenable 0x01C2 6044 INTEN_SET Interruptenableset 0x01C2 6048 INTEN_CLR Interruptenableclear 0x01C2 604C INTSTAT Interruptstatus 0x01C2 6050 INTSTAT_CLR Interruptstatusclear 0x01C2 6054 EMU_CTRL Emulationcontrol 0x01C2 6058 -0x01C2 607F - Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 239 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-56.CRGEN1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 6400 PID CRGEN PeripheralIdentificationRegister 0x01C2 6404 CONTROL CRGEN controlregister 0x01C2 6408 STC_HI System Time Clock(STC) currentvalue(upper17 bits) 0x01C2 640C STC_LO STC currentvalue(lower16 bitsplusextension) 0x01C2 6410 STC_VAL_HI STC value(upper17 bits)on TSIF1 PCR packetdetection STC value(lower16 bitsplusextension)on TSIF1 PCR packet0x01C2 6414 STC_VAL_LO detection Program ClockReference(PCR) value(upper17 bits)from0x01C2 6418 PCR_HI TSIF1 Receivepacket PCR value(lower16 bitsplusextension)fromTSIF1 Receive0x01C2 641C PCR_LO packet 0x01C2 6420 PCR_PKT_STAT PCR packetstatus 0x01C2 6424 LOOP_FILTER Loop filter(LPF)interface OffsetvalueoftheSTC counterforthehigher17 bits.This 0x01C2 6428 STC_OFFSET_HI valueisdetectedintheSTC counterwiththefirstPCR loading pulsesignal. OffsetvalueoftheSTC counterforthelower16 bits.The role0x01C2 642C STC_OFFSET_LO ofthisregisterissame as theSTC_LO register0x01C2 640C. 0x01C2 6430 -0x01C2 643F - Reserved 0x01C2 6440 INTEN Interruptenable 0x01C2 6444 INTEN_SET Interruptenableset 0x01C2 6448 INTEN_CLR Interruptenableclear 0x01C2 644C INTSTAT Interruptstatus 0x01C2 6450 INTSTAT_CLR Interruptstatusclear 0x01C2 6454 EMU_CTRL Emulationcontrol 0x01C2 6458 -0x01C2 647F - Reserved

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CRGx_PO CRGx_VCXI 2 3 1 4 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012

7.13.2 CRGEN ElectricalData/Timing

Table7-57.Timing Requirements forCRGx_VCXI Input(seeFigure7-48) -594,-729 NO. UNIT MIN NOM MAX 1 tc(VCXI) Cycletime,CRGx_VCXI 29.63 37.037 44.44 ns 2 tw(VCXIH) Pulseduration,CRGx_VCXI high 0.4P ns 3 tw(VCXIL) Pulseduration,CRGx_VCXI low 0.4P ns 4 tt(VCXI) Transitiontime,CRGx_VCXI 5 ns Figure7-48.CRGx_VCXI InputTiming Table7-58.SwitchingCharacteristicsOver Recommended OperatingConditionsforCRGx_PO Output (seeFigure7-49) -594,-729 NO. PARAMETER UNIT MIN MAX 1 tw(POH) Pulseduration,CRGx_PO high 59.26 ns 2 tw(POL) Pulseduration,CRGx_PO low 59.26 ns 3 tt(PO) Transitiontime,CRGx_PO 5 ns Figure7-49.CRGx_PO Output Timing Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 241 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.14 Video Data Conversion Engine (VDCE)

The DM6467 VideoData ConversionEngine(VDCE) supportsthefollowingfeatures:

Resizefunctionon horizontal(HRSZ) and vertical(VRSZ) withratiodefinedby 256/N (N isa natural number thatrangesfrom256 to2048)with4 tapsinterpolation.Magnificationratioofhorizontalresize and verticalresizecan be configuredseparately(differentvaluecan be configured).
Anti-aliasfilter(combinationoftwo kindsoflow-passfilter)withhorizontal7 taps,and verticaldirection.
Chrominance signalformatconversion(CCV) on bothdirections,one isfrom4:2:2to4:2:0and one is from 4:2:0to 4:2:2.Thisfunctionalsouses 4 tapsinterpolation.MPEG-1 specificformat(half-pixel phased fromeven pixelpositionofluminance)isalsosupported.
Edge paddingforpreparationofMC withunrestrictedmotionvector(requiredby MPEG-4, H.264,VC- 1).Allmodes (progressive,interlaceframe,and interlacefield)are supported(macro-blocklevel controlthatisrequiredinH.264 isnot currentlysupported).
VC-1 range mapping inadvanced profile(incase of displayingdecoded referenceimage or trans- codingfromVC-1 toany otherformatofvideocodec).
2-bithardwaremenu overlaywith256 stepsofblendingforeach color.

7.14.1 VDCE Bus Master

The VDCE includesa bus master interfacethataccesses the DM646x system bus to transferdata. Table7-59shows thememory map fortheVDCE interface. Table7-59.VDCE Master Memory Map SIZESTART ADDRESS END ADDRESS VDCE ACCESS(BYTES) 0x0000 0000 0x0FFF FFFF 256M Reserved 0x1000 0000 0x1000 FFFF 64K Reserved 0x1001 0000 0x1001 3FFF 16K ARM RAM 0 (Data) 0x1001 4000 0x1001 7FFF 16K ARM RAM 1 (Data) 0x1001 8000 0x1001 FFFF 32K ARM ROM (Data) 0x1002 0000 0x10FF FFFF 16256K Reserved 0x1100 0000 0x41FF FFFF 784M 0x4200 0000 0x43FF FFFF 32M EMIFA Data (CS2) 0x4400 0000 0x45FF FFFF 32M EMIFA Data (CS3) 0x4600 0000 0x47FF FFFF 32M EMIFA Data (CS4) 0x4800 0000 0x49FF FFFF 32M EMIFA Data (CS5) 0x4A00 0000 0x4BFF FFFF 32M Reserved 0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) 0x5000 0000 0x7FFF FFFF 768M Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved

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7.14.2 VDCE RegisterDescription(s)

Table7-60shows theVDCE registers. Table7-60.VDCE Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 2800 PID VDCE peripheralidentificationregister 0x01C1 2804 CTRL VDCE controlregister 0x01C1 2808 INTEN Interruptenableregister 0x01C1 280C INTEN_SET Interruptenablesetregister 0x01C1 2810 INTEN_CLR Interruptenableclearregister 0x01C1 2814 INTSTAT Interruptstatusregister 0x01C1 2818 INTSTAT_CLR Interruptstatusclearregister 0x01C1 281C EMU_CTRL Emulationcontrolregister 0x01C1 2820 SRD_FRMT Source/Resultdatastoreformatregister 0x01C1 2824 REQ_SIZE Requestunitsizeregister 0x01C1 2828 PROC_SIZE Processingunitsizeregister 0x01C1 282C -0x01C1 283F – Reserved 0x01C1 2840 TY_SRCADDR Luma topfieldsourcestartaddressregister 0x01C1 2844 TY_SRCSPSIZE Luma topfieldsourcesub-picturesizeregister 0x01C1 2848 TY_SRCOFFSET Luma topfieldlinesourceaddressoffsetsizeregister 0x01C1 284C BY_SRCADDR Luma bottomfieldsourcestartaddressregister 0x01C1 2850 BY_SRCSPSIZE Luma bottomfieldsourcesub-picturesizeregister 0x01C1 2854 BY_SRCOFFSET Luma bottomfieldlinesourceaddressoffsetsizeregister 0x01C1 2858 TC_SRCADDR Chroma topfieldsourcestartaddressregister 0x01C1 285C TC_SRCSPSIZE Chroma topfieldsourcesub-picturesizeregister 0x01C1 2860 TC_SRCOFFSET Chroma topfieldlinesourceaddressoffsetsizeregister 0x01C1 2864 BC_SRCADDR Chroma bottomfieldsourcestartaddressregister 0x01C1 2868 BC_SRCSPSIZE Chroma bottomfieldsourcesub-picturesizeregister 0x01C1 286C BC_SRCOFFSET Chroma bottomfieldlinesourceaddressoffsetsizeregister 0x01C1 2870 TBMP_SRCADDR Bitmaptopfieldsourcestartaddressregister 0x01C1 2874 TBMP_SRCOFFSET Bitmaptopfieldlinesourceaddressoffsetregister 0x01C1 2878 BBMP_SRCADDR Bitmapbottomfieldsourcestartaddressregister 0x01C1 287C BBMP_SRCOFFSET Bitmapbottomfieldlinesourceaddressoffsetregister 0x01C1 2880 TY_RESADDR Luma topfieldresultstartaddressregister 0x01C1 2884 TY_RESSPSIZE Luma topfieldresultsub-picturesizeregister 0x01C1 2888 TY_RESOFFSET Luma topfieldlineresultaddressoffsetsizeregister 0x01C1 288C BY_RESADDR Luma bottomfieldresultstartaddressregister 0x01C1 2890 BY_RESSPSIZE Luma bottomfieldresultsub-picturesizeregister 0x01C1 2894 BY_RESOFFSET Luma bottomfieldlineresultaddressoffsetsizeregister 0x01C1 2898 TC_RESADDR Chroma topfieldresultstartaddressregister 0x01C1 289C TC_RESSPSIZE Chroma topfieldresultsub-picturesizeregister 0x01C1 28A0 TC_RESOFFSET Chroma topfieldresultlineaddressoffsetsizeregister 0x01C1 28A4 BC_RESADDR Chroma bottomfieldresultstartaddressregister 0x01C1 28A8 BC_RESSPSIZE Chroma bottomfieldresultsub-picturesizeregister 0x01C1 28AC BC_RESOFFSET Chroma bottomfieldlineresultaddressoffsetsizeregister 0x01C1 28B0 -0x01C1 28BF – Reserved 0x01C1 28C0 IMG_Y_SRCSTRTPOS Luminance sourceimage startpositionregister 0x01C1 28C4 IMG_Y_SRCSIZE Luminance sourceimage sizeregister 0x01C1 28C8 IMG_C_SRCSTRTPOS Chrominancesourceimage startpositionregister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 243 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-60.VDCE Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C1 28CC IMG_C_SRCSIZE Chrominancesourceimage sizeregister 0x01C1 28D0 IMG_BMP_SRCSTRTPOS Bitmapsourceimage startpositionregister 0x01C1 28D4 IMG_BMP_SRCSIZE Bitmapsourceimage sizeregister 0x01C1 28D8 -0x01C1 28DF – Reserved 0x01C1 28E0 IMG_Y_RESSTRTPOS Luminance resultimage startpositionregister 0x01C1 28E4 IMG_Y_RESSIZE Luminance resultimage sizeregister 0x01C1 28E8 IMG_C_RESSTRTPOS Chrominanceresultimage startpositionregister 0x01C1 28EC IMG_C_RESSIZE Chrominanceresultimage sizeregister 0x01C1 28F0 IMG_BMP_RESSTRTPOS Bitmapresultimage startposition(location)register 0x01C1 28F4 -0x01C1 28FF – Reserved 0x01C1 2900 RSZ_MODE Resizemode definitionregister 0x01C1 2904 RSZ_HMAG Horizontalresizemagnificationratiocontrolregister 0x01C1 2908 RSZ_VMAG Verticalresizemagnificationratiocontrolregister 0x01C1 290C RSZ_HPHASE Phase ofinitialpixelon horizontalresizeregister 0x01C1 2910 RSZ_VPHASE Phase ofinitialpixelon verticalresizeregister 0x01C1 2914 RSZ_AFILTER Horizontalanti-aliasing(flicker)filtercontrolregister 0x01C1 2918 -0x01C1 291F – Reserved 0x01C1 2920 CCV_MODE Chrominanceconversionmode controlregister 0x01C1 2924 -0x01C1 293F – Reserved 0x01C1 2940 BLD_LUT_00 Look-uptableforindex00 register 0x01C1 2944 BLD_LUT_01 Look-uptableforindex01 register 0x01C1 2948 BLD_LUT_02 Look-uptableforindex02 register 0x01C1 294C BLD_LUT_03 Look-uptableforindex03 register 0x01C1 2950 -0x01C1 295F – Reserved 0x01C1 2960 RGMP_CTRL Ramp mapping controlreigster 0x01C1 2964 -0x01C1 2983 – Reserved 0x01C1 2984 EPD_LUMA_WIDTH Edge paddingwidthforluminanceregister 0x01C1 2988 EPD_CHROMA_WIDTH Edge paddingwidthforchrominanceregister 0x01C1 298C -0x01C1 291F – Reserved

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7.15 PeripheralComponent Interconnect(PCI)

The DM6467 DMSoC supportsconnectionstoPCI-compliantdevicesviatheintegratedPCI master/slave bus interface.The PCI portinterfacestoDSP internalresourcesviathedataswitchedcentralresource. The dataswitchedcentralresourceisdescribedinmore detailinSection5,System Interconnect. For more detailedinformationon the PCI port peripheralmodule, see the TMS320DM643x DMP PeripheralComponent Interconnect(PCI)User'sGuide (literaturenumber SPRU985).

7.15.1 PCI Device-SpecificInformation

The PCI peripheralon the DM6467 DMSoC conformsto the PCI LocalBus SpecificationRevision2.3. The PCI peripheralcan actbothas a PCI bus masterand as a target.ItsupportsPCI bus operationof speeds up to33 MHz and uses a 32-bitdata/addressbus. On theDM6467 device,thepinsofthePCI peripheralaremultiplexedwiththepinsoftheEMIFA, GPIO, HPI, and ATA peripherals.For more detailedinformationon how to selectPCI, see Section4, Device Configurations. The DM6467 deviceprovidesan initializationmechanism throughwhichthedefaultvaluesforsome ofthe PCI configurationregisterscan be readfroman I2C EEPROM. Table7-61shows theregisterswhichcan be initializedthroughthe PCI auto-initialization.The defaultvalue of these registerswhen PCI auto- initializationisnot used.PCI auto-initializationisenabledby selectingPCI bootwithauto-initialization.For informationon how to selectPCI boot withauto-initialization,see Section4.4.1, Boot Modes. For more informationon PCI auto-initialization,see the TMS320DM646x DMSoC PeripheralComponent Interconnect(PCI) User'sGuide (literaturenumber SPRUER2 ) and the Using the TMIS320DM646x BootloaderApplicationReport(literaturenumber SPRAAS0 ). The PCI peripheralisa masterperipheralwithintheDM6467 DMSoC. Table7-61.DefaultValues forPCI ConfigurationRegisters REGISTER DEFAULT VALUE (HEX) 0x01C1 A000 — Vendor ID/DeviceID Register(PCIVENDEV) B002 104Ch DeviceID B002h Vendor ID 104Ch 0x01C1 A008 — Class Code/RevisionID Register(PCICLREV) 1180 0001h ClassCode 80h RevisionID 01h 0x01C1 A02C — System Vendor ID/Subsystem ID (PCISUBID) 0000 0000h Subsystem ID 0000 System Vendor ID 0000 0x01C1 A03C — Max Latency/MinGrant/InterruptPin/InterruptLine 0000 0100h Max Latency 00 Min Grant 00 InterruptPin 01 InterruptLine 00 The on-chipBootloadersupportsa hostbootwhichallowsan externalPCI devicetoloadapplicationcode intotheDMSoC's memory space. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 245 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.15.2 PCI ExternalMaster Memory Map

The PCI portincludesa localDMA interfacethatallowsexternalPCI masterdeviceintiatedtransfersto accesstheDM646x systembus.Table7-62shows thememory map forthePCI interface. Table7-62.PCI DMA Master Memory Map SIZESTART ADDRESS END ADDRESS PCI DMA ACCESS(BYTES) 0x0000 0000 0x01BF FFFF 28M Reserved 0x01C0 0000 0x0FFF FFFF 228M CFG Bus Peripherals 0x1001 0000 0x1001 3FFF 16K ARM RAM 0 (Data) 0x1001 4000 0x1001 7FFF 16K ARM RAM 1 (Data) 0x1001 8000 0x1001 FFFF 32K ARM ROM (Data) 0x1002 0000 0x10FF FFFF 16256K 0x1100 0000 0x113F FFFF 4M 0x1140 0000 0x114F FFFF 1M 0x1150 0000 0x115F FFFF 1M Reserved 0x1160 0000 0x116F FFFF 1M 0x1170 0000 0x117F FFFF 1M 0x1180 0000 0x1180 FFFF 64K 0x1181 0000 0x1181 7FFF 32K 0x1181 8000 0x1183 7FFF 128K C64x+ L2 RAM/Cache 0x1183 8000 0x118F FFFF 800K Reserved 0x1190 0000 0x11DF FFFF 5M 0x11E0 0000 0x11E0 7FFF 32K C64x+ L1P RAM/Cache 0x11E0 8000 0x11EF FFFF 992K Reserved 0x11F0 0000 0x11F0 7FFF 32K C64x+ L1D RAM/Cache 0x11F0 8000 0x11FF FFFF 992K Reserved 0x1200 0000 0x4BFF FFFF 928M 0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) 0x5000 0000 0x7FFF FFFF 768M Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved

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7.15.3 PCI PeripheralRegisterDescription(s)

Table7-63.PCI Back End ConfigurationRegisters DMSoC ACCESS ACRONYM DMSoC ACCESS REGISTER NAMEHEX ADDRESS RANGE 01C1 A000 -01C1 A00F - Reserved 01C1 A010 PCISTATSET PCI StatusSetRegister 01C1 A014 PCISTATCLR PCI StatusClearRegister 01C1 A018 -01C1 A01F - Reserved 01C1 A020 PCIHINTSET PCI HostInterruptEnableSetRegister 01C1 A024 PCIHINTCLR PCI HostInterruptEnableClearRegister 01C1 A028 -01C1 A02F - Reserved 01C1 A030 PCIBINTSET PCI Back End ApplicationInterruptEnableSetRegister 01C1 A034 PCIBINTCLR PCI Back End ApplicationInterruptEnableClearRegister 01C1 A038 - Reserved 01C1 A03C -01C1 A0FF - Reserved 01C1 A100 PCIVENDEVMIR PCI Vendor ID/DeviceID MirrorRegister 01C1 A104 PCICSRMIR PCI Command/Status MirrorRegister 01C1 A108 PCICLREVMIR PCI ClassCode/RevisionID MirrorRegister 01C1 A10C PCICLINEMIR PCI BIST/HeaderType/LatencyTimer/CachelineSizeMirrorRegister 01C1 A110 PCIBAR0MSK PCI Base AddressMask Register0 01C1 A114 PCIBAR1MSK PCI Base AddressMask Register1 01C1 A118 PCIBAR2MSK PCI Base AddressMask Register2 01C1 A11C PCIBAR3MSK PCI Base AddressMask Register3 01C1 A120 PCIBAR4MSK PCI Base AddressMask Register4 01C1 A124 PCIBAR5MSK PCI Base AddressMask Register5 01C1 A128 -01C1 A12B - Reserved 01C1 A12C PCISUBIDMIR PCI Subsystem Vendor ID/SubsystemID MirrorRegister 01C1 A130 - Reserved 01C1 A134 PCICPBPTRMIR PCI CapabilitiesPointerMirrorRegister 01C1 A138 -01C1 A13B - Reserved 01C1 A13C PCILGINTMIR PCI Max Latency/MinGrant/InterruptPin/InterruptLineMirrorRegister 01C1 A140 -01C1 A17F - Reserved 01C1 A180 PCISLVCNTL PCI SlaveControlRegister 01C1 A184 -01C1 A1BF - Reserved 01C1 A1C0 PCIBAR0TRL PCI SlaveBase Address0 TranslationRegister 01C1 A1C4 PCIBAR1TRL PCI SlaveBase Address1 TranslationRegister 01C1 A1C8 PCIBAR2TRL PCI SlaveBase Address2 TranslationRegister 01C1 A1CC PCIBAR3TRL PCI SlaveBase Address3 TranslationRegister 01C1 A1D0 PCIBAR4TRL PCI SlaveBase Address4 TranslationRegister 01C1 A1D4 PCIBAR5TRL PCI SlaveBase Address5 TranslationRegister 01C1 A1D8 -01C1 A1DF - Reserved 01C1 A1E0 PCIBAR0MIR PCI Base AddressRegister0 MirrorRegister 01C1 A1E4 PCIBAR1MIR PCI Base AddressRegister1 MirrorRegister 01C1 A1E8 PCIBAR2MIR PCI Base AddressRegister2 MirrorRegister 01C1 A1EC PCIBAR3MIR PCI Base AddressRegister3 MirrorRegister 01C1 A1F0 PCIBAR4MIR PCI Base AddressRegister4 MirrorRegister 01C1 A1F4 PCIBAR5MIR PCI Base AddressRegister5 MirrorRegister 01C1 A1F8 -01C1 A2FF - Reserved 01C1 A300 PCIMCFGDAT PCI MasterConfiguration/IOAccess Data Register Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 247 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-63.PCI Back End ConfigurationRegisters(continued) DMSoC ACCESS ACRONYM DMSoC ACCESS REGISTER NAMEHEX ADDRESS RANGE 01C1 A304 PCIMCFGADR PCI MasterConfiguration/IOAccess AddressRegister 01C1 A308 PCIMCFGCMD PCI MasterConfiguration/IOAccess Command Register 01C1 A30C -01C1 A30F - Reserved 01C1 A310 PCIMSTCFG PCI MasterConfigurationRegister Table7-64.DMSoC-to-PCI Address TranslationRegisters DMSoC ACCESS ACRONYM DMSoC ACCESS REGISTER NAMEHEX ADDRESS RANGE 01C1 A314 PCIADDSUB0 PCI AddressSubstitute0 Register 01C1 A318 PCIADDSUB1 PCI AddressSubstitute1 Register 01C1 A31C PCIADDSUB2 PCI AddressSubstitute2 Register 01C1 A320 PCIADDSUB3 PCI AddressSubstitute3 Register 01C1 A324 PCIADDSUB4 PCI AddressSubstitute4 Register 01C1 A328 PCIADDSUB5 PCI AddressSubstitute5 Register 01C1 A32C PCIADDSUB6 PCI AddressSubstitute6 Register 01C1 A330 PCIADDSUB7 PCI AddressSubstitute7 Register 01C1 A334 PCIADDSUB8 PCI AddressSubstitute8 Register 01C1 A338 PCIADDSUB9 PCI AddressSubstitute9 Register 01C1 A33C PCIADDSUB10 PCI AddressSubstitute10 Register 01C1 A340 PCIADDSUB11 PCI AddressSubstitute11 Register 01C1 A344 PCIADDSUB12 PCI AddressSubstitute12 Register 01C1 A348 PCIADDSUB13 PCI AddressSubstitute13 Register 01C1 A34C PCIADDSUB14 PCI AddressSubstitute14 Register 01C1 A350 PCIADDSUB15 PCI AddressSubstitute15 Register 01C1 A354 PCIADDSUB16 PCI AddressSubstitute16 Register 01C1 A358 PCIADDSUB17 PCI AddressSubstitute17 Register 01C1 A35C PCIADDSUB18 PCI AddressSubstitute18 Register 01C1 A360 PCIADDSUB19 PCI AddressSubstitute19 Register 01C1 A364 PCIADDSUB20 PCI AddressSubstitute20 Register 01C1 A368 PCIADDSUB21 PCI AddressSubstitute21 Register 01C1 A36C PCIADDSUB22 PCI AddressSubstitute22 Register 01C1 A370 PCIADDSUB23 PCI AddressSubstitute23 Register 01C1 A374 PCIADDSUB24 PCI AddressSubstitute24 Register 01C1 A378 PCIADDSUB25 PCI AddressSubstitute25 Register 01C1 A37C PCIADDSUB26 PCI AddressSubstitute26 Register 01C1 A380 PCIADDSUB27 PCI AddressSubstitute27 Register 01C1 A384 PCIADDSUB28 PCI AddressSubstitute28 Register 01C1 A388 PCIADDSUB29 PCI AddressSubstitute29 Register 01C1 A38C PCIADDSUB30 PCI AddressSubstitute30 Register 01C1 A390 PCIADDSUB31 PCI AddressSubstitute31 Register

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-65.PCI Hook ConfigurationRegisters DMSoC ACCESS ACRONYM DMSoC ACCESS REGISTER NAMEHEX ADDRESS RANGE 01C1 A394 PCIVENDEVPRG PCI Vendor ID and DeviceID Program Register 01C1 A398 – Reserved 01C1 A39C PCICLREVPRG PCI ClassCode and RevisionID Program Register 01C1 A3A0 PCISUBIDPRG PCI Subsystem Vendor ID and Subsystem ID Program Register 01C1 A3A4 PCIMAXLGPRG PCI Max Latencyand Min GrantProgram Register 01C1 A3A8 – Reserved 01C1 A3AC PCICFGDONE PCI ConfigurationDone Register 01C1 A3B0 -01C1 A3FB – Reserved 01C1 A3FC -01C1 A3FF – Reserved 01C1 A400 -01C1 A7FF – Reserved Table7-66.PCI ExternalMemory Space DMSoC HEX ADDRESS ACRONYM DESCRIPTIONRANGE 3000 0000 -307F FFFF – PCI MasterWindow 0 3080 0000 -30FF FFFF – PCI MasterWindow 1 3100 0000 -317F FFFF – PCI MasterWindow 2 3180 0000 -31FF FFFF – PCI MasterWindow 3 3200 0000 -327F FFFF – PCI MasterWindow 4 3280 0000 -32FF FFFF – PCI MasterWindow 5 3300 0000 -337F FFFF – PCI MasterWindow 6 3380 0000 -33FF FFFF – PCI MasterWindow 7 3400 0000 -347F FFFF – PCI MasterWindow 8 3480 0000 -34FF FFFF – PCI MasterWindow 9 3500 0000 -357F FFFF – PCI MasterWindow 10 3580 0000 -35FF FFFF – PCI MasterWindow 11 3600 0000 -367F FFFF – PCI MasterWindow 12 3680 0000 -36FF FFFF – PCI MasterWindow 13 3700 0000 -377F FFFF – PCI MasterWindow 14 3780 0000 -37FF FFFF – PCI MasterWindow 15 3800 0000 -387F FFFF – PCI MasterWindow 16 3880 0000 -38FF FFFF – PCI MasterWindow 17 3900 0000 -397F FFFF – PCI MasterWindow 18 3980 0000 -39FF FFFF – PCI MasterWindow 19 3A00 0000 -3A7F FFFF – PCI MasterWindow 20 3A80 0000 -3AFF FFFF – PCI MasterWindow 21 3B00 0000 -3B7F FFFF – PCI MasterWindow 22 3B80 0000 -3BFF FFFF – PCI MasterWindow 23 3C00 0000 -3C7F FFFF – PCI MasterWindow 24 3C80 0000 -3CFF FFFF – PCI MasterWindow 25 3D00 0000 -3D7F FFFF – PCI MasterWindow 26 3D80 0000 -3DFF FFFF – PCI MasterWindow 27 3E00 0000 -3E7F FFFF – PCI MasterWindow 28 3E80 0000 -3EFF FFFF – PCI MasterWindow 29 3F00 0000 -3F7F FFFF – PCI MasterWindow 30 3F80 0000 -3FFF FFFF – PCI MasterWindow 31 Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 249 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.15.4 PCI ElectricalData/Timing

Texas Instruments(TI)has performedthesimulationand system characterizationtoensurethatthePCI peripheralmeets allAC timingspecificationsas requiredby thePCI LocalBus SpecificationRevision2.3. Therefore,theAC timingspecificationsare not reproducedhere.For more informationon theAC timing specifications,see Section4.2.3,TimingSpecification(33-MHz timing)ofthePCI LocalBus Specification

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7.16 EthernetMAC (EMAC)

The EthernetMedia Access Controller(EMAC) module providesan efficientinterfacebetween the DM6467 and the networkedcommunity.The EMAC supports10Base-T (10 Mbits/second[Mbps]),and 100BaseTX (100 Mbps), ineitherhalf-or full-duplexmode, and 1000BaseT (1000 Mbps) infull-duplex mode, withhardwareflowcontroland quality-of-service(QOS) support. The EMAC controlsthe flowof packetdata from the DM6467 deviceto the PHY. The MDIO module controlsthePHY configurationand statusmonitoring. The EMAC module conformsto the IEEE 802.3-2002standard,describingthe “CarrierSense Multiple Access withCollisionDetection(CSMA/CD) Access Method and PhysicalLayer”specifications.The IEEE 802.3standardhas alsobeen adoptedby ISO/IECand re-designatedas ISO/IEC8802-3:2000(E). Deviatingfrom thisstandard,theEMAC module does notuse theTransmitCoding ErrorsignalMTXER. Insteadofdrivingtheerrorpinwhen an underflowconditionoccurson a transmittedframe,theEMAC will intentionallygeneratean incorrectchecksum by invertingthe frame CRC, so thatthe transmittedframe willbe detectedas an errorby the network.In addition,the EMAC I/Osoperateat 3.3 V and are not compatiblewith2.5-VI/Osignaling.Therefore,onlyEthernetPHYs with3.3-VI/Ointerfaceshouldbe used. BoththeEMAC and MDIO modules interfacetotheDM6467 devicethrougha custom interfacethatallows efficientdata transmissionand reception.This custom interfaceis referredto as the EMAC control module. The EMAC controlmodule containsthe necessarycomponents to allowthe EMAC to make efficientuse ofdevicememory, plusitcontrolsdeviceinterrupts.The EMAC controlmodule incorporates 8K bytesofinternalRAM toholdEMAC bufferdescriptors. For more detailedinformationon the EMAC, see the TMS320DM646x DMSoC EthernetMedia Access Controller(EMAC)/Management Data Input/Output(MDIO) Module User's Guide (literaturenumber SPRUEQ6 ).

7.16.1 EMAC Device-SpecificInformation

The EMAC module on theDM6467 supportstwo interfacemodes: Media IndependentInterface(MII)and GigabitMedia IndependentInterface(GMII).The MIIand GMII interfacemodes are definedintheIEEE 802.3-2002standard. The DM6467 EMAC uses thesame pinsfortheMIIand GMII modes ofoperation.Only one mode can be used ata time.The mode used isselectedatdeviceresetbased on theGMIIEN bitintheMACCONTROL register.For more detailedinformationon the EMAC GMIIEN bit,see the TMS320DM646x DMSoC EthernetMedia Access Controller(EMAC)/Management Data Input/Output(MDIO) Module User'sGuide (literaturenumber SPRUEQ6 ). The MIIand GMII modes-of-operationpinsareas follows:

MII:MTCLK, MRCLK, MTXD[3:0],MRXD[3:0],MTXEN, MRXDV, MRXER, MCOL, MCRS, MDCLK, and MDIO.
GMII: RFTCLK, GMTCLK, MTCLK, MRCLK, MTXD[7:0],MRXD[7:0], MTXEN, MRXDV, MRXER, MCOL, MCRS, MDCLK, and MDIO. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 251 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.16.2 EMAC Bus Master Memory Map

The EMAC controlmodule includesa multi-channelDMA enginewhich isused to transferreceiveand transmitpacketsbetween theEMAC and DM6467 memory. Table7-67 shows thememory map forthe EMAC DMA. Table7-67.EMAC DMA Master Memory Map SIZESTART ADDRESS END ADDRESS EMAC DMA ACCESS(BYTES) 0x0000 0000 0x3FFF FFFF 1G Reserved 0x4000 0000 0x4BFF FFFF 192M Reserved 0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) 0x5000 0000 0x7FFF FFFF 768M Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved

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7.16.3 EMAC PeripheralRegisterDescription(s)

Table7-68.EthernetMAC (EMAC) ControlRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 0000 TXIDVER Transmitidentificationand versionregister 0x01C8 0004 TXCONTROL Transmitcontrolregister 0x01C8 0008 TXTEARDOWN Transmitteardownregister 0x01C8 000C -0x01C8 000F – Reserved 0x01C8 0010 RXIDVER Receiveidentificationand versionregister 0x01C8 0014 RXCONTROL Receivecontrolregister 0x01C8 0018 RXTEARDOWN Receiveteardownregister 0x01C8 001C -0x01C8 007F – Reserved 0x01C8 0080 TXINTSTATRAW Transmitinterruptstatus(unmasked)register 0x01C8 0084 TXINTSTATMASKED Transmitinterruptstatus(masked)register 0x01C8 0088 TXINTMASKSET Transmitinterruptmask setregister 0x01C8 008C TXINTMASKCLEAR Transmitinterruptmask clearregister 0x01C8 0090 MACINVECTOR MAC inputvectorregister 0x01C8 0094 MACEOIVECTOR MAC end ofinterruptvectorregister 0x01C8 0098 -0x01C8 009F – Reserved 0x01C8 00A0 RXINTSTATRAW Receiveinterruptstatus(unmasked)register 0x01C8 00A4 RXINTSTATMASKED Receiveinterruptstatus(masked)register 0x01C8 00A8 RXINTMASKSET Receiveinterruptmask setregister 0x01C8 00AC RXINTMASKCLEAR Receiveinterruptmask clearregister 0x01C8 00B0 MACINTSTATRAW MAC interruptstatus(unmasked)register 0x01C8 00B4 MACINTSTATMASKED MAC interruptstatus(masked)register 0x01C8 00B8 MACINTMASKSET MAC interruptmask setregister 0x01C8 00BC MACINTMASKCLEAR MAC interruptmask clearregister 0x01C8 00C0 -0x01C8 00FF – Reserved 0x01C8 0100 RXMBPENABLE Receivemulticast/broadcast/promiscuouschannelenableregister 0x01C8 0104 RXUNICASTSET Receiveunicastenablesetregister 0x01C8 0108 RXUNICASTCLEAR Receiveunicastclearregister 0x01C8 010C RXMAXLEN Receivemaximum lengthregister 0x01C8 0110 RXBUFFEROFFSET Receivebufferoffsetregister 0x01C8 0114 RXFILTERLOWTHRESH Receivefilterlowpriorityframethresholdregister 0x01C8 0118 -0x01C8 011F – Reserved 0x01C8 0120 RX0FLOWTHRESH Receivechannel0 flowcontrolthresholdregister 0x01C8 0124 RX1FLOWTHRESH Receivechannel1 flowcontrolthresholdregister 0x01C8 0128 RX2FLOWTHRESH Receivechannel2 flowcontrolthresholdregister 0x01C8 012C RX3FLOWTHRESH Receivechannel3 flowcontrolthresholdregister 0x01C8 0130 RX4FLOWTHRESH Receivechannel4 flowcontrolthresholdregister 0x01C8 0134 RX5FLOWTHRESH Receivechannel5 flowcontrolthresholdregister 0x01C8 0138 RX6FLOWTHRESH Receivechannel6 flowcontrolthresholdregister 0x01C8 013C RX7FLOWTHRESH Receivechannel7 flowcontrolthresholdregister 0x01C8 0140 RX0FREEBUFFER Receivechannel0 freebuffercountregister 0x01C8 0144 RX1FREEBUFFER Receivechannel1 freebuffercountregister 0x01C8 0148 RX2FREEBUFFER Receivechannel2 freebuffercountregister 0x01C8 014C RX3FREEBUFFER Receivechannel3 freebuffercountregister 0x01C8 0150 RX4FREEBUFFER Receivechannel4 freebuffercountregister 0x01C8 0154 RX5FREEBUFFER Receivechannel5 freebuffercountregister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 253 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-68.EthernetMAC (EMAC) ControlRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 0158 RX6FREEBUFFER Receivechannel6 freebuffercountregister 0x01C8 015C RX7FREEBUFFER Receivechannel7 freebuffercountregister 0x01C8 0160 MACCONTROL MAC controlregister 0x01C8 0164 MACSTATUS MAC statusregister 0x01C8 0168 EMCONTROL Emulationcontrolregister 0x01C8 016C FIFOCONTROL FIFO controlregister(transmitand receive) 0x01C8 0170 MACCONFIG MAC configurationregister 0x01C8 0174 SOFTRESET Softresetregister 0x01C8 0178 -0x01C8 01CF – Reserved 0x01C8 01D0 MACSRCADDRLO MAC sourceaddresslowbytesregister(lower16-bits) 0x01C8 01D4 MACSRCADDRHI MAC sourceaddresshighbytesregister(upper32-bits) 0x01C8 01D8 MACHASH1 MAC hash addressregister1 0x01C8 01DC MACHASH2 MAC hash addressregister2 0x01C8 01E0 BOFFTEST Back offtestregister 0x01C8 01E4 TPACETEST Transmitpacingalgorithmtestregister 0x01C8 01E8 RXPAUSE Receivepause timerregister 0x01C8 01EC TXPAUSE Transmitpause timerregister 0x01C8 01F0 -0x01C8 01FF – Reserved 0x01C8 0200 -0x01C8 02FF (seeTable7-69) EMAC statisticsregisters 0x01C8 0300 -0x01C8 04FF – Reserved 0x01C8 0500 MACADDRLO MAC addresslowbytesregister(usedinreceiveaddressmatching) 0x01C8 0504 MACADDRHI MAC addresshighbytesregister(usedinreceiveaddressmatching) 0x01C8 0508 MACINDEX MAC indexregister 0x01C8 050C -0x01C8 05FF – Reserved 0x01C8 0600 TX0HDP Transmitchannel0 DMA head descriptorpointerregister 0x01C8 0604 TX1HDP Transmitchannel1 DMA head descriptorpointerregister 0x01C8 0608 TX2HDP Transmitchannel2 DMA head descriptorpointerregister 0x01C8 060C TX3HDP Transmitchannel3 DMA head descriptorpointerregister 0x01C8 0610 TX4HDP Transmitchannel4 DMA head descriptorpointerregister 0x01C8 0614 TX5HDP Transmitchannel5 DMA head descriptorpointerregister 0x01C8 0618 TX6HDP Transmitchannel6 DMA head descriptorpointerregister 0x01C8 061C TX7HDP Transmitchannel7 DMA head descriptorpointerregister 0x01C8 0620 RX0HDP Receivechannel0 DMA head descriptorpointerregister 0x01C8 0624 RX1HDP Receivechannel1 DMA head descriptorpointerregister 0x01C8 0628 RX2HDP Receivechannel2 DMA head descriptorpointerregister 0x01C8 062C RX3HDP Receivechannel3 DMA head descriptorpointerregister 0x01C8 0630 RX4HDP Receivechannel4 DMA head descriptorpointerregister 0x01C8 0634 RX5HDP Receivechannel5 DMA head descriptorpointerregister 0x01C8 0638 RX6HDP Receivechannel6 DMA head descriptorpointerregister 0x01C8 063C RX7HDP Receivechannel7 DMA head descriptorpointerregister Transmitchannel0 completionpointer(interruptacknowledge)0x01C8 0640 TX0CP register Transmitchannel1 completionpointer(interruptacknowledge)0x01C8 0644 TX1CP register Transmitchannel2 completionpointer(interruptacknowledge)0x01C8 0648 TX2CP register Transmitchannel3 completionpointer(interruptacknowledge)0x01C8 064C TX3CP register

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-68.EthernetMAC (EMAC) ControlRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME Transmitchannel4 completionpointer(interruptacknowledge)0x01C8 0650 TX4CP register Transmitchannel5 completionpointer(interruptacknowledge)0x01C8 0654 TX5CP register Transmitchannel6 completionpointer(interruptacknowledge)0x01C8 0658 TX6CP register Transmitchannel7 completionpointer(interruptacknowledge)0x01C8 065C TX7CP register Receivechannel0 completionpointer(interruptacknowledge)0x01C8 0660 RX0CP register Receivechannel1 completionpointer(interruptacknowledge)0x01C8 0664 RX1CP register Receivechannel2 completionpointer(interruptacknowledge)0x01C8 0668 RX2CP register Receivechannel3 completionpointer(interruptacknowledge)0x01C8 066C RX3CP register Receivechannel4 completionpointer(interruptacknowledge)0x01C8 0670 RX4CP register Receivechannel5 completionpointer(interruptacknowledge)0x01C8 0674 RX5CP register Receivechannel6 completionpointer(interruptacknowledge)0x01C8 0678 RX6CP register Receivechannel7 completionpointer(interruptacknowledge)0x01C8 067C RX7CP register 0x01C8 0680 -0x01C8 07FF – Reserved Table7-69.EMAC StatisticsRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 0200 RXGOODFRAMES Good receiveframesregister Broadcastreceiveframesregister0x01C8 0204 RXBCASTFRAMES (Totalnumber ofgood broadcastframesreceived) Multicastreceiveframesregister0x01C8 0208 RXMCASTFRAMES (Totalnumber ofgood multicastframesreceived) 0x01C8 020C RXPAUSEFRAMES Pause receiveframesregister ReceiveCRC errorsregister0x01C8 0210 RXCRCERRORS (Totalnumber offramesreceivedwithCRC errors) Receivealignment/codeerrorsregister0x01C8 0214 RXALIGNCODEERRORS (Totalnumber offramesreceivedwithalignment/codeerrors) Receiveoversizedframesregister0x01C8 0218 RXOVERSIZED (Totalnumber ofoversizedframesreceived) Receivejabberframesregister0x01C8 021C RXJABBER (Totalnumber ofjabberframesreceived) Receiveundersizedframesregister0x01C8 0220 RXUNDERSIZED (Totalnumber ofundersizedframesreceived) 0x01C8 0224 RXFRAGMENTS ReceiveFrame FragmentsRegister 0x01C8 0228 RXFILTERED Filteredreceiveframesregister 0x01C8 022C RXQOSFILTERED ReceivedQOS filteredframesregister Receiveoctetframesregister0x01C8 0230 RXOCTETS (Totalnumber ofreceivedbytesingood frames) Good TransmitFrames Register0x01C8 0234 TXGOODFRAMES (Totalnumber ofgood framestransmitted) 0x01C8 0238 TXBCASTFRAMES Broadcasttransmitframesregister 0x01C8 023C TXMCASTFRAMES Multicasttransmitframesregister 0x01C8 0240 TXPAUSEFRAMES Pause transmitframesregister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 255 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-69.EMAC StatisticsRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 0244 TXDEFERRED Deferredtransmitframesregister 0x01C8 0248 TXCOLLISION Transmitcollisionframesregister 0x01C8 024C TXSINGLECOLL Transmitsinglecollisionframesregister 0x01C8 0250 TXMULTICOLL Transmitmultiplecollisionframesregister 0x01C8 0254 TXEXCESSIVECOLL Transmitexcessivecollisionframesregister 0x01C8 0258 TXLATECOLL Transmitlatecollisionframesregister 0x01C8 025C TXUNDERRUN Transmitunderrunerrorregister 0x01C8 0260 TXCARRIERSENSE Transmitcarriersense errorsregister 0x01C8 0264 TXOCTETS Transmitoctetframesregister 0x01C8 0268 FRAME64 Transmitand receive64 octetframesregister 0x01C8 026C FRAME65T127 Transmitand receive65 to127 octetframesregister 0x01C8 0270 FRAME128T255 Transmitand receive128 to255 octetframesregister 0x01C8 0274 FRAME256T511 Transmitand receive256 to511 octetframesregister 0x01C8 0278 FRAME512T1023 Transmitand receive512 to1023 octetframesregister 0x01C8 027C FRAME1024TUP Transmitand receive1024 to1518 octetframesregister 0x01C8 0280 NETOCTETS Networkoctetframesregister 0x01C8 0284 RXSOFOVERRUNS ReceiveFIFO orDMA startofframeoverrunsregister 0x01C8 0288 RXMOFOVERRUNS ReceiveFIFO orDMA middleofframeoverrunsregister 0x01C8 028C RXDMAOVERRUNS ReceiveDMA startofframeand middleofframeoverrunsregister 0x01C8 0290 -0x01C8 02FF – Reserved Table7-70.EMAC ControlModule Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 1000 CMIDVER Identificationand versionregister 0x01C8 1004 CMSOFTRESET Softwareresetregister 0x01C8 1008 CMEMCONTROL Emulationcontrolregister 0x01C8 100C CMINTCTRL Interruptcontrolregister 0x01C8 1010 CMRXTHRESHINTEN Receivethresholdinterruptenableregister 0x01C8 1014 CMRXINTEN Receiveinterruptenableregister 0x01C8 1018 CMTXINTEN Transmitinterruptenableregister 0x01C8 101C CMMISCINTEN Miscellaneousinterruptenableregister 0x01C8 1020 -0x01C8 103F – Reserved 0x01C8 1040 CMRXTHRESHINTSTAT Receivethresholdinterruptstatusregister 0x01C8 1044 CMRXINTSTAT Receiveinterruptstatusregister 0x01C8 1048 CMTXINTSTAT Transmitinterruptstatusregister 0x01C8 104C CMMISCINTSTAT Miscellaneousinterruptstatusregister 0x01C8 1050 -0x01C8 106F – Reserved 0x01C8 1070 CMRXINTMAX Receiveinterruptspermillisecondregister 0x01C8 1074 CMTXINTMAX Transmitinterruptspermillisecondregister 0x01C8 1078 -0x01C8 10FF – Reserved 0x01C8 1100 -0x01C8 1FFF – Reserved Table7-71.EMAC DescriptorMemory HEX ADDRESS RANGE ACRONYM DESCRIPTION 0x01C8 2000 -0x01C8 3FFF – EMAC ControlModule DescriptorMemory

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(Input) 2 3 MRCLK (Input) 2 3 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012

7.16.4 EMAC ElectricalData/Timing

Table7-72.Timing Requirements forMRCLK -MIIand GMII Operation(seeFigure7-50) -594,-729 1000 MbpsNO. 100 Mbps 10 Mbps UNIT(GMIIOnly) MIN MAX MIN MAX MIN MAX 1 tc(MRCLK) Cycletime,MRCLK 8 40 400 ns 2 tw(MRCLKH) Pulseduration,MRCLK high 2.8 14 140 ns 3 tw(MRCLKL) Pulseduration,MRCLK low 2.8 14 140 ns 4 tt(MRCLK) Transitiontime,MRCLK 1 3 3 ns Figure7-50.MRCLK Timing (EMAC – Receive)[MIIand GMII Operation] Table7-73.Timing Requirements forMTCLK -MIIand GMII Operation(seeFigure7-51) -594,-729 NO. 100 Mbps 10 Mbps UNIT MIN MAX MIN MAX 1 tc(MTCLK) Cycletime,MTCLK 40 400 ns 2 tw(MTCLKH) Pulseduration,MTCLK high 14 140 ns 3 tw(MTCLKL) Pulseduration,MTCLK low 14 140 ns 4 tt(MTCLK) Transitiontime,MTCLK 3 3 ns Figure7-51.MTCLK Timing (EMAC – Transmit)[MIIand GMII Operation] Table7-74.Timing Requirements forRFTCLK -GMII Operation(seeFigure7-52) -594,-729 NO. 1000 Mbps UNIT MIN MAX 1 tc(RFTCLK) Cycletime,RFTCLK 8 ns 2 tw(RFTCLKH) Pulseduration,RFTCLK high 2.8 ns 3 tw(RFTCLKL) Pulseduration,RFTCLK low 2.8 ns 4 tt(RFTCLK) Transitiontime,RFTCLK 1 ns Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 257 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

(Input) 2 3 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-52.RFTCLK Timing [GMIIOperation]

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MRCLK (Input) MRXD7−MRXD4(GMII only), MRXD3−MRXD0, MRXDV , MRXER (Inputs) GMTCLK (Output) 2 3 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-75.SwitchingCharacteristicsOver Recommended OperatingConditionsforGMTCLK -GMII Operation(seeFigure7-53) -594,-729 NO. PARAMETER 1000 Mbps UNIT MIN MAX 1 tc(GMTCLK) Cycletime,GMTCLK 8 ns 2 tw(GMTCLKH) Pulseduration,GMTCLK high 2.8 ns 3 tw(GMTCLKL) Pulseduration,GMTCLK low 2.8 ns 4 tt(GMTCLK) Transitiontime,GMTCLK 1 ns Figure7-53.GMTCLK Timing (EMAC – Transmit)[GMIIOperation] Table7-76.Timing Requirements forEMAC MIIand GMII Receive 10/100/1000Mbit/s(1)(seeFigure7-54) -594,-729 NO. 1000 Mbps 100/10Mbps UNIT MIN MAX MIN MAX Setuptime,receiveselectedsignalsvalidbefore1 tsu(MRXD-MRCLKH) 2 8 nsMRCLK high Holdtime,receiveselectedsignalsvalidafter2 th(MRCLKH-MRXD) 0 8 nsMRCLK high (1) ForMII,Receiveselectedsignalsinclude:MRXD[3:0],MRXDV, and MRXER. ForGMII,Receiveselectedsignalsinclude:MRXD[7:0],MRXDV, and MRXER. Figure7-54.EMAC Receive InterfaceTiming [MIIand GMII Operation] Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 259 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

GMTCLK (Output) MTXD7−MTXD0, MTXEN (Outputs) MTCLK (Input) MTXD7−MTXD4(GMII only), MTXD3−MTXD0, MTXEN (Outputs) TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-77.SwitchingCharacteristicsOver Recommended OperatingConditionsforEMAC MIIand GMII Transmit10/100Mbit/s(1)(seeFigure7-55) -594,-729 NO. PARAMETER 100/10Mbps UNIT MIN MAX 1 td(MTCLKH-MTXD) Delaytime,MTCLK hightotransmitselectedsignalsvalid 5 25 ns (1) ForMII,Transmitselectedsignalsinclude:MTXD[3:0]and MTXEN. ForGMII,Transmitselectedsignalsinclude:MTXD[7:0]and MTXEN. Figure7-55.EMAC TransmitInterfaceTiming [MIIand GMII Operation] Table7-78.SwitchingCharacteristicsOver Recommended OperatingConditionsforEMAC GMII Transmit

1000 Mbit/s(1)(seeFigure7-56)

-594,-729 NO. PARAMETER 1000 Mbps UNIT MIN MAX 1 td(GMTCLKH-MTXD) Delaytime,GMTCLK hightotransmitselectedsignalsvalid 0.5 5 ns (1) ForGMII,Transmitselectedsignalsinclude:MTXD[7:0]and MTXEN. Figure7-56.EMAC TransmitInterfaceTiming [GMIIOperation]

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7.17 Management Data Input/Output(MDIO)

The Management Data Input/Output(MDIO) module continuouslypollsall32 MDIO addressesinorderto enumerateallPHY devicesinthesystem. The Management Data Input/Output(MDIO) module implementsthe802.3serialmanagement interfaceto interrogateand controlEthernetPHY(s) usinga shared two-wirebus. Host softwareuses the MDIO module to configurethe auto-negotiationparametersof each PHY attachedto the EMAC, retrievethe negotiationresults,and configurerequiredparametersinthe EMAC module forcorrectoperation.The module is designed to allow almost transparentoperationof the MDIO interface,with very little maintenancefromthecoreprocessor.Onlyone PHY may be connectedatany giventime. For more detailedinformationon theMDIO peripheral,see theTMS320DM646x DMSoC EthernetMedia Access Controller(EMAC)/Management Data Input/Output(MDIO) Module User's Guide (literature number SPRUEQ6 ).For a listofsupportedregistersand registerfields,see Table7-79,MDIO Registers inthisdatamanual.

7.17.1 MDIO PeripheralRegisterDescription(s)

Table7-79.MDIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 4000 VERSION MDIO versionregister 0x01C8 4004 CONTROL MDIO controlregister 0x01C8 4008 ALIVE MDIO PHY alivestatusregister 0x01C8 400C LINK MDIO PHY linkstatusregister 0x01C8 4010 LINKINTRAW MDIO linkstatuschange interrupt(unmasked)register 0x01C8 4014 LINKINTMASKED MDIO linkstatuschange interrupt(masked)register 0x01C8 4018 -0x01C8 401F – Reserved 0x01C8 4020 USERINTRAW MDIO usercommand completeinterrupt(unmasked)register 0x01C8 4024 USERINTMASKED MDIO usercommand completeinterrupt(masked)register 0x01C8 4028 USERINTMASKSET MDIO usercommand completeinterruptmask setregister 0x01C8 402C USERINTMASKCLEAR MDIO usercommand completeinterruptmask clearregister 0x01C8 4030 -0x01C8 407F – Reserved 0x01C8 4080 USERACCESS0 MDIO useraccessregister0 0x01C8 4084 USERPHYSEL0 MDIO userPHY selectregister0 0x01C8 4088 USERACCESS1 MDIO useraccessregister1 0x01C8 408C USERPHYSEL1 MDIO userPHY selectregister1 0x01C8 4090 -0x01C8 47FF – Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 261 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

(output) MDCLK MDIO (input) 3 3 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com

7.17.2 Management Data Input/Output(MDIO) ElectricalData/Timing

Table7-80.Timing Requirements forMDIO Input(seeFigure7-57and Figure7-58) -594,-729 NO. UNIT MIN MAX 1 tc(MDCLK) Cycletime,MDCLK 400 ns 2 tw(MDCLK) Pulseduration,MDCLK high/low 180 ns 3 tt(MDCLK) Transitiontime,MDCLK 5 ns 4 tsu(MDIO-MDCLKH) Setuptime,MDIO datainputvalidbeforeMDCLK high 10 ns 5 th(MDCLKH-MDIO) Holdtime,MDIO datainputvalidafterMDCLK high 0 ns Figure7-57.MDIO InputTiming Table7-81.SwitchingCharacteristicsOver Recommended OperatingConditionsforMDIO Output (seeFigure7-58) -594,-729 NO. PARAMETER UNIT MIN MAX 7 td(MDCLKL-MDIO) Delaytime,MDCLK lowtoMDIO dataoutputvalid 100 ns Figure7-58.MDIO Output Timing

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7.18 Host-PortInterface(HPI)Peripheral

The HPI isa parallelportthroughwhich a hostprocessorcan directlyaccess theCPU memory space. The hostdevicefunctionsas a master to the interface,which increasesease of access.The hostand CPU can exchange informationvia internalor externalmemory. The host also has directaccess to memory-mapped peripherals.Connectivityto the CPU memory space isprovidedthroughthe EDMA3 controller.

7.18.1 HPI Device-SpecificInformation

The DM6467 deviceincludesa user-configurable32-or16-bitHost-portinterface(HPI32/HPI16).

Multiplexed(address/data)operation
Configurablesinglefull-wordcycleand dualhalf-wordcycleaccessmodes
Burstingavailableutilizing8-wordreadand writeFIFOs
HPIA registersupportsauto-incrementing
HPID register/FIFOsprovidingdata-pathbetween externalhostinterfaceand systembus
Multiplestrobesand controlsignalstoallowflexiblehostconnection
ConfigurableasynchronousHRDY outputtoallowHPI toinsertwaitstatestotheHost [SystemModule RegisterHPICTL.HRDYMODE]
SoftwarecontrolofdataprefetchingtotheHPID/FIFOs
DMSoC-to-Hostinterruptoutputsignalcontrolledby HPIC accesses
Host-to-DMSoCinterruptcontrolledby HPIC accesses NOTE: The DM6467 HPI does not supporttheHAS feature.For properHPI operationiftheHAS pin(D4) isroutedout,theHAS pinmust be pulledup viaan externalresistor. The DM6467 HPICTL register(0x01C4 0030) is partof the System Module Registers.The HPICTL registercontrolswriteaccess totheHPI peripheralcontroland addressregistersas wellas determines thehosttime-outvalue.The HPICTL System Module RegisteralsodeterminestheoperationoftheHRDY outputwhichallowstheHPI toinsertwaitstatestotheHost.For more detailedinformationon theHPICTL System Module Register,see Section4.6.2,PeripheralSelectionAfterDeviceReset. For more detailedinformationon theHPI peripheral,see theTMS320DM646x DMSoC Host PortInterface (HPI)User'sGuide (literaturenumber SPRUES1 ).

7.18.2 HPI Bus Master

The HPI peripheralincludesa bus masterinterfacethatallowsexternaldeviceinitiatedtransferstoaccess theDM6467 systembus.Table7-82shows thememory map fortheHPI masterinterface. Table7-82.HPI Master Memory Map SIZESTART ADDRESS END ADDRESS HPI ACCESS(BYTES) 0x0000 0000 0x01BF FFFF 28M Reserved 0x01C0 0000 0x0FFF FFFF 228M CFG Bus Peripherals 0x1000 0000 0x1000 FFFF 64K Reserved 0x1001 0000 0x1001 3FFF 16K ARM RAM 0 (Data) 0x1001 4000 0x1001 7FFF 16K ARM RAM 1 (Data) 0x1001 8000 0x1001 FFFF 32K ARM ROM (Data) Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 263 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-82.HPI Master Memory Map (continued) SIZESTART ADDRESS END ADDRESS HPI ACCESS(BYTES) 0x1002 0000 0x10FF FFFF 16256K 0x1100 0000 0x113F FFFF 4M 0x1140 0000 0x114F FFFF 1M 0x1150 0000 0x115F FFFF 1M Reserved 0x1160 0000 0x116F FFFF 1M 0x1170 0000 0x117F FFFF 1M 0x1180 0000 0x1180 FFFF 64K 0x1181 0000 0x1181 7FFF 32K 0x1181 8000 0x1183 7FFF 128K C64x+ L2 RAM/Cache 0x1183 8000 0x118F FFFF 800K Reserved 0x1190 0000 0x11DF FFFF 5M 0x11E0 0000 0x11E0 7FFF 32K C64x+ L1P RAM/Cache 0x11E0 8000 0x11EF FFFF 992K Reserved 0x11F0 0000 0x11F0 7FFF 32K C64x+ L1D RAM/Cache 0x11F0 8000 0x11FF FFFF 992K Reserved 0x1200 0000 0x4BFF FFFF 928M 0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) 0x5000 0000 0x7FFF FFFF 768M Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved

7.18.3 HPI PeripheralRegisterDescription(s)

Table7-83.HPI ControlRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01C6 7800 PID PeripheralIdentificationRegister The ARM/C64x+ has 01C6 7804 PWREMU_MGMT HPI power and emulationmanagement register read/writeaccesstothe PWREMU_MGMT register. 01C6 7808 -01C6 782F - Reserved The Hostand the ARM/C64x+ bothhave01C6 7830 HPIC HPI controlregister read/writeaccesstothe HPIC register. HPIA HPI addressregister The Hosthas read/write01C6 7834 (HPIAW) (1) (Write) accesstotheHPIA registers. The ARM/C64x+ has only HPIA HPI addressregister readaccesstotheHPIA01C6 7838 (HPIAR)(1) (Read) registers. 01C6 783C -01C6 7FFF - Reserved (1) Therearetwo 32-bitHPIA registers:HPIAR forreadoperationsand HPIAW forwriteoperations.The HPI can be configuredsuch that HPIAR and HPIAW actas a single32-bitHPIA (single-HPIAmode) oras two separate32-bitHPIAs (dual-HPIAmode) fromthe perspectiveoftheHost.The ARM/C64x+ can accessHPIAW and HPIAR independently.Formore detailsabouttheHPIA registersand theirmodes, see theTMS320DM646x DMSoC HostPortInterface(HPI)User's Guide (literaturenumber SPRUES1 ).

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7.18.4 HPI ElectricalData/Timing

Table7-84.Timing Requirements forHost-PortInterfaceCycles(1)(2)(seeFigure7-59through Figure7- 62) -594,-729 NO. UNIT MIN MAX 1 tsu(SELV-HSTBL) Setuptime,selectsignals(3)validbeforeHSTROBE low 5 ns 2 th(HSTBL-SELV) Holdtime,selectsignals(3)validafterHSTROBE low 2 ns 3 tw(HSTBL) Pulseduration,HSTROBE activelow 15 ns 4 tw(HSTBH) Pulseduration,HSTROBE inactivehighbetween consecutiveaccesses 2M ns 11 tsu(HDV-HSTBH) Setuptime,hostdatavalidbeforeHSTROBE high 5 ns 12 th(HSTBH-HDV) Holdtime,hostdatavalidafterHSTROBE high 0.15 ns Holdtime,HSTROBE lowafterHRDY low.HSTROBE shouldnotbe 13 th(HRDYL-HSTBL) inactivateduntilHRDY isactive(low);otherwise,HPI writeswillnot 0 ns completeproperly. (1) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (2) M = SYSCLK3 period= (CPU clockfrequency)/4inns.Forexample,when runningpartsat594 MHz, use M = M = 1.68ns. (3) Selectsignalsinclude:HCNTL[1:0],HR/W. ForHPI16 mode only,selectsignalsalsoincludesHHWIL. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 265 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-85.SwitchingCharacteristicsforHost-PortInterfaceCycles(1)(2)(3) (seeFigure7-59through Figure7-62) -594,-729 NO. PARAMETER UNIT MIN MAX ForHPI Write,HRDY can go high(not ready)fortheseHPI Writeconditions; otherwise,HRDY stayslow(ready): Case 1:Back-to-backHPIA writes(can be eitherfirstorsecond half-word) Case 2:HPIA writefollowinga PREFETCH command (canbe either firstorsecond half-word) Case 3:HPID writewhen FIFO isfull orflushing(canbe eitherfirstor second half-word) Case 4:HPIA writeand WriteFIFO not empty ForHPI Read, HRDY can go high(not ready)fortheseHPI Read conditions: Case 1:HPID read(withauto-Delaytime,HSTROBE lowto5 td(HSTBL-HRDYV) 12 nsincrement)and datanotinRead FIFOHRDY valid (canonlyhappen tofirsthalf-wordof HPID access) Case 2:Firsthalf-wordaccessofHPID Read withoutauto-increment ForHPI Read, HRDY stayslow(ready) fortheseHPI Read conditions: Case 1:HPID readwithauto-increment and dataisalreadyinRead FIFO (appliestoeitherhalf-wordofHPID access) Case 2:HPID readwithoutauto- incrementand dataisalreadyinRead FIFO (alwaysappliestosecond half- word ofHPID access) Case 3:HPIC orHPIA read(appliesto eitherhalf-wordaccess) 6 ten(HSTBL-HD) Enabletime,HD drivenfromHSTROBE low 2 ns 7 td(HRDYL-HDV) Delaytime,HRDY lowtoHD valid 0 ns 8 toh(HSTBH-HDV) Outputholdtime,HD validafterHSTROBE high 1.5 ns 14 tdis(HSTBH-HDV) Disabletime,HD high-impedancefromHSTROBE high 12 ns ForHPI Read. Appliestoconditions where dataisalreadyresidingin HPID/FIFO: Case 1:HPIC orHPIA readDelaytime,HSTROBE lowto15 td(HSTBL-HDV) Case 2:Firsthalf-wordofHPID read 12 nsHD valid withauto-incrementand datais alreadyinRead FIFO Case 3:Second half-wordofHPID readwithorwithoutauto-increment (1) M = SYSCLK3 period= (CPU clockfrequency)/4inns.Forexample,when runningpartsat594 MHz, use M = 1.68ns. (2) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (3) By design,whenever HCS isdriveninactive(high),HPI willdriveHRDY active(low).

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HAS (D) HCNTL[1:0] HR/W HHWIL HSTROBE (A)(C) HD[15:0] (output) HRDY (B) 1st Half-Word 2nd Half-Word A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface (HPI) User’s Guide (literature number SPRUES1). C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by parameters for HSTROBE. D. For proper HPI operation, HAS must be pulled up via an external resistor. TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-59.HPI16 Read Timing (HAS Not Used, TiedHigh) Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 267 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

HAS (D) HCNTL[1:0] HR/W HHWIL HSTROBE (A)(C) HCS HD[15:0] (input) HRDY (B) 2 1 21 1 2 1 2 3 4 3 11 12 11 12 2nd Half-Word1st Half-Word A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface (HPI) User’s Guide (literature number SPRUES1). C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by parameters for HSTROBE. D. For proper HPI operation, HAS must be pulled up via an external resistor. TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-60.HPI16 WriteTiming (HAS Not Used, TiedHigh)

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HCS (input) HAS(D) (Input) HSTROBE(A)(C) (Input) HR/ (Input)W HRDY(B) (output) HD[31:0]□(output) HCNTL[1:0]□□(input) A. refers□to□the□following□logical□operation□on , ,□and :□[NOT( XOR )]□OR .HSTROBE HCS□□HDS1 HDS2 HDS1 HDS2 HCS B. Depending□on□the□type□of□write□or□read□operation□(HPID□without□auto-incrementing;□HPIA,□HPIC,□or□HPID□with□auto- incrementing)□and□the□state□of□the□FIFO,□transitions□on may□or□may□not□occur. For□more□detailed□information□on□the□HPI□peripheral,□see□the User's□Guide (literature□number□SPRUES1). C. reflects□typical behavior□when assertion□is□caused□by or . timing□requirements□are reflected□by□parameters□for . HRDY HCS HCS HSTROBE HDS1 HDS2□□HCS HSTROBE HAS TMS320DM646x□DMSoC□Host□Port□Interface□(HPI) must TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-61.HPI32 Read Timing (HAS Not Used, TiedHigh) Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 269 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

HCS (input) HAS (D) (input) HSTROBE (A)(C) (input) HR/W (input) HRDY (B) (output) HD[31:0] (input) HCNTL[1:0] (input) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface (HPI) User’s Guide (literature number SPRUES1). C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by parameters for HSTROBE. D. For proper HPI operation, HAS must be pulled up via an external resistor. TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-62.HPI32 WriteTiming (HAS Not Used, TiedHigh)

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 7.19 USB 2.0 The DM6467 USB2.0 peripheralsupportsthefollowingfeatures:

USB 2.0peripheralatspeeds highspeed (HS:480 Mb/s)and fullspeed (FS:12 Mb/s)
USB 2.0hostatspeeds HS, FS, and lowspeed (LS:1.5Mb/s)
Each endpoint(otherthan endpoint0) can supportalltransfermodes (control,bulk,interrupt,and isochronous)
4 Transmit(TX)and 4 Receive(RX)endpointsinadditiontoendpoint0
FIFO RAM – 4K endpoint – Programmable size
Connectstoa standardUTMI+ PHY witha 60-MHz, 8-bitinterface
External5-V power supplyforVBUS, when operatingas Host,enableddirectlyby theUSB controller viaa dedicatedsignal
RNDIS mode foracceleratingRNDIS typeprotocolsusingshortpacketterminationoverUSB

7.19.1 USB DMA Master

The USB2.0 peripheralinterfaceincludesa master DMA engine thatallowsthe USB to access the DM6467 systembus.Table7-86shows thememory map fortheUSB2.0 DMA engine. Table7-86.USB2.0 DMA Master Memory Map SIZESTART ADDRESS END ADDRESS USB2.0 DMA ACCESS(BYTES) 0x0000 0000 0x0FFF FFFF 256M Reserved 0x1000 0000 0x1000 FFFF 64K Reserved 0x1001 0000 0x1001 3FFF 16K ARM RAM 0 (Data) 0x1001 4000 0x1001 7FFF 16K ARM RAM 1 (Data) 0x1001 8000 0x1001 FFFF 32K ARM ROM (Data) 0x1002 0000 0x10FF FFFF 16256K 0x1100 0000 0x113F FFFF 4M 0x1140 0000 0x114F FFFF 1M 0x1150 0000 0x115F FFFF 1M Reserved 0x1160 0000 0x116F FFFF 1M 0x1170 0000 0x117F FFFF 1M 0x1180 0000 0x1180 FFFF 64K 0x1181 0000 0x1181 7FFF 32K 0x1181 8000 0x1183 7FFF 128K C64x+ L2 RAM/Cache 0x1183 8000 0x118F FFFF 800K Reserved 0x1190 0000 0x11DF FFFF 5M 0x11E0 0000 0x11E0 7FFF 32K C64x+ L1P RAM/Cache 0x11E0 8000 0x11EF FFFF 992K Reserved 0x11F0 0000 0x11F0 7FFF 32K C64x+ L1D RAM/Cache 0x11F0 8000 0x11FF FFFF 992K Reserved 0x1200 0000 0x4BFF FFFF 928M 0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) 0x5000 0000 0x7FFF FFFF 768M Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 271 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-86.USB2.0 DMA Master Memory Map (continued) SIZESTART ADDRESS END ADDRESS USB2.0 DMA ACCESS(BYTES) 0xC000 0000 0xFFFF FFFF 1G Reserved 7.19.2 USB2.0 Device-SpecificInformation The DM6467 USBCTL register(0x01C4 00034) ispartof the System Module Registers.The USBCTL registercontrolstheUSB datapolarity,host/peripheralmode, and VBUS sense,alongwiththePHY power and clockgood,PHY PLL suspend override,and PHY power down. For more detailedinformationon the USBCTL System Module Register,see Section4.6.2,PeripheralSelectionAfterDeviceReset For more detailedinformationon the USB2.0 peripheral,see the TMS320DM646x DMSoC Universal SerialBus (USB) ControllerUser'sGuide (literaturenumber SPRUER7 ).

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 7.19.3 USB2.0 PeripheralRegisterDescription(s) Table7-87shows theUSB perripheralregistermemory mapping. Table7-87.USB2.0 Registers HEX ADDRESS ACRONYM REGISTER NAMERANGE 0x01C6 4000 REVR RevisionRegister 0x01C6 4004 CTRLR ControlRegister 0x01C6 4008 STATR StatusRegister 0x01C6 400C - Reserved–0x01C6 400F 0x01C6 4010 RNDISR RNDIS Register 0x01C6 4014 AUTOREQ AutoRequestRegister 0x01C6 4018 - Reserved–0x01C6 401F 0x01C6 4020 INTSRCR USB InterruptSourceRegister 0x01C6 4024 INTSETR USB InterruptSourceSetRegister 0x01C6 4028 INTCLRR USB InterruptSourceClearRegister 0x01C6 402C INTMSKR USB InterruptMask Register 0x01C6 4030 INTMSKSETR USB InterruptMask SetRegister 0x01C6 4034 INTMSKCLRR USB InterruptMask ClearRegister 0x01C6 4038 INTMASKEDR USB InterruptSourceMasked Register 0x01C6 403C EOIR USB End ofInterruptRegister 0x01C6 4040 INTVECTR USB InterruptVectorRegister 0x01C6 4044 - Reserved–0x01C6 407F 0x01C6 4080 TCPPICR TX CPPI ControlRegister 0x01C6 4084 TCPPITDR TX CPPI Teardown Register 0x01C6 4088 TCPPIEOIR TX CPPI DMA ControllerEnd ofInterruptRegister 0x01C6 408C TCPPIIVECTR TX CPPI DMA ControllerInterruptVectorRegister 0x01C6 4090 TCPPIMSKSR TX CPPI Masked StatusRegister 0x01C6 4094 TCPPIRAWSR TX CPPI Raw StatusRegister 0x01C6 4098 TCPPIIENSETR TX CPPI InterruptEnableSetRegister 0x01C6 409C TCPPIIENCLRR TX CPPI InterruptEnableClearRegister 0x01C6 40A0 - Reserved–0x01C6 40BF 0x01C6 40C0 RCPPICR RX CPPI ControlRegister 0x01C6 40C4 - Reserved–0x01C6 40CF 0x01C6 40D0 RCPPIMSKSR RX CPPI Masked StatusRegister 0x01C6 40D4 RCPPIRAWSR RX CPPI Raw StatusRegister 0x01C6 40D8 RCPPIENSETR RX CPPI InterruptEnableSetRegister 0x01C6 40DC RCPPIIENCLRR RX CPPI InterruptEnableClearRegister 0x01C6 40E0 RBUFCNT0 RX BufferCount 0 Register 0x01C6 40E4 RBUFCNT1 RX BufferCount 1 Register 0x01C6 40E8 RBUFCNT2 RX BufferCount 2 Register 0x01C6 40EC RBUFCNT3 RX BufferCount 3 Register 0x01C6 40F0 - Reserved–0x01C6 40FF TX/RX CCPI Channel 0 StateBlock 0x01C6 4100 TCPPIDMASTATEW0 TX CPPI DMA StateWord 0 Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 273 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-87.USB2.0 Registers(continued) HEX ADDRESS ACRONYM REGISTER NAMERANGE 0x01C6 4104 TCPPIDMASTATEW1 TX CPPI DMA StateWord 1 0x01C6 4108 TCPPIDMASTATEW2 TX CPPI DMA StateWord 2 0x01C6 410C TCPPIDMASTATEW3 TX CPPI DMA StateWord 3 0x01C6 4110 TCPPIDMASTATEW4 TX CPPI DMA StateWord 4 0x01C6 4114 TCPPIDMASTATEW5 TX CPPI DMA StateWord 5 0x01C6 4118 – Reserved 0x01C6 411C TCPPICOMPPTR TX CPPI CompletionPointer 0x01C6 4120 RCPPIDMASTATEW0 RX CPPI DMA StateWord 0 0x01C6 4124 RCPPIDMASTATEW1 RX CPPI DMA StateWord 1 0x01C6 4128 RCPPIDMASTATEW2 RX CPPI DMA StateWord 2 0x01C6 412C RCPPIDMASTATEW3 RX CPPI DMA StateWord 3 0x01C6 4130 RCPPIDMASTATEW4 RX CPPI DMA StateWord 4 0x01C6 4134 RCPPIDMASTATEW5 RX CPPI DMA StateWord 5 0x01C6 4138 RCPPIDMASTATEW6 RX CPPI DMA StateWord 6 0x01C6 413C RCPPICOMPPTR RX CPPI CompletionPointer TX/RX CCPI Channel 1 StateBlock 0x01C6 4140 TCPPIDMASTATEW0 TX CPPI DMA StateWord 0 0x01C6 4144 TCPPIDMASTATEW1 TX CPPI DMA StateWord 1 0x01C6 4148 TCPPIDMASTATEW2 TX CPPI DMA StateWord 2 0x01C6 414C TCPPIDMASTATEW3 TX CPPI DMA StateWord 3 0x01C6 4150 TCPPIDMASTATEW4 TX CPPI DMA StateWord 4 0x01C6 4154 TCPPIDMASTATEW5 TX CPPI DMA StateWord 5 0x01C6 4158 – Reserved 0x01C6 415C TCPPICOMPPTR TX CPPI CompletionPointer 0x01C6 4160 RCPPIDMASTATEW0 RX CPPI DMA StateWord 0 0x01C6 4164 RCPPIDMASTATEW1 RX CPPI DMA StateWord 1 0x01C6 4168 RCPPIDMASTATEW2 RX CPPI DMA StateWord 2 0x01C6 416C RCPPIDMASTATEW3 RX CPPI DMA StateWord 3 0x01C6 4170 RCPPIDMASTATEW4 RX CPPI DMA StateWord 4 0x01C6 4174 RCPPIDMASTATEW5 RX CPPI DMA StateWord 5 0x01C6 4178 RCPPIDMASTATEW6 RX CPPI DMA StateWord 6 0x01C6 417C RCPPICOMPPTR RX CPPI CompletionPointer TX/RX CCPI Channel 2 StateBlock 0x01C6 4180 TCPPIDMASTATEW0 TX CPPI DMA StateWord 0 0x01C6 4184 TCPPIDMASTATEW1 TX CPPI DMA StateWord 1 0x01C6 4188 TCPPIDMASTATEW2 TX CPPI DMA StateWord 2 0x01C6 418C TCPPIDMASTATEW3 TX CPPI DMA StateWord 3 0x01C6 4190 TCPPIDMASTATEW4 TX CPPI DMA StateWord 4 0x01C6 4194 TCPPIDMASTATEW5 TX CPPI DMA StateWord 5 0x01C6 4198 – Rserved 0x01C6 419C TCPPICOMPPTR TX CPPI CompletionPointer 0x01C6 41A0 RCPPIDMASTATEW0 RX CPPI DMA StateWord 0 0x01C6 41A4 RCPPIDMASTATEW1 RX CPPI DMA StateWord 1 0x01C6 41A8 RCPPIDMASTATEW2 RX CPPI DMA StateWord 2 0x01C6 41AC RCPPIDMASTATEW3 RX CPPI DMA StateWord 3 0x01C6 41B0 RCPPIDMASTATEW4 RX CPPI DMA StateWord 4 0x01C6 41B4 RCPPIDMASTATEW5 RX CPPI DMA StateWord 5

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-87.USB2.0 Registers(continued) HEX ADDRESS ACRONYM REGISTER NAMERANGE 0x01C6 41B8 RCPPIDMASTATEW6 RX CPPI DMA StateWord 6 0x01C6 41BC RCPPICOMPPTR RX CPPI CompletionPointer TX/RX CCPI Channel 3 StateBlock 0x01C6 41C0 TCPPIDMASTATEW0 TX CPPI DMA StateWord 0 0x01C6 41C4 TCPPIDMASTATEW1 TX CPPI DMA StateWord 1 0x01C6 41C8 TCPPIDMASTATEW2 TX CPPI DMA StateWord 2 0x01C6 41CC TCPPIDMASTATEW3 TX CPPI DMA StateWord 3 0x01C6 41D0 TCPPIDMASTATEW4 TX CPPI DMA StateWord 4 0x01C6 41D4 TCPPIDMASTATEW5 TX CPPI DMA StateWord 5 0x01C6 41D8 – Rserved 0x01C6 41DC TCPPICOMPPTR TX CPPI CompletionPointer 0x01C6 41E0 RCPPIDMASTATEW0 RX CPPI DMA StateWord 0 0x01C6 41E4 RCPPIDMASTATEW1 RX CPPI DMA StateWord 1 0x01C6 41E8 RCPPIDMASTATEW2 RX CPPI DMA StateWord 2 0x01C6 41EC RCPPIDMASTATEW3 RX CPPI DMA StateWord 3 0x01C6 41F0 RCPPIDMASTATEW4 RX CPPI DMA StateWord 4 0x01C6 41F4 RCPPIDMASTATEW5 RX CPPI DMA StateWord 5 0x01C6 41F8 RCPPIDMASTATEW6 RX CPPI DMA StateWord 6 0x01C6 41FC RCPPICOMPPTR RX CPPI CompletionPointer 0x01C6 4200 - Reserved–0x01C6 43FF Core Registers 0x01C6 4400 FADDR FunctionAddressRegister 0x01C6 4401 POWER Power Management Register 0x01C6 4402 INTRTX InterruptRegisterforEndpoint0 plusTX Endpoints1 to4 0x01C6 4404 INTRRX InterruptRegisterforRX Endpoints1 to4 0x01C6 4406 INTRTXE InterruptEnableRegisterforINTRTX 0x01C6 4408 INTRRXE InterruptEnableRegisterforINTRRX 0x01C6 440A INTRUSB InterruptRegisterforCommon USB Interrupts 0x01C6 440B INTRUSBE InterruptEnableRegisterforINTRUSB 0x01C6 440C FRAME Frame Number Register 0x01C6 440E INDEX Indexregisterforselectingtheendpointstatusand controlregisters 0x01C6 440F TESTMODE RegistertoenabletheUSB 2.0testmodes Maximum packetsizeforperipheral/hostTX endpoint(Indexregistersettoselect0x01C6 4410 TXMAXP Endpoints1 -4 only) ControlStatusregisterforEndpoint0 inPeripheralmode. (IndexregistersettoPERI_CSR0 selectEndpoint0) ControlStatusregisterforEndpoint0 inHostmode. (IndexregistersettoselectHOST_CSR0 Endpoint0) 0x01C6 4412 ControlStatusregisterforperipheralTX endpoint.(IndexregistersettoselectPERI_TXCSR Endpoints1 -4) ControlStatusregisterforhostTX endpoint.(IndexregistersettoselectHOST_TXCSR Endpoints1 -4) Maximum packetsizeforperipheral/hostRX endpoint(Indexregistersettoselect0x01C6 4414 RXMAXP Endpoints1 -4 only) ControlStatusregisterforperipheralRX endpoint.(IndexregistersettoselectPERI_RXCSR Endpoints1 -4) 0x01C6 4416 ControlStatusregisterforhostRX endpoint.(IndexregistersettoselectHOST_RXCSR Endpoints1 -4) Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 275 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-87.USB2.0 Registers(continued) HEX ADDRESS ACRONYM REGISTER NAMERANGE Number ofreceivedbytesinEndpoint0 FIFO.(IndexregistersettoselectCOUNT0 Endpoint0) 0x01C6 4418 Number ofbytesinhostRX endpointFIFO.(IndexregistersettoselectRXCOUNT Endpoints1 -4) 0x01C6 441A HOST_TYPE0 Definesthespeed ofEndpoint0 Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 441A HOST_TXTYPE forthehostTX endpoint.(IndexregistersettoselectEndpoints1 -4 only) SetstheNAK responsetimeouton Endpoint0.(Indexregistersettoselect0x01C6 441B HOST_NAKLIMIT0 Endpoint0) SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response 0x01C6 441B HOST_TXINTERVAL timeouton BulktransactionsforhostTX endpoint.(Indexregistersettoselect Endpoints1 -4 only) Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 441C HOST_RXTYPE forthehostRX endpoint.(IndexregistersettoselectEndpoints1 -4 only) SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response 0x01C6 441D HOST_RXINTERVAL timeouton BulktransactionsforhostRX endpoint.(Indexregistersettoselect Endpoints1 -4 only) 0x01C6 441F CONFIGDATA Returnsdetailsofcoreconfiguration(IndexregistersettoselectEndpoint0) 0x01C6 4420 FIFO0 TX and RX FIFO RegisterforEndpoint0 0x01C6 4424 FIFO1 TX and RX FIFO RegisterforEndpoint1 0x01C6 4428 FIFO2 TX and RX FIFO RegisterforEndpoint2 0x01C6 442C FIFO3 TX and RX FIFO RegisterforEndpoint3 0x01C6 4430 FIFO4 TX and RX FIFO RegisterforEndpoint4 0x01C6 4460 DEVCTL DeviceControlRegister 0x01C6 4462 TXFIFOSZ TX EndpointFIFO Size(IndexregistersettoselectEndpoints0 -4 only) 0x01C6 4463 RXFIFOSZ RX EndpointFIFO Size(IndexregistersettoselectEndpoints0 -4 only) 0x01C6 4464 TXFIFOADDR TX EndpointFIFO Address(IndexregistersettoselectEndpoints0 -4 only) 0x01C6 4466 RXFIFOADDR RX EndpointFIFO Address(IndexregistersettoselectEndpoints0 -4 only) TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG0 Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX0x01C6 4480 TXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. 0x01C6 4482 TXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This 0x01C6 4483 TXHUBPORT isused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX0x01C6 4484 RXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 4486 RXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 4487 RXHUBPORT Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG1 Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX0x01C6 4488 TXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. 0x01C6 448A TXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This 0x01C6 448B TXHUBPORT isused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-87.USB2.0 Registers(continued) HEX ADDRESS ACRONYM REGISTER NAMERANGE Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX0x01C6 448C RXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 448E RXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 highspeed hub Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 448F RXHUBPORT Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG2 Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX0x01C6 4490 TXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. 0x01C6 4492 TXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This 0x01C6 4493 TXHUBPORT isused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX0x01C6 4494 RXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 4496 RXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 4497 RXHUBPORT Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG3 Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX0x01C6 4498 TXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. 0x01C6 449A TXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This 0x01C6 449B TXHUBPORT isused onlywhen full-peedorlow-speeddeviceisconnectedviaa USB2.0 high- speed hub. Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX0x01C6 449C RXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 449E RXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 449F RXHUBPORT Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG4 Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX0x01C6 44A0 TXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. 0x01C6 44A2 TXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This 0x01C6 44A3 TXHUBPORT isused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX0x01C6 44A4 RXFUNCADDR Endpoint Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 44A6 RXHUBADDR Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 277 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-87.USB2.0 Registers(continued) HEX ADDRESS ACRONYM REGISTER NAMERANGE Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. 0x01C6 44A7 RXHUBPORT Thisisused onlywhen full-speedorlow-speeddeviceisconnectedviaa USB2.0 high-speedhub. Controland StatusRegisterforEndpoint 0 -EOCSR0 PERI_CSR0 ControlStatusRegisterforEndpoint0 inPeripheralmode 0x01C6 4502 HOST_CSR0 ControlStatusRegisterforEndpoint0 inHostmode 0x01C6 4508 COUNT0 Number ofReceivedBytesinEndpoint0 FIFO 0x01C6 450A HOST_TYPE0 DefinestheSpeed ofEndpoint0 0x01C6 450B HOST_NAKLIMIT0 SetstheNAK responsetimeouton Endpoint0. 0x01C6 450F CONFIGDATA Returnsdetailsofcoreconfiguration Controland StatusRegisterforEndpoint 1 -EOCSR1 0x01C6 4510 TXMAXP Maximum PacketsizeforPeripheral/HostTX Endpoint PERI_TXCSR ControlStatusRegisterforPeripheralTX Endpoint 0x01C6 4512 HOST_TXCSR ControlStatusRegisterforHostTX Endpoint 0x01C6 4514 RXMAXP Maximum PacketSizeforPeripheral/HostRX Endpoint PERI_RXCSR ControlStatusRegisterforPeripheralRX Endpoint 0x01C6 4516 HOST_RXCSR ControlStatusRegisterforHostRX Endpoint 0x01C6 4518 RXCOUNT Number ofBytesinHostRX EndpointFIFO Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 451A HOST_TXTYPE forthehostTX endpoint. SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response0x01C6 451B HOST_TXINTERVAL timeouton BulktransactionsforhostTX endpoint. Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 451C HOST_RXTYPE forthehostRX endpoint. SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response0x01C6 451D HOST_RXINTERVAL timeouton BulktransactionsforhostRX endpoint. Controland StatusRegisterforEndpoint 2 -EOCSR2 0x01C6 4520 TXMAXP Maximum PacketSizeforPeripheral/HostTX Endpoint PERI_TXCSR ControlStatusRegisterforPeripheralTX Endpoint 0x01C6 4522 HOST_TXCSR ControlStatusRegisterforHostTX Endpoint 0x01C6 4524 RXMAXP Maximum PacketSizeforPeripheral/HostRX Endpoint PERI_RXCSR ControlStatusRegisterforPeripheralRX Endpoint 0x01C6 4526 HOST_RXCSR ControlStatusRegisterforHostRX Endpoint 0x01C6 4528 RXCOUNT Number ofBytesinHostRX EndpointFIFO Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 452A HOST_TXTYPE forthehostTX endpoint. SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response0x01C6 452B HOST_TXINTERVAL timeouton BulktransactionsforhostTX endpoint. Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 452C HOST_RXTYPE forthehostRX endpoint. SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response0x01C6 452D HOST_RXINTERVAL timeouton BulktransactionsforhostRX endpoint. Controland StatusRegisterforEndpoint 3 -EOCSR3 0x01C6 4530 TXMAXP Maximum PacketSizeforPeripheral/HostTX Endpoint PERI_TXCSR ControlStatusRegisterforPeripheralTX Endpoint 0x01C6 4532 HOST_TXCSR ControlStatusRegisterforHostTX Endpoint 0x01C6 4534 RXMAXP Maximum PacketSizeforPeripheral/HostRX Endpoint PERI_RXCSR ControlStatusRegisterforPeripheralRX Endpoint 0x01C6 4536 HOST_RXCSR ControlStatusRegisterforHostRX Endpoint 0x01C6 4538 RXCOUNT Number ofBytesinHostRX EndpointFIFO

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-87.USB2.0 Registers(continued) HEX ADDRESS ACRONYM REGISTER NAMERANGE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 453A HOST_TXTYPE forthehostTX endpoint. SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response0x01C6 453B HOST_TXINTERVAL timeouton BulktransactionsforhostTX endpoint. Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 453C HOST_RXTYPE forthehostRX endpoint. SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response0x01C6 453D HOST_RXINTERVAL timeouton BulktransactionsforhostRX endpoint. Controland StatusRegisterforEndpoint 4 -EOCSR4 0x01C6 4540 TXMAXP Maximum PacketSizeforPeripheral/HostTX Endpoint PERI_TXCSR ControlStatusRegisterforPeripheralTX Endpoint 0x01C6 4542 HOST_TXCSR ControlStatusRegisterforHostTX Endpoint 0x01C6 4544 RXMAXP Maximum PacketSizeforPeripheral/HostRX Endpoint PERI_RXCSR ControlStatusRegisterforPeripheralRX Endpoint 0x01C6 4546 HOST_RXCSR ControlStatusRegisterforHostRX Endpoint 0x01C6 4548 RXCOUNT Number ofBytesinHostRX EndpointFIFO Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 454A HOST_TXTYPE forthehostTX endpoint. SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response0x01C6 454B HOST_TXINTERVAL timeouton BulktransactionsforhostTX endpoint. Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber0x01C6 454C HOST_RXTYPE forthehostRX endpoint. SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response0x01C6 454D HOST_RXINTERVAL timeouton BulktransactionsforhostRX endpoint. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 279 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

USB_VSSREF USB_R1 USB 10□K ±1%Ω (A) tr tf VCRS 90% VOH 10% VOL USB_DN USB_DP tper − tjr TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 7.19.4 USB2.0 ElectricalData/Timing Table7-88.SwitchingCharacteristicsOver Recommended OperatingConditionsforUSB2.0 (see Figure7-63) -594,-729 LOW SPEED FULL SPEED HIGH SPEEDNO. PARAMETER UNIT1.5Mbps 12 Mbps 480 Mbps MIN MAX MIN MAX MIN MAX 1 tr(D) Risetime,USB_DP and USB_DN signals(1) 75 300 4 20 0.5 ns 2 tf(D) Falltime,USB_DP and USB_DN signals(1) 75 300 4 20 0.5 ns 3 trfM Rise/Falltime,matching(2) 80 125 90 111.11 – – % 4 VCRS Outputsignalcross-overvoltage(1) 1.3 2 1.3 2 – – V 5 tjr(source)NT Source(Host)Driverjitter,nexttransition 2 2 (3) ns tjr(FUNC)NT FunctionDriverjitter,nexttransition 25 2 (3) ns 6 tjr(source)PT Source(Host)Driverjitter,pairedtransition(4) 1 1 (3) ns tjr(FUNC)PT FunctionDriverjitter,pairedtransition 10 1 (3) ns 7 tw(EOPT) Pulseduration,EOP transmitter 1250 1500 160 175 – – ns 8 tw(EOPR) Pulseduration,EOP receiver 670 82 – ns 9 t(DRATE) Data Rate 1.5 12 480 Mb/s 10 ZDRV DriverOutputResistance – – 28 49.5 40.5 49.5 Ω (1) Low Speed:C L = 200 pF,FullSpeed:C L = 50 pF,HighSpeed:C L = 50 pF (2) tRFM = (tr/tf)x 100.[ExcludingthefirsttransactionfromtheIdlestate.] (3) Formore detailedinformation,see theUniversalSerialBus SpecificationRevision2.0,Chapter7.Electrical. (4) tjr= tpx(1)-tpx(0) Figure7-63.USB2.0 IntegratedTransceiverInterfaceTiming Figure7-64.USB ReferenceResistorRouting

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7.20 ATA Controller

The ATA peripheralsupportsthefollowingfeatures:

PIO,multiwordDMA, and UltraATA 33/66/100
Up tomode 4 timingson PIO mode
Up tomode 2 timingson multiwordDMA
Up tomode 5 timingson UltraATA
Programmable timingparameters
SupportsTrueIDEmode forCompact Flash

7.20.1 ATA Bus Master Memory Map

The ATA ControllersupportsmultiwordDMA transfersbetween externalIDE/ATAPI devicesand a system memory bus interface.Table7-89shows thememory map fortheATA DMA engine. Table7-89.ATA DMA Master Memory Map SIZESTART ADDRESS END ADDRESS ATA DMA ACCESS(BYTES) 0x0000 0000 0x0FFF FFFF 256M Reserved 0x1000 0000 0x1000 FFFF 64K Reserved 0x1001 0000 0x1001 3FFF 16K ARM RAM 0 (Data) 0x1001 4000 0x1001 7FFF 16K ARM RAM 1 (Data) 0x1001 8000 0x1001 FFFF 32K ARM ROM (Data) 0x1002 0000 0x10FF FFFF 16256K 0x1100 0000 0x113F FFFF 4M 0x1140 0000 0x114F FFFF 1M 0x1150 0000 0x115F FFFF 1M Reserved 0x1160 0000 0x116F FFFF 1M 0x1170 0000 0x117F FFFF 1M 0x1180 0000 0x1180 FFFF 64K 0x1181 0000 0x1181 7FFF 32K 0x1181 8000 0x1183 7FFF 128K C64x+ L2 RAM/Cache 0x1183 8000 0x118F FFFF 800K Reserved 0x1190 0000 0x11DF FFFF 5M 0x11E0 0000 0x11E0 7FFF 32K C64x+ L1P RAM/Cache 0x11E0 8000 0x11EF FFFF 992K Reserved 0x11F0 0000 0x11F0 7FFF 32K C64x+ L1D RAM/Cache 0x11F0 8000 0x11FF FFFF 992K Reserved 0x1200 0000 0x4BFF FFFF 928M 0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) 0x5000 0000 0x7FFF FFFF 768M Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 281 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.20.2 ATA PeripheralRegisterDescription(s)

Table7-90shows theATA registers. Table7-90.ATA RegisterMemory Map HEX ADDRESS RANGE ACRONYM REGISTER NAME ATA Bus Master InterfaceDMA Engine Registers 0x01C6 6000 BMICP PrimaryIDE ChannelDMA ControlRegister 0x01C6 6002 BMISP PrimaryIDE ChannelDMA StatusRegister 0x01C6 6004 BMIDTP PrimaryIDE ChannelDMA DescriptorTablePointerRegister 0x01C6 6008 -0x01C6 603F – Reserved ATA ConfigurationRegisters 0x01C6 6040 IDETIMP PrimaryIDE ChannelTimingRegister 0x01C6 6042 -0x01C6 6046 – Reserved 0x01C6 6047 IDESTAT IDE ControllerStatusRegister 0x01C6 6048 UDMACTL Ultra-DMAControlRegister 0x01C6 604A – Reserved 0x01C6 6050 MISCCTL MiscellaneousControlRegister 0x01C6 6054 REGSTB Task FileRegisterStrobeTimingRegister 0x01C6 6058 REGRCVR Task FileRegisterRecoveryTimingRegister 0x01C6 605C DATSTB Data RegisterAccess PIO StrobeTimingRegister 0x01C6 6060 DATRCVR Data RegisterAccess PIO RecoveryTimingRegister 0x01C6 6064 DMASTB MultiwordDMA StrobeTimingRegister 0x01C6 6068 DMARCVR MultiwordDMA RecoveryTimingRegister 0x01C6 606C UDMASTB Ultra-DMAStrobeTimingRegister 0x01C6 6070 UDMATRP Ultra-DMAReady-to-PauseTimingRegister 0x01C6 6074 UDMATENV Ultra-DMATimingEnvelopeRegister 0x01C6 6078 IORDYTMP PrimaryI/OReady TimerConfigurationRegister 0x01C6 607C -0x01C6 67FF – Reserved

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7.20.3 ATA ElectricalData/Timing

pins.Formore details,see Section7.1,ParameterInformation. configurationoftheATA memory-mapped controlregistersfortheselectedATA frequencyofoperation. 7.20.3.1ATA PIO Data TransferAC Timing Table7-91.Timings forATA Module — PIO Data Transfer(1)(2)(seeFigure7-65) -594,-729 NO. UNIT MODE MIN MAX 1 t0 Cycletime 0-4(3) (DATSTB + DATRCVR + 2)P -0.5 ns 2 t1 AddressvalidtoDIOW/ DIOR setup 0-4(3) 12P -1.6 ns 3 t2 DIOW/ DIOR pulsedurationlow 0-4(3) (DATSTB + 1)P -1 ns 0-2 – ns 4 t2i DIOW/ DIOR recoverytime,pulsedurationhigh 3-4(3) (DATRCVR + 1)P -1 ns DIOW datasetuptime,DD[15:0]validbefore5 t3 0-4(3) (DATSTB + 1)P nsDIOW risingedge DIOW dataholdtime,DD[15:0]validafterDIOW6 t4 0-4(3) (HWNHLD + 1)P + 1 nsrisingedge 0 50 ns DIOR datasetuptime,DD[15:0]validbeforeDIOR7 t5 1 35 nsrisingedge 2-4(3) 20 ns DIOR dataholdtime,DD[15:0]validafterDIOR8 t6 0-4(3) 5 nsrisingedge Outputdata3-state,DD[15:0]3-stateafterDIOR9 t6Z 0-4(3) 30 nsrisingedge 10 t9 DIOW/ DIOR toaddressvalidhold 0-4(3) (HWNHLD + 1)P -2.1 ns Read datasetuptime,DD[15:0]validbefore11 tRD 0-4(3) 0 nsIORDY active 12 tA IORDY setup 0-4(3)(4) 35 ns 13 tB IORDY pulsewidth 0-4(3) 1250 ns 14 tC IORDY assertiontorelease 0-4(3) 5 ns (1) P = SYSCLK4 period,inns,forATA. Forexample,when runningtheDSP CPU at594 MHz, use P = 10.1nsand when runningtheDSP CPU at729 MHz, use P = 9.6ns. (2) DATSTB equalsthevalueprogrammed intheDATSTBxP bitfieldintheDATSTB register.DATRCVR equalsthevalueprogrammed in theDATRCVRxP bitfieldintheDATRCVR register.HWNHLD equalsthevalueprogrammed intheHWNHLDxP bitfieldinthe MISCCTL register.Formore detailedinformation,see theTMS320DM646x DMSoC ATA ControllerUser's Guide (literaturenumber SPRUEQ3 ). (3) The sustainedthroughputforPIO modes 3 and 4 islimitedtothethroughputequivalentofPIO mode 2.Formore detailedinformation, see theTMS320DM646x DMSoC ATA ControllerUser's Guide (literaturenumber SPRUEQ3 ). (4) The tA parametermust be met onlywhen theIORDY timerisenabledtoallowa devicetoinsertwaitstatesduringa transaction.Inorder tomeet thetA parameter,a minimum frequencyforSYSCLK4 isspecifiedforeach PIO as follows:

PIO mode 0,MIN frequency= 15 MHz
PIO mode 1,MIN frequency= 22 MHz
PIO mode 2,MIN frequency= 31 MHz
PIO mode 3,MIN frequency= 45 MHz

DA[2:0], ATA_CS0 , ATA_CS1 IORDY (A) DIOW /DIOR DD15:0 DD[15:0] (IN) IORDY (B) IORDY (C) t1 t2 t9 t2i t6t5 t6Z tRDtC tA tC tB A. IORDY is not negated for transfer (no wait generated) B. IORDY is negative but is re-asserted before tA (no wait is generated) C. IORDY is negative before tA and remains asserted until tB; data is driven valid at tRD (wait is generated) TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-65.ATA PIO Data TransferTiming

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 7.20.3.2ATA MultiwordDMA Timing Table7-92.Timings forATA Module — MultiwordDMA AC Timing(1)(2)(seeFigure7-66) -594,-729 NO. UNIT MODE MIN MAX 1 t0 Cycletime 0-2 (DMASTB + DMARCVR + 2)P -0.5 ns 2 tD DIOW/ DIOR activelowpulseduration 0-2 (DMASTB + 1)P -1 ns 0 150 ns DIOR dataaccess,DIOR fallingedge toDD[15:0]3 tE 1 60 nsvalid 2 50 ns DIOR dataholdtime,DD[15:0]validafterDIOR4 tF 0-2 5 nsrisingedge DIOW/ DIOR datasetuptime,DD[15:0](OUT )valid 0-2 (DMASTB)P nsbeforeDIOW/ DIOR risingedge 0 100 ns5 tG DIOW/ DIOR datasetuptime,DD15:0valid 1 30 nsbeforeDIOW/ DIOR risingedge 2 20 ns DIOW dataholdtime,DD[15:0]validafterDIOW6 tH 0-2 (HWNHLD + 1)P + 1 nsrisingedge 7 tI DMACK toDIOW/ DIOR setup 0-2 (DMARCVR + 1)P -1.7 ns 8 tJ DIOW/ DIOR toDMACK hold 0-2 5P -5.9 ns 9 tKR DIOR negatedpulsewidth 0-2 (DMARCVR + 1)P -1 ns 10 tKW DIOW negatedpulsewidth 0-2 (DMARCVR + 1)P -1 ns 0 120 ns 11 tLR DIOR toDMARQ delay 1 45 ns 2 35 ns 0-1 40 ns 12 tLW DIOW toDMARQ delay 2 35 ns 13 tM ATA_CSx validtoDIOW/ DIOR setup 0-2 (DATRCVR)P -1.7 ns 14 tN ATA_CSx validafterDIOW/ DIOR risingedge hold 0-2 5P -1.7 ns 0 20 ns 15 tZ DMACK toreaddata(DD[15:0])released 1-2 25 ns (1) P = SYSCLK4 period,inns,forATA. Forexample,when runningtheDSP CPU at594 MHz, use P = 10.1nsand when runningtheDSP CPU at729 MHz, use P = 9.6ns (2) DMASTB equalsthevalueprogrammed intheDMASTBxP bitfieldintheDMASTB register.DMARCVR equalsthevalueprogrammed intheDMARCVRxP bitfieldintheDMARCVR register.HWNHLD equalsthevalueprogrammed intheHWNHLDxP bitfieldinthe MISCCTL register.Formore detailedinformation,see theTMS320DM646x DMSoC ATA ControllerUser's Guide (literaturenumber SPRUEQ3 ). Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 285 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

DA[2:0], ATA_CS0 , ATA_CS1 tM t0 tN tL tJ tZ tK tH tF tD tI tG tE tG DMARQ DMACK DIOW /DIOR DD15:0 DD[15:0] (IN) TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-66.ATA MultiwordDMA Timing

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 7.20.3.3ATA UltraDMA Timing Table7-93.Timings forATA Module — UltraDMA AC Timing(1)(2) (seeFigure7-67through Figure7-76) -594,-729 NO. UNIT MODE MIN MAX 28 f(SYSCLK4) Operatingfrequency,SYSCLK4 0-5 25 MHz 0 240 ns 1 160 ns 2 120 ns 1 t2CYCTYP Typicalsustainedaveragetwo cycletime 3 90 ns 4 60 ns 5 40 ns 2 tCYC Cycletime,Strobeedge toStrobeedge 0-5 (UDMASTB + 1)P ns Two cycletime,risingtorisingedge orfallingto3 t2CYC 0-5 2(UDMASTB + 1)P nsfallingedge 0 15 ns 1 10 ns 4 tDS Data setup,datavalidbeforeSTROBE edge 2-3 7 ns 4 5 ns 5 4 ns 0-4 5 ns 5 tDH Data hold,datavalidafterSTROBE edge 5 4.6 ns 0 70 ns 1 48 ns 2 31 nsData validINPUT setuptime,datavalidbefore STROBE 3 20 ns6 tDVS 4 6.7 ns 5 4.8 ns Data validOUTPUT setuptime,datavalidbefore 0-5 (UDMASTB)P -3.1 nsSTROBE 0-4 6.2 nsData validINPUT holdtime,datavalidafter STROBE 5 4.8 ns7 tDVH Data validOUTPUT holdtime,datavalidafter 0-5 1P -2 nsSTROBE CRC word validsetuptimeathost,CRC valid10 tCVS 0-5 P nsbeforeDMACK negation CRC word validholdtimeatsender,CRC valid11 tCVH 0-5 2P nsafterDMACK negation 0-4 0 nsTime fromSTROBE outputreleased-to-driving12 tZFS untilthefirsttransitionofcriticaltiming 5 35 ns 0 70 ns 1 48 ns 2 31 nsTime fromdataoutputreleased-to-drivinguntil13 tDZFS thefirsttransitionofcriticaltiming 3 20 ns 4 6.7 ns 5 25 ns (1) P = SYSCLK4 period,inns,forATA. Forexample,when runningtheDSP CPU at594 MHz, use P = 10.1ns and when runningthe DSP CPU at729 MHz, use P = 9.6ns (2) UDMASTB equalsthevalueprogrammed intheUDMSTBxP bitfieldintheUDMASTB register.UDMATRP equalsthevalue programmed intheUDMTRPxP bitfieldintheUDMATRP register.TENV equalsthevalueprogrammed intheUDMATNVxP bitfieldin theUDMATENV register.Formore detailedinformation,see theTMS320DM646x DMSoC ATA ControllerUser's Guide (literature number SPRUEQ3 ). Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 287 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-93.Timings forATA Module — UltraDMA AC Timing(1)(2) (seeFigure7-67through Figure7-76)(continued) -594,-729 NO. UNIT MODE MIN MAX 0 230 ns 1 200 ns 2 170 ns 14 tFS FirstSTROBE time 3 130 ns 4 120 ns 5 90 ns 0-2 0 150 ns 15 tLI Limitedinterlocktime 3-4 0 100 ns 5 0 75 ns 16 tMLI Interlocktimewithminimum 0-5 20 ns 17 tUI Unlimitedinterlocktime 0-5 0 ns Maximum timeallowedforoutputdriversto18 tAZ 0-5 10 nsrelease 19 tZAH Minimum delaytimerequiredforoutput 0-5 20 ns Minimum delaytimefordrivertoassertornegate20 tZAD 0-5 0 ns(fromreleased) Envelopetime,DMACK toSTOP and DMACK to 21 tENV HDMARDY duringin-burstinitiationand from 0-5 (TENV + 1)P -0.5 (TENV + 1)P + 1.4 ns DMACK toSTOP duringdataoutburstinitiation 0 75 ns 1 70 ns 22 tRFS Ready-to-final-STROBEtime 2-4 60 ns 5 50 ns Ready topause time,(HDMARDY (DIOR) to 0-5 (UDMATRP + 1)P -0.8 nsSTOP (DIOW)) 0 160 ns 23 tRP 1 125 nsReady topause time,(DDMARDY (IORDY) to DMARQ) 2-4 100 ns 5 85 ns 24 tIORDYZ Maximum timebeforereleasingIORDY 0-5 20 ns 25 tZIORDY Minimum timebeforedrivingIORDY 0-5 0 ns Setupand holdtimeforDMACK (before26 tACK 0-5 20 nsassertionornegation) STROBE edge tonegationofDMARQ or 27 tSS assertionofSTOP (when senderterminatesa 0-5 50 ns burst)

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(IORDY) DD[15:0] tCYC (A) tCYC (A) DMARQ tDVH tENV DSTROBE (IORDY) (A) STOP (DIOW )(A) HDMARDY (DIOR )(A) DD[15:0] DA[2:0], ATA_CS0 , ATA_CS1 tFS tENV tZFS tDZFS tDVS tZAD tZAD tFS tUI tACK tACK tZIORDY tAZ tACK DMACK TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 A. The definitionsforthe DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signallinesare not in effectuntil DMARQ and DMACK areasserted. Figure7-67.ATA Initiatingan UltraDMA Data-InBurstTiming A. While DSTROBE (IORDY) timingistCYC at the device,itmay be differentat the host due to propagationdelay differenceson thecable. Figure7-68.ATA SustainedUltraDMA Data-InData TransferTiming Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 289 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

(IORDY) STOP (DIOW ) HDMARDY (DIOR) DD[15:0] DMACK DA[2:0], ATA_CS0 , ATA_CS1 tACK tACK tIORDYZ tCVH tCVS CRC tACK tZAH tAZ tLI tLI tLI tSS DMARQ tRP DSTROBE (IORDY) STOP (DIOW ) HDMARDY (DIOR) DD[15:0] DMACK tRFS TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-69.ATA Host Pausing an UltraDMA Data-InBurstTiming Figure7-70.ATA Device Terminatingan UltraDMA Data-InBurstTiming

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HSTROBE (DIOR )(A) STOP (DIOW )(A) DDMARDY (IORDY) (A) DD[15:0] DMACK DA[2:0], ATA_CS0 , ATA_CS1 tUI tZIORDY tENV tACK tACK tACK tDZFS tLI tUI tDVS tDVH DMARQ DSTROBE (IORDY) STOP (DIOW ) HDMARDY (DIOR) DD[15:0] DMACK DA[2:0], ATA_CS0 , ATA_CS1 tCVH tLI CRC tIORDYZ tAZ tMLI tZAH tACK tACK tLI tRP tRFS tACK tCVS tMLI TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-71.ATA Host Terminatingan UltraDMA Data-InBurstTiming A. The definitionsforthe DIOW:STOP, IORDY:DDMARDY, and DIOR:HSTROBE signallinesare not in effectuntil DMARQ and DMACK areasserted. Figure7-72.ATA Initiatingan UltraDMA Data-OutBurstTiming Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 291 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

STOP (DIOW ) DDMARDY (IORDY) HSTROBE (DIOR) DD[15:0] HSTROBE (DIOR ) DD[15:0] (OUT) t2CYC tCYC (A) tCYC (A) t2CYC tDVH tDVS tDVH tDVS tDVH TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com A. While HSTROBE (DIOR) timingistCYC at the host,itmay be differentat the devicedue to propagationdelay differenceson thecable. Figure7-73.ATA SustainedUltraDMA Data-OutTransferTiming Figure7-74.ATA Device Pausing an UltraDMA Data-OutBurstTiming

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STOP (DIOW ) DDMARDY (IORDY) HSTROBE (DIOR) DD[15:0] tMLI DA[2:0], ATA_CS0 , ATA_CS1 tLI tRP tRFS tLI tMLI tCVS tIORDYZ tACK tACK tACK tCVH CRC DMARQ DMACK tLI STOP (DIOW ) DDMARDY (IORDY) HSTROBE (DIOR ) DD[15:0] tLI tLI tSS tMLI tACK tIORDYZ tACK tCVS tCVH CRC DA[2:0], ATA_CS0 , ATA_CS1 tACK TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-75.ATA Host Terminatingan UltraDMA Data-OutBurstTiming Figure7-76.ATA Device Terminatingan UltraDMA Data-OutBurstTiming Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 293 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

DA[2:0], ATA_CS0 , ATA_CS1 HDDIR DIOW DD[15:0] (OUT) tC (A) tC (A) A. tC ≥ one cycle DA[2:0], ATA_CS0 , ATA_CS1 tC (A) HDDIR DIOW DD[15:0] (OUT) tC (A) A. tC ≥ one cycle TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com 7.20.3.4ATA HDDIR Timing Figure7-77throughFigure7-80show thebehaviorofHDDIR forthedifferenttypesoftransfers. Table7-94.Timing Requirements forHDDIR (1) -594,-729 NO. UNIT MIN MAX 1 tc Cycletime,ATA_CS[1:0]toHDDIR low E -3.1 ns (1) E = ATA clockcycle Figure7-77.ATA HDDIR TaskfileWrite/SinglePIO WriteTiming Figure7-78.ATA HDDIR PIO PostwriteStartTiming

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DA[2:0], ATA_CS0 , ATA_CS1 HDDIR DIOW DD[15:0] (OUT) DMACK CRC tC (A) A. tC ≥ one cycle DA[2:0], ATA_CS0 , ATA_CS1 tC (A) HDDIR DIOW DD[15:0] (OUT) DMACK tC (A) A. tC ≥ one cycle TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-79.ATA HDDIR MultiwordDMA WriteTransferTiming Figure7-80.ATA HDDIR UltraDMA WriteTransferTiming Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 295 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.21 VLYNQ

The DM6467 VLYNQ peripheralprovidesa highspeed serialcommunicationsinterfacewiththefollowing features.

Low PinCount
ScalablePerformance/Support
SimplePacketBased TransferProtocolforMemory Mapped Access – WriteRequest/DataPacket – Read RequestPacket – Read Response Data Packet – InterruptRequestPacket
SupportsbothSymmetricand AsymmetricOperation – Tx pinson firstdeviceconnecttoRx pinson second deviceand viceversa – Data pinwidthsareautomaticallydetectedafterreset – Request packets,response packets,and flowcontrolinformationare allmultiplexedand sent acrossthesame physicalpins – SupportsbothHost/Peripheraland Peer-to-Peercommunication
SimpleBlockCode PacketFormatting(8-bit/10-bit)
InBand Flow Control – No extrapinsneeded – Allowsreceivertomomentarilythrottleback transmitterwhen overflowisabouttooccur – Uses builtinspecialcode capabilityofblockcode toseamlesslyinterleaveflowcontrolinformation withuserdata – Allowssystemdesignertobalancecostofdatabufferingversusperformance
Multipleoutstandingtransactions
Automaticpacketformattingoptimizations
Internalloop-backmode

7.21.1 VLYNQ Bus Master Memory Map

The VLYNQ peripheralincludesa bus master interfacethatallowsexternaldeviceinitiatedtransfersto accesstheDM6467 systembus.Table7-95shows thememory map fortheVLYNQ masterinterface. Table7-95.VLYNQ Master Memory Map SIZESTART ADDRESS END ADDRESS HPI ACCESS(BYTES) 0x0000 0000 0x01BF FFFF 28M Reserved 0x01C0 0000 0x0FFF FFFF 228M CFG Bus Peripherals 0x1000 0000 0x1000 FFFF 64K Reserved 0x1001 0000 0x1001 3FFF 16K ARM RAM 0 (Data) 0x1001 4000 0x1001 7FFF 16K ARM RAM 1 (Data) 0x1001 8000 0x1001 FFFF 32K ARM ROM (Data)

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-95.VLYNQ Master Memory Map (continued) SIZESTART ADDRESS END ADDRESS HPI ACCESS(BYTES) 0x1002 0000 0x10FF FFFF 16256K 0x1100 0000 0x113F FFFF 4M 0x1140 0000 0x114F FFFF 1M 0x1150 0000 0x115F FFFF 1M Reserved 0x1160 0000 0x116F FFFF 1M 0x1170 0000 0x117F FFFF 1M 0x1180 0000 0x1180 FFFF 64K 0x1181 0000 0x1181 7FFF 32K 0x1181 8000 0x1183 7FFF 128K C64x+ L2 RAM/Cache 0x1183 8000 0x118F FFFF 800K Reserved 0x1190 0000 0x11DF FFFF 5M 0x11E0 0000 0x11E0 7FFF 32K C64x+ L1P RAM/Cache 0x11E0 8000 0x11EF FFFF 992K Reserved 0x11F0 0000 0x11F0 7FFF 32K C64x+ L1D RAM/Cache 0x11F0 8000 0x11FF FFFF 992K Reserved 0x1200 0000 0x41FF FFFF 768M 0x4200 0000 0x43FF FFFF 32M EMIFA Data (CS2) 0x4400 0000 0x45FF FFFF 32M EMIFA Data (CS3) 0x4600 0000 0x47FF FFFF 32M EMIFA Data (CS4) 0x4800 0000 0x49FF FFFF 32M EMIFA Data (CS5) 0x4A00 0000 0x7FFF FFFF 864M Reserved 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved

7.21.2 VLYNQ PeripheralRegisterDescription(s)

Table7-96.VLYNQ Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x2001 0000 REVID VLYNQ RevisionRegister 0x2001 0004 CTRL VLYNQ LocalControlRegister 0x2001 0008 STAT VLYNQ LocalStatusRegister 0x2001 000C INTPRI VLYNQ LocalInterruptPriorityVectorStatus/ClearRegister 0x2001 0010 INTSTATCLR VLYNQ LocalUnmasked InterruptStatus/ClearRegister 0x2001 0014 INTPENDSET VLYNQ LocalInterruptPending/SetRegister 0x2001 0018 INTPTR VLYNQ LocalInterruptPointerRegister 0x2001 001C XAM VLYNQ LocalTransmitAddressMap Register 0x2001 0020 RAMS1 VLYNQ LocalReceiveAddressMap Size1 Register 0x2001 0024 RAMO1 VLYNQ LocalReceiveAddressMap Offset1 Register 0x2001 0028 RAMS2 VLYNQ LocalReceiveAddressMap Size2 Register 0x2001 002C RAMO2 VLYNQ LocalReceiveAddressMap Offset2 Register 0x2001 0030 RAMS3 VLYNQ LocalReceiveAddressMap Size3 Register 0x2001 0034 RAMO3 VLYNQ LocalReceiveAddressMap Offset3 Register 0x2001 0038 RAMS4 VLYNQ LocalReceiveAddressMap Size4 Register 0x2001 003C RAMO4 VLYNQ LocalReceiveAddressMap Offset4 Register 0x2001 0040 CHIPVER VLYNQ LocalChipVersionRegister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 297 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-96.VLYNQ Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x2001 0044 AUTNGO VLYNQ LocalAutoNegotiationRegister 0x2001 0048 – Reserved 0x2001 004C – Reserved 0x2001 0050 -0x2001 005C – Reserved 0x2001 0060 – Reserved 0x2001 0064 – Reserved 0x2001 0068 -0x2001 007C – Reservedforfutureuse 0x2001 0080 RREVID VLYNQ Remote RevisionRegister 0x2001 0084 RCTRL VLYNQ Remote ControlRegister 0x2001 0088 RSTAT VLYNQ Remote StatusRegister 0x2001 008C RINTPRI VLYNQ Remote InterruptPriorityVectorStatus/ClearRegister 0x2001 0090 RINTSTATCLR VLYNQ Remote Unmasked InterruptStatus/ClearRegister 0x2001 0094 RINTPENDSET VLYNQ Remote InterruptPending/SetRegister 0x2001 0098 RINTPTR VLYNQ Remote InterruptPointerRegister 0x2001 009C RXAM VLYNQ Remote TransmitAddressMap Register 0x2001 00A0 RRAMS1 VLYNQ Remote ReceiveAddressMap Size1 Register 0x2001 00A4 RRAMO1 VLYNQ Remote ReceiveAddressMap Offset1 Register 0x2001 00A8 RRAMS2 VLYNQ Remote ReceiveAddressMap Size2 Register 0x2001 00AC RRAMO2 VLYNQ Remote ReceiveAddressMap Offset2 Register 0x2001 00B0 RRAMS3 VLYNQ Remote ReceiveAddressMap Size3 Register 0x2001 00B4 RRAMO3 VLYNQ Remote ReceiveAddressMap Offset3 Register 0x2001 00B8 RRAMS4 VLYNQ Remote ReceiveAddressMap Size4 Register 0x2001 00BC RRAMO4 VLYNQ Remote ReceiveAddressMap Offset4 Register VLYNQ Remote ChipVersionRegister(valueson thedevice_idand0x2001 00C0 RCHIPVER device_revpinsofremoteVLYNQ) 0x2001 00C4 RAUTNGO VLYNQ Remote AutoNegotiationRegister 0x2001 00C8 RMANNGO VLYNQ Remote Manual NegotiationRegister 0x2001 00CC RNGOSTAT VLYNQ Remote NegotiationStatusRegister 0x2001 00D0 -0x2001 00DC – Reserved VLYNQ Remote InterruptVectors3 -0 (sourcedfromvlynq_int_i[3:0]portof0x2001 00E0 RINTVEC0 remoteVLYNQ) VLYNQ Remote InterruptVectors7 -4 (sourcedfromvlynq_int_i[7:4]portof0x2001 00E4 RINTVEC1 remoteVLYNQ) 0x2001 00E8 -0x2001 00FC – Reservedforfutureuse 0x2001 0100 -0x2001 0FFF – Reserved VLYNQ Remote Devices 64 MB Remote Data Region.Translatedintoone offourmapped registerson0x4C00 0000 -0x4FFF FFFF VLYNQREMOTE theremotedevice.

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7.21.3 VLYNQ ElectricalData/Timing

Table7-97.Timing Requirements forVLYNQ_CLOCK Input(seeFigure7-81) -594 -729 NO. UNIT MIN MAX MIN MAX 1 tc(VCLK) Cycletime,VLYNQ_CLOCK 10 9.6 ns 2 tw(VCLKH) Pulseduration,VLYNQ_CLOCK high 3 3 ns 3 tw(VCLKL) Pulseduration,VLYNQ_CLK low 3 3 ns 4 tt(VCLK) Transitiontime,VLYNQ_CLOCK 3 3 ns Table7-98.SwitchingCharacteristicsOver Recommended OperatingConditionsforVLYNQ_CLOCK Output (seeFigure7-81) -594 -729NO PARAMETER UNIT. MIN MAX MIN MAX 1 tc(VCLK) Cycletime,VLYNQ_CLOCK 10 9.6 ns 2 tw(VCLKH) Pulseduration,VLYNQ_CLOCK high 4 4 ns 3 tw(VCLKL) Pulseduration,VLYNQ_CLOCK low 4 4 ns 4 tt(VCLK) Transitiontime,VLYNQ_CLOCK 3 3 ns Figure7-81.VLYNQ_CLOCK Timing forVLYNQ Table7-99.SwitchingCharacteristicsOver Recommended OperatingConditionsforTransmitData forthe VLYNQ Module (seeFigure7-82) -594,-729 NO PARAMETER FAST MODE SLOW MODE UNIT. MIN MAX MIN MAX td(VCLKH-1 Delaytime,VLYNQ_CLOCK hightoVLYNQ_TXD[3:0] invalid 1 2.21 ns TXDI) td(VCLKH-2 Delaytime,VLYNQ_CLOCK hightoVLYNQ_TXD[3:0] valid 7.14 8.5 ns TXDV) Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 299 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

VL YNQ_CLOCK VL YNQ_TXD[3:0] VL YNQ_RXD[3:0] 3 4 Data Data TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-100.Timing Requirements forReceive Data fortheVLYNQ Module (1)(seeFigure7-82) -594,-729 NO. UNIT MIN MAX RTM disabled,RTM sample = 3 0.2 nsSetuptime,VLYNQ_RXD[3:0] validbefore3 tsu(RXDV-VCLKH) VLYNQ_CLOCK high RTM enabled (1) ns RTM disabled,RTM sample = 3 2 nsHoldtime,VLYNQ_RXD[3:0] validafter4 th(VCLKH-RXDV) VLYNQ_CLOCK high RTM enabled (1) ns (1) The VLYNQ receivetimingmanager (RTM) isa serialreceivelogicdesignedtoeliminatesetupand holdviolationsthatcouldoccurin traditionalinputsignals.RTM logicautomaticallyselectsthesetupand holdtimingfromone ofeightdataflops(seeTable7-101).When RTM logicisdisabled,thesetupand holdtimingfromthedefaultdataflop(3)isused. Table7-101.RTM RX Data Flop Hold/SetupTiming Constraints RX Data Flop HOLD (Y) SETUP (X) 0 0.62 1.3 1 1.43 0.8 2 1.66 0.4 3 2.12 0.2 4 2.5 0 5 3.18 -0.3 6 3.87 -0.5 7 4.25 -0.7 Figure7-82.VLYNQ Transmit/ReceiveTiming

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7.22 MultichannelAudio SerialPort(McASP0/1) Peripherals

The multichannelaudioserialport(McASP) functionsas a general-purposeaudioserialportoptimizedfor the needs of multichannelaudioapplications.The McASP isusefulfortime-divisionmultiplexed(TDM) stream,Inter-IntegratedSound (I2S)protocols,and intercomponentdigitalaudiointerfacetransmission (DIT).

7.22.1 McASP Device-SpecificInformation

The DM6467 deviceincludestwo multichannelaudioserialport(McASP) interfaceperipherals(McASP0 and McASP1). The McASP0 module consistsof a transmitand receivesection.These sectionscan operatecompletelyindependentlywithdifferentdata formats,separatemaster clocks,bitclocks,and framesyncsoralternatively,thetransmitand receivesectionsmay be synchronized.The McASP0 module alsoincludesa pool of 4 shiftregistersthatmay be configuredto operateas eithertransmitdata or receivedata. The transmitsectionof the McASP0 can transmitdata in eithera time-division-multiplexed(TDM) synchronousserialformator ina digitalaudiointerface(DIT)formatwhere thebitstreamisencoded for S/PDIF,AES-3, IEC-60958,CP-430 transmission.The receivesectionoftheMcASP0 peripheralsupports theTDM synchronousserialformat. The McASP0 module can supportone transmitdataformat(eithera TDM formatorDIT format)and one receiveformatata time.Alltransmitshiftregistersuse thesame formatand allreceiveshiftregistersuse thesame format.However,thetransmitand receiveformatsneed notbe thesame. Both thetransmitand receivesectionsoftheMcASP alsosupportburstmode which isusefulfornon-audiodata(forexample, passingcontrolinformationbetween two DSPs). The McASP0 peripheralhas additionalcapabilityfor flexibleclock generation,and error detection/handling,as wellas errormanagement. The DM6467 McASP1 module is a reduced featureversionof the McASP peripheral.The McASP1 module providesa singletransmit-onlyshiftregisterand can transmitdatainDIT formatonly. For more detailedinformationon and thefunctionalityoftheMcASP peripheral,see theTMS320DM646x DMSoC MultichannelAudioSerialPort(McASP) User'sGuide (literaturenumber SPRUER1 ). Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 301 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.22.2 McASP0 and McASP1 PeripheralRegisterDescription(s)

Table7-102.McASP0 ControlRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 01D0 1000 PID PeripheralIdentificationregister[Registervalue:0x0010 0101] 01D0 1004 – Reserved 01D0 1008 – Reserved 01D0 100C – Reserved 01D0 1010 PFUNC Pinfunctionregister 01D0 1014 PDIR Pindirectionregister 01D0 1018 – Reserved 01D0 101C – Reserved 01D0 1020 – Reserved 01D0 1024 – 01D0 1040 – Reserved 01D0 1044 GBLCTL Globalcontrolregister 01D0 1048 AMUTE Mute controlregister 01D0 104C DLBCTL DigitalLoop-backcontrolregister 01D0 1050 DITCTL DIT mode controlregister 01D0 1054 – 01D0 105C – Reserved AliasofGBLCTL containingonlyReceiverResetbits,allowstransmittobe reset01D0 1060 RGBLCTL independentlyfromreceive. 01D0 1064 RMASK ReceiverformatUNIT bitmask register 01D0 1068 RFMT Receivebitstreamformatregister 01D0 106C AFSRCTL Receiveframesynccontrolregister 01D0 1070 ACLKRCTL Receiveclockcontrolregister 01D0 1074 AHCLKRCTL High-frequencyreceiveclockcontrolregister 01D0 1078 RTDM ReceiveTDM slot0–31 register 01D0 107C RINTCTL Receiverinterruptcontrolregister 01D0 1080 RSTAT Statusregister– Receiver 01D0 1084 RSLOT CurrentreceiveTDM slotregister 01D0 1088 RCLKCHK Receiverclockcheckcontrolregister 01D0 108C REVTCTL ReceiverDMA eventcontrolregister 01D0 1090 – 01D0 109C – Reserved AliasofGBLCTL containingonlyTransmitterResetbits,allowstransmittobe reset01D0 10A0 XGBLCTL independentlyfromreceive. 01D0 10A4 XMASK TransmitformatUNIT bitmask register 01D0 10A8 XFMT Transmitbitstreamformatregister 01D0 10AC AFSXCTL Transmitframesynccontrolregister 01D0 10B0 ACLKXCTL Transmitclockcontrolregister 01D0 10B4 AHCLKXCTL High-frequencyTransmitclockcontrolregister 01D0 10B8 XTDM TransmitTDM slot0–31 register 01D0 10BC XINTCTL Transmitinterruptcontrolregister 01D0 10C0 XSTAT Statusregister– Transmitter 01D0 10C4 XSLOT CurrenttransmitTDM slot 01D0 10C8 XCLKCHK Transmitclockcheckcontrolregister 01D0 10CC XEVTCTL TransmitDMA eventcontrolregister

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-102.McASP0 ControlRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01D0 10D0 – 01D0 10FC – Reserved 01D0 1100 DITCSRA0 Left(evenTDM slot)channelstatusregisterfile 01D0 1104 DITCSRA1 Left(evenTDM slot)channelstatusregisterfile 01D0 1108 DITCSRA2 Left(evenTDM slot)channelstatusregisterfile 01D0 110C DITCSRA3 Left(evenTDM slot)channelstatusregisterfile 01D0 1110 DITCSRA4 Left(evenTDM slot)channelstatusregisterfile 01D0 1114 DITCSRA5 Left(evenTDM slot)channelstatusregisterfile 01D0 1118 DITCSRB0 Right(oddTDM slot)channelstatusregisterfile 01D0 111C DITCSRB1 Right(oddTDM slot)channelstatusregisterfile 01D0 1120 DITCSRB2 Right(oddTDM slot)channelstatusregisterfile 01D0 1124 DITCSRB3 Right(oddTDM slot)channelstatusregisterfile 01D0 1128 DITCSRB4 Right(oddTDM slot)channelstatusregisterfile 01D0 112C DITCSRB5 Right(oddTDM slot)channelstatusregisterfile 01D0 1130 DITUDRA0 Left(evenTDM slot)userdataregisterfile 01D0 1134 DITUDRA1 Left(evenTDM slot)userdataregisterfile 01D0 1138 DITUDRA2 Left(evenTDM slot)userdataregisterfile 01D0 113C DITUDRA3 Left(evenTDM slot)userdataregisterfile 01D0 1140 DITUDRA4 Left(evenTDM slot)userdataregisterfile 01D0 1144 DITUDRA5 Left(evenTDM slot)userdataregisterfile 01D0 1148 DITUDRB0 Right(oddTDM slot)userdataregisterfile 01D0 114C DITUDRB1 Right(oddTDM slot)userdataregisterfile 01D0 1150 DITUDRB2 Right(oddTDM slot)userdataregisterfile 01D0 1154 DITUDRB3 Right(oddTDM slot)userdataregisterfile 01D0 1158 DITUDRB4 Right(oddTDM slot)userdataregisterfile 01D0 115C DITUDRB5 Right(oddTDM slot)userdataregisterfile 01D0 1160 – 01D0 117C – Reserved 01D0 1180 SRCTL0 Serializer0 controlregister 01D0 1184 SRCTL1 Serializer1 controlregister 01D0 1188 SRCTL2 Serializer2 controlregister 01D0 118C SRCTL3 Serializer3 controlregister 01D0 1190 – 01D0 11FC – Reserved 01D0 1200 XBUF0 TransmitBufferforSerializer0 01D0 1204 XBUF1 TransmitBufferforSerializer1 01D0 1208 XBUF2 TransmitBufferforSerializer2 01D0 120C XBUF3 TransmitBufferforSerializer3 01D0 1210 – 01D0 127C – Reserved 01D0 1280 RBUF0 ReceiveBufferforSerializer0 01D0 1284 RBUF1 ReceiveBufferforSerializer1 01D0 1288 RBUF2 ReceiveBufferforSerializer2 01D0 128C RBUF3 ReceiveBufferforSerializer3 01D0 1290 – 01D0 13FF – Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 303 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-103.McASP0 Data Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS (Used when RSEL orXSEL McASP0 receivebuffersorMcASP0 transmitbuffersvia bits= 0 [thesebitsarelocated01D0 1400 – 01D0 17FF RBUF0/XBUF0 thePeripheralData Bus. intheRFMT orXFMT registers, respectively].)

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-104.McASP1 ControlRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 01D0 1800 PID PeripheralIdentificationregister[Registervalue:0x0010 0101] 01D0 1804 – Reserved 01D0 1808 – Reserved 01D0 180C – Reserved 01D0 1810 PFUNC Pinfunctionregister 01D0 1814 PDIR Pindirectionregister 01D0 1818 – Reserved 01D0 181C – Reserved 01D0 1820 – Reserved 01D0 1824 – 01D0 1843 – Reserved 01D0 1844 GBLCTL Globalcontrolregister 01D0 1848 – Reserved 01D0 184C DLBCTL DigitalLoop-backcontrolregister 01D0 1850 DITCTL DIT mode controlregister 01D0 1854 – 01D0 185F – Reserved AliasofGBLCTL containingonlyReceiverResetbits,allowstransmittobe reset01D0 1860 RGBLCTL independentlyfromreceive. 01D0 1864 – Reserved 01D0 1868 – Reserved 01D0 186C – Reserved 01D0 1870 – Reserved 01D0 1874 – Reserved 01D0 1878 – Reserved 01D0 187C RINTCTL Receiverinterruptcontrolregister 01D0 1880 RSTAT Statusregister– Receiver 01D0 1884 – 01D0 1888 – 01D0 188C – 01D0 1890 – 01D0 189F – Reserved AliasofGBLCTL containingonlyTransmitterResetbits,allowstransmittobe reset01D0 18A0 XGBLCTL independentlyfromreceive. 01D0 18A4 XMASK TransmitformatUNIT bitmask register 01D0 18A8 XFMT Transmitbitstreamformatregister 01D0 18AC AFSXCTL Transmitframesynccontrolregister 01D0 18B0 ACLKXCTL Transmitclockcontrolregister 01D0 18B4 AHCLKXCTL High-frequencyTransmitclockcontrolregister 01D0 18B8 XTDM TransmitTDM slot0–31 register 01D0 18BC XINTCTL Transmitinterruptcontrolregister 01D0 18C0 XSTAT Statusregister– Transmitter 01D0 18C4 XSLOT CurrenttransmitTDM slot 01D0 18C8 XCLKCHK Transmitclockcheckcontrolregister 01D0 18CC XEVTCTL TransmitDMA eventcontrolregister Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 305 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-104.McASP1 ControlRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01D0 18D0 – 01D0 18FF – Reserved 01D0 1900 DITCSRA0 Left(evenTDM slot)channelstatusregisterfile 01D0 1904 DITCSRA1 Left(evenTDM slot)channelstatusregisterfile 01D0 1908 DITCSRA2 Left(evenTDM slot)channelstatusregisterfile 01D0 190C DITCSRA3 Left(evenTDM slot)channelstatusregisterfile 01D0 1910 DITCSRA4 Left(evenTDM slot)channelstatusregisterfile 01D0 1914 DITCSRA5 Left(evenTDM slot)channelstatusregisterfile 01D0 1918 DITCSRB0 Right(oddTDM slot)channelstatusregisterfile 01D0 191C DITCSRB1 Right(oddTDM slot)channelstatusregisterfile 01D0 1920 DITCSRB2 Right(oddTDM slot)channelstatusregisterfile 01D0 1924 DITCSRB3 Right(oddTDM slot)channelstatusregisterfile 01D0 1928 DITCSRB4 Right(oddTDM slot)channelstatusregisterfile 01D0 192C DITCSRB5 Right(oddTDM slot)channelstatusregisterfile 01D0 1930 DITUDRA0 Left(evenTDM slot)userdataregisterfile 01D0 1934 DITUDRA1 Left(evenTDM slot)userdataregisterfile 01D0 1938 DITUDRA2 Left(evenTDM slot)userdataregisterfile 01D0 193C DITUDRA3 Left(evenTDM slot)userdataregisterfile 01D0 1940 DITUDRA4 Left(evenTDM slot)userdataregisterfile 01D0 1944 DITUDRA5 Left(evenTDM slot)userdataregisterfile 01D0 1948 DITUDRB0 Right(oddTDM slot)userdataregisterfile 01D0 194C DITUDRB1 Right(oddTDM slot)userdataregisterfile 01D0 1950 DITUDRB2 Right(oddTDM slot)userdataregisterfile 01D0 1954 DITUDRB3 Right(oddTDM slot)userdataregisterfile 01D0 1958 DITUDRB4 Right(oddTDM slot)userdataregisterfile 01D0 195C DITUDRB5 Right(oddTDM slot)userdataregisterfile 01D0 1960 – 01D0 197F – Reserved 01D0 1980 SRCTL0 Serializer0 controlregister 01D0 1984 – 01D0 19FF – Reserved 01D0 1A00 XBUF0 TransmitBufferforSerializer0 01D0 1A04 – 01D0 13FF – Reserved Table7-105.McASP1 Data Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS (Used when XSEL bits= 0 01D0 1C00 – 01D0 1FFF XBUF1 McASP1 transmitbuffersviathePeripheralData Bus. [thesebitsarelocatedinthe XFMT register].)

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7.22.3 McASP0 and McASP1 ElectricalData/Timing

7.22.3.1 MultichannelAudio SerialPort(McASP0) Timing

Table7-106.Timing Requirements forMcASP0 (seeFigure7-83and Figure7-84)(1) -594,-729 NO. UNIT MIN MAX 1 tc(AHCKRX) Cycletime,AHCLKR/X 20.8 ns 2 tw(AHCKRX) Pulseduration,AHCLKR/X highorlow 8.3 ns 3 tc(CKRX) Cycletime,ACLKR/X ACLKR/X ext 37 ns 4 tw(CKRX) Pulseduration,ACLKR/X highorlow ACLKR/X ext 15 ns ACLKR/X int 15 ns 5 tsu(FRX-CKRX) Setuptime,AFSR/X inputvalidbeforeACLKR/X latchesdata ACLKR/X ext 3 ns ACLKR/X int 0 ns 6 th(CKRX-FRX) Holdtime,AFSR/X inputvalidafterACLKR/X latchesdata ACLKR/X ext 3 ns ACLKR int 15 ns 7 tsu(AXR-CKRX) Setuptime,AXR inputvalidbeforeACLKR/X latchesdata ACLKX int 14 ns ACLKR/X ext 3 ns ACLKR/X int 3 ns 8 th(CKRX-AXR) Holdtime,AXR inputvalidafterACLKR/X latchesdata ACLKR/X ext 3 ns (1) ACLKX internal:ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX externalinput:ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX externaloutput:ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 ACLKR internal:ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR externalinput:ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR externaloutput:ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 307 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-107.SwitchingCharacteristicsOver Recommended OperatingConditionsforMcASP0 (1)(2)(3) (seeFigure7-83and Figure7-84) -594,-729 NO. PARAMETER UNIT MIN MAX 9 tc(AHCKRX) Cycletime,AHCLKR/X 41.7 ns 10 tw(AHCKRX) Pulseduration,AHCLKR/X highorlow AH -2.5 ns 11 tc(CKRX) Cycletime,ACLKR/X ACLKR/X int 41.7 ns 12 tw(CKRX) Pulseduration,ACLKR/X highorlow ACLKR/X int A -2.5 ns ACLKR int -2 5 ns ACLKX int -1 5 ns 13 td(CKRX-FRX) Delaytime,ACLKR/X transmitedge toAFSX/R outputvalid ACLKR ext 0 15 ns ACLKX ext 0 16 ns ACLKX int -2 5 ns 14 td(CKX-AXRV) Delaytime,ACLKX transmitedge toAXR outputvalid ACLKX ext 0 16 ns ACLKR/X int -3 8 nsDisabletime,AXR highimpedance followinglastdatabit15 tdis(CKRX-AXRHZ) fromACLKR/X transmitedge ACLKR/X ext -3 15 ns (1) A = (ACLKR/X period)/2inns.Forexample,when ACLKR/X periodis25 ns,use A = 12.5ns. (2) AH = (AHCLKR/X period)/2inns.Forexample,when AHCLKR/X periodis25 ns,use AH = 12.5ns. (3) ACLKX internal:ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX externalinput:ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX externaloutput:ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 ACLKR internal:ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR externalinput:ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR externaloutput:ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

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A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data In/Receive) ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 A. For CLKRP = CLKXP = 0, the McASP transmitterisconfiguredforrisingedge (toshiftdata out)and the McASP receiverisconfiguredforfallingedge (toshiftdatain). B. For CLKRP = CLKXP = 1,theMcASP transmitterisconfiguredforfallingedge (toshiftdataout)and theMcASP receiverisconfiguredforrisingedge (toshiftdatain). Figure7-83.McASP0 and McASP1 InputTimings Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 309 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data Out/Transmit) ACLKR/X (CLKRP = CLKXP = 0)(B) ACLKR/X (CLKRP = CLKXP = 1)(A) TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com A. For CLKRP = CLKXP = 1,theMcASP transmitterisconfiguredforfallingedge (toshiftdataout)and theMcASP receiverisconfiguredforrisingedge (toshiftdatain). B. For CLKRP = CLKXP = 0, the McASP transmitterisconfiguredforrisingedge (toshiftdata out)and the McASP receiverisconfiguredforfallingedge (toshiftdatain). Figure7-84.McASP0 and McASP1 Output Timings

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7.22.3.2 MultichannelAudio SerialPort(McASP1) DIT Timing

Table7-108.Timing Requirements forMcASP1 (seeFigure7-83and Figure7-84)(1) -594,-729 NO. UNIT MIN MAX 1 tc(AHCKRX) Cycletime,AHCLKX 20.8 ns 2 tw(AHCKRX) Pulseduration,AHCLKX highorlow 8.3 ns 3 tc(CKRX) Cycletime,ACLKX ACLKX ext 37 ns 4 tw(CKRX) Pulseduration,ACLKX highorlow ACLKX ext 15 ns (1) ACLKX internal:ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX externalinput:ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX externaloutput:ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 311 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-109.SwitchingCharacteristicsOver Recommended OperatingConditionsforMcASP1 (1)(2)(3) (seeFigure7-83and Figure7-84) -594,-729 NO. PARAMETER UNIT MIN MAX 9 tc(AHCKRX) Cycletime,AHCLKX 41.7 ns 10 tw(AHCKRX) Pulseduration,AHCLKX highorlow AH -2.5 ns 11 tc(CKRX) Cycletime,ACLKX 41.7 ns 12 tw(CKRX) Pulseduration,ACLKX highorlow ACLKR/X int A -2.5 ns ACLKX int -1 5 ns 14 td(CKX-AXRV) Delaytime,ACLKX transmitedge toAXR outputvalid ACLKX ext 0 16 ns ACLKX int -3 8 nsDisabletime,AXR highimpedance followinglastdatabit15 tdis(CKRX-AXRHZ) fromACLKX transmitedge ACLKX ext -3 15 ns (1) A = (ACLKX period)/2inns.Forexample,when ACLKX periodis25 ns,use A = 12.5ns. (2) AH = (AHCLKX period)/2inns.Forexample,when AHCLKX periodis25 ns,use AH = 12.5ns. (3) ACLKX internal:ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX externalinput:ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX externaloutput:ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

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7.23 SerialPeripheralInterface(SPI)

The SPI isa high-speedsynchronousserialinput/outputportthatallowsa serialbitstreamofprogrammed length(2-to-16bits)tobe shiftedintoand outofthedeviceata programmed bit-transferrate.The SPI is normallyused forcommunicationbetween theTMS320DM646x DMSoC and externalperipherals.Typical applicationsinlcudea interfacetoexternalI/Oorperipheralexpansionviadevicessuch as shiftregisers, displaydrivers,SPI EEPROMs, and Analog-to-DigitalConverters(ADCs).

7.23.1 SPI Device-SpecificInformation

The DM6467 SPI supportsthefollowingfeatures:

Master/slaveoperation
2 chipselectsforinterfacing/controltomultipleSPI slavedevices
3-,4-,5-wireinterface[TheDM6467 supports3-pinmode, 2 4-pinmodes, and the5-pinmode.]
16-bitshiftregister
Receivebufferregister
8-bitclockprescaler
Programmable SPI clockfrequencyrange,characterlength,and clockphase and polarity

7.23.2 SPI PeripheralRegisterDescription(s)

Table7-110shows theSPI registers. Table7-110.SPI Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C6 6800 SPIGCR0 SPI GlobalControlRegister0 01C6 6804 SPIGCR1 SPI GlobalControlRegister1 01C6 5808 SPIINT SPI InterruptRegister 01C6 680C SPIILVL SPI InterruptLevelRegister 01C6 6810 SPIFLG SPI FlagStatusRegister 01C6 6814 SPIPC0 SPI PinControlRegister0 01C6 6818 – Reserved 01C6 681C SPIPC2 SPI PinControlRegister2 01C6 6820 – 01C6 6838 – Reserved 01C6 683C SPIDAT1 SPI ShiftRegister1 01C6 6840 SPIBUF SPI BufferRegister 01C6 6844 SPIEMU SPI EmulationRegister 01C6 6848 SPIDELAY SPI DelayRegister 01C6 684C SPIDEF SPI DefaultChipSelectRegister 01C6 6850 SPIFMT0 SPI Data FormatRegister0 01C6 6854 SPIFMT1 SPI Data FormatRegister1 01C6 6858 SPIFMT2 SPI Data FormatRegister2 01C6 685C SPIFMT3 SPI Data FormatRegister3 01C6 6860 INTVEC0 SPI InterruptVectorRegister0 01C6 6864 INTVEC1 SPI InterruptVectorRegister1 01C6 6868 – 01C6 6FFF – Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 313 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.23.3 SPI ElectricalData/Timing

Master Mode — General Table7-111.GeneralSwitchingCharacteristicsinMaster Mode (1) NO. PARAMETER MIN MAX UNIT 1 tc(CLK) Cycletime,SPI_CLK 2P ns 2 tw(CLKH) Pulsewidth,SPI_CLK high P ns 3 tw(CLKL) Pulsewidth,SPI_CLK low P ns Outputsetuptime,SPI_SIMO valid(1stbit)beforeinitialSPI_CLK risingedge,3-/4-/5-pinmode, 2P polarity= 0,phase = 0 Outputsetuptime,SPI_SIMO valid(1stbit)beforeinitialSPI_CLK risingedge,3-/4-/5-pinmode, 0.5T+ 2P polarity= 0,phase = 1 4 tosu(SIMO-CLK) ns Outputsetuptime,SPI_SIMO valid(1stbit)beforeinitialSPI_CLK fallingedge,3-/4-/5-pinmode, 2P polarity= 1,phase = 0 Outputsetuptime,SPI_SIMO valid(1stbit)beforeinitialSPI_CLK fallingedge,3-/4-/5-pinmode, 0.5T+ 2P polarity= 1,phase = 1 Delaytime,SPI_CLK transmitrisingedge toSPI_SIMO outputvalid 5(subsequentbitdriven),3-/4-/5-pinmode, polarity= 0,phase = 0 Delaytime,SPI_CLK transmitfallingedge toSPI_SIMO output valid(subsequentbitdriven),3-/4-/5-pinmode, polarity= 0,phase 5 = 1 5 td(CLK-SIMO) ns Delaytime,SPI_CLK transmitfallingedge toSPI_SIMO output valid(subsequentbitdriven),3-/4-/5-pinmode, polarity= 1,phase 5 = 0 Delaytime,SPI_CLK transmitrisingedge toSPI_SIMO outputvalid 5(subsequentbitdriven),3-/4-/5-pinmode, polarity= 1,phase = 1 Outputholdtime,SPI_SIMO valid(exceptfinalbit)afterreceive fallingedge ofSPI_CLK, 0.5T– 4 3-/4-/5-pinmode, polarity= 0,phase = 0 Outputholdtime,SPI_SIMO valid(exceptfinalbit)afterreceive risingedge ofSPI_CLK, 0.5T– 4 3-/4-/5-pinmode, polarity= 0,phase = 1 6 toh(CLK-SIMO) ns Outputholdtime,SPI_SIMO valid(exceptfinalbit)afterreceive risingedge ofSPI_CLK, 0.5T– 4 3-/4-/5-pinmode, polarity= 1,phase = 0 Outputholdtime,SPI_SIMO valid(exceptfinalbit)afterreceive fallingedge ofSPI_CLK, 0.5T– 4 3-/4-/5-pinmode, polarity= 1,phase = 1 (1) T = periodofSPI_CLK; P = periodofSPI coreclock

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-112.GeneralInputTiming Requirements inMaster Mode NO. MIN MAX UNIT Setuptime,SPI_SOMI validbeforereceivefallingedge of SPI_CLK, 3-/4-/5-pinmode, 4 polarity= 0,phase = 0 Setuptime,SPI_SOMI validbeforereceiverisingedge of SPI_CLK, 3-/4-/5-pinmode, 4 polarity= 0,phase = 1 7 tsu(SOMI-CLK) ns Setuptime,SPI_SOMI validbeforereceiverisingedge of SPI_CLK, 3-/4-/5-pinmode, 4 polarity= 1,phase = 0 Setuptime,SPI_SOMI validbeforereceivefallingedge of SPI_CLK, 3-/4-/5-pinmode, 4 polarity= 1,phase = 1 Holdtime,SPI_SOMI validafterreceivefallingedge ofSPI_CLK, 23-/4-/5-pinmode, polarity= 0,phase = 0 Holdtime,SPI_SOMI validafterreceiverisingedge ofSPI_CLK, 3- 2/4-/5-pinmode, polarity= 0,phase = 1 8 th(CLK-SOMI) ns Holdtime,SPI_SOMI validafterreceiverisingedge ofSPI_CLK, 3- 2/4-/5-pinmode, polarity= 1,phase = 0 Holdtime,SPI_SOMI validafterreceivefallingedge ofSPI_CLK, 23-/4-/5-pinmode, polarity= 1,phase = 1 Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 315 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com SlaveMode — General Table7-113.GeneralSwitchingCharacteristicsinSlaveMode (For3-/4-/5-PinModes) (1) NO. PARAMETER MIN MAX UNIT Delaytime,transmitrisingedge ofSPI_CLK toSPI_SOMI output 15valid,3-/4-/5-pinmode, polarity= 0,phase = 0 Delaytime,transmitfallingedge ofSPI_CLK toSPI_SOMI output 15valid,3-/4-/5-pinmode, polarity= 0,phase = 1 13 td(CLK-SOMI) ns Delaytime,transmitfallingedge ofSPI_CLK toSPI_SOMI output 15valid,3-/4-/5-pinmode, polarity= 1,phase = 0 Delaytime,transmitrisingedge ofSPI_CLK toSPI_SOMI output 15valid,3-/4-/5-pinmode, polarity= 1,phase = 1 Outputholdtime,SPI_SOMI valid(exceptfinalbit)afterreceive 0.5T– 4fallingedge ofSPI_CLK, 3-/4-/5-pinmode, polarity= 0,phase = 0 Outputholdtime,SPI_SOMI valid(exceptfinalbit)afterreceive 0.5T– 4risingedge ofSPI_CLK, 3-/4-/5-pinmode, polarity= 0,phase = 1 14 toh(CLK-SOMI) ns Outputholdtime,SPI_SOMI valid(exceptfinalbit)afterreceive 0.5T– 4risingedge ofSPI_CLK, 3-/4-/5-pinmode, polarity= 1,phase = 0 Outputholdtime,SPI_SOMI valid(exceptfinalbit)afterreceive 0.5T– 4fallingedge ofSPI_CLK, 3-/4-/5-pinmode, polarity= 1,phase = 1 (1) T = periodofSPI_CLK

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-114.GeneralInputTiming Requirements inSlaveMode (1) NO. MIN MAX UNIT 9 tc(CLK) Cycletime,SPI_CLK 2P ns 10 tw(CLKH) Pulsewidth,SPI_CLK high P ns 11 tw(CLKL) Pulsewidth,SPI_CLK low P ns Setuptime,SPI_SIMO datavalidbeforereceivefallingedge of SPI_CLK, 3-/4-/5-pinmode, 2P polarity= 0,phase = 0 Setuptime,SPI_SIMO datavalidbeforereceiverisingedge of SPI_CLK, 3-/4-/5-pinmode, 2P polarity= 0,phase = 1 15 tsu(SIMO-CLK) ns Setuptime,SPI_SIMO datavalidbeforereceiverisingedge of SPI_CLK, 3-/4-/5-pinmode, 2P polarity= 1,phase = 0 Setuptime,SPI_SIMO datavalidbeforereceivefallingedge of SPI_CLK, 3-/4-/5-pinmode, 2P polarity= 1,phase = 1 Holdtime,SPI_SIMO datavalidafterreceivefallingedge of SPI_CLK, 3-/4-/5-pinmode, 2 polarity= 0,phase = 0 Holdtime,SPI_SIMO datavalidafterreceiverisingedge of SPI_CLK, 3-/4-/5-pinmode, 2 polarity= 0,phase = 1 16 th(CLK-SIMO) ns Holdtime,SPI_SIMO datavalidafterreceiverisingedge of SPI_CLK, 3-/4-/5-pinmode, 2 polarity= 1,phase = 0 Holdtime,SPI_SIMO datavalidafterreceivefallingedge of SPI_CLK, 3-/4-/5-pinmode, 2 polarity= 1,phase = 1 (1) P = periodofSPI coreclock Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 317 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Master Mode — Additional Table7-115.AdditionalOutput SwitchingCharacteristicsof4-PinEnable Option inMaster Mode (1)(2) NO. PARAMETER MIN MAX UNIT Delaytime,slaveassertionofSPI_EN activetofirstSPI_CLK 3P + 6risingedge frommaster,4-pinmode, polarity= 0,phase = 0 Delaytime,slaveassertionofSPI_EN activetofirstSPI_CLK 0.5T+ 3P + 6risingedge frommaster,4-pinmode, polarity= 0,phase = 1 17 td(EN-CLK) ns Delaytime,slaveassertionofSPI_EN activetofirstSPI_CLK 3P + 6fallingedge frommaster,4-pinmode, polarity= 1,phase = 0 Delaytime,slaveassertionofSPI_EN activetofirstSPI_CLK 0.5T+ 3P + 6fallingedge frommaster,4-pinmode, polarity= 1,phase = 1 (1) T = periodofSPI_CLK; P = periodofSPI coreclock (2) Figure7-87shows onlypolarity= 0,phase = 0 as an example.Inthiscase,theMasterSPI isreadywithnew databeforeSPI_EN assertion. Table7-116.AdditionalInputTiming Requirements of4-PinEnable Option inMaster Mode (1)(2) NO. MIN MAX UNIT Delaytime,max delayforslavetodeassertSPI_EN afterfinal SPI_CLK fallingedge,4-pinmode, 0.5T+ P polarity= 0,phase = 0 Delaytime,max delayforslavetodeassertSPI_EN afterfinal SPI_CLK fallingedge,4-pinmode, P polarity= 0,phase = 1 18 td(CLK-EN) ns Delaytime,max delayforslavetodeassertSPI_EN afterfinal SPI_CLK risingedge,4-pinmode, 0.5T+ P polarity= 1,phase = 0 Delaytime,max delayforslavetodeassertSPI_EN afterfinal SPI_CLK risingedge,4-pinmode, P polarity= 1,phase = 1 (1) T = periodofSPI_CLK; P = periodofSPI coreclock (2) Figure7-87shows onlypolarity= 0,phase = 0 as an example.Inthiscase,theMasterSPI isreadywithnew databeforeSPI_EN deassertion.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-117.AdditionalOutput SwitchingCharacteristicsof4-PinChip-SelectOption inMaster Mode (1)(2) NO. PARAMETER MIN MAX UNIT Outputsetuptime,SPI_CS[n]activebeforefirst SPI_CLK risingedge,polarity= 0,phase = 0, (C2TDELAY + 2)*P -6 SPIDELAY.C2TDELAY = 0 Outputsetuptime,SPI_CS[n]activebeforefirst SPI_CLK risingedge,polarity= 0,phase = 1, (C2TDELAY + 2)*P -6 SPIDELAY.C2TDELAY = 0 19 tosu(CS-CLK) (3) ns Outputsetuptime,SPI_CS[n]activebeforefirst SPI_CLK fallingedge,polarity= 1,phase = 0, (C2TDELAY + 2)*P -6 SPIDELAY.C2TDELAY = 0 Outputsetuptime,SPI_CS[n]activebeforefirst SPI_CLK fallingedge,polarity= 1,phase = 1, (C2TDELAY + 2)*P -6 SPIDELAY.C2TDELAY = 0 Delaytime,finalSPI_CLK fallingedge tomaster deassertingSPI_CS[n],polarity= 0,phase = 0, (T2CDELAY + 1)*P -6SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD notenabled Delaytime,finalSPI_CLK fallingedge tomaster deassertingSPI_CS[n],polarity= 0,phase = 1, (T2CDELAY + 1)*P -6SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD notenabled 20 td(CLK-CS) ns Delaytime,finalSPI_CLK risingedge tomaster deassertingSPI_CS[n],polarity= 1,phase = 0, (T2CDELAY + 1)*P -6SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD notenabled Delaytime,finalSPI_CLK risingedge tomaster deassertingSPI_CS[n],polarity= 1,phase = 1, (T2CDELAY + 2)*P -6SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD notenabled (1) P = periodofSPI coreclock (2) Figure7-87shows onlypolarity= 0,phase = 0 as an example. (3) The MasterSPI isreadywithnew databeforeSPI_CS[n]assertion. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 319 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-118.AdditionalOutput SwitchingCharacteristicsof5-PinOption inMaster Mode (1) NO. PARAMETER MIN MAX UNIT Delaytime,finalSPI_CLK fallingedge to masterdeassertingSPI_CS[n], (T2CDELAY + 2)*P -6polarity= 0,phase = 0,SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD notenabled Delaytime,finalSPI_CLK risingedge tomaster deassertingSPI_CS[n], polarity= 0,phase = 1, (T2CDELAY + 2)*P -6 SPIDELAY.T2CDELAY[4:0] = 0, SPIDAT1.CSHOLD notenabled32 td(CLK-CS) (2) ns Delaytime,finalSPI_CLK risingedge tomaster deassertingSPI_CS[n], (T2CDELAY + 2)*P -6polarity= 1,phase = 0,SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD notenabled Delaytime,finalSPI_CLK fallingedge to masterdeassertingSPI_CS[n], (T2CDELAY + 2)*P -6polarity= 1,phase = 1,SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD notenabled Outputsetuptime,SPI_CS[n]activebeforefirst SPI_CLK risingedge,polarity= 0, (C2TDELAY + 2)*P -6 phase = 0,SPIDELAY.C2TDELAY = 0 Outputsetuptime,SPI_CS[n]activebeforefirst SPI_CLK risingedge,polarity= 0, (C2TDELAY + 2)*P -6 phase = 1,SPIDELAY.C2TDELAY = 0tosu(CS-CLK) (2) 22 ns(3) Outputsetuptime,SPI_CS[n]activebeforefirst SPI_CLK fallingedge,polarity= 1, (C2TDELAY + 2)*P -6 phase = 0,SPIDELAY.C2TDELAY = 0 Outputsetuptime,SPI_CS[n]activebeforefirst SPI_CLK fallingedge,polarity= 1, (C2TDELAY + 2)*P -6 phase = 1,SPIDELAY.C2TDELAY = 0 Delaytime,SPI_EN assertionlowtofirst SPI_CLK risingedge,polarity= 0, 0.5T+ Pphase = 0,SPI_EN was initiallydeassertedand SPI_CLK delayed Delaytime,SPI_EN assertionlowtofirst SPI_CLK risingedge,polarity= 0, Pphase = 1,SPI_EN was initiallydeassertedand SPI_CLK delayed 23 td(CLK-EN) (2) ns Delaytime,SPI_EN assertionlowtofirst SPI_CLK fallingedge,polarity= 1, 0.5T+ Pphase = 0,SPI_EN was initiallydeassertedand SPI_CLK delayed Delaytime,SPI_EN assertionlowtofirst SPI_CLK fallingedge,polarity= 1, Pphase = 1,SPI_EN was initiallydeassertedand SPI_CLK delayed (1) T = periodofSPI_CLK; P = periodofSPI coreclock (2) Figure7-87shows onlypolarity= 0,phase = 0 as an example. (3) SPI_EN isimmediatelyasserted,theSPI Masterisreadywithnew databeforeSPI_CS[n]assertion.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-119.AdditionalInputTiming Requirements of5-PinOption inMaster Mode (1) NO. MIN MAX MIN MAX UNIT Delaytime,max delayforslave SPI todriveSPI_ENA validafter 21 td(CSL-ENA) masterassertsSPI_CS[n]to 0.5P 0.5D ns delaythemasterfrombeginning thenexttransfer Delaytime,max delayforslave todeassertSPI_ENA afterfinal 0.5T 0.5TSPI_CLK fallingedge,5-pin mode, polarity= 0,phase = 0 Delaytime,max delayforslave todeassertSPI_ENA afterfinal 0 0SPI_CLK fallingedge,5-pin mode, polarity= 0,phase = 1 31 td(CLK-ENA) (2)(3) ns Delaytime,max delayforslave todeassertSPI_ENA afterfinal 0.5T 0.5TSPI_CLK risingedge,5-pin mode, polarity= 1,phase = 0 Delaytime,max delayforslave todeassertSPI_ENA afterfinal 0 0SPI_CLK risingedge,5-pin mode, polarity= 1,phase = 1 (1) T = periodofSPI_CLK; P = periodofSPI coreclock;D = periodof24-MHz clock (2) SPI masterisreadywithnew databeforeSPI_ENA deassertion. (3) Figure7-87shows onlypolarity= 0,phase = 0 as an example. SlaveMode — Additional Table7-120.AdditionalOutput SwitchingCharacteristicsof4-PinEnable Option inSlaveMode (1) NO. PARAMETER MIN MAX UNIT Delaytime,finalSPI_CLK fallingedge to slavedeassertingSPI_EN, polarity= 0, P – 6 3P + 15 phase = 0 Delaytime,finalSPI_CLK fallingedge to slavedeassertingSPI_EN, polarity= 0, 0.5T+ P – 6 0.5T+ 3P + 15 phase = 1 SPI24 td(CLK-EN) (2) ns Delaytime,finalSPI_CLK risingedge toslave deassertingSPI_EN, polarity= 1, P – 6 3P + 15 phase = 0 Delaytime,finalSPI_CLK risingedge toslave deassertingSPI_EN, polarity= 1, 0.5T+ P – 6 0.5T+ 3P + 15 phase = 1 (1) T = periodofSPI_CLK; P = periodofSPI coreclock (2) Figure7-88shows onlypolarity= 0,phase = 0 as an example. Table7-121.AdditionalOutput SwitchingCharacteristicsof4-PinChip-SelectOption inSlaveMode (1) NO. PARAMETER MIN MAX UNIT Delaytime,masterassertingSPI_CS[n]toslavedrivingSPI_SOMI27 td(CSL-SOMI) P + 6 nsdatavalid Disabletime,masterdeassertingSPI_CS[n]toslavedriving28 tdis(CSH-SOMI) P + 6 nsSPI_SOMI highimpedance (1) T = periodofSPI_CLK; P = periodofSPI coreclock Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 321 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-122.AdditionalInputTiming Requirements of4-PinChip-SelectOption inSlaveMode (1) NO. MIN MAX UNIT Setuptime,SPI_CS[n]assertedatslavetofirstSPI_CLK edge25 tsu(CSL-CLK) 2P + 6 ns(risingorfalling)atslave Delaytime,finalfallingedge SPI_CLK toSPI_CS[n]deasserted, 0.5T+ P + 6polarity= 0,phase = 0 Delaytime,finalfallingedge SPI_CLK toSPI_CS[n]deasserted, P + 6polarity= 0,phase = 1 26 td(CLK-CSH) (2) ns Delaytime,finalrisingedge SPI_CLK toSPI_CS[n]deasserted, 0.5T+ P + 6polarity= 1,phase = 0 Delaytime,finalrisingedge SPI_CLK toSPI_CS[n]deasserted, P + 6polarity= 1,phase = 1 (1) T = periodofSPI_CLK; P = periodofSPI coreclock (2) Figure7-88shows onlypolarity= 0,phase = 0 as an example. Table7-123.AdditionalOutput SwitchingCharacteristicsof5-PinOption inSlaveMode (1) NO. PARAMETER MIN MAX UNIT Enabletime,masterassertingSPI_CS[n]toslavedrivingSPI33 ten(CSL-SOMI) P + 6 nsSPI_SOMI valid Disabletime,masterdeassertingSPI_CS[n]toslavedrivingSPI34 tdis(CSH-SOMI) P + 6 nsSPI_SOMI highimpedance SPI29 ten(CSL-EN) Enabletime,masterassertingSPI_CS[n]toslavedrivingSPI_EN 6 ns Disabletime,finalclockreceivefallingedge ofSPI_CLK toslave driveSPI_EN highimpedance,polarity= 0,phase = 0, 1.5P+ 6 SPIINT0.ENABLE HIGHZ = 1 Disabletime,finalclockreceiverisingedge ofSPI_CLK toslave driveSPI_EN highimpedance,polarity= 0,phase = 1, 1.5P+ 6 SPIINT0.ENABLE HIGHZ = 1 SPI30 tdis(CLK-ENZ) (2) ns Disabletime,finalclockreceiverisingedge ofSPI_CLK toslave driveSPI_EN highimpedance,polarity= 1,phase = 0, 1.5P+ 6 SPIINT0.ENABLE HIGHZ = 1 Disabletime,finalclockreceivefallingedge ofSPI_CLK toslave driveSPI_EN highimpedance,polarity= 1,phase = 1, 1.5P+ 6 SPIINT0.ENABLE HIGHZ = 1 Disabletime,SPI_CS[n]deassertiontoslavedriveSPI_EN high impedance,polarity= 0,phase = 0, P + 6 SPIINT0.ENABLE HIGHZ = 1 Disabletime,SPI_CS[n]deassertiontoslavedriveSPI_EN high impedance,polarity= 0,phase = 1, P + 6 SPIINT0.ENABLE HIGHZ = 1 37 tdis(CSH-ENH) (2) ns Disabletime,SPI_CS[n]deassertiontoslavedriveSPI_EN high impedance,polarity= 1,phase = 0, P + 6 SPIINT0.ENABLE HIGHZ = 1 Disabletime,SPI_CS[n]deassertiontoslavedriveSPI_EN high impedance,polarity= 1,phase = 1, P + 6 SPIINT0.ENABLE HIGHZ = 1 Delaytime,finalclockreceiveedge on SPI_CLK toslave deassertingSPI_EN, polarity= 0,phase = 0, 3P + 15 SPIINT0.ENABLE HIGHZ = 0 Delaytime,finalclockreceiveedge on SPI_CLK toslave 0.5T+ 3P +deassertingSPI_EN, polarity= 0,phase = 1, 15SPIINT0.ENABLE HIGHZ = 0 38 td(CLK-ENZ) (2) ns Delaytime,finalclockreceiveedge on SPI_CLK toslave deassertingSPI_EN, polarity= 1,phase = 0, 3P + 15 SPIINT0.ENABLE HIGHZ = 0 Delaytime,finalclockreceiveedge on SPI_CLK toslave 0.5T+ 3P +deassertingSPI_EN, polarity= 1,phase = 1, 15SPIINT0.ENABLE HIGHZ = 0 (1) T = periodofSPI_CLK; P = periodofSPI coreclock (2) Figure7-88shows onlypolarity= 0,phase = 0 as an example.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-123.AdditionalOutput SwitchingCharacteristicsof5-PinOption inSlaveMode (1) (continued) NO. PARAMETER MIN MAX UNIT Delaytime,SPI_CS[n]deassertiontoslavedeassertingSPI_EN, 6polarity= 0,phase = 0,SPIINT0.ENABLE HIGHZ = 0 Delaytime,SPI_CS[n]deassertiontoslavedeassertingSPI_EN, 6polarity= 0,phase = 1,SPIINT0.ENABLE HIGHZ = 0 39 td(CSH-ENH) (2) ns Delaytime,SPI_CS[n]deassertiontoslavedeassertingSPI_EN, 6polarity= 1,phase = 0,SPIINT0.ENABLE HIGHZ = 0 Delaytime,SPI_CS[n]deassertiontoslavedeassertingSPI_EN 6polarity= 1,phase = 1,SPIINT0.ENABLE HIGHZ = 0 Table7-124.AdditionalInputTiming Requirements of5-PinOption inSlaveMode (1) NO. MIN MAX UNIT Delaytime,SPI_CS[n]assertedatslavetofirstclockedge (rising35 td(CSL-CLK) P nsorfalling)ofSPI_CLK atslave Delaytime,SPI_CLK fallingedge toSPI_CS[n]deasserted, 0.5T+ P + 6polarity= 0,phase = 0 Delaytime,SPI_CLK fallingedge toSPI_CS[n]deasserted, P + 6polarity= 0,phase = 1 36 td(CLK-CSH) (2) ns Delaytime,SPI_CLK risingedge toSPI_CS[n]deasserted,polarity 0.5T+ P + 6= 1,phase = 0 Delaytime,SPI_CLK risingedge toSPI_CS[n]deasserted,polarity P + 6= 1,phase = 1 (1) T = periodofSPI_CLK; P = periodofSPI coreclock (2) Figure7-88shows onlypolarity= 0,phase = 0 as an example. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 323 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI MO(0) MO(1) MO(n-1) MO(n) MI(0) MI(1) MI(n-1) MI(n) MO(n) MI(n-1) MO(1) 4 5 5 6 MASTER□MODE MASTER□MODE MASTER□MODE MASTER□MODE MO(0) MO(1) MO(n-1) MI(n)MI(n-1)MI(1)MI(0) MO(0) MO(1) MO(n-1) MO(n) MI(n)MI(1)MI(0) MO(0) MO(n-1) MO(n) MI(n)MI(n-1)MI(1)MI(0) TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-85.SPI Timings— Master Mode

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SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SI(1) SI(n-1) SI(n) SO(0) SO(1) SO(n-1) SO(n) SI(0) SI(1) SI(n) SO(0) SO(1) SLAVE□MODE SLAVE□MODE POLARITY =□0□PHASE□=□1 SLAVE□MODE POLARITY =□1□PHASE□=□0 SLAVE□MODE SI(1)SI(0) SI(n-1) SO(n-1) SO(n) SO(n-1) SI(n)SI(n-1)SI(1)SI(0) SO(n)SO(1)SO(0) SI(n)SI(n-1) SO(n-1) SO(n)SO(1)SO(0) SI(0) TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 A. The firstbitoftransmitdatabecomes validon theSPI_SOMI pinwhen softwarewritestotheSPIDAT0/1 register(s). See theTMS320DM646x DMSoC SerialPeripheralInterface(SPI)User's Guide (literaturenumber SPRUER4 ). Figure7-86.SPI Timings— SlaveMode Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 325 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

MASTER□MODE□4□PIN□WITH□CHIP SELECT SPI_CLK SPI_SIMO SPI_SOMI SPI_EN SPI_CLK SPI_SIMO SPI_SOMI SPI_CS[n] SPI_CLK SPI_SIMO SPI_SOMI SPI_EN SPI_CS[n] MO(0) MASTER□MODE□4□PIN□WITH□ENABLE MASTER□MODE□5□PIN A.□□□Deselected□is□programmable□either□high□or□□3-state□(requires□external□pullup) DESEL(A) DESEL(A) MO(0) MO(1) MO(n-1) MO(n) MI(n)MI(n-1)MI(1)MI(0) MO(0) MO(1) MO(n-1) MO(n) MI(n)MI(n-1)MI(1)MI(0) MO(1) MO(n-1) MO(n) MI(n-1)MI(1)MI(0) MI(n) TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Figure7-87.SPI Timings— Master Mode (4-Pinand 5-Pin)

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SPI_CLK SPI_SOMI SPI_SIMO SPI_EN SPI_CLK SPI_SOMI SPI_SIMO SPI_CS[n] SPI_CLK SPI_SOMI SPI_SIMO SPI_EN SPI_CS[n] SO(1) SO(n-1) SO(n) SO(0) SI(1) SO(0) SO(n-1) SO(n) 30,□38 SLAVE□MODE□4□PIN□WITH□ENABLE SLAVE□MODE□4□PIN□WITH□CHIP SELECT SLAVE□MODE□5□PIN DESEL(A) DESEL(A) 37,□39 A.□□□Deselected□is□programmable□either□high□or□□3-state□(requires□external□pullup) SO(n) SO(0) SI(0) SI(1) SI(n-1) SI(n) SO(n-1) SI(0) SI(n-1) SI(n) SI(0) SI(1) SI(n-1) SI(n) SO(1) SO(1) TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-88.SPI Timings— SlaveMode (4-Pinand 5-Pin) Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 327 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.24 UniversalAsynchronouse Receiver/Transmitter(UART)

The UART performsserial-to-parallelconversionson datareceivedfroma peripheraldeviceand parallel- to-serialconversionon datareceivedfromtheCPU.

7.24.1 UART Device-SpecificInformation

DM6467 providesup to3 UART peripheralinterfacesdependingon theselectedpinmultiplexing. Each UART has thefollowingfeatures:

SelectableUART/IrDA (SIR/MIR)/CIRmodes
Dual64 entryFIFOs forreceivedand transmitteddatapayload
Programmable and selectabletransmitand receiveFIFO triggerlevelsfor DMA and interrupt generation
Frequencyprescalervaluesfrom0 to16 383 itgeneratetheappropriatebaud rates
Two DMA requestsand one interruptrequesttothesystem UART functionsinclude:
Baud-rateup to1.8432Mbit/s
Software/Hardwareflowcontrol – Programmable Xon/Xoffcharacters – Programmable Auto-RTS and Auto-CTS
Programmable serialinterfacescharacteristics – 5,6,7,or8-bitcharacters – Even,odd,mark,space,orno paritybitgenerationand detection – 1,1.5,or2 stopbitgeneration
AdditionalModem controlfunctions(UDTR0, UDSR0, UDCD0, and URIN0) [UART0 only] IR-IrDAfunctionsinclude:
Bothslowinfrared(SIR,baud-rateup to115.2Kbit/s)and medium infrared(MIR,baud-rateup to0.576 Mbits/s)supported
Supportsframingerror,cyclicredundancycheck(CRC) error,and abortpattern(SIR,MIR) detection
8-entrystatusFIFO (withselectabletriggerlevels)availabletomonitorframelengthand frameerrors IR-CIRfunctionsinclude:
Consumer Infrared(CIR)remotecontrolmode withprogrammabledataencoding

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7.24.2 UART PeripheralRegisterDescription(s)

Table7-125shows theUART registername summary. Table7-126,Table7-127,and Table7-128show theUART0/1/2 registers,respectivelyalongwiththeirconfigurationrequirements. Table7-125.UART RegisterSummary ACRONYM REGISTER NAME ACRONYM REGISTER NAME RHR ReceiveHoldingRegister RXFLH ReceiveFrame LengthHighRegister THR TransmitHoldingRegister BLR BOF ControlRegister IER InterruptEnableRegister ACREG AuxilliaryControlRegister IIR InterruptIdentificationRegister SCR SupplementaryControlRegister FCR FIFO ControlRegister SSR SupplementaryStatusRegister LCR LineControlRegister EBLR BOF LengthRegister MCR Modem ControlRegister MVR Module VersionRegister LSR LineStatusRegister SYSC System ConfigurationRegister MSR Modem StatusRegister SYSS System StatusRegister SPR ScratchpadRegister WER Wake-up EnableRegister TCR TransmissionControlRegister CFPS CarrierFrequencyPrescalerRegister TLR TriggerLevelRegister DLL DivisorLatchLow Register MDR1 Mode DefinitionRegister1 DLH DivisorLatchHighRegister MDR2 Mode DefinitionRegister2 UASR UART AutobaudingStatusRegister SFLSR StatusFIFO LineStatusRegister EFR Enhanced FeatureRegister RESUME Resume Register XON1 UART XON1 CharacterRegister SFREGL StatusFIFO RegisterLow XON2 UART XON2 CharacterRegister SFREGH StatusFIFO RegisterHigh XOFF1 UART XOFF1 CharacterRegister TXFLL TransmitFrame LengthLow Register XOFF2 UART XOFF2 CharacterRegister TXFLH TransmitFrame LengthHighRegister ADDR1 IrDAAddress1 Register RXFLL ReceiveFrame LengthLow Register ADDR2 IrDAAddress2 Register Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 329 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-126.UART0 – UART/IrDA/CIR RegisterProgram Map HEX ADDRESS REGISTER RANGE LCR[7] = 0 LCR[7] = 1 & LCR[7:0]≠ 0xBF LCR[7:0]= 0xBF READ WRITE READ WRITE READ WRITE 0x01C2 0000 RHR THR DLL DLL DLL DLL 0x01C2 0004 IER(1) IER(1) DLH DLH DLH DLH 0x01C2 0008 IIR FCR (2) IIR FCR (2) EFR EFR 0x01C2 000C LCR LCR LCR LCR LCR LCR 0x01C2 0010 MCR (2) MCR (2) MCR (2) MCR (2) XON1/ADDR1 XON1/ADDR1 0x01C2 0014 LSR – LSR – XON2/ADR2 XON2/ADDR2 0x01C2 0018 MSR/TCR (3) TCR (3) MSR/TCR (3) TCR (3) XOFF1/TCR (3) XOFF1/TCR (3) 0x01C2 001C SPR/TLR (3) SPR/TLR (3) SPR/TLR (3) SPR/TLR (3) XOFF2/TLR (3) XOFF2/TLR (3) 0x01C2 0020 MDR1 MDR1 MDR1 MDR1 MDR1 MDR1 0x01C2 0024 MDR2 MDR2 MDR2 MDR2 MDR2 MDR2 0x01C2 0028 SFLSR TXFLL SFLSR TXFLL SFLSR TXFLL 0x01C2 002C RESUME TXFLH RESUME TXFLH RESUME TXFLH 0x01C2 0030 SFREGL RXFLL SFREGL RXFLL SFREGL RXFLL 0x01C2 0034 SFREGH RXFLH SFREGH RXFLH SFREGH RXFLH 0x01C2 0038 BLR BLR UASR – UASR – 0x01C2 003C ACREG ACREG – – – – 0x01C2 0040 SCR SCR SCR SCR SCR SCR 0x01C2 0044 SSR – SSR – SSR – 0x01C2 0048 EBLR EBLR – – – – 0x01C2 0050 MVR – MVR – MVR – 0x01C2 0054 SYSC SYSC SYSC SYSC SYSC SYSC 0x01C2 0058 SYSS – SYSS – SYSS – 0x01C2 005C WER WER WER WER WER WER 0x01C2 0060 CFPS CFPS CFPS CFPS CFPS CFPS 0x01C2 007F (1) InUART modes, IER.[7:4]can onlybe writtenwhen ENHANCED_EN inEFR = 1.InIrDA/CIRmodes, ENHANCED_EN inEFR has no impacton theaccesstoIER.[7:4]. (2) MCR.[7:5]and theTX_FIFO_TRIG bitsinFCR can onlybe writtentowhen theENHANCED_EN bitinEFR = 1. (3) Transmissioncontrolregister(TCR) and triggerlevelregister(TLR)areaccessibleonlywhen theENHANCED_EN bitintheEFR =1 and theTCR_TLR bitintheMCR = 1.

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Table7-127.UART1 – UART/IrDA/CIR RegisterProgram Map HEX ADDRESS REGISTER RANGE LCR[7] = 0 LCR[7] = 1 & LCR[7:0]≠ 0xBF LCR[7:0]= 0xBF READ WRITE READ WRITE READ WRITE 0x01C2 0400 RHR THR DLL DLL DLL DLL 0x01C2 0404 IER(1) IER(1) DLH DLH DLH DLH 0x01C2 0408 IIR FCR (2) IIR FCR (2) EFR EFR 0x01C2 040C LCR LCR LCR LCR LCR LCR 0x01C2 0410 MCR (2) MCR (2) MCR (2) MCR (2) XON1/ADDR1 XON1/ADDR1 0x01C2 0414 LSR – LSR – XON2/ADR2 XON2/ADDR2 0x01C2 0418 MSR/TCR (3) TCR (3) MSR/TCR (3) TCR (3) XOFF1/TCR (3) XOFF1/TCR (3) 0x01C2 041C SPR/TLR (3) SPR/TLR (3) SPR/TLR (3) SPR/TLR (3) XOFF2/TLR (3) XOFF2/TLR (3) 0x01C2 0420 MDR1 MDR1 MDR1 MDR1 MDR1 MDR1 0x01C2 0424 MDR2 MDR2 MDR2 MDR2 MDR2 MDR2 0x01C2 0428 SFLSR TXFLL SFLSR TXFLL SFLSR TXFLL 0x01C2 042C RESUME TXFLH RESUME TXFLH RESUME TXFLH 0x01C2 0430 SFREGL RXFLL SFREGL RXFLL SFREGL RXFLL 0x01C2 0434 SFREGH RXFLH SFREGH RXFLH SFREGH RXFLH 0x01C2 0438 BLR BLR UASR – UASR – 0x01C2 043C ACREG ACREG – – – – 0x01C2 0440 SCR SCR SCR SCR SCR SCR 0x01C2 0444 SSR – SSR – SSR – 0x01C2 0448 EBLR EBLR – – – – 0x01C2 0450 MVR – MVR – MVR – 0x01C2 0454 SYSC SYSC SYSC SYSC SYSC SYSC 0x01C2 0458 SYSS – SYSS – SYSS – 0x01C2 045C WER WER WER WER WER WER 0x01C2 0460 CFPS CFPS CFPS CFPS CFPS CFPS 0x01C2 047F (1) InUART modes, IER.[7:4]can onlybe writtenwhen ENHANCED_EN inEFR = 1.InIrDA/CIRmodes, ENHANCED_EN inEFR has no impacton theaccesstoIER.[7:4]. (2) MCR.[7:5]and theTX_FIFO_TRIG bitsinFCR can onlybe writtentowhen theENHANCED_EN bitinEFR = 1. (3) Transmissioncontrolregister(TCR) and triggerlevelregister(TLR)areaccessibleonlywhen theENHANCED_EN bitintheEFR =1 and theTCR_TLR bitintheMCR = 1. Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 331 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-128.UART2 – UART/IrDA/CIR RegisterProgram Map HEX ADDRESS REGISTER RANGE LCR[7] = 0 LCR[7] = 1 & LCR[7:0]≠ 0xBF LCR[7:0]= 0xBF READ WRITE READ WRITE READ WRITE 0x01C2 0800 RHR THR DLL DLL DLL DLL 0x01C2 0804 IER(1) IER(1) DLH DLH DLH DLH 0x01C2 0808 IIR FCR (2) IIR FCR (2) EFR EFR 0x01C2 080C LCR LCR LCR LCR LCR LCR 0x01C2 0810 MCR (2) MCR (2) MCR (2) MCR (2) XON1/ADDR1 XON1/ADDR1 0x01C2 0814 LSR – LSR – XON2/ADR2 XON2/ADDR2 0x01C2 0818 MSR/TCR (3) TCR (3) MSR/TCR (3) TCR (3) XOFF1/TCR (3) XOFF1/TCR (3) 0x01C2 081C SPR/TLR (3) SPR/TLR (3) SPR/TLR (3) SPR/TLR (3) XOFF2/TLR (3) XOFF2/TLR (3) 0x01C2 0820 MDR1 MDR1 MDR1 MDR1 MDR1 MDR1 0x01C2 0824 MDR2 MDR2 MDR2 MDR2 MDR2 MDR2 0x01C2 0828 SFLSR TXFLL SFLSR TXFLL SFLSR TXFLL 0x01C2 082C RESUME TXFLH RESUME TXFLH RESUME TXFLH 0x01C2 0830 SFREGL RXFLL SFREGL RXFLL SFREGL RXFLL 0x01C2 0834 SFREGH RXFLH SFREGH RXFLH SFREGH RXFLH 0x01C2 0838 BLR BLR UASR – UASR – 0x01C2 083C ACREG ACREG – – – – 0x01C2 0840 SCR SCR SCR SCR SCR SCR 0x01C2 0844 SSR – SSR – SSR – 0x01C2 0848 EBLR EBLR – – – – 0x01C2 0850 MVR – MVR – MVR – 0x01C2 0854 SYSC SYSC SYSC SYSC SYSC SYSC 0x01C2 0858 SYSS – SYSS – SYSS – 0x01C2 085C WER WER WER WER WER WER 0x01C2 0860 CFPS CFPS CFPS CFPS CFPS CFPS 0x01C2 087F (1) InUART modes, IER.[7:4]can onlybe writtenwhen ENHANCED_EN inEFR = 1.InIrDA/CIRmodes, ENHANCED_EN inEFR has no impacton theaccesstoIER.[7:4]. (2) MCR.[7:5]and theTX_FIFO_TRIG bitsinFCR can onlybe writtentowhen theENHANCED_EN bitinEFR = 1. (3) Transmissioncontrolregister(TCR) and triggerlevelregister(TLR)areaccessibleonlywhen theENHANCED_EN bitintheEFR =1 and theTCR_TLR bitintheMCR = 1.

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7.24.3 UART ElectricalData/Timing[Receive/Transmit]

Table7-129.Timing Requirements forUARTx Receive(1)(seeFigure7-89) -594,-729 NO. UNIT MIN MAX 4 tw(URXDB) Pulseduration,receivedatabit(URXDx) [15/30/100pF] 0.96U 1.05U ns 5 tw(URXSB) Pulseduration,receivestartbit[15/30/100pF] 0.96U 1.05U ns (1) U = UART baud time= 1/programmedbaud rate. Table7-130.SwitchingCharacteristicsOver Recommended OperatingConditionsforUARTx Transmit(1) (seeFigure7-89) -594,-729 NO. PARAMETER UNIT MIN MAX 1 f(baud) Maximum programmablebaud rate 128 kHz 2 tw(UTXDB) Pulseduration,transmitdatabit(UTXDx) [15/30/100pF] U -2 U + 2 ns 3 tw(UTXSB) Pulseduration,transmitstartbit[15/30/100pF] U -2 U + 2 ns (1) U = UART baud time= 1/programmedbaud rate. Figure7-89.UART Transmit/ReceiveTiming Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 333 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.24.4 IrDA InterfaceReceive/TransmitTimings

Table7-131.SignalingRate and Pulse DurationSpecificationinReceive Mode ELECTRICAL PULSE DURATION SIGNALING RATE UNIT MAX NOM MIN SIR MODE 2.4Kbit/s(Kbps) 1.41 78.1 88.55 μs 9.6Kbps 1.41 19.5 22.13 μs 19.2Kbps 1.41 9.75 11.07 μs 38.4Kbps 1.41 4.87 5.96 μs 57.6Kbps 1.41 3.25 4.34 μs 115.2Kbps 1.41 1.62 2.23 μs MIR MODE 0.576Mbit/s(Mbps) 297.2 416 518.8 ns Table7-132.Timing Requirements forIrDA Receive -594,-729 NO. UNIT MIN MAX 1 tr(URXD) Risetime,receivedatabitURXDx 200 ns 2 tf(URXD) Falltime,receivedatabitURXDx 200 ns Table7-133.SignalingRate and Pulse DurationSpecificationinTransmitMode ELECTRICAL PULSE DURATION SIGNALING RATE UNIT MAX NOM MIN SIR MODE 2.4Kbit/s(Kbps) 78.10 78.1 78.10 μs 9.6Kbps 19.50 19.5 19.50 μs 19.2Kbps 9.75 9.75 9.75 μs 38.4Kbps 4.87 4.87 4.87 μs 57.6Kbps 3.25 3.25 3.25 μs 115.2Kbps 1.62 1.62 1.62 μs MIR MODE 0.576Mbit/s(Mbps) 414.0 416.0 419.0 ns

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7.25 Inter-IntegratedCircuit(I2C)

The inter-integratedcircuit(I2C)module providesan interfacebetween DM6467 and otherdevices compliantwith PhilipsSemiconductorsInter-ICbus (I2C-bus™ ) specificationversion2.1. External components attachedto this2-wireserialbus can transmit/receive2 to 8-bitdata to/fromthe DMSoC throughtheI2C module.The I2C portdoes notsupportCBUS compatibledevices. The I2C portsupportsthefollowingfeatures:

CompatiblewithPhilipsI2C SpecificationRevision2.1(January2000)
Standardand FastModes from10 – 400 Kbps (nofail-safeI/Obuffers)
NoiseFiltertoRemove Noise50 ns orless
Seven-and Ten-BitDeviceAddressingModes
Master(Transmit/Receive)and Slave(Transmit/Receive)Functionality
Events:DMA, Interrupt,orPolling
Slew-RateLimitedOpen-DrainOutputBuffers For more detailedinformationon the I2C peripheral,see the TMS320DM646x DMSoC Inter-Integrated Circuit(I2C)Module User'sGuide (literaturenumber SPRUER0 ). Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 335 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.25.1 I2C PeripheralRegisterDescription(s)

Table7-134.I2C Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x1C2 1000 ICOAR I2C Own AddressRegister 0x1C2 1004 ICIMR I2C InterruptMask Register 0x1C2 1008 ICSTR I2C InterruptStatusRegister 0x1C2 100C ICCLKL I2C ClockDividerLow Register 0x1C2 1010 ICCLKH I2C ClockDividerHighRegister 0x1C2 1014 ICCNT I2C Data Count Register 0x1C2 1018 ICDRR I2C Data ReceiveRegister 0x1C2 101C ICSAR I2C SlaveAddressRegister 0x1C2 1020 ICDXR I2C Data TransmitRegister 0x1C2 1024 ICMDR I2C Mode Register 0x1C2 1028 ICIVR I2C InterruptVectorRegister 0x1C2 102C ICEMDR I2C ExtendedMode Register 0x1C2 1030 ICPSC I2C PrescalerRegister 0x1C2 1034 ICPID1 I2C PeripheralIdentificationRegister1 0x1C2 1038 ICPID2 I2C PeripheralIdentificationRegister2

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7.25.2 I2C ElectricalData/Timing

Table7-135.Timing Requirements forI2C Timings(1)(seeFigure7-90) -594,-729 STANDARDNO. FAST MODE UNITMODE MIN MAX MIN MAX 1 tc(SCL) Cycletime,SCL 10 2.5 µs Setuptime,SCL highbeforeSDA low(fora repeatedSTART2 tsu(SCLH-SDAL) 4.7 0.6 µscondition) Holdtime,SCL lowafterSDA low(fora START and a repeated3 th(SCLL-SDAL) 4 0.6 µsSTART condition) 4 tw(SCLL) Pulseduration,SCL low 4.7 1.3 µs 5 tw(SCLH) Pulseduration,SCL high 4 0.6 µs 6 tsu(SDAV-SCLH) Setuptime,SDA validbeforeSCL high 250 100(2) ns 7 th(SDA-SCLL) Holdtime,SDA validafterSCL low 0(3) 0(3) 0.9(4) µs Pulseduration,SDA highbetween STOP and START8 tw(SDAH) 4.7 1.3 µsconditions 20 + 0.1Cb9 tr(SDA) Risetime,SDA 1000 300 ns(5) 20 + 0.1Cb10 tr(SCL) Risetime,SCL 1000 300 ns(5) 20 + 0.1Cb11 tf(SDA) Falltime,SDA 300 300 ns(5) 20 + 0.1Cb12 tf(SCL) Falltime,SCL 300 300 ns(5) 13 tsu(SCLH-SDAH) Setuptime,SCL highbeforeSDA high(forSTOP condition) 4 0.6 µs 14 tw(SP) Pulseduration,spike(mustbe suppressed) 0 50 ns

15 C b

(5) Capacitiveloadforeach bus line 400 400 pF (1) The I2C pinsSDA and SCL do notfeaturefail-safeI/Obuffers.These pinscouldpotentiallydraw currentwhen thedeviceispowered down. (2) A Fast-modeI2C-bus™ devicecan be used ina Standard-modeI2C-bus system,buttherequirementtsu(SDA-SCLH)≥ 250 ns must thenbe met.Thiswillautomaticallybe thecase ifthedevicedoes notstretchtheLOW periodoftheSCL signal.Ifsuch a devicedoes stretch theLOW periodoftheSCL signal,itmust outputthenextdatabittotheSDA linetr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (accordingtotheStandard-modeI2C-Bus Specification)beforetheSCL lineisreleased. (3) A devicemust internallyprovidea holdtimeofatleast300 ns fortheSDA signal(referredtotheVIHmin oftheSCL signal)tobridgethe undefinedregionofthefallingedge ofSCL. (4) The maximum th(SDA-SCLL) has onlytobe met ifthedevicedoes notstretchthelowperiod[tw(SCLL)]oftheSCL signal. (5) C b = totalcapacitanceofone bus lineinpF.Ifmixed withHS-mode devices,fasterfall-timesareallowed. Figure7-90.I2C Receive Timings Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 337 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-136.SwitchingCharacteristicsforI2C Timings(1)(seeFigure7-91) -594,-729 STANDARDNO. PARAMETER FAST MODE UNITMODE MIN MAX MIN MAX 16 tc(SCL) Cycletime,SCL 10 2.5 µs Delaytime,SCL hightoSDA low(fora repeatedSTART17 td(SCLH-SDAL) 4.7 0.6 µscondition) Delaytime,SDA lowtoSCL low(fora START and a repeated18 td(SDAL-SCLL) 4 0.6 µsSTART condition) 19 tw(SCLL) Pulseduration,SCL low 4.7 1.3 µs 20 tw(SCLH) Pulseduration,SCL high 4 0.6 µs 21 td(SDAV-SCLH) Delaytime,SDA validtoSCL high 250 100 ns 22 tv(SCLL-SDAV) Validtime,SDA validafterSCL low 0 0 0.9 µs Pulseduration,SDA highbetween STOP and START23 tw(SDAH) 4.7 1.3 µsconditions 20 + 0.1Cb24 tr(SDA) Risetime,SDA 1000 300 ns(2) 20 + 0.1Cb25 tr(SCL) Risetime,SCL 1000 300 ns(2) 20 + 0.1Cb26 tf(SDA) Falltime,SDA 300 300 ns(2) 20 + 0.1Cb27 tf(SCL) Falltime,SCL 300 300 ns(2) 28 td(SCLH-SDAH) Delaytime,SCL hightoSDA high(forSTOP condition) 4 0.6 µs

29 C p Capacitanceforeach I2C pin 10 10 pF

(1) C b = totalcapacitanceofone bus lineinpF.Ifmixed withHS-mode devices,fasterfall-timesareallowed. (2) C b = totalcapacitanceofone bus lineinpF.Ifmixed withHS-mode devices,fasterfall-timesareallowed. Figure7-91.I2C TransmitTimings

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7.26 Pulse Width Modulator(PWM)

The PWM providesa way togeneratea pulseperiodicwaveform formotorcontrolorcan actas a digital- to-analogconverterwithsome externalcomponents.

7.26.1 PWM Device-SpecificInformation

The 2 DM6467 PulseWidthModulator(PWM) peripheralssupportthefollowingfeatures:

32-bitperiodcounter
32-bitfirst-phasedurationcounter
32-bitrepeatcountforone-shotoperation.One-shotoperationgeneratesN+1 periodsofwaveform,N beingtherepeatcountregistervalue.
Configurabletooperateineitherone-shotorcontinuousmode
Programmable bufferedperiodand first-phasedurationregisters
One-shotoperationtriggerableby VPIF or GPIO withprogrammable edge transitions.(low-to-highor high-to-low).
One-shotoperationgeneratesN+1 periodsofwaveform,N beingtherepeatcountregistervalue
ConfigurablePWM outputpininactivestate
Interruptand EDMA synchronizationevents
Emulationsupportforstoporfree-runoperation

7.26.2 PWM PeripheralRegisterDescription(s)

Table7-137and Table7-138show theregistermemory maps forPWM0/1. Table7-137.PWM0 Register HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 2000 PID PWM0 PeripheralIdentificationRegister 0x01C2 2004 PCR PWM0 PeripheralControlRegister 0x01C2 2008 CFG PWM0 ConfigurationRegister 0x01C2 200C START PWM0 StartRegister 0x01C2 2010 RPT PWM0 Repeat Count Register 0x01C2 2014 PER PWM0 PeriodRegister 0x01C2 2018 PH1D PWM0 First-PhaseDurationRegister 0x01C2 201C -0x01C2 23FF - Reserved Table7-138.PWM1 RegisterMemory Map HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 2400 PID PWM1 PeripheralIdentificationRegister 0x01C2 2404 PCR PWM1 PeripheralControlRegister 0x01C2 2408 CFG PWM1 ConfigurationRegister 0x01C2 240C START PWM1 StartRegister 0x01C2 2410 RPT PWM1 Repeat Count Register 0x01C2 2414 PER PWM1 PeriodRegister 0x01C2 2418 PH1D PWM1 First-PhaseDurationRegister 0x01C2 241C -0x01C2 27FF - Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 339 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

VPIF(VSYNC) INV ALID INV ALID V ALID V ALID PWM0 PWM1 PWM0/1 TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com

7.26.3 PWM0/1 ElectricalData/Timing

Table7-139.SwitchingCharacteristicsOver Recommended OperatingConditionsforPWM0/1 Outputs(1) (seeFigure7-92and Figure7-93) -594,-729 NO. PARAMETER UNIT MIN MAX 1 tw(PWMH) Pulseduration,PWMx high 37 ns 2 tw(PWML) Pulseduration,PWMx low 37 ns 3 tt(PWM) Transitiontime,PWMx 5 ns 4 td(VPIF-PWMV) Delaytime,VPIF (VSYNC) orGPIO triggereventtoPWMx valid 4P 6P + 20 ns (1) P = SYSCLK3 periodinns. Figure7-92.PWM Output Timing Figure7-93.PWM Output Delay Timing

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7.27 Timers

The timerssupportfourmodes ofoperation:a 64-bitgeneral-purpose(GP) timer,dual-unchained32-bit GP timers,dual-chained32-bittimers,ora watchdog timer.The GP timermode can be used togenerate periodicinterruptsor EDMA synchronizationevents.The watchdog timermode is used to providea recoverymechanism forthedeviceintheeventofa faultcondition,such as a non-exitingcode loop.

7.27.1 Timers Device-SpecificInformation

The DM6467 devicehas 3 64-bitgeneral-purposetimerswhichhave thefollowingfeatures:

64-bitcount-upcounter
Timermodes: – 64-bitgeneral-purposetimermode (Timer0 and 1) – Dual32-bitgeneral-purposetimermode (Timer0 and 1) – Watchdog timermode (Timer2)[mainlycontrolledby theARM]
2 possibleclocksources: – Internalclock – ExternalclockinputviatimerinputpinTINP0U, TINP0L,and TINP1L,(Timer0 and 1 only)
2 operationmodes: – One-timeoperation(timerrunsforone periodthenstops) – Continuousoperation(timerautomaticallyresetsaftereach period)
GeneratesinterruptstotheDSP and theARM CPUs
GeneratessynceventtoEDMA
Causes deviceglobalresetupon watchdogtimertimeout(Timer2 only) For more detailedinformation,see the TMS320DM646x DMSoC 64-BitTimer User'sGuide (literature number SPRUER5 ).

7.27.2 Timer PeripheralRegisterDescription(s)

Table 7-140, Table 7-141, and Table 7-142 show the registersforTimer 0, Timer 1, and Timer 2 (Watchdog). Table7-140.Timer 0 Registers HEX ADDRESS RANGE ACRONYM DESCRIPTION 0x01C2 1400 PID12 Timer0 PeripheralIdentificationRegister12 0x01C2 1404 EMUMGT Timer0 EmulationManagement 0x01C2 1410 TIM12 Timer0 CounterRegister12 0x01C2 1414 TIM34 Timer0 CounterRegister34 0x01C2 1418 PRD12 Timer0 PeriodRegister12 0x01C2 141C PRD34 Timer0 PeriodRegister34 0x01C2 1420 TCR Timer0 ControlRegister 0x01C2 1424 TGCR Timer0 GlobalControlRegister 0x01C2 1428 -0x01C2 17FF - Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 341 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-141.Timer 1 Registers HEX ADDRESS RANGE ACRONYM DESCRIPTION 0x01C2 1800 PID12 Timer1 PeripheralIdentificationRegister12 0x01C2 1804 EMUMGT Timer1 EmulationManagement 0x01C2 1810 TIM12 Timer1 CounterRegister12 0x01C2 1814 TIM34 Timer1 CounterRegister34 0x01C2 1818 PRD12 Timer1 PeriodRegister12 0x01C2 181C PRD34 Timer1 PeriodRegister34 0x01C2 1820 TCR Timer1 ControlRegister 0x01C2 1824 TGCR Timer1 GlobalControlRegister 0x01C2 1828 -0x01C2 1BFF - Reserved Table7-142.Timer 2 (Watchdog) Registers HEX ADDRESS RANGE ACRONYM DESCRIPTION 0x01C2 1C00 PID12 Timer2 PeripheralIdentificationRegister12 0x01C2 1C04 EMUMGT Timer2 EmulationManagement 0x01C2 1C10 TIM12 Timer2 CounterRegister12 0x01C2 1C14 TIM34 Timer2 CounterRegister34 0x01C2 1C18 PRD12 Timer2 PeriodRegister12 0x01C2 1C1C PRD34 Timer2 PeriodRegister34 0x01C2 1C20 TCR Timer2 ControlRegister 0x01C2 1C24 TGCR Timer2 GlobalControlRegister 0x01C2 1C28 WDTCR Timer2 Watchdog TimerControlRegister 0x01C2 1C2C -0x01C2 1FFF - Reserved

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7.27.3 Timer ElectricalData/Timing

Table7-143.Timing Requirements forTimer Input(1)(seeFigure7-94) -594,-729 NO. UNIT MIN MAX 1 tw(TINPH) Pulseduration,TINPxL/TINP0U high 2P ns 2 tw(TINPL) Pulseduration,TINPxL/TINP0U low 2P ns (1) P = DEV_MXI/DEV_CLKIN cycletimeinns.Forexample,when DEV_MXI/DEV_CLKIN frequencyis27 MHz, use P = 37.037 ns. Table7-144.SwitchingCharacteristicsOver Recommended OperatingConditionsforTimer Output(1)(see Figure7-94) -594,-729 NO. UNIT MIN MAX 3 tw(TOUTH) Pulseduration,TOUTxL/TOUTxU/TOUT2 high P ns 4 tw(TOUTL) Pulseduration,TOUTxL/TOUTxU/TOUT2 low P ns (1) P = DEV_MXI/DEV_CLKIN cycletimeinns.Forexample,when DEV_MXI/DEV_CLKIN frequencyis27 MHz, use P = 37.037 ns. Figure7-94.Timer Timing Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 343 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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7.28 General-PurposeInput/Output(GPIO)

The GPIO peripheralprovidesgeneral-purposepinsthatcan be configuredas eitherinputsor outputs. When configuredas an output,a writetoan internalregistercan controlthestatedrivenon theoutputpin. When configuredas an input,the stateof the inputisdetectableby readingthe stateof an internal register.In addition,the GPIO peripheralcan produce CPU interruptsand EDMA events in different interrupt/eventgenerationmodes. The GPIO peripheralprovidesgenericconnectionstoexternaldevices. The GPIO pinsaregroupedintobanks of16 pinsperbank (i.e.,bank 0 consistsofGP[0:15]).

7.28.1 GPIO Device-SpecificInformation

The DM6467 GPIO peripheralsupportsthefollowing:

Up to33 3.3-VGPIO pins,GP[0:47;notallpinnedout]
Interrupts: – Up to8 uniqueGP[0:7]interruptsfromBank 0 – 3 GPIO bank (aggregated)interruptsignalsfromeach ofthe3 banks ofGPIOs – Interruptscan be triggeredby risingand/orfallingedge,specifiedforeach interruptcapableGPIO signal
DMA events: – Up to8 uniqueGPIO DMA eventsfromBank 0 – 3 GPIO bank (aggregated)DMA eventsignalsfromeach ofthe3 banks ofGPIOs
Set/clearfunctionality:Softwarewrites1 to correspondingbitposition(s)to set or to clearGPIO signal(s).ThisallowsmultiplesoftwareprocessestotoggleGPIO outputsignalswithoutcriticalsection protection(disableinterrupts,program GPIO, re-enableinterrupts,to preventcontextswitchingto antherprocessduringGPIO programming).
SeparateInput/Outputregisters
Outputregisterinadditiontoset/clearso that,ifpreferredby software,some GPIO outputsignalscan be toggledby directwritetotheoutputregister(s).
Outputregister,when read,reflectsoutputdrivestatus.This,inadditiontotheinputregisterreflecting pinstatusand open-drainI/Ocell,allowswiredlogicbe implemented. Although,theDM6467 deviceimplementsthreeGPIO banks,notallGPIOs from allbanks are available externally(pinnedout).The followingGPIOs arenot pinnedouton theDM6467 device:
BANK 0 – GP[9] – GP[14] – GP[15]
BANK 1 – GP[27:31]
BANK 2
GP[34]
GP[35]
GP[43:47] For more detailedinformationon GPIOs, see theTMS320DM646x DMSoC General-PurposeInput/Output (GPIO)User'sGuide (literaturenumber SPRUEQ8 ).

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7.28.2 GPIO PeripheralRegisterDescription(s)

Table7-145shows theGPIO peripheralregisters. Table7-145.GPIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C6 7000 PID PeripheralIdentificationRegister 0x01C6 7004 - Reserved 0x01C6 7008 BINTEN GPIO interruptper-bankenable GPIO Banks 0 and 1 0x01C6 700C - Reserved 0x01C6 7010 DIR01 GPIO Banks 0 and 1 DirectionRegister(GP[0:31]) 0x01C6 7014 OUT_DATA01 GPIO Banks 0 and 1 OutputData Register(GP[0:31]) 0x01C6 7018 SET_DATA01 GPIO Banks 0 and 1 SetData Register(GP[0:31]) 0x01C6 701C CLR_DATA01 GPIO Banks 0 and 1 Cleardataforbanks 0 and 1 (GP[0:31]) 0x01C6 7020 IN_DATA01 GPIO Banks 0 and 1 InputData Register(GP[0:31]) 0x01C6 7024 SET_RIS_TRIG01 GPIO Banks 0 and 1 SetRisingEdge InterruptRegister(GP[0:31]) 0x01C6 7028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 ClearRisingEdge InterruptRegister(GP[0:31]) 0x01C6 702C SET_FAL_TRIG01 GPIO Banks 0 and 1 SetFallingEdge InterruptRegister(GP[0:31]) 0x01C6 7030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 ClearFallingEdge InterruptRegister(GP[0:31]) 0x01C6 7034 INSTAT01 GPIO Banks 0 and 1 InterruptStatusRegister(GP[0:31]) GPIO Bank 2 0x01C6 7038 DIR2 GPIO Bank 2 DirectionRegister(GP[32:47]) 0x01C6 703C OUT_DATA2 GPIO Bank 2 OutputData Register(GP[32:47]) 0x01C6 7040 SET_DATA2 GPIO Bank 2 SetData Register(GP[32:47]) 0x01C6 7044 CLR_DATA2 GPIO Bank 2 ClearData Register(GP[32:47]) 0x01C6 7048 IN_DATA2 GPIO Bank 2 InputData Register(GP[32:47]) 0x01C6 704C SET_RIS_TRIG2 GPIO Bank 2 SetRisingEdge InterruptRegister(GP[32:47]) 0x01C6 7050 CLR_RIS_TRIG2 GPIO Bank 2 ClearRisingEdge InterruptRegister(GP[32:47]) 0x01C6 7054 SET_FAL_TRIG2 GPIO Bank 2 SetFallingEdge InterruptRegister(GP[32:47]) 0x01C6 7058 CLR_FAL_TRIG2 GPIO Bank 2 ClearFallingEdge InterruptRegister(GP[32:47]) 0x01C6 705C INSTAT2 GPIO Bank 2 InterruptStatusRegister(GP[32:47]) 0x01C6 7060 -0x01C6 77FF - Reserved Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 345 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

GP[x] Input GP[x] Output TMS320DM6467 SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com

7.28.3 GPIO PeripheralInput/OutputElectricalData/Timing

Table7-146.Timing Requirements forGPIO Inputs(1)(seeFigure7-95) -594,-729 NO. UNIT MIN MAX 1 tw(GPIH) Pulseduration,GP[x]inputhigh 2C (2) ns 2 tw(GPIL) Pulseduration,GP[x]inputlow 2C (2) ns (1) The pulsewidthgivenissufficienttogeneratea CPU interruptoran EDMA event.However,ifa userwantstohave DM6467 recognize theGP[x]inputchanges throughsoftwarepollingoftheGPIO register,theGP[x]inputdurationmust be extendedtoallowDM6467 enough timetoaccesstheGPIO registerthroughtheinternalbus. (2) C = SYSCLK3 periodinns.Forexample,when runningpartsat594 MHz, use C = 6.7ns. Table7-147.SwitchingCharacteristicsOver Recommended OperatingConditionsforGPIO Outputs (seeFigure7-95) -594,-729 NO. PARAMETER UNIT MIN MAX 3 tw(GPOH) Pulseduration,GP[x]outputhigh C (1)(2) ns 4 tw(GPOL) Pulseduration,GP[x]outputlow C (1)(2) ns (1) Thisparametervalueshouldnotbe used as a maximum performancespecification.Actualperformanceofback-to-backaccessesofthe GPIO isdependentupon internalbus activity. (2) C = SYSCLK3 periodinns.Forexample,when runningpartsat594 MHz, use C = 6.7ns. Figure7-95.GPIO PortTiming

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www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 7.29 IEEE 1149.1JTAG The JTAG (3)interfaceisused forBSDL testingand emulationoftheDM6467 device. TRST onlyneeds tobe releasedwhen itisnecessarytouse a JTAG controllertodebug thedeviceor exercisethedevice'sboundaryscan functionality. RESET must be releasedonlyin orderforboundary-scanJTAG to read the variantfieldof IDCODE correctly.Otherboundary-scaninstructionswork correctlyindependentofcurrentstateofRESET. DM6467 includesan internalpulldown(IPD)on theTRST pintoensurethatTRST willalwaysbe asserted upon power up and thedevice'sinternalemulationlogicwillalwaysbe properlyinitialized. JTAG controllersfrom Texas InstrumentsactivelydriveTRST high.However, some third-partyJTAG controllersmay notdriveTRST highbutexpecttheuse ofa pullupresistoron TRST. When usingthistype of JTAG controller,assertTRST to initializethe deviceafterpowerup and externallydriveTRST high beforeattemptingany emulationorboundaryscan operations.

7.29.1 JTAG ID (JTAGID) RegisterDescription(s)

Table7-148.JTAG ID Register HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Read-only.Provides32-bit0x01C4 0028 JTAGID JTAG IdentificationRegister JTAG ID ofthedevice. (3) IEEE Standard1149.1-1990Standard-Test-AccessPortand BoundaryScan Architecture. The JTAG ID registerisa read-onlyregisterthatidentifiestothecustomertheJTAG/Device ID.For the DM6467 device,theJTAG ID registerresidesataddresslocation0x01C4 0028.The registerhex valuefor DM6467 is:0x1B77 002F [forSiliconRevision3.0and later]and 0x0B77 002F [forSiliconRevision1.1 and earlier].For theactualregisterbitnames and theirassociatedbitfielddescriptions,see Figure7-96 and Table7-149. 31-28 27-12 11-1 0 VARIANT (4-Bit) PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB R-000X R-1011 0111 0111 0000 R-0000 0010 111 R-1 LEGEND: R = Read, W = Write,n = valueatreset,X = SiliconRevisiondependent Figure7-96.JTAG ID RegisterDescription-DM6467 RegisterValue -0xXB77 002F Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 347 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

SPRS403H –DECEMBER 2007–REVISED JUNE 2012 www.ti.com Table7-149.JTAG ID RegisterSelectionBitDescriptions BIT NAME DESCRIPTION Variant(4-Bit)value.DM6467 value:0000 [SiliconRevision1.1and earlier]and 0001 [Silicon31:28 VARIANT Revision3.0and later]. 27:12 PART NUMBER PartNumber (16-Bit)value.DM6467 value:1011 0111 0111 0000. 11-1 MANUFACTURER Manufacturer(11-Bit)value.DM6467 value:0000 0010 111. 0 LSB LSB. Thisbitisreadas a "1"forDM6467.

7.29.2 JTAG Test-PortElectricalData/Timing

Table7-150.Timing Requirements forJTAG TestPort(1)(2)(seeFigure7-97) -594,-729 NO. UNIT MIN MAX 1 tc(TCK) Cycletime,TCK 20 ns 2 tw(TCKH) Pulseduration,TCK high 0.4T ns 3 tw(TCKL) Pulseduration,TCK low 0.4T ns 4 tc(RTCK) Cycletime,RTCK 20 ns 5 tw(RTCKH) Pulseduration,RTCK high 0.4R ns 6 tw(RTCKL) Pulseduration,RTCK low 0.4R ns 7 tsu(TDIV-RTCKH) Setuptime,TDI/TMS/TRST validbeforeRTCK high 12 ns 8 th(RTCKH-TDIV) Holdtime,TDI/TMS/TRST validafterRTCK high 0 ns 9 tsu(EMUV-TCKH) Setuptime,EMU[1:0]validbeforeTCK high 1.5 ns 10 th(TCKH-EMUV) Holdtime,EMU[1:0]validafterTCK high 4 ns (1) T = TCK cycletimeinns.Forexample,when TCK frequencyis20 MHz, use T = 50 ns. (2) R = RTCLK cycletimeinns.Forexample,when RTCK frequencyis20 MHz, use T = 50 ns. Table7-151.SwitchingCharacteristicsOver Recommended OperatingConditionsforJTAG TestPort(1) (seeFigure7-97) -594,-729 NO. PARAMETER UNIT MIN MAX 11 td(RTCKL-TDOV) Delaytime,RTCK lowtoTDO valid -1 8 ns 12 td(TCKH-EMUV) Delaytime,TCK hightoEMU[1:0]valid 2.5 T -2.5 ns (1) T = TCK cycletimeinns.Forexample,when TCK frequencyis20 MHz, use T = 50 ns.

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EMU1:0 EMU1:0 TMS320DM6467 www.ti.com SPRS403H –DECEMBER 2007–REVISED JUNE 2012 Figure7-97.JTAG Test-PortTiming Copyright© 2007–2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 349 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6467

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8 MechanicalPackaging and OrderableInformation

The followingtable(s)show the thermalresistancecharacteristicsfor the PBGA –CUT mechanical package.

8.1 Thermal Data forCUT

Table8-1.Thermal ResistanceCharacteristics(PBGA Package) [CUT] NO. °C/W (1) AIR FLOW (m/s)(2) 1 R ΘJC Junction-to-case 1.5 N/A 2 R ΘJB Junction-to-board 9.9 N/A 3 R ΘJA Junction-to-freeair 19.2 0.00 4 14.8 0.50 5 13.8 1.00 R ΘJMA Junction-to-movingair 6 12.7 2.00 7 11.9 3.00 8 0.3 0.00 9 0.4 0.50 10 PsiJT Junction-to-packagetop 0.4 1.00 11 0.4 2.00 12 0.5 3.00 13 9.0 0.00 14 8.0 0.50 15 PsiJB Junction-to-board 7.7 1.00 16 7.3 2.00 17 7.0 3.00 (1) These measurements were conductedina JEDEC defined2S2P systemand willchange based on environmentas wellas application. Formore information,see theseEIA/JEDEC standards– EIA/JESD51-2,IntegratedCircuitsThermalTestMethod Environment Conditions-NaturalConvection(StillAir)and JESD51-7,HighEffectiveThermalConductivityTestBoard forLeaded SurfaceMount Packages. (2) m/s = meterspersecond

8.2 Packaging Information

The followingpackaging informationand addendum reflectthe most currentdata availableforthe designateddevice(s).Thisdataissubjecttochange withoutnoticeand withoutrevisionofthisdocument.

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www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMS320DM6467CCUT NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR 0 to 85 TMS320 DM6467CCUT TMS320DM6467CCUT4 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR 0 to 85 TMS320 DM6467CCUT4 TMS320DM6467CCUT6 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR TMS320 DM6467CCUT6 TMS320DM6467CCUT7 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR 0 to 85 TMS320 DM6467CCUT7 TMS320DM6467CCUTA NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR TMS320 DM6467CCUTA TMS320DM6467CCUTA6 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR TMS320 DM6467CCUTA6 TMS320DM6467CCUTAV NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR -40 to 105 TMS320 DM6467CUTAVH TMS320DM6467CCUTD7 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR -40 to 85 TMS320 DM6467CCUTD7 TMS320DM6467CCUTV NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR 0 to 85 TMS320 DM6467CCUTVH TMS320DM6467CCUTV6 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR TMS320 DM6467CCUTV6H TMS320DM6467CZUT LIFEBUY FCBGA ZUT 529 TBD Call TI Call TI 0 to 85 TMS320 DM6467CZUT TMS320DM6467CZUT7 LIFEBUY FCBGA ZUT 529 TBD Call TI Call TI 0 to 85 TMS320 DM6467CZUT7 TMS320DM6467CZUTA LIFEBUY FCBGA ZUT 529 TBD Call TI Call TI -40 to 105 TMS320 DM6467CZUTA TMS32DM6467CCUTAV6 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR -40 to 105 TMS320 DM6467CCUTAV6H TMSDDVI6007CZUT7HV LIFEBUY FCBGA ZUT 529 TBD Call TI Call TI 0 to 85 TMS320 DM6467CZUT7 TMSDM6467CCUT6TAN NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR TMS320 DM6467CCUT6 TMSDM6467CCUT7TAN NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR 0 to 85 TMS320 DM6467CCUT7

www.ti.com 15-Apr-2017 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMSDM6467CCUTV6TAN NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR TMS320 DM6467CCUTV6H VCBUP7CCUT6 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR TMS320 DM6467CCUT6 VCBUP7CT7 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR 0 to 85 TMS320 DM6467CCUT7 VCBUP7TC6 NRND FCBGA CUT 529 84 Green (RoHS & no Sb/Br) SNAGCU Level-4-245C-72HR TMS320 DM6467CCUT6 VCBUSAM6467CT LIFEBUY FCBGA ZUT 529 TBD Call TI Call TI 0 to 85 TMS320 DM6467CZUT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

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Product Information

TMSDM6467CCUT7TAN specifications and overview.

Summary

Digital Media System-on-Chip

Description

Digital Media System-on-Chip

Source title TMSDM6467CCUT7TAN Datasheet(PDF) - Texas Instruments

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