TMSDC6722BRFPA225

TMS320C6727B_07 TI | Alldatasheet

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TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 C672x: 32-/64-Bit 350-MHz Floating-Point DSPs Three Multichannel Audio Serial Ports Transmit/Receive Clocks up to MHz Upgrades to C67x+ CPU From C67x DSP Six Clock Zones and Serial Data Pins Generation: Supports TDM, I2S, and Similar Formats CPU Registers [64 General-Purpose] DIT-Capable (McASP2) New Audio-Specific Instructions Compatible With the C67x CPU Universal Host-Port Interface (UHPI) 32-Bit-Wide Data Bus for High Bandwidth Enhanced Memory System Muxed and Non-Muxed Address and Data 256K-Byte Unified Program/Data RAM 384K-Byte Unified Program/Data ROM Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin Single-Cycle Data Access From CPU Options Large Program Cache (32K Byte) Supports Two Inter-Integrated Circuit (I2C) Ports RAM, ROM, and External Memory Real-Time Interrupt Counter/Watchdog External Memory Interface (EMIF) Supports Oscillator- and Software-Controlled PLL 133-MHz SDRAM (16- or 32-Bit) Applications: Asynchronous NOR Flash, SRAM (8-,16-, or Professional Audio 32-Bit) Mixers NAND Flash (8- or 16-Bit) Effects Boxes Enhanced I/O System Audio Synthesis High-Performance Crossbar Switch Instrument/Amp Modeling Dedicated McASP DMA Bus Audio Conferencing Deterministic I/O Performance Audio Broadcast dMAX (Dual Data Movement Accelerator) Audio Encoder Supports: Emerging Audio

Applications

1-, 2-, and 3-Dimensional Commercial or Extended Temperature Memory-to-Memory and Memory-to-Peripheral Data Transfers 144-Pin, 0.5-mm, PowerPAD Thin Quad Circular Addressing Where the Size of a Flatpack (TQFP) [RFP Suffix] Circular Buffer (FIFO) is not Limited to n 256-Terminal, 1.0-mm, 16x16 Array Plastic Ball Table-Based Multi-Tap Delay Read and Grid Array (PBGA) [GDH and ZDH Suffixes] Write Transfers From/To a Circular Buffer Please be aware that an important notice concerning availability, standard warranty, and use in critical document. C67x, PowerPAD, TMS320C6000, C6000, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments. Philips is a registered trademark of Koninklijki Philips Electronics N.V. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2006 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Description

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices. (1) Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic. Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices. The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM. Up to three parallel accesses to the internal RAM and ROM from three of the following four sources are supported: Two 64-bit data accesses from the C67x+ CPU One 256-bit program fetch from the core and program cache One 32-bit data access from the peripheral system (either dMAX or UHPI) The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents most program/data access conflicts to the on-chip memory. It also enables effective program execution from an off-chip memory such as an SDRAM. High-Performance Crossbar Switch. A high-performance crossbar switch acts as a central hub between the different bus masters (CPU, dMAX, UHPI) and different targets (peripherals and memory). The crossbar is partially connected; some connections are not supported (for example, UHPI-to-peripheral connections). Multiple transfers occur in parallel through the crossbar as long as there is no conflict between bus masters for a particular target. When a conflict does occur, the arbitration is a simple and deterministic fixed-priority scheme. The dMAX is given highest-priority since it is responsible for the most time-critical I/O transfers, followed next by the UHPI, and finally by the CPU. dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data Movement Acceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSPs. The dMAX allows movement of data to/from any addressable memory space including internal memory, peripherals, and external memory. The dMAX controller includes sorting, and the capability to manage a section of the memory as a circular buffer/FIFO with delay-tap based reading and writing of data. The dMAX controller is capable of concurrently processing two transfer requests (provided that they are to/from different source/destinations). External Memory Interface (EMIF) for Flexibility and Expansion. The external memory interface on the C672x supports a single bank of SDRAM and a single bank of asynchronous memory. The EMIF data width is bits wide on the C6726B, C6722B, and C6720 and bits wide on the C6727B. SDRAM support includes x16 and x32 SDRAM devices with or banks. The C6726B, C6722B, and C6720 support SDRAM devices up to 128M bits. (1) Throughout the remainder of the document, TMS320C6727B (or C6727B), TMS320C6726B (or C6726B), TMS320C6722B (or C6722B), and/or TMS320C6720 (or C6720) will be referred to as TMS320C672x (or C672x). TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 DSPs Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C6727B extends SDRAM support to 256M-bit and 512M-bit devices. Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device that can be 16, or bits wide. Booting from larger flash devices than are natively supported by the dedicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address lines. The asynchronous memory interface can also be configured to support or 16-bit-wide NAND flash. It includes a hardware ECC calculation (for single-bit errors) that can operate on blocks of data up to 512 bytes. Universal Host-Port Interface (UHPI) for High-Speed Parallel I/O. The Universal Host-Port Interface (UHPI) is a parallel interface through which an external host CPU can access memories on the DSP. Three modes are supported by the C672x UHPI: Multiplexed Address/Data Half-Word (16-bit-wide) Mode (similar to C6713) Multiplexed Address/Data Full Word (32-bit-wide) Mode Non-Multiplexed Mode 16-bit Address and 32-bit Data Bus The UHPI can also be restricted to accessing a single page (64K bytes) of memory anywhere in the address space of the C672x; this page can be changed, but only by the C672x CPU. This feature allows the UHPI to be used for high-speed data transfers even in systems where security is an important requirement. The UHPI is only available on the C6727B. Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) Up to Stereo Channels I2S. The multichannel audio serial port (McASP) seamlessly interfaces to CODECs, DACs, ADCs, and other devices. It supports the ubiquitous IIS format as well as many variations of this format, including time division multiplex (TDM) formats with up to time slots. Each McASP includes a transmit and receive section which may operate independently or synchronously; furthermore, each section includes its own flexible clock generator and extensive error-checking logic. As data passes through the McASP, it can be realigned so that the fixed-point representation used by the application code can be independent of the representation used by the external devices without requiring any CPU overhead to make the conversion. The McASP is a configurable module and supports between and serial data pins. It also has the option of supporting a Digital Interface Transmitter (DIT) mode with a full 384 bits of channel status and user data memory. McASP2 is not available on the C6722B and C6720. Inter-Integrated Circuit Serial Ports (I2C0, I2C1). The C672x includes two inter-integrated circuit (I2C) serial ports. A typical application is to configure one I2C serial port as a slave to an external user-interface microcontroller. The other I2C serial port may then be used by the C672x DSP to control external peripheral devices, such as a CODEC or network controller, which are functionally peripherals of the DSP device. The two I2C serial ports are pin-multiplexed with the SPI0 serial port. Serial Peripheral Interface Ports (SPI0, SPI1). As in the case of the I2C serial ports, the C672x DSP also includes two serial peripheral interface (SPI) serial ports. This allows one SPI port to be configured as a slave to control the DSP while the other SPI serial port is used by the DSP to control external peripherals. The SPI ports support a basic 3-pin mode as well as optional and 5-pin modes. The optional pins include a slave chip-select pin and an enable pin which implements handshaking automatically in hardware for maximum SPI throughput. The SPI0 port is pin-multiplexed with the two I2C serial ports (I2C0 and I2C1). The SPI1 serial port is pin-multiplexed with five of the serial data pins from McASP0 and McASP1. Submit Documentation Feedback TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 DSPs

www.ti.com 1.2.1 Device Compatibility TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes: Two 32-bit counter/prescaler pairs Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement) Four compares with automatic update capability Digital Watchdog (optional) for enhanced system robustness Clock Generation (PLL and OSC). The C672x DSP includes an on-chip oscillator that supports crystals in the range of MHz to MHz. Alternatively, the clock can be provided externally through the CLKIN pin. The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF. The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant enhancements including additional floating-point instructions. See Section 2.2 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 DSPs Submit Documentation Feedback

www.ti.com 1.3 Functional Block Diagram Program/Data RAM 256K Bytes 256 256 Program/Data ROM Page0 256K Bytes 256 Program/Data ROM Page1 128K Bytes 3232 DMPPMP CSP 32 256 32K Bytes Program Cache Data R/W R/W Data 256 Program FetchINTI/O C67x+ CPU Memory Controller High-Performance Crossbar Switch 32 McASP DMA Bus JTAG EMU Peripheral Configuration Bus EMIF Events In MAX1MAX0 CONTROL Interrupts Out I/O dMAX McASP0

16 Serializers

6 Serializers

2 Serializers

+ DIT SPI1 SPI0 I2C1 I2C0 RTI32 UHPI PLL Peripheral Interrupt and DMA Events TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 1-1 shows the functional block diagram of the C672x device. UHPI is available only on the C6727B. McASP2 is not available on the C6722B and C6720. Figure 1-1. C672x DSP Block Diagram Submit Documentation Feedback TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 DSPs

www.ti.com Device Overview 2.1 Device Characteristics TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 2-1 provides an overview of the C672x DSPs. The table shows significant device, including the capacity of on-chip memory, the peripherals, the execution time, and the package type with pin count. Table 2-1. Characteristics of the C672x Processors HARDWARE (32-bit) (16-bit) (16-bit) (16-bit) Peripherals UHPI Not all peripheral pins are available at the same McASP (McASP2 DIT only) time. (For more details, see the Device SPI Configurations section.) I2C RTI 32KB Program 32KB Program 32KB Program 32KB Program Cache Cache Cache Cache On-Chip Memory Size (KB) 256KB RAM 256KB RAM 128KB RAM 64KB RAM 384KB ROM 384KB ROM 384KB ROM 384KB ROM Control Status Register CPU ID CPU Rev ID 0x0300 (CSR.[31:16]) Frequency MHz 350, 300, 275, 250 266, 225 250, 225, 200 200 2.8 ns (C6727B-350) ns 3.3 ns 3.75 ns (C6722B-250) (C6727B-300) (C6726B-266) 4.4 ns ns Cycle Time ns 3.6 ns 4.4 ns (C6722B A -225) (1) (C6720-200) (C6727B-275) (C6726B A -225) (1) ns ns (C6722B-200) (C6727B A -250) (1) 133 (266-MHz CPU Frequency) EMIF Frequency MHz 133 100 100 100 (225-MHz CPU Frequency) 1.4 V (C6727B-350) 1.2 V Core (V) 1.2 V (C6727B-300) Voltage (C6727B-275) (C6727B A -250) (1) I/O (V) 3.3 V Prescaler /1, /2, /3, ..., /32 Clock Generator Options Multiplier x4, x5, x6, ..., x25 Postscaler /1, /2, /3, ..., /32 256-Terminal PBGA (GDH) x mm 256-Terminal Green PBGA Packages (see Section (ZDH) 144-Pin PowerPAD 144-Pin PowerPAD 144-Pin PowerPAD x mm Green TQFP Green TQFP Green TQFP (RFP) (RFP) (RFP) Process Technology µ m 0.13 µ m (1) TMS320C6727B A -250, TMS320C6726B A -225, and TMS320C6722B A -225 are extended-temperature devices. Submit Documentation Feedback Device Overview

www.ti.com 2.2 Enhanced C67x+ CPU .D1 .M1 .S1 .L1 Register File A Data Path A Cross Paths .D2 .M2 .S2 .L2 Register File B Data Path B TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 2-1. Characteristics of the C672x Processors (continued) HARDWARE (PP), Advance Information (AI), Product Status PD (2) or Production Data (PD) (2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant enhancements including an increase in core operating frequency from 225 MHz to 350 MHz (3) while operating at 1.2 V (1.4 V for C6727B-350). The CPU fetches 256-bit-wide advanced very-long instruction word (VLIW) fetch packets that are composed of variable-length execute packets. The execute packets can supply from one to eight 32-bit instructions to the eight functional units during every clock cycle. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. Additionally, execute packets can now span fetch packets, providing a code size improvement over the C67x CPU core. The CPU paths, shown in Figure 2-1 each composed of four functional units (.D, .M, .S, and .L) and a register file. The unit in each data path is a data-addressing unit that is responsible for all data transfers between the register files and the memory. The functional units are dedicated for multiplies, and the and functional units perform a general set of arithmetic, logical, and branch functions. All instructions operate on registers as opposed to data in memory, but results stored in the 32-bit registers can be subsequently moved to memory as bytes, half-words, or words. Figure 2-1. CPU Data Paths The register file in each data path contains 32-bit registers for a total of general-purpose registers. This doubles the number of registers found on the C67x CPU core, allowing the optimizing C compiler to pipeline more complex loops by decreasing register pressure significantly. The four functional units in each data path of the CPU can freely share the registers belonging to that data path. Each data path also a single cross path connected to the register file on the opposing data path. This allows each data path to source one cross-path operand per cycle from the opposing register file. On the C67x+ CPU, this single cross-path operand can be used by two functional units per cycle, an improvement over the C67x CPU in which only one functional unit could use the cross-path operand. In addition, the cross-path register read(s) are not counted as part of the limit of four reads of the same register in a single cycle. The C67x+ CPU executes all C67x instructions plus new floating-point instructions to improve performance specifically during audio processing. These new instructions are listed in Table 2-2 (3) CPU speed is device-dependent. See Table 2-1 Device Overview Submit Documentation Feedback

www.ti.com 2.3 CPU Interrupt Assignments TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 2-2. New Floating-Point Instructions for C67x+ CPU FLOATING-POINT INSTRUCTION IMPROVES OPERATION (1) MPYSPDP SP x DP DP Faster than MPYDP. Improves high Q biquads (bass management) and FFT. MPYSP2DP SP x SP DP Faster than MPYDP. Improves Long FIRs (EQ). ADDSP (new to CPU S Unit) SP SP SP ADDDP (new to CPU S Unit) DP DP DP Now up to four floating-point add and subtract operations in parallel. Improves FFT performance and symmetric FIR. SUBSP (new to CPU S Unit) SP SP SP SUBDP (new to CPU S Unit) DP DP DP (1) SP means IEEE Single-Precision (32-bit) operations and DP means IEEE Double-Precision (64-bit) operations. Finally, two new registers, which are dedicated to communication with the dMAX unit, have been added to the C67x+ CPU. These registers are the dMAX Event Trigger Register (DETR) and the dMAX Event Status Register (DESR). They allow the CPU and dMAX to communicate without requiring any accesses to the memory system. Table 2-3 lists the interrupt channel assignments on the C672x device. If more than one source is listed, the interrupt channel is shared and an interrupt on this channel could have come from any of the enabled peripherals on that channel. The dMAX peripheral has two CPU interrupts dedicated to reporting FIFO status (INT7) and transfer completion (INT8). In addition, the dMAX can generate interrupts to the CPU on lines INT9 and INT15 in response to peripheral events. To enable this functionality, the associated Event Entry within the dMAX can be programmed so that a CPU interrupt is generated when the peripheral event is received. Table 2-3. CPU Interrupt Assignments CPU INTERRUPT INTERRUPT SOURCE INT0 RESET INT1 NMI (From dMAX or EMIF Interrupt) INT2 Reserved INT3 Reserved INT4 RTI Interrupt INT5 RTI Interrupts and RTI Overflow Interrupts and INT6 UHPI CPU Interrupt (from External Host MCU) INT7 FIFO status notification from dMAX INT8 Transfer completion notification from dMAX INT9 dMAX event (0x2 specified in the dMAX interrupt event entry) INT10 dMAX event (0x3 specified in the dMAX interrupt event entry) INT11 dMAX event (0x4 specified in the dMAX interrupt event entry) INT12 dMAX event (0x5 specified in the dMAX interrupt event entry) INT13 dMAX event (0x6 specified in the dMAX interrupt event entry) INT14 I2C0, I2C1, SPI0, SPI1 Interrupts INT15 dMAX event (0x7 specified in the dMAX interrupt event entry) Submit Documentation Feedback Device Overview

www.ti.com 2.4 Internal Program/Data ROM and RAM 00 20 2707 2808 Byte ROM Page 1 Base Address 0x0004 0000 ROM Page 0 Base Address 0x0000 0000Bank Bank Bank Bank 13 33 10 30 17 37 14 34 1B 3B 18 38 1F 3F 1C 3C RAM Page 0 Base Address 0x1000 0000 00 20 03 23 Byte Bank Bank Bank Bank Bank Bank Bank Bank TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The organization of program/data ROM and RAM on C672x is simple and efficient. ROM is organized as two 256-bit-wide pages with four 64-bit-wide banks. RAM is organized as a single 256-bit-wide page with eight 32-bit-wide banks. The internal memory organization is illustrated in Figure 2-2 (ROM) and Figure 2-3 (RAM). Figure 2-2. Program/Data ROM Organization Figure 2-3. Program/Data RAM Organization The C672x memory controller supports up to three parallel accesses to the internal RAM and ROM from three of the following four sources as long as there are no bank conflicts: Two 64-bit data accesses from the C67x+ CPU One 256-bit-wide program fetch from the program cache One 32-bit data access from the peripheral system (either dMAX or UHPI) A program cache miss is 256 bits wide and conflicts only with data accesses to the same page. Multiple data accesses to different pages, or to the same page but different banks will occur without conflict. The organization of the C672x internal memory system into multiple pages total) and a large number of banks (16 total) means that it is straightforward to optimize DSP code to avoid data conflicts. Several factors, including the large program cache and the partitioning of the memory system into multiple pages, minimize the number of program versus data conflicts. The result is an efficient memory system which allows easy tuning towards the maximum possible CPU performance. The C672x ROM consists of a software bootloader plus additional software. Please refer to the C9230C100 TMS320C672x Floating-Point Digital Signal Processors ROM Data Manual (literature number SPRS277) for more details on the ROM contents. Device Overview Submit Documentation Feedback

www.ti.com 2.5 Program Cache TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cache has these key features: Wide 256-bit path to internal ROM/RAM Single-cycle access on cache hits 2-cycle miss penalty to internal ROM/RAM Caches external memory as well as ROM/RAM Direct-mapped Modes: Enable, Freeze, Bypass Software invalidate to support code overlay The program cache line size is 256 bits wide and is matched with a 256-bit-wide path between cache and internal memory. This allows the program cache to fill an entire line (corresponding to eight C67x+ CPU instructions) with only a single miss penalty of cycles. The program cache control registers are listed in Table 2-4 Table 2-4. Program Cache Control Registers REGISTER NAME BYTE ADDRESS

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(for example, a program overlay) must invalidate the addresses from program cache to maintain coherency by explicitly writing to the L1PISAR and L1PICR registers. The Cache Mode (Enable, Freeze, Bypass) is configured through a CPU internal register (CSR, bits 7:5). These options are listed in Table 2-5 Typically, only the Cache Enable Mode is used. But advanced users may utilize Freeze and Bypass modes to tune performance. Table 2-5. Cache Modes Set Through PCC Field of CSR CPU Register on C672x CPU CSR[7:5] CACHE MODE 000b Enable (Deprecated Means direct mapped RAM on some C6000 devices) 010b Enable Cache is enabled, cache misses cause a line fill. 011b Freeze Cache is enabled, but misses. 100b Bypass Forces cache misses, cache frozen. Other Values Reserved Not Supported CAUTION Although the reset value of CSR[7:5] (PCC field) is 000b, the value may be modified during the boot process by the ROM code. Refer to the appropriate ROM data sheet for more details. However, note that the cache may be disabled when control is actually passed to application code. Therefore, it may be necessary to write '010b' to the PCC field to explicitly enable the cache at the start of application code. CAUTION Changing the cache mode through CSR[7:5] does not invalidate any lines already in the cache. To invalidate the cache after modifications are made to program space, the control registers L1PISAR and L1PICR must be used. Submit Documentation Feedback Device Overview

www.ti.com 2.6 High-Performance Crossbar Switch SYSCLK3 SYSCLK1 SYSCLK2 SYSCLK3 BR3 BR4 2 1 Priority EMIF External Memory SDRAM/ Flash Priority 21 3 4 SYSCLK2 SYSCLK1 BR1 SYSCLK2 SYSCLK1 BR2 Program Master Port (PMP) CPU Slave Port (CSP) Data Master Port (DMP) Memory Controller M1 T1 M2 Priority 1 2 3 PLL SPI0 I2C0 I2C1RTI SPI1 Peripheral Configuration Bus McASP2McASP1McASP0 McASP DMA Bus Priority 1 2 3 Priority 1 2 dMAX MAX0 Unit Master Port − High Priority dMAX MAX1 Unit Master Port − Second Priority Memory Controller DMP − Data Read/Write by CPU UHPI Master Interface (External Host CPU) UHPI Universal Host-Port Interface MAX0 MAX1 1 2 3 Priority Config dMAX T5M3 M4 External Host MCU Config ROM RAM CPU Program Cache Crossbar TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus masters and targets. Figure 2-4 illustrates the connectivity of the crossbar switch. Figure 2-4. Block Diagram of Crossbar Switch As shown in Figure 2-4 there are five bus masters: Memory controller DMP for CPU data accesses to peripherals and EMIF. Memory controller PMP for program cache fills from the EMIF. dMAX HiMAX master port for high-priority DMA accesses. dMAX LoMAX master port for lower-priority DMA accesses. UHPI master port for an external MCU to access on-chip and off-chip memories. Device Overview Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The five bus masters arbitrate for five different target groups: On-chip memories through the CPU Slave Port (CSP). Memories on the external memory interface (EMIF). Peripheral registers through the peripheral configuration bus. McASP serializers through the dedicated McASP DMA bus. dMAX registers. The crossbar switch supports parallel accesses from different bus masters to different targets. When two or more bus masters contend for the same target beginning at the same cycle, then the highest-priority master is given ownership of the target while the other master(s) are stalled. However, once ownership of the target is given to a bus master, it is allowed to complete its access before ownership is arbitrated again. Following are two examples. Example Simultaneous accesses without conflict dMAX HiMAX accesses McASP Data Port for transfer of audio data. dMAX LoMAX accesses SPI port for control processing. UHPI accesses internal RAM through the CSP. CPU fills program cache from EMIF. Example Conflict over a shared resource dMAX HiMAX accesses RTI port for McASP sample rate measurement. dMAX LoMAX accesses SPI port for control processing. In Example both masters contend for the same target, the peripheral configuration bus. The HiMAX access will be given priority over the LoMAX access. The master priority is illustrated in Figure 2-4 by the numbers through in the bus arbiter symbols. Note that the EMIF arbitration is distributed so that only one bridge crossing is necessary for PMP accesses. The effect is that PMP has 5th priority to the EMIF but lower latency. A bus bridge is needed between masters and targets which run at different clock rates. The bus bridge contains a small FIFO to allow the bridge to accept an incoming (burst) access at one clock rate and pass it through the bridge to a target running at a different rate. Table 2-6 lists the FIFO properties of the four bridges (BR1, BR2, BR3, and BR4) in Figure 2-4 Table 2-6. Bus Bridges LABEL BRIDGE peripherals, dMAX, EMIF SYSCLK1 SYSCLK2 BR2 dMAX, UHPI to ROM/RAM (CSP) SYSCLK2 SYSCLK1 BR3 PMP to EMIF SYSCLK1 SYSCLK3 BR4 CPU, UHPI, and dMAX to EMIF SYSCLK2 SYSCLK3 Submit Documentation Feedback Device Overview

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7 contains a bits. Reserved Reserved CSPRST R/W, LEGEND: R/W Read/Write; R Read only; n value after reset Figure 2-5. CFGBRIDGE Register Bit Layout (0x4000 0024) Table 2-7. CFGBRIDGE Register Bit Field (0x4000 0024) BIT NO. NAME RESET VALUE READ WRITE 31:1 Reserved N/A N/A Reads are indeterminate. Only should be written to these bits. CSPRST R/W Resets the CSP Bridge (BR2 in Figure 2-4 Bridge Reset Asserted Bridge Reset Released CAUTION The CSPRST bit must be asserted after any change to the PLL that affects SYSCLK1 and SYSCLK2 and must be released before any accesses to the CSP bridge occur from either the dMAX or the UHPI. Device Overview Submit Documentation Feedback

www.ti.com 2.7 Memory Map Summary TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 A high-level memory map of the C672x DSP appears in Table 2-8 The base address of each region is listed. Any address past the end address must not be read or written. The table also lists whether the regions are word-addressable or byte- and word-addressable. Table 2-8. C672x Memory Map (256K Bytes) 0x0000 0000 0x0003 FFFF Byte and Word Internal ROM Page (128K Bytes) 0x0004 0000 0x0005 FFFF Byte and Word Internal RAM Page (256K Bytes) 0x1000 0000 0x1003 FFFF Byte and Word Memory and Cache Control Registers 0x2000 0000 0x2000 001F Word Only Emulation Control Registers (Do Not Access) 0x3000 0000 0x3FFF FFFF Word Only Device Configuration Registers 0x4000 0000 0x4000 0083 Word Only PLL Control Registers 0x4100 0000 0x4100 015F Word Only Real-time Interrupt (RTI) Control Registers 0x4200 0000 0x4200 00A3 Word Only Universal Host-Port Interface (UHPI) Registers 0x4300 0000 0x4300 0043 Word Only McASP0 Control Registers 0x4400 0000 0x4400 02BF Word Only McASP1 Control Registers 0x4500 0000 0x4500 02BF Word Only McASP2 Control Registers 0x4600 0000 0x4600 02BF Word Only SPI0 Control Registers 0x4700 0000 0x4700 007F Word Only SPI1 Control Registers 0x4800 0000 0x4800 007F Word Only I2C0 Control Registers 0x4900 0000 0x4900 007F Word Only I2C1 Control Registers 0x4A00 0000 0x4A00 007F Word Only McASP0 DMA Port (any address in this range) 0x5400 0000 0x54FF FFFF Word Only McASP1 DMA Port (any address in this range) 0x5500 0000 0x55FF FFFF Word Only McASP2 DMA Port (any address in this range) 0x5600 0000 0x56FF FFFF Word Only dMAX Control Registers 0x6000 0000 0x6000 008F Word Only MAX0 (HiMAX) Event Entry Table 0x6100 8000 0x6100 807F Byte and Word Reserved 0x6100 8080 0x6100 809F MAX0 (HiMAX) Transfer Entry Table 0x6100 80A0 0x6100 81FF Byte and Word MAX1 (LoMAX) Event Entry Table 0x6200 8000 0x6200 807F Byte and Word Reserved 0x6200 8080 0x6200 809F MAX1 (LoMAX) Transfer Entry Table 0x6200 80A0 0x6200 81FF Byte and Word External SDRAM space on EMIF 0x8000 0000 0x8FFF FFFF Byte and Word External Asynchronous Flash space on EMIF 0x9000 0000 0x9FFF FFFF Byte and Word EMIF Control Registers 0xF000 0000 0xF000 00BF Word Only (1) (1) The upper byte of the EMIF s SDRAM Configuration Register (SDCR[31:24]) is byte-addressable to support placing the EMIF into the Self-Refresh State without triggering the SDRAM Initialization Sequence. Submit Documentation Feedback Device Overview

www.ti.com 2.8 Boot Modes TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader stored in ROM. The software bootloader uses the CFGPIN0 and CFGPIN1 registers, which capture the state of various device pins at reset, to determine which mode to enter. Note that in practice, only a few pins are used by the software. CAUTION Only an externally applied RESET causes the CFGPIN0 and CFGPIN1 registers to recapture their associated pin values. Neither an emulator reset nor a RTI reset causes these registers to update. The ROM bootmodes include: Parallel Flash on EM_CS[2] SPI0 or I2C1 master mode from serial EEPROM SPI0 or I2C1 slave mode from external MCU UHPI from an external MCU Table 2-9 describes the required boot pin settings at device reset for each bootmode. Table 2-9. Required Boot Pin Settings at Device Reset BOOT MODE UHPI_HCS SPI0_SOMI SPI0_SIMO SPI0_CLK UHPI BYTEAD (1) FULL (1) NMUX (1) Parallel Flash SPI0 Master SPI0 Slave I2C1 Master I2C1 Slave (1) When UHPI_HCS is the state of the SPI0_SOMI, SPI0_SIMO, and SPI0_CLK pins is copied into the specified bits in the CFGHPI register described in Table 4-14 Refer to the C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM Data Manual (literature number SPRS277) for details on supported bootmodes and their implementation. Device Overview Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a bits. Reserved PINCAP7 PINCAP6 PINCAP5 PINCAP4 PINCAP3 PINCAP2 PINCAP1 PINCAP0 LEGEND: R/W Read/Write; R Read only; n value after reset Figure 2-6. CFGPIN0 Register Bit Layout (0x4000 0000) Table 2-10. CFGPIN0 Register Bit Field (0x4000 0000) BIT NO. NAME 31:8 Reserved Reads are indeterminate. Only should be written to these bits. PINCAP7 SPI0_SOMI/I2C0_SDA pin state captured on rising edge of RESET pin. PINCAP6 SPI0_SIMO pin state captured on rising edge of RESET pin. PINCAP5 SPI0_CLK/I2C0_SCL pin state captured on rising edge of RESET pin. PINCAP4 SPI0_SCS /I2C1_SCL pin state captured on rising edge of RESET pin. PINCAP3 SPI0_ENA /I2C1_SDA pin state captured on rising edge of RESET pin. PINCAP2 AXR0[8]/AXR1[5]/SPI1_SOMI pin state captured on rising edge of RESET pin. PINCAP1 AXR0[9]/AXR1[4]/SPI1_SIMO pin state captured on rising edge of RESET pin. PINCAP0 AXR0[7]/SPI1_CLK pin state captured on rising edge of RESET pin. Submit Documentation Feedback Device Overview

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 2-7 shows the bit layout of the CFGPIN1 register and Table 2-11 contains a bits. Reserved PINCAP15 PINCAP14 PINCAP13 PINCAP12 PINCAP11 PINCAP10 PINCAP9 PINCAP8 LEGEND: R/W Read/Write; R Read only; n value after reset Figure 2-7. CFGPIN1 Register Bit Layout (0x4000 0004) Table 2-11. CFGPIN1 Register Bit Field (0x4000 0004) BIT NO. NAME 31:8 Reserved Reads are indeterminate. Only should be written to these bits. PINCAP15 AXR0[5]/ SPI1_SCS pin state captured on rising edge of RESET pin. PINCAP14 AXR0[6]/ SPI1_ENA pin state captured on rising edge of RESET pin. PINCAP13 UHPI_HCS pin state captured on rising edge of RESET pin. PINCAP12 UHPI_HD[0] pin state captured on rising edge of RESET pin. PINCAP11 EM_D[16]/UHPI_HA[0] pin state captured on rising edge of RESET pin. PINCAP10 AFSX0 pin state captured on rising edge of RESET pin. PINCAP9 AFSR0 pin state captured on rising edge of RESET pin. PINCAP8 AXR0[0] pin state captured on rising edge of RESET pin. Device Overview Submit Documentation Feedback

www.ti.com 2.9 Pin Assignments 2.9.1 Pin Maps /C0083/C0080/C0073/C0048/C0095/C0069/C0078/C0065 /C0047/C0073/C0050/C0067/C0049/C0095 /C0083/C0068/C0065 /C0083/C0080/C0073/C0048/C0095/C0067/C0076/C0075 /C0047/C0073/C0050/C0067/C0048/C0095 /C0083/C0067/C0076 /C0068/C0086/C0068/C0068 /C0086/C0083/C0083 /C0069/C0077/C0095/C0082/C0087 /C0069/C0077/C0095/C0082/C0065/C0083 /C0086/C0083/C0083 /C0069/C0077/C0095/C0066/C0065/C0091/C0049/C0093 /C0069/C0077/C0095/C0065/C0091/C0048/C0093 /C0086/C0083/C0083 /C0069/C0077/C0095/C0065/C0091/C0051/C0093 /C0069/C0077/C0095/C0065/C0091/C0053/C0093 /C0069/C0077/C0095/C0065/C0091/C0055/C0093 /C0069/C0077/C0095/C0065/C0091/C0057/C0093 /C0068/C0086/C0068/C0068 /C0086/C0083/C0083/C0068/C0086/C0068/C0068 /C0069/C0077/C0095/C0087/C0069/C0095 /C0068/C0081/C0077/C0091/C0051/C0093 /C0069/C0077/C0095/C0065/C0091/C0049/C0049/C0093 /C0069/C0077/C0095/C0065/C0091/C0056/C0093 /C0069/C0077/C0095/C0065/C0091/C0054/C0093 /C0069/C0077/C0095/C0065/C0091/C0052/C0093 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/C0079/C0083/C0067/C0086/C0083/C0083 /C0072/C0068/C0091/C0049/C0054/C0093 /C0047/C0072/C0072/C0087/C0073/C0076 /C0085/C0072/C0080/C0073/C0095 /C0086/C0083/C0083 /C0065/C0070/C0083/C0082/C0049 /C0065/C0067/C0076/C0075/C0082/C0049 /C0065/C0072/C0067/C0076/C0075/C0088/C0049 /C0065/C0077/C0085/C0084/C0069/C0048 /C0084 /C0082 /C0080 /C0078 /C0077 /C0076 /C0075 /C0074 /C0072 /C0071 /C0070 /C0069 /C0068 /C0067 /C0066 /C0065 /C0049 /C0050 /C0051 /C0052 /C0053 /C0054 /C0055 /C0056 /C0057 /C0049/C0048 /C0049/C0049 /C0049/C0050 /C0049/C0051 /C0049/C0052 /C0049/C0053 /C0049/C0054 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 2-8 and Figure 2-9 show the pin assignments on the 256-terminal GDH/ZDH package and the 144-pin RFP package, respectively. Figure 2-8. 256-Terminal Ball Grid Array (GDH/ZDH Suffix) Bottom View Submit Documentation Feedback Device Overview

www.ti.com EM_A[7] 109 1 108 2 107 3 106 4 105 5 104 6 103 7 102 8 101 9 100 10 99 11 98 12 97 13 96 14 95 15 94 16 93 17 92 18 91 19 90 20 89 21 88 22 87 23 86 24 85 25 84 26 83 27 82 28 81 29 80 30 79 32 77 33 76 34 75 35 74 36 73 110 71 111 70 112 69 113 68 114 67 115 66 116 65 117 64 118 63 119 62 120 61 121 60 122 59 123 58 124 57 125 56 126 55 127 54 128 53 129 52 130 51 131 50 132 49 133 48 134 47 135 46 136 45 137 44 138 43 139 42 140 41 141 40 142 39 143 38 37144 VSS AHCLKX0/AHCLKX2 AMUTE0 AMUTE1 AHCLKX1 VSS ACLKX1 CV DD ACLKR1 DV DD AFSX1 AFSR1 VSS RESET VSS CV DD CLKIN VSS TMS CV DD TRST OSCV SS OSCIN OSCOUT OSCV DD VSS PLLHV TDI TDO VSS DV DD EMU[0] CV DD EMU[1] TCK VSS SPI0_CLK/I2C0_SCL SPI0_SCS /I2C1_SCL VSS SPI0_ENA /I2C1_SDA EM_OE DV DD EM_RW CV DD EM_CS[2] VSS EM_RAS EM_CS[0] EM_BA[0] VSS EM_BA[1] EM_A[10] DV DD EM_A[0] CV DD EM_A[1] EM_A[2] VSS EM_A[3] CV DD EM_A[4] EM_A[5] VSS DV DD EM_A[6] VSS CV DD EM_A[8] EM_A[9] EM_A[11] DV DD VSS SPI0_SIMO SPI0_SOMI/I2C0_SDA DV DD AXR0[0] VSS AXR0[1] AXR0[2] AXR0[3] V SS AXR0[4] AXR0[5]/SPI1_SCS AXR0[6]/SPI1_ENA AXR0[7]/SPI1_CLK CV DD VSS DV DD AXR0[8]/AXR1[5]/SPI1_SOMI AXR0[9]/AXR1[4]/SPI1_SIMO CV DD VSS AXR0[10]/AXR1[3] AXR0[11]/AXR1[2] CV DD VSS AXR0[12]/AXR1[1] AXR0[13]/AXR1[0] DV DD AXR0[14]/AXR2[1] AXR0[15]/AXR2[0] ACLKR0 V SS AFSR0 ACLKX0 AHCLKR0/AHCLKR1 AFSX0 VSS EM_CLK EM_CKE V SS DV DD EM_WE _DQM[1] EM_D[8] CV DD EM_D[9] EM_D[10] V SS EM_D[11] DV DD EM_D[12] EM_D[13] CV DD EM_D[14] EM_D[15] V SS CV DD EM_D[0] EM_D[1] DV DD EM_D[2] EM_D[3] V SS EM_D[4] EM_D[5] CV DD EM_D[6] DV DD EM_D[7] V SS EM_WE _DQM[0] EM_WE EM_CAS TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Actual size of Thermal Pad is 5.4 mm נ 5.4 mm. See Section 7.3 Figure 2-9. 144-Pin Low-Profile Quad Flatpack (RFP Suffix) Top View Device Overview Submit Documentation Feedback

www.ti.com 2.9.2 Terminal Functions TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 2-12 the Terminal Functions table, identifies the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description. Table 2-12. Terminal Functions GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) (EMIF) Address and Control EM_A[0] J16 O N EM_A[1] J15 O N EM_A[2] K15 O N EM_A[3] L16 O N EM_A[4] L15 O N EM_A[5] M16 O N EM_A[6] M15 O N EMIF Address Bus EM_A[7] N16 O N EM_A[8] N15 O N EM_A[9] P16 O N EM_A[10] H15 O N EM_A[11] P15 O N EM_A[12] P12 O IPD N EM_BA[0] G15 O N SDRAM Bank Address and Asynchronous Memory Low-Order Address EM_BA[1] H16 O N EM_CS[0] F15 O N SDRAM Chip Select EM_CS[2] 100 E15 O N Asynchronous Memory Chip Select EM_CAS O N SDRAM Column Address Strobe EM_RAS F16 O N SDRAM Row Address Strobe EM_WE O N SDRAM/Asynchronous Write Enable EM_CKE T14 O N SDRAM Clock Enable EM_CLK R14 O N EMIF Output Clock EM_ WE _DQM[0] O N Write Enable or Byte Enable for EM_D[7:0] EM_ WE _DQM[1] T13 O N Write Enable or Byte Enable for EM_D[15:8] EM_ WE _DQM[2] P13 O IPU N Write Enable or Byte Enable for EM_D[23:16] EM_ WE _DQM[3] R15 O IPU N Write Enable or Byte Enable for EM_D[31:24] EM_OE 104 D15 O N SDRAM/Asynchronous Output Enable EM_R W 102 E16 O N Asynchronous Memory Read/not Write Asynchronous Wait Input Programmable Polarity or EM_WAIT D14 I IPU N Interrupt NAND (1) TYPE column refers to pin direction in functional mode. If a pin has more than one function with different directions, the functions are separated with a slash (/). (2) PULL column: IPD Internal Pulldown resistor IPU Internal Pullup resistor (3) If the GPIO column is 'Y', then in GPIO mode, the pin is configurable as an IO unless otherwise marked. Submit Documentation Feedback Device Overview

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) (EMIF) Data Bus Universal Host-Port Interface (UHPI) Address Bus Option EM_D[0] IO N EM_D[1] IO N EM_D[2] IO N EM_D[3] IO N EM_D[4] IO N EM_D[5] IO N EM_D[6] IO N EM_D[7] IO N EMIF Data Bus [Lower Bits] EM_D[8] R13 IO N EM_D[9] T12 IO N EM_D[10] R12 IO N EM_D[11] T11 IO N EM_D[12] R11 IO N EM_D[13] R10 IO N EM_D[14] IO N EM_D[15] IO N EM_D[16]/UHPI_HA[0] IO/I IPD N EM_D[17]/UHPI_HA[1] IO/I IPD N EM_D[18]/UHPI_HA[2] IO/I IPD N EM_D[19]/UHPI_HA[3] IO/I IPD N EM_D[20]/UHPI_HA[4] IO/I IPD N EM_D[21]/UHPI_HA[5] IO/I IPD N EM_D[22]/UHPI_HA[6] IO/I IPD N EM_D[23]/UHPI_HA[7] IO/I IPD N EMIF Data Bus [Upper Bits (IO)] or UHPI Address Input (I) EM_D[24]/UHPI_HA[8] P11 IO/I IPD N EM_D[25]/UHPI_HA[9] N11 IO/I IPD N EM_D[26]/UHPI_HA[10] P10 IO/I IPD N EM_D[27]/UHPI_HA[11] N10 IO/I IPD N EM_D[28]/UHPI_HA[12] IO/I IPD N EM_D[29]/UHPI_HA[13] IO/I IPD N EM_D[30]/UHPI_HA[14] IO/I IPD N EM_D[31]/UHPI_HA[15] IO/I IPD N Device Overview Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) (UHPI) Data and Control UHPI_HD[0] K13 IO IPD Y UHPI_HD[1] K14 IO IPD Y UHPI_HD[2] M14 IO IPD Y UHPI_HD[3] L13 IO IPD Y UHPI_HD[4] L14 IO IPD Y UHPI_HD[5] N13 IO IPD Y UHPI_HD[6] N14 IO IPD Y UHPI_HD[7] P14 IO IPD Y UHPI Data Bus [Lower Bits] UHPI_HD[8] E14 IO IPD Y UHPI_HD[9] F14 IO IPD Y UHPI_HD[10] F13 IO IPD Y UHPI_HD[11] G14 IO IPD Y UHPI_HD[12] G13 IO IPD Y UHPI_HD[13] H14 IO IPD Y UHPI_HD[14] H13 IO IPD Y UHPI_HD[15] J13 IO IPD Y UHPI_HD[16]/HHWIL IO/I IPD Y UHPI_HD[17] IO IPD Y UHPI_HD[18] IO IPD Y UHPI_HD[19] IO IPD Y UHPI_HD[20] IO IPD Y UHPI Data Bus [Upper Bits (IO)] in the following modes: UHPI_HD[21] IO IPD Y Fullword Multiplexed Address and Data UHPI_HD[22] IO IPD Y Fullword Non-Multiplexed UHPI_HD[23] IO IPD Y UHPI_HHWIL (I) on pin UHPI_HD[16]/HHWIL and GPIO UHPI_HD[24] IO IPD Y on other pins in the following mode: UHPI_HD[25] IO IPD Y Half-word Multiplexed Address and Data UHPI_HD[26] IO IPD Y In this mode, UHPI_HHWIL indicates whether the high or low half-word is being addressed. UHPI_HD[27] IO IPD Y UHPI_HD[28] IO IPD Y UHPI_HD[29] IO IPD Y UHPI_HD[30] IO IPD Y UHPI_HD[31] IO IPD Y Universal Host-Port Interface (UHPI) Control UHPI_HBE[0] I IPD Y UHPI Byte Enable for UHPI_HD[7:0] UHPI_HBE[1] I IPD Y UHPI Byte Enable for UHPI_HD[15:8] UHPI_HBE[2] I IPD Y UHPI Byte Enable for UHPI_HD[23:16] UHPI_HBE[3] I IPD Y UHPI Byte Enable for UHPI_HD[31:24] UHPI_HCNTL[0] I IPD Y UHPI Control Inputs Select Access Mode UHPI_HCNTL[1] C10 I IPD Y UHPI Host Address Strobe for Hosts with Multiplexed UHPI_HAS I IPD Y Address/Data bus UHPI_HR W I IPD Y UHPI Read/not Write Input UHPI_HDS[1] I IPU Y UHPI Select Signals which create the internal HSTROBE active when: UHPI_HDS[2] I IPU Y UHPI_HCS '0') UHPI_HDS[1] UHPI_HDS[2] UHPI_HCS I IPU Y UHPI_HRDY O IPD Y UHPI Ready Output Submit Documentation Feedback Device Overview

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) McASP0, McASP1, McASP2, and SPI1 Serial Ports (4) AHCLKR0/AHCLKR1 143 IO Y McASP0 and McASP1 Receive Master Clock ACLKR0 139 IO Y McASP0 Receive Bit Clock AFSR0 141 IO Y McASP0 Receive Frame Sync (L/R Clock) AHCLKX0/AHCLKX2 IO Y McASP0 and McASP2 Transmit Master Clock (4) ACLKX0 142 IO Y McASP0 Transmit Bit Clock AFSX0 144 IO Y McASP0 Transmit Frame Sync (L/R Clock) AMUTE0 O Y McASP0 MUTE Output AXR0[0] 113 A14 IO Y McASP0 Serial Data AXR0[1] 115 B13 IO Y McASP0 Serial Data AXR0[2] 116 A13 IO Y McASP0 Serial Data AXR0[3] 117 B12 IO Y McASP0 Serial Data AXR0[4] 119 A12 IO Y McASP0 Serial Data AXR0[5]/ SPI1_SCS 120 B11 IO Y McASP0 Serial Data or SPI1 Slave Chip Select AXR0[6]/ SPI1_ENA 121 A11 IO Y McASP0 Serial Data or SPI1 Enable (Ready) AXR0[7]/SPI1_CLK 122 B10 IO Y McASP0 Serial Data or SPI1 Serial Clock AXR0[8]/AXR1[5]/ McASP0 Serial Data or McASP1 Serial Data or SPI1 126 IO Y SPI1_SOMI Data Pin Slave Out Master In AXR0[9]/AXR1[4]/ McASP0 Serial Data or McASP1 Serial Data or SPI1 127 IO Y SPI1_SIMO Data Pin Slave In Master Out AXR0[10]/AXR1[3] 130 IO Y McASP0 Serial Data or McASP1 Serial Data AXR0[11]/AXR1[2] 131 IO Y McASP0 Serial Data or McASP1 Serial Data AXR0[12]/AXR1[1] 134 IO Y McASP0 Serial Data or McASP1 Serial Data AXR0[13]/AXR1[0] 135 IO Y McASP0 Serial Data or McASP1 Serial Data AXR0[14]/AXR2[1] 137 IO Y McASP0 Serial Data or McASP2 Serial Data (4) AXR0[15]/AXR2[0] 138 IO Y McASP0 Serial Data or McASP2 Serial Data (4) ACLKR1 IO Y McASP1 Receive Bit Clock AFSR1 IO Y McASP1 Receive Frame Sync (L/R Clock) AHCLKX1 IO Y McASP1 Transmit Master Clock ACLKX1 IO Y McASP1 Transmit Bit Clock AFSX1 IO Y McASP1 Transmit Frame Sync (L/R Clock) AMUTE1 O Y McASP1 MUTE Output AHCLKR2 C14 IO IPD Y McASP2 Receive Master Clock ACLKR2 C13 IO IPD Y McASP2 Receive Bit Clock AFSR2 C12 IO IPD Y McASP2 Receive Frame Sync (L/R Clock) ACLKX2 D11 IO IPD Y McASP2 Transmit Bit Clock AFSX2 C11 IO IPD Y McASP2 Transmit Frame Sync (L/R Clock) AMUTE2/ HINT D10 O IPD Y McASP2 MUTE Output or UHPI Host Interrupt SPI0, I2C0, and I2C1 Serial Port Pins SPI0_SOMI/I2C0_SDA 111 B14 IO Y SPI0 Data Pin Slave Out Master In or I2C0 Serial Data SPI0_SIMO 110 B15 IO Y SPI0 Data Pin Slave In Master Out SPI0_CLK/I2C0_SCL 108 C16 IO Y SPI0 Serial Clock or I2C0 Serial Clock SPI0_SCS /I2C1_SCL 107 C15 IO Y SPI0 Slave Chip Select or I2C1 Serial Clock SPI0_ENA /I2C1_SDA 105 D16 IO Y SPI0 Enable (Ready) or I2C1 Serial Data (4) McASP2 is not available on the C6722B and C6720. Device Overview Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME RFP TYPE (1) PULL (2) GPIO (3) I N 1.2-V Oscillator Input OSCOUT O N 1.2-V Oscillator Output OSCV DD PWR N Oscillator 1.2-V V DD tap point (for filter only) OSCV SS PWR N Oscillator V SS tap point (for filter only) CLKIN I N Alternate clock input (3.3-V LVCMOS Input) PLLHV PWR N PLL 3.3-V Supply Input (requires external filter) Device Reset RESET I N Device reset pin Emulation/JTAG Port TCK I IPU N Test Clock TMS I IPU N Test Mode Select TDI I IPU N Test Data In TDO OZ IPU N Test Data Out TRST I IPD N Test Reset EMU[0] IO IPU N Emulation Pin EMU[1] IO IPU N Emulation Pin Power Pins 256-Terminal GDH/ZDH Package Core Supply (CV DD E6, E7, E8, E9, E10, E11, G5, G12, H5, H12, J5, J12, K5, K12, M6, M7, M8, M9, M10, M11 IO Supply (DV DD A2, A15, B1, B16, D4, D5, D12, D13, E4, E13, J14, M4, M13, N5, N12, P8, R1, R16, T2, T15 A1, A7, A10, A16, E5, E12, F5, F6, F7, F8, F9, F10, F11, F12, G1, G6, G7, G8, G9, G10, G11, G16, H3, H6, Ground SS H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K1, K6, K7, K8, K9, K10, K11, K16, L5, L6, L7, L8, L9, L10, L11, L12, M5, M12, T1, T7, T10, T16 Power Pins 144-Pin RFP Package Core Supply (CV DD 16, 20, 33, 44, 53, 57, 65, 77, 85, 90, 101, 123, 128, 132 IO Supply (DV DD 10, 31, 42, 50, 60, 68, 73, 81, 92, 103, 112, 125, 136 Ground SS 13, 15, 18, 26, 30, 36, 40, 47, 54, 62, 69, 72, 78, 82, 87, 95, 99, 106, 109, 114, 118, 124, 129, 133, 140 Submit Documentation Feedback Device Overview

www.ti.com 2.10 Development 2.10.1 Development Support 2.10.2 Device Support TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software DSP/BIOS which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System XDS Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 2.10.2.1 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS 320C6727BZDH275). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX TMDX) through fully qualified production devices/tools (TMS TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully-qualified production device Support tool development evolutionary flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI s standard warranty applies. Device Overview Submit Documentation Feedback

www.ti.com C672x DSP: 6727B 6726B 6722B 6720 PREFIX DEVICE SPEED RANGE TMS 320 C6727B GDH 250 TMX = Experimental device TMP = Prototype device TMS = Qualified device DEVICE FAMIL Y 320 = TMS320 /C0116 DSP family PACKAGE TYPE ³§ GDH = 256-terminal plastic BGA ZDH = 256-terminal Green plastic BGA RFP = 144-pin PowerPAD  Green TQFP DEVICE ¶ † The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices. For more details, see the recommended operating conditions portion of this data sheet. ‡ BGA = Ball Grid Array TQFP = Thin Quad Flatpack § The ZDH mechanical package designator represents the Green version of the GDH package. For more detailed information, see the Mechanical Data section of this document. ¶ For actual device part numbers (P/Ns) and ordering information, see the TI website (www.ti.com). TEMPERA TURE RANGE (DEF AULT : 0°C TO 90°C)² A Blank = 0°C to 90°C, commercial temperature A = −40 °C to 105°C, extended temperature 350 (350-MHz CPU) 300 (300-MHz CPU) 275 (275-MHz CPU) 266 (266-MHz CPU) 250 (250-MHz CPU) 225 (225-MHz CPU) 200 (200-MHz CPU) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZDH), the temperature range (for example, A is the extended temperature range), and the device speed range in megahertz (for example, -300 is 300 MHz). Figure 2-10 provides a legend for reading the complete device name for any TMS320C6000 DSP platform member. The ZDH package, like the GDH package, is a 256-ball plastic BGA, but Green. For device part numbers and further ordering information for TMS320C672x in the GDH, ZDH, and RFP package types, see the Texas Instruments (TI) website at http://www.ti.com or contact your TI sales representative. Figure 2-10. TMS320C672x DSP Device Nomenclature Submit Documentation Feedback Device Overview

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 2.10.2.2 Documentation Support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through development. The types of documentation available include: data manuals, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C672x DSP devices: SPRS277 C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM Data Manual. Describes the ROM. SPRZ232 TMS320C6727, TMS320C6727B, TMS320C6726, TMS320C6726B, TMS320C6722, TMS320C6722B, TMS320C6720 Digital Signal Processors Silicon Errata. Describes the known exceptions to the functional specifications for the TMS320C6727, TMS320C6727B, TMS320C6726, TMS320C6726B, TMS320C6722, TMS320C6722B, and TMS320C6720 digital signal processors (DSPs). SPRU723 TMS320C672x DSP Peripherals Overview Reference Guide. This document provides an overview and briefly describes the peripherals available on the TMS320C672x digital signal processors (DSPs) of the TMS320C6000 DSP platform. SPRU877 TMS320C672x DSP Inter-Integrated Circuit (I2C) Module Reference Guide. This document describes the inter-integrated circuit (I2C) module in the TMS320C672x digital signal processors (DSPs) of the TMS320C6000 DSP platform. SPRU795 TMS320C672x DSP Dual Data Movement Accelerator (dMAX) Reference Guide. This document provides an overview and describes the common operation of the data movement accelerator (dMAX) controller in the TMS320C672x digital signal processors (DSPs) of the TMS320C6000 DSP platform. This document also describes operations and registers unique to the dMAX controller. SPRAA78 TMS320C6713 to TMS320C672x Migration. This document describes the issues related to migrating from the TMS320C6713 to TMS320C672x digital signal processor (DSP). SPRU711 TMS320C672x DSP External Memory Interface (EMIF) User's Guide. This document describes the operation of the external memory interface (EMIF) in the TMS320C672x digital signal processors (DSPs) of the TMS320C6000 DSP platform. SPRU718 TMS320C672x DSP Serial Peripheral Interface (SPI) Reference Guide. This reference guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length shift register, used for high speed communication between external peripherals or other DSPs. SPRU719 TMS320C672x DSP Universal Host Port Interface (UHPI) Reference Guide. This document provides an overview and describes the common operation of the universal host port interface (UHPI). SPRU878 TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide. This document describes the multichannel audio serial port (McASP) in the TMS320C672x digital signal processors (DSPs) of the TMS320C6000 DSP platform. SPRU879 TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide. This document describes the operation of the software-programmable phase-locked loop (PLL) controller in the TMS320C672x digital signal processors (DSPs) of the TMS320C6000 DSP platform. Device Overview Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 SPRU733 TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C67x and TMS320C67x+ digital signal processors (DSPs) of the TMS320C6000 DSP platform. The C67x/C67x+ DSP generation comprises floating-point devices in the C6000 DSP platform. The C67x+ DSP is an enhancement of the C67x DSP with added functionality and an expanded instruction set. SPRAA69 Using the TMS320C672x Bootloader Application Report. This document describes the design details about the TMS320C672x bootloader. This document also addresses parallel flash and HPI boot to the extent relevant. SPRU301 TMS320C6000 Code Composer Studio Tutorial. This tutorial introduces you to some of the key Studio. Code Composer Studio extends the capabilities of the Code Composer Integrated Development Environment (IDE) to include full awareness of the DSP target by the host and real-time analysis tools. This tutorial assumes that you have Code Composer Studio, which includes the TMS320C6000 code generation tools along with the APIs and plug-ins for both DSP/BIOS and RTDX. This manual also assumes that you have installed a target board in your PC containing the DSP device. SPRU198 TMS320C6000 Programmer's Guide. Reference for programming the TMS320C6000 digital signal processors (DSPs). Before you use this manual, you should install your code generation and debugging tools. Includes a brief flow, includes C code examples and discusses optimization methods for the C code, describes the structure of assembly code and includes examples and discusses optimizations for the assembly code, and describes programming considerations for the C64x DSP. SPRU186 TMS320C6000 Assembly Language Tools v6.0 Beta User's Guide. Describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C6000 platform of devices (including the C64x+ and C67x+ generations). NOTE: The enhancements to tools release v5.3 to support the C672x devices are documented in the tools v6.0 documentation. SPRU187 TMS320C6000 Optimizing Compiler v6.0 Beta User's Guide. Describes the TMS320C6000 C compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code and produces assembly language source code for the TMS320C6000 platform of devices (including the C64x+ and C67x+ generations). The assembly optimizer helps you optimize your assembly code. NOTE: The enhancements to tools release v5.3 to support the C672x devices are documented in the tools v6.0 documentation. SPRA839 Using IBIS Models for Timing Analysis Describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). Submit Documentation Feedback Device Overview

www.ti.com Device Configurations 3.1 Device Configuration Registers 3.2 Peripheral Pin Multiplexing Options TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x DSP includes several device-level configuration registers, which are listed in Table 3-1 These registers need to be programmed as part of the device initialization procedure. See Section 3.2 Table 3-1. Device-Level Configuration Registers REGISTER NAME BYTE ADDRESS pin. Table 2-10 CFGPIN1 0x4000 0004 Captures values of eight pins on rising edge of RESET pin. Table 2-11 CFGHPI 0x4000 0008 Controls enable of UHPI and selection of its operating mode. Table 4-14 CFGHPIAMSB 0x4000 000C Controls upper byte of UHPI address into C672x address space in Table 4-15 Non-Multiplexed Mode or if explicitly enabled for security purposes. CFGHPIAUMB 0x4000 0010 Controls upper middle byte of UHPI address into C672x address space Table 4-16 in Non-Multiplexed Mode or if explicitly enabled for security purposes. CFGRTI 0x4000 0014 Selects the sources for the RTI Input Captures from among the six Table 4-39 McASP DMA events. CFGMCASP0 0x4000 0018 Selects the peripheral pin to be used as AMUTEIN0. Table 4-21 CFGMCASP1 0x4000 001C Selects the peripheral pin to be used as AMUTEIN1. Table 4-22 CFGMCASP2 (1) 0x4000 0020 Selects the peripheral pin to be used as AMUTEIN2. Table 4-23 CFGBRIDGE 0x4000 0024 Controls reset of the bridge BR2 in Figure 2-4 This bridge must be reset Table 2-7 explicitly after any change to the PLL controller affecting SYSCLK1 and SYSCLK2 and before the dMAX or UHPI accesses the CPU Slave Port (CSP). (1) CFGMCASP2 is reserved on the C6722B and C6720. This section describes the options for configuring peripherals which share pins on the C672x DSP. Table 3-2 lists the options for configuring the SPI0, I2C0, and I2C1 peripheral pins. Table 3-2. Options for Configuring SPI0, I2C0, and I2C1 CONFIGURATION OPTION OPTION OPTION PERIPHERAL SPI0 3-, 4,- or 5-pin mode 3-pin mode disabled I2C0 disabled disabled enabled I2C1 disabled enabled enabled PINS SPI0_SOMI/I2C0_SDA SPI0_SOMI SPI0_SOMI I2C0_SDA SPI0_SIMO SPI0_SIMO SPI0_SIMO GPIO through SPI0_SIMO pin control SPI0_CLK/I2C0_SCL SPI0_CLK SPI0_CLK I2C0_SCL SPI0_SCS /I2C1_SCL SPI0_SCS I2C1_SCL I2C1_SCL SPI0_ENA /I2C1_SDA SPI0_ENA I2C1_SDA I2C1_SDA Device Configurations Submit Documentation Feedback

www.ti.com 3.3 Peripheral Pin Multiplexing Control TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 3-3 lists the options for configuring the SPI1, McASP0, and McASP1 pins. Note that there are additional finer grain options when selecting which McASP controls the particular AXR serial data pins but these options are not listed here and can be made on a pin by pin basis. Table 3-3. Options for Configuring SPI1, McASP0, and McASP1 Data Pins CONFIGURATION OPTION OPTION OPTION OPTION OPTION PERIPHERAL SPI1 5-pin mode 4-pin mode 4-pin mode 3-pin mode disabled McASP0 (max data pins) McASP1 (max data pins) PINS AXR0[5]/ SPI1_SCS SPI1_SCS AXR0[5] AXR0[5] AXR0[5] SPI1_SCS AXR0[6]/ SPI1_ENA AXR0[6] SPI1_ENA AXR0[6] AXR0[6] SPI1_ENA AXR0[7]/ SPI1_CLK SPI1_CLK SPI1_CLK SPI1_CLK AXR0[7] SPI1_CLK AXR0[8]/AXR1[5]/ SPI1_SOMI SPI1_SOMI SPI1_SOMI SPI1_SOMI AXR0[8] or AXR1[5] SPI1_SOMI AXR0[9]/AXR1[4]/ SPI1_SIMO SPI1_SIMO SPI1_SIMO SPI1_SIMO AXR0[9] or AXR1[4] SPI1_SIMO Table 3-4 lists the options for configuring the shared EMIF and UHPI pins. Table 3-4. Options for Configuring EMIF and UHPI (C6727B Only) CONFIGURATION OPTION OPTION PERIPHERAL UHPI Multiplexed Address/Data Mode, Fullword, or Non-Multiplexed Address/Data Mode Half-Word Fullword EMIF 32-bit EMIF Data 16-bit EMIF Data PINS EM_D[31:16]/ EM_D[31:16] UHPI_HA[15:0] UHPI_HA[15:0] While Section 3.2 describes at a high level the most common pin multiplexing options, the control of pin multiplexing is largely determined on an individual pin-by-pin basis. Typically, each peripheral that shares a particular pin has internal control registers to determine the pin function and whether it is an input or an output. The C672x device determines whether a particular pin is an input or output based upon the following rules: The pin will be configured as an output if it is configured as an output in any of the peripherals sharing the pin. It is recommended that only one peripheral configure a given pin as an output. If more than one peripheral does configure a particular pin as an output, then the output value is controlled by the peripheral with highest priority for that pin. The priorities for each pin are given in Table 3-5 The value input on the pin is passed to all peripherals sharing the pin for input simultaneously. Submit Documentation Feedback Device Configurations

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 3-5. Priority of Control of Data Output on Multiplexed Pins PIN FIRST PRIORITY SECOND PRIORITY THIRD PRIORITY SPI0_SOMI/I2C0_SDA SPI0_SOMI I2C0_SDA SPI0_CLK/I2C0_SCL SPI0_CLK I2C0_SCL SPI0_SCS /I2C1_SCL SPI0_SCS I2C1_SCL SPI0_ENA /I2C1_SDA SPI0_ENA I2C1_SDA AXR0[5]/ SPI1_SCS AXR0[5] SPI1_SCS AXR0[6]/ SPI1_ENA AXR0[6] SPI1_ENA AXR0[7]/SPI1_CLK AXR0[7] SPI1_CLK AXR0[8]/AXR1[5]/SPI1_SOMI AXR0[8] AXR1[5] SPI1_SOMI AXR0[9]/AXR1[4]/SPI1_SIMO AXR0[9] AXR1[4] SPI1_SIMO AXR0[10]/AXR1[3] AXR0[10] AXR1[3] AXR0[11]/AXR1[2] AXR0[11] AXR1[2] AXR0[12]/AXR1[1] AXR0[12] AXR1[1] AXR0[13]/AXR1[0] AXR0[13] AXR1[0] AXR0[14]/AXR2[1] AXR0[14] AXR2[1] AXR0[15]/AXR2[0] AXR0[15] AXR2[0] AHCLKR0/AHCLKR1 AHCLKR0 AHCLKR1 AHCLKX0/AHCLKX2 AHCLKX0 AHCLKX2 AMUTE2/HINT AMUTE2 HINT HD[16]/HHWIL HD[16] HHWIL EM_D[31:16]/UHPI_HA[15:0] (1) EM_D[31:16] (Disabled if UHPI_HA[15:0] (Input Only) CFGHPI.NMUX=1) (1) When using the UHPI in non-multiplexed mode, ensure EM_D[31:16] are configured as inputs so that these pins may be used as UHPI_HA[15:0]. To ensure this, you must set the CFGHPI.NMUX bit to a '1' before the EMIF SDRAM initialization completes otherwise, a drive conflict will occur. [The EMIF bus parking function drives the data bus in between accesses.] Device Configurations Submit Documentation Feedback

www.ti.com Peripheral and Electrical Specifications 4.1 Electrical Specifications 4.2 Absolute Maximum Ratings (1) (2) 4.3 Recommended Operating Conditions (1) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320C672x DSP. All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified. Over Operating Case Temperature Range (Unless Otherwise Noted) UNIT Supply voltage range, CV DD OSCV DD (3) 0.3 to 1.8 V Supply voltage range, DV DD PLLHV 0.3 to V Input Voltage Range All pins except OSCIN 0.3 to DV DD 0.5 V OSCIN pin 0.3 to CV DD 0.5 Output Voltage Range All pins except OSCOUT 0.3 to DV DD 0.5 V OSCOUT pin 0.3 to CV DD 0.5 Clamp Current mA Operating case temperature range T C Default to C A version to 105 Storage temperature range, T stg to 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with referenced to V SS unless otherwise specified. (3) If OSCV DD and OSCV SS pins are used as filter pins for reduced oscillator jitter, they should not be connected to CV DD and V SS externally. MIN NOM MAX UNIT CV DD Core Supply Voltage Default 1.14 1.2 1.32 V C6727B-350 1.33 1.40 1.47 DV DD I/O Supply Voltage 3.13 3.3 3.47 V T C Operating Case Temperature Range Default C A version 105 (1) All voltage values are with referenced to V SS unless otherwise specified. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.4 Electrical Characteristics TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Over Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH High Level Output Voltage I O 100 µ A DV DD 0.2 V V OL Low Level Output Voltage I O 100 µ A 0.2 V I OH High-Level Output Current V O 0.8 DV DD mA I OL Low-Level Output Current V O 0.22 DV DD mA V IH High-Level Input Voltage DV DD V V IL Low-Level Input Voltage 0.8 V V HYS Input Hysterisis 0.13 DV DD V I I I OZ Input Current and Off State Output Pins without pullup or pulldown Current Pins with internal pullup 170 µ A Pins with internal pulldown 170 t tr Input Transition Time ns C I Input Capacitance pF C O Output Capacitance pF I DD2V CV DD Supply (1) GDH/ZDH, CV DD 1.2 658 CPU clock 300 MHz mA RFP, CV DD 1.2 555 CPU clock 250 MHz I DD3V DV DD Supply (1) GDH/ZDH, DV DD 3.3 32-bit EMIF speed 100 MHz mA RFP, DV DD 3.3 16-bit EMIF speed 100 MHz (1) Assumes the following conditions: C case temperature; 60% CPU utilization; EMIF at 50% utilization (100 MHz), 50% writes, (32 bits for GDH/ZDH, bits for RFP), 50% bit switching; two 10-MHz SPI at 100% utilization, 50% bit switching. The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C672x Power Consumption Summary Application Report (literature number SPRAAA4 Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.5 Parameter Information 4.5.1 Parameter Information Device-Specific Information Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see note) Tester Pin Electronics Data Sheet Timing Reference Point Output Under Test 42 Ω 3.5 nH Device Pin (see note) Vref = 1.5 V Vref = VIL MAX (or VOL MAX) Vref = VIH MIN (or VOH MIN) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not neccessary to add or subtract the transmission line delay ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of Volts per nanosecond V/ns) at the device pin. Figure 4-1. Test Load Circuit for AC Timing Measurements 4.5.1.1 Signal Transition Levels All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels. Figure 4-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to V IL MAX and V IH MIN for input clocks, V OL MAX and V OH MIN for output clocks. Figure 4-3. Rise and Fall Transition Time Voltage Reference Levels 4.5.1.2 Signal Transition Rates All timings are tested with an input edge rate of Volts per nanosecond V/ns). Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.6 Timing Parameter Symbology TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid dis disable time Z High impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) X Unknown, changing, or don't care level Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.7 Power Supplies 4.7.1 Power-Supply Sequencing 4.7.2 Power-Supply Decoupling TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 For more information regarding TI s power management products and suggested devices to power TI DSPs, visit www.ti.com/dsppower This device does not require specific power-up sequencing between the DV DD and CV DD voltage rails; however, there are some considerations that the system designer should take into account: Neither supply should be powered up for an extended period of time second) while the other supply is powered down. The I/O buffers powered from the DV DD rail also require the CV DD rail to be powered up in order to be controlled; therefore, an I/O pin that is supposed to be 3-stated by default may actually drive momentarily until the CV DD rail has powered up. Systems should be evaluated to determine if there is a possibility for contention that needs to be addressed. In most systems where both the DV DD and CV DD supplies ramp together, as long as CV DD tracks DV DD closely, any contention is also mitigated by the fact that the CV DD rail would reach its specified operating range well before the DV DD rail has fully ramped. In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. The core supply caps can be placed in the interior space of the package and the I/O supply caps can be placed around the exterior space of the package. For the BGA package, it is recommended that both the core and I/O supply caps be placed on the underside of the PCB. For the TQFP package, it is recommended that the core supply caps be placed on the underside of the PCB and the I/O supply caps be placed on the top side of the PCB. Both core and I/O decoupling can be accomplished by alternating small (0.1 μ low ESR ceramic bypass caps with medium (0.220 μ low ESR ceramic bypass caps close to the DSP power pins and adding large tantalum or ceramic caps (ranging from μ F to 100 μ further away. Assuming 0603 caps, it is recommended that at least small, medium, and large caps be used for the core supply and small, medium, and large caps be used for the I/O supply. Any cap selection needs to be evaluated from an electromagnetic radiation (EMI) point-of-view; EMI varies from one system design to another so it is expected that engineers alter the decoupling capacitors to minimize radiation. Refer to the High-Speed DSP Systems Design Reference Guide (literature number SPRU889) for more detailed design information on decoupling techniques. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.8 Reset 4.8.1 Reset Electrical Data/Timing TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 A hardware reset RESET is required to place the DSP into a known good state out of power-up. The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be held low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions. Table 4-1 assumes testing over recommended operating conditions. Table 4-1. Reset Timing Requirements NO. MIN MAX UNIT t w(RSTL) Pulse width, RESET low 100 ns t su(BPV-RSTH) Setup time, boot pins valid before RESET high ns t h(RSTH-BPV) Hold time, boot pins valid after RESET high ns Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.9 Dual Data Movement Accelerator (dMAX) 4.9.1 dMAX Device-Specific Information TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The dMAX is a module designed to perform Data Movement Acceleration. The dMAX controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSP. The dMAX allows movement of data to/from any addressable memory space, including internal memory, peripherals, and external memory. The dMAX controller in the C672x DSP has a different architecture from the previous EDMA controller in the C621x/C671x devices. The dMAX controller includes features, such as capability to perform three-dimensional data transfers for advanced data sorting, capability to manage a section of the memory as a circular buffer/FIFO with delay tap based reading and writing data. The dMAX controller is capable of concurrently processing two transfer requests (provided that they are to/from different source/destinations). Figure 4-4 shows a block diagram of the dMAX controller. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com Event Entry #0 Event Entry #k Event Entry #31 Transfer Entry #0 Transfer Entry #k Transfer Entry #7 Reserved Event Entry Table Transfer Entry Table HiMAX RAM R/W Control R/W HiMAX (MAX0) Event Encoder Event and Interrupt Registers LoMAX (MAX1) Transfer Entry Table LoMAX RAM R/W Transfer Entry #7 Transfer Entry #k Transfer Entry #0 Event Entry #31 Reserved Event Table Entry Event Entry #k Event Entry #0 High-Priority REQ Low-Priority REQ High-Priority PaRAM To/From Crossbar Switch LoMAX Master Crossbar Switch Port Events Interrupt Lines to the CPU HiMAX Master Crossbar Switch Port dMAX Low-Priority PaRAM TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-4. dMAX Controller Block Diagram Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The dMAX controller comprises: Event and interrupt processing registers Event encoder High-priority event Parameter RAM (PaRAM) Low-priority event Parameter RAM (PaRAM) Address-generation hardware for High-Priority Events MAX0 (HiMAX) Address-generation hardware for Low-Priority Events MAX1 (LoMAX) The TMS320C672x Peripheral Bus Structure can be described logically as a Crossbar Switch with five master ports and five slave ports. When accessing the slave ports, the MAX0 (HiMAX) module is always given the highest priority followed by the MAX1 (LoMAX) module. In other words, in case several masters (including MAX0 and MAX1) attempt to access same slave port concurrently, the MAX0 will be given the highest priority followed by MAX1. Event signals are connected to bits of the dMAX Event Register (DER), and the bits in the DER reflect the current state of the event signals. An event is defined as a transition of the event signal. The dMAX Event Flag Register (DEFR) can be programmed, individually for each event signal, to capture either low-to-high or high-to-low transitions of the bits in the DER (event polarity is individually programmable). An event is a synchronization signal that can be used: to either trigger dMAX to start a transfer, or to generate an interrupt to the CPU. All the events are sorted into two groups: low-priority event group and high-priority event group. The High-Priority Data Movement Accelerator MAX0 (HiMAX) module is dedicated to serving requests coming from the high-priority event group. The Low-Priority Data Movement Accelerator MAX1 (LoMAX) module is dedicated to serving requests coming from the low-priority event group. Each PaRAM contains two sections: the event entry table section and the transfer entry table section. An event entry describes an event type and associates the event to either one of transfer types or to an interrupt. In case an event entry associates the event to one of the transfer types, the event entry will contain a pointer to the specific transfer entry in the transfer entry table. The transfer table may contain up to eight transfer entries. A transfer entry specifies details required by the dMAX controller to perform the transfer. In case an event entry associates the event to an interrupt, the event entry specifies which interrupt should be generated to the CPU in case the event arrives. Prior to enabling events and triggering a transfer, the event entry and transfer entry must be configured. The event entry must specify: type of transfer, transfer details (type of synchronization, reload, element size, etc.), and should include a pointer to the transfer entry. The transfer entry must specify: source, destination, counts, and indexes. If an event is sorted in the high-priority event group, the event entry and transfer entry must be specified in the high-priority Parameter RAM. If an event is sorted in the low-priority event group, the event entry and transfer entry must be specified in the low-priority parameter RAM. The dMAX Event Flag Register (DEFR) captures up to separate events; therefore, it is possible for events to occur simultaneously on the dMAX event inputs. In such cases, the event encoder resolves the order of processing. This mechanism sorts simultaneous events and sets the priority of the events. The dMAX controller can simultaneously process one event from each priority group. Therefore, the two highest-priority events (one from each group) can be processed at the same time. An event-triggered dMAX transfer allows the submission of transfer requests to occur automatically based on system events, without any intervention by the CPU. The dMAX also includes support for CPU-initiated transfers for added control and robustness, and they can be used to start memory-to-memory transfers. To generate an event to the dMAX controller the CPU must create a transition on one of the bits from the dMAX Event Trigger (DETR) Register, which are mapped to the DER register. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-2 lists how the synchronization events are associated with event numbers in the dMAX controller. Table 4-2. dMAX Peripheral Event Input Assignments EVENT NUMBER EVENT ACRONYM EVENT DETR[0] The CPU triggers the event by creating appropriate transition (edge) on bit0 in DETR register. DETR[16] The CPU triggers the event by creating appropriate transition (edge) on bit16 in DETR register. RTIREQ0 RTI DMA REQ[0] RTIREQ1 RTI DMA REQ[1] MCASP0TX McASP0 TX DMA REQ MCASP0RX McASP0 RX DMA REQ MCASP1TX McASP1 TX DMA REQ MCASP1RX McASP1 RX DMA REQ MCASP2TX McASP2 TX DMA REQ MCASP2RX McASP2 RX DMA REQ DETR[1] The CPU triggers the event by creating appropriate transition (edge) on bit1 in DETR register. DETR[17] The CPU triggers the event by creating appropriate transition (edge) on bit17 in DETR register. UHPIINT UHPI CPU_INT SPI0RX SPI0 DMA_RX_REQ SPI1RX SPI1 DMA_RX_REQ RTIREQ2 RTI DMA REQ[2] RTIREQ3 RTI DMA REQ[3] DETR[2] The CPU triggers the event by creating appropriate transition (edge) on bit2 in DETR register. DETR[18] The CPU triggers the event by creating appropriate transition (edge) on bit18 in DETR register. I2C0XEVT I2C Transmit Event I2C0REVT I2C Receive Event I2C1XEVT I2C Transmit Event I2C1REVT I2C Receive Event DETR[3] The CPU triggers the event by creating appropriate transition (edge) on bit3 in DETR register. DETR[19] The CPU triggers the event by creating appropriate transition (edge) on bit19 in DETR register. Reserved MCASP0ERR AMUTEIN0 or McASP0 TX INT or McASP0 RX INT (error on McASP0) MCASP1ERR AMUTEIN1 or McASP1 TX INT or McASP1 RX INT (error on McASP1) MCASP2ERR AMUTEIN2 or McASP2 TX INT or McASP2 RX INT (error on McASP2) OVLREQ[0/1] Error on RTI DETR[20] The CPU triggers the event by creating appropriate transition (edge) on bit20 in DETR register. DETR[21] The CPU triggers the event by creating appropriate transition (edge) on bit21 in DETR register. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.9.2 dMAX Peripheral Registers Description(s) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-3 is a list of the dMAX registers. Table 4-3. dMAX Configuration Registers BYTE ADDRESS REGISTER NAME (Located in C67x+ DSP Register File) N/A DESR Event Status Register (Located in C67x+ DSP Register File) Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.10 External Interrupts TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x DSP has no dedicated general-purpose interrupt pins, but the dMAX can be used in combination with a McASP AMUTEIN signal to provide external interrupt capability. There is a multiplexer for each McASP, controlled by the CFGMCASP0/1/2 registers, which allows the AMUTEIN input for that McASP to be sourced from one of seven I/O pins on the DSP. Once a pin is configured as an AMUTEIN source, a very short pulse (two SYSCLK2 cycles or more) on that pin will generate an event to the dMAX. This event can trigger the dMAX to generate a CPU interrupt by programming the assoicated Event Entry. There are a few additional points to consider when using the AMUTEIN signal to enable external interrupts as described above. The I/O pin selected by the CFGMCASP0/1/2 registers must be configured as a general-purpose input pin within the associated peripheral. Also, the AMUTEIN signal should be disabled within the corresponding McASP so that AMUTE is not driven when AMUTEIN is active. This can be done by clearing the INEN bit of the AMUTE register inside the McASP. Finally, AMUTEIN events are logically ORed with the McASP transmit and receive error events within the dMAX; therefore, the ISR that processes the dMAX interrupt generated by these events must discern the source of the event. The EMIF EM_WAIT pin has the ability to generate an NMI (INT1) based upon a rising edge on the EM_WAIT pin. Note that while this interrupt is connected to the CPU NMI (non-maskable interrupt), it is actually maskable through the EMIF control registers. In fact, the default state for this interrupt is disabled. Also, interrupt generation always occurs on a rising edge of EM_WAIT; the polarity selection for wait state generation has no effect on the interrupt polarity. The EM_WAIT pin should remain asserted for at least two SYSCLK3 cycles to ensure that the edge is detected. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.11 External Memory Interface (EMIF) 4.11.1 EMIF Device-Specific Information TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x DSP includes an external memory interface (EMIF) for optional SDRAM, NOR FLASH, NAND FLASH, or SRAM. The key are: One chip select EM_CS[0] dedicated for x16 and x32 SDRAM (x8 not supported) One chip select EM_CS[2] dedicated for x8, x16, or x32 NOR FLASH; x8, x16, or x32 Asynchronous SRAM; or or x16 NAND FLASH Data bus width is bits on the C6726B, C6722B, and C6720; and bits on the C6727B. SDRAM burst length of bytes External Wait Input on the C6727B through EM_WAIT (programmable active-high or active-low) External Wait pin functions as an interrupt for NAND Flash support NAND Flash logic calculates ECC on blocks of up to 512 bytes ECC logic suitable for single-bit errors Figure 4-5 and Figure 4-6 show typical examples of EMIF-to-memory hookup on the C672x DSP. As the figures illustrate, the C672x DSP includes a limited number of EMIF address lines. These are sufficient to connect to SDRAM seamlessly. Asynchronous memory such as FLASH typically will need to use additional GPIO pins to act as upper address lines during device boot up when the FLASH SDRAM. (Normally, code is executed from SDRAM since SDRAM has faster access times). Any pins listed with a in the GPIO column of Table 2-12 may be used for this purpose, as long as it can be assured that they be pulled low at (and after) reset and held low until configured as outputs by the DSP. Note that EM_BA[1:0] are used as low-order address lines for the asynchronous interface. For example, in Figure 4-5 and Figure 4-6 the flash memory is not byte-addressable and its A[0] input selects a 16-bit value. The corresponding DSP address comes from EM_BA[1]. The remaining address lines from the DSP (EM_A[12:0]) drive a word address into the flash inputs A[13:1]. For a more detailed explanation of the C672x EMIF operation please refer to the document TMS320C672x External Memory Interface (EMIF) User's Guide (literature number SPRU711). Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com EM_CS[0] EM_CAS EM_RAS EM_WE EM_CLK EM_CKE EM_BA[1:0] EM_A[11:0] EM_WE _DQM[0] EM_WE _DQM[1] EM_D[15:0] EM_CS[2] EM_RW EM_OE GPIO (6 Pins)RESET C6726B/C6722B/C6720 DSP EMIF CE CAS RAS WE CLK CKE BA[1:0] A[11:0] LDQM UDQM DQ[15:0] 2M x 16 x 4 Bank SDRAM A[18:13] RY/BY RESET OE WE CE DQ[15:0] 512K x 16 A[0] A[12:1] FLASH EM_BA[1] RESET Any GPIO-capable pins which can be pulled down at reset can be used to control A[18:13] for FLASH BOOTLOAD Examples: AHCLKR0, SPI0_SCS /SCL1 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-5. C6726B/C6722B/C6720 DSP 16-Bit EMIF Example Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com EM_CS[0] EM_CAS EM_RAS EM_WE EM_CLK EM_CKE EM_BA[1:0] EM_A[12:0] EM_WE _DQM[0] EM_WE _DQM[1] EM_D[15:0] EM_WE _DQM[2] GPIO (5 Pins)RESET C6727B DSP EMIF CE CAS RAS WE CLK CKE BA[1:0] A[12:0] LDQM UDQM DQ[15:0] 4M x 16 x 4 Bank SDRAM A[18:14] RY/BY RESET OE WE CE DQ[15:0] 512K x 16 A[0] A[13:1] FLASH EM_BA[1] RESET Any GPIO-capable pins which can be pulled down at reset can be used to control A[18:14] for FLASH BOOTLOAD Examples: AHCLKR0, SPI0_SCS /SCL1 EM_WE _DQM[3] EM_D[31:16]/UHPI_HA[15:0] EM_CS[2] EM_RW EM_OE EM_WAIT BA[1:0] A[12:0] DQ[15:0] LDQM UDQM 4M x 16 x 4 Bank RAS CLK CKE WE CAS CE SDRAM TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-6. C6727B DSP 32-Bit EMIF Example Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.11.2 EMIF Peripheral Registers Description(s) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-4 is a list of the EMIF registers. For more information about these registers, see the TMS320C672x DSP External Memory Interface (EMIF) User's Guide (literature number SPRU711). Table 4-4. EMIF Registers BYTE ADDRESS REGISTER NAME

www.ti.com 4.11.3 EMIF Electrical Data/Timing TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-5 through Table 4-10 assume testing over recommended operating conditions (see Figure 4-7 through Figure 4-13 Table 4-5. 100-MHz EMIF SDRAM Interface Timing Requirements (1) NO. MIN MAX UNIT t su(EM_DV-EM_CLKH) Input setup time, read data valid on D[31:0] before EM_CLK rising ns t h(EM_CLKH-EM_DIV) Input hold time, read data valid on D[31:0] after EM_CLK rising 1.9 ns (1) For more information about supported EMIF frequency, see Table 2-1 Table 4-6. 100-MHz EMIF SDRAM Interface Switching Characteristics (1) NO. PARAMETER MIN MAX UNIT t c(EM_CLK) Cycle time, EMIF clock EM_CLK ns t w(EM_CLK) Pulse width, EMIF clock EM_CLK high or low ns t d(EM_CLKH-EM_CSV)S Delay time, EM_CLK rising to EM_CS[0] valid 7.7 ns t oh(EM_CLKH-EM_CSIV)S Output hold time, EM_CLK rising to EM_CS[0] invalid 1.15 ns t d(EM_CLKH-EM_WE-DQMV)S Delay time, EM_CLK rising to EM_ WE _DQM[3:0] valid 7.7 ns t oh(EM_CLKH-EM_WE-DQMIV)S Output hold time, EM_CLK rising to EM_ WE _DQM[3:0] invalid 1.15 ns t d(EM_CLKH-EM_AV)S Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid 7.7 ns Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] t oh(EM_CLKH-EM_AIV)S 1.15 ns invalid t d(EM_CLKH-EM_DV)S Delay time, EM_CLK rising to EM_D[31:0] valid 7.7 ns t oh(EM_CLKH-EM_DIV)S Output hold time, EM_CLK rising to EM_D[31:0] invalid 1.15 ns t d(EM_CLKH-EM_RASV)S Delay time, EM_CLK rising to EM_RAS valid 7.7 ns t oh(EM_CLKH-EM_RASIV)S Output hold time, EM_CLK rising to EM_RAS invalid 1.15 ns t d(EM_CLKH-EM_CASV)S Delay time, EM_CLK rising to EM_CAS valid 7.7 ns t oh(EM_CLKH-EM_CASIV)S Output hold time, EM_CLK rising to EM_CAS invalid 1.15 ns t d(EM_CLKH-EM_WEV)S Delay time, EM_CLK rising to EM_WE valid 7.7 ns t oh(EM_CLKH-EM_WEIV)S Output hold time, EM_CLK rising to EM_WE invalid 1.15 ns t dis(EM_CLKH-EM_DHZ)S Delay time, EM_CLK rising to EM_D[31:0] 3-stated 7.7 ns t ena(EM_CLKH-EM_DLZ)S Output hold time, EM_CLK rising to EM_D[31:0] driving 1.15 ns (1) For more information about supported EMIF frequency, see Table 2-1 Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-7. 133-MHz EMIF SDRAM Interface Timing Requirements (1) NO. MIN MAX UNIT t su(EM_DV-EM_CLKH) Input setup time, read data valid on D[31:0] before EM_CLK rising 0.4 ns t h(EM_CLKH-EM_DIV) Input hold time, read data valid on D[31:0] after EM_CLK rising 1.9 ns (1) For more information about supported EMIF frequency, see Table 2-1 Table 4-8. 133-MHz EMIF SDRAM Interface Switching Characteristics (1) NO. PARAMETER MIN MAX UNIT t c(EM_CLK) Cycle time, EMIF clock EM_CLK 7.5 ns t w(EM_CLK) Pulse width, EMIF clock EM_CLK high or low 2.25 ns t d(EM_CLKH-EM_CSV)S Delay time, EM_CLK rising to EM_CS[0] valid 5.1 ns t oh(EM_CLKH-EM_CSIV)S Output hold time, EM_CLK rising to EM_CS[0] invalid 1.15 ns t d(EM_CLKH-EM_WE-DQMV)S Delay time, EM_CLK rising to EM_ WE _DQM[3:0] valid 5.1 ns t oh(EM_CLKH-EM_WE-DQMIV)S Output hold time, EM_CLK rising to EM_ WE _DQM[3:0] invalid 1.15 ns t d(EM_CLKH-EM_AV)S Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid 5.1 ns Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] t oh(EM_CLKH-EM_AIV)S 1.15 ns invalid t d(EM_CLKH-EM_DV)S Delay time, EM_CLK rising to EM_D[31:0] valid 5.1 ns t oh(EM_CLKH-EM_DIV)S Output hold time, EM_CLK rising to EM_D[31:0] invalid 1.15 ns t d(EM_CLKH-EM_RASV)S Delay time, EM_CLK rising to EM_RAS valid 5.1 ns t oh(EM_CLKH-EM_RASIV)S Output hold time, EM_CLK rising to EM_RAS invalid 1.15 ns t d(EM_CLKH-EM_CASV)S Delay time, EM_CLK rising to EM_CAS valid 5.1 ns t oh(EM_CLKH-EM_CASIV)S Output hold time, EM_CLK rising to EM_CAS invalid 1.15 ns t d(EM_CLKH-EM_WEV)S Delay time, EM_CLK rising to EM_WE valid 5.1 ns t oh(EM_CLKH-EM_WEIV)S Output hold time, EM_CLK rising to EM_WE invalid 1.15 ns t dis(EM_CLKH-EM_DHZ)S Delay time, EM_CLK rising to EM_D[31:0] 3-stated 5.1 ns t ena(EM_CLKH-EM_DLZ)S Output hold time, EM_CLK rising to EM_D[31:0] driving 1.15 ns (1) For more information about supported EMIF frequency, see Table 2-1 Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-9. EMIF Asynchronous Interface Timing Requirements (1) (2) NO. MIN MAX UNIT Input setup time, read data valid on EM_D[31:0] before EM_CLK t su(EM_DV-EM_CLKH)A ns rising t h(EM_CLKH-EM_DIV)A Input hold time, read data valid on EM_D[31:0] after EM_CLK rising ns t su(EM_CLKH-EM_WAITV)A Setup time, EM_WAIT valid before EM_CLK rising edge ns t h(EM_CLKH-EM_WAITIV)A Hold time, EM_WAIT valid after EM_CLK rising edge ns t w(EM_WAIT)A Pulse width of EM_WAIT assertion and deassertion ns Delay from EM_WAIT sampled deasserted on EM_CLK rising to t d(EM_WAITD-HOLD)A (3) ns beginning of HOLD phase Setup before end of STROBE phase (if no extended wait states are t su(EM_WAITA-HOLD)A inserted) by which EM_WAIT must be sampled asserted on (3) ns EM_CLK rising in order to add extended wait states. (4) (1) E SYSCLK3 (EM_CLK) period. (2) These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes. (3) These parameters specify the number of EM_CLK cycles of latency between EM_WAIT being sampled at the device pin and the EMIF entering the HOLD phase. However, the asynchronous setup (parameter 30) and hold time (parameter 31) around each EM_CLK edge must also be met in order to ensure the EM_WAIT signal is correctly sampled. (4) In Figure 4-13 it appears that there are more than EM_CLK cycles encompassed by parameter 35. However, EM_CLK cycles that are part of the extended wait period should not be counted; the EM_CLK requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. Table 4-10. EMIF Asynchronous Interface Switching Characteristics (1) NO. PARAMETER MIN MAX UNIT 100-MHz EMIF Frequency t c(EM_CLK) Cycle time, EMIF clock EM_CLK ns 133-MHz EMIF Frequency 7.5 t w(EM_CLK) Pulse width, high or low, EMIF clock EM_CLK ns t dis(EM_CLKH-EM_DHZ)S Delay time, EM_CLK rising to EM_D[31:0] 3-stated 7.7 ns t ena(EM_CLKH-EM_DLZ)S Output hold time, EM_CLK rising to EM_D[31:0] driving 1.15 ns t d(EM_CLKH-EM_CS2V)A Delay time, from EM_CLK rising edge to EM_CS[2] valid ns t d(EM_CLKH-EM_WE_DQMV)A Delay time, EM_CLK rising to EM_ WE _DQM[3:0] valid ns t d(EM_CLKH-EM_AV)A Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid ns t d(EM_CLKH-EM_DV)A Delay time, EM_CLK rising to EM_D[31:0] valid ns t d(EM_CLKH-EM_OEV)A Delay time, EM_CLK rising to EM_OE valid ns t d(EM_CLKH-EM_RW)A Delay time, EM_CLK rising to EM_R W valid ns t dis(EM_CLKH-EM_DDIS)A Delay time, EM_CLK rising to EM_D[31:0] 3-stated ns t d(EM_CLKH-EM_WE)A Delay time, EM_CLK rising to EM_WE valid ns (1) These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] 2 2 BASIC SDRAM WRITE OPERA TION EM_CS[0] EM_WE _DQM[3:0] EM_RAS EM_CAS EM_WE EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] 2 2 17 182 EM_CLK Delay BASIC SDRAM READ OPERA TION EM_CS[0] EM_WE _DQM[3:0] EM_RAS EM_CAS EM_WE TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-7. Basic SDRAM Write Operation Figure 4-8. Basic SDRAM Read Operation Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] READ DA TA SETUP STROBE HOLD TA 25 25 28 2917 ASYNCHRONOUS READ WE STROBE MODE ADDRESS ADDRESS EM_CS[2] EM_WE _DQM[3:0] EM_OE EM_WE EM_RW EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] READ DA TA SETUP STROBE HOLD TA 25 25 28 29 21 21 BYTE LANE ENABLES ADDRESS ADDRESS ASYNCHRONOUS READ SELECT STROBE MODE EM_CS[2] EM_WE _DQM[3:0] EM_OE EM_WE EM_RW TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-9. Asynchronous Read WE Strobe Mode Figure 4-10. Asynchronous Read Select Strobe Mode Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] SETUP STROBE HOLD 32 32 26 26 24 27 ASYNCHRONOUS WRITE WE STROBE MODE ADDRESS ADDRESS WRITE DA TA BYTE WRITE STROBES EM_CS[2] EM_WE _DQM[3:0] EM_OE EM_WE EM_RW EM_CLK EM_BA[1:0] EM_A[12:0] EM_D[31:0] SETUP STROBE HOLD 32 32 26 26 21 21 ASYNCHRONOUS WRITE SELECT STROBE MODE BYTE LANE ENABLES ADDRESS ADDRESS WRITE DA TA EM_CS[2] EM_WE _DQM[3:0] EM_OE EM_WE EM_RW TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-11. Asynchronous Write WE Strobe Mode Figure 4-12. Asynchronous Write Select Strobe Mode Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com EM_CLK EM_WAIT ASSERTED DEASSERTED SETUP HOLDSTROBESTROBE EXTENDED W AIT STATES 30 31 3333 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-13. EM_WAIT Timing Requirements Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.12 Universal Host-Port Interface (UHPI) [C6727B Only] 4.12.1 UHPI Device-Specific Information UHPI_HDS[2] UHPI_HDS[1] UHPI_HCS UHPI_HRDY Internal HSTROBE Internal HRDY TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x DSP includes a flexible universal host-port interface (UHPI) with more options than the host-port interface on the C671x DSP. The UHPI on the C672x DSP supports three major operating modes listed in Table 4-11 Table 4-11. UHPI Major Modes on C672x UHPI MAJOR MODE EXAMPLE FIGURE Multiplexed Host Address/Data Half-Word (16-Bit) Mode Figure 4-15 Multiplexed Host Address/Data Fullword (32-Bit) Mode Figure 4-16 Non-Multiplexed Host Address/Data Fullword (32-Bit) Mode Figure 4-17 In all modes, the UHPI uses three select inputs UHPI_HCS UHPI_HDS[2:1] which are combined internally to produce the internal strobe signal HSTROBE The HSTROBE strobe signal is used in the UHPI to capture incoming address and control signals on its falling edge and write data on its rising edge. The UHPI_HCS signal also gates the deassertion of the UHPI_HRDY signal externally. Figure 4-14. UHPI Strobe and Ready Interaction The two HPI control pins UHPI_HCNTL[1:0] determine the type of access that the host will perform. Note that only two of the four access types are supported in Non-Multiplexed Host Address/Data Fullword Mode. Table 4-12. HPI Access Types Selected by UHPI_HCNTL[1:0] NON- MULTIPLEXED MULTIPLEXED UHPI_HCNTL[1:0] (HPIC) Access Y Y Y HPI Data Access (HPID) with autoincrementing address Y Y N HPI Address Register (HPIA) Access Y Y N HPI Data Access (HPID) without autoincrementing Y Y Y address CAUTION When performing a set of HPID with autoincrementing address accesses (UHPI_HCNTL[1:0] '01'), the set must begin and end at a word-aligned address. In addition, all four of the UHPI_HBE[3:0] must be enabled on every access in the set. CAUTION The encoding of UHPI_CNTL[1:0] on the C672x DSP is different from HCNTL[1:0] on the C671x DSP. Modes and are swapped. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com EM_D[31:16]/UHPI_HA15:0 UHPI_HCNTL[1:0] UHPI_HD[15:0] UHPI_HD[16]/HHWIL UHPI_HD[31:17] UHPI_HAS (B) UHPI_HBE1:0 UHPI_HRW UHPI_HDS2 UHPI_HDS1 UHPI_HCS UHPI_HRDY AMUTE2/HINT NC or GPIO NC Ax:y D[15:0] A[1] (E) BE1:0 R/W WE (G) RD (G) CS RDY INTERRUPT DSP External Host MCU TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-15 illustrates the Multiplexed Host Address/Data Half-Word Mode hookup between the C672x DSP and an external host microcontroller. In this mode, each 32-bit HPI access is broken up into two halves. The UHPI_HD[16]/HHWIL pin functions as UHPI_HHWIL which must be '0' during the first half of access and '1' during the second half. CAUTION Unless configured as general-purpose I/O in the UHPI module, UHPI_HD[31:17] and UHPI_HD[16]/HHWIL will be driven as outputs along with UHPI_HD[15:0] when the HPI is read, even though only the lower half-word is used to transfer data. This can be especially problematic for the UHPI_HD[16]/HHWIL pin which should be used as an input in this mode. Therefore, be sure to configure the upper half of the UHPI_HD bus as general-purpose I/O pins. Furthermore, be sure to program the UHPI_HD[16] function as a general-purpose input to avoid a drive conflict with the external host MCU. In this mode, as well as the Multiplexed Host Address/Data Fullword mode, the UHPI can be made more secure by restricting the upper bits of the DSP addresses it can access to what is set in CFGHPIAMSB and CFGHPIAUMB registers. (See Table 4-15 and Table 4-16 The host is responsible for configuring the internal HPIA register whether or not it is being overridden by the device configuration registers CFGHPIAMSB and CFGHPIAUMB. After the HPIA register has been set, either a single or a group of autoincrementing accesses to HPID may be performed. The UHPI_HRDY adds wait states to extend the host MCU access until the C672x DSP has completed the desired operation. The HINT signal is available for the DSP to interrupt the host MCU. The UHPI also includes an interrupt to the DSP core from the host as part of the HPIC register. May be used as EM_D[31:16] Optional for hosts supporting multiplexed address and data. Pull up if not used. Low when address is on the bus. DSP byte enables UHPI_HBE[3:2] are not required in this mode. Two host address lines or host GPIO if address lines are not available. A[1], assuming this address increments from to between two successive 16-bit accesses. Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write-enable pins. Only required if needed for strobe timing. Not required if CS meets strobe timing requirements. Tie UHPI_HDS[2] and UHPI_HDS[1] opposite. For more information, see Figure 4-14 Figure 4-15. UHPI Multiplexed Host Address/Data Half-Word Mode Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com EM_D[31:16]/UHPI_HA15:0 UHPI_HCNTL[1:0] UHPI_HD[15:0] UHPI_HD[16]/HHWIL UHPI_HD[31:17] UHPI_HAS (B) UHPI_HBE[3:0] UHPI_HRW UHPI_HDS[2] UHPI_HDS[1] UHPI_HCS UHPI_HRDY AMUTE2/HINT NC Ax:y D[15:0] D[16] BE3:0 R/W WE (E) RD (E) CS RDY INTERRUPT DSP External Host MCU D[31:17] TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-16 illustrates the Multiplexed Host Address/Data Fullword Mode hookup between the C672x DSP and an external host microcontroller. In this mode, all bits of UHPI_HD[31:0] are used and the host can access HPIA, HPID, and HPIC in a single bus cycle. May be used as EM_D[31:16] Optional for hosts supporting multiplexed address and data. Pull up if not used. Low when address is on the bus. Two host address lines or host GPIO if address lines are not available. Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write enable pins. Only required if needed for strobe timing. Not required if CS meets strobe timing requirements. Figure 4-16. UHPI Multiplexed Host Address/Data Fullword Mode Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com EM_D[31:16]/UHPI_HA[15:0] UHPI_HCNTL[1:0] UHPI_HD[15:0] UHPI_HD[16]/HHWIL UHPI_HD[31:17] UHPI_HAS (B) UHPI_HBE[3:0] UHPI_HRW UHPI_HDS[2] UHPI_HDS[1] UHPI_HCS UHPI_HRDY AMUTE2/HINT Ax:y D[15:0] D[16] BE[3:0] (C) R/W WE (D) RD (D) CS RDY INTERRUPT DSP External Host MCU D[31:17] A[17:2] TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-17 illustrates the Non-Multiplexed Host Address/Data Fullword mode of the UHPI. In this mode, the UHPI behaves almost like an asynchronous SRAM except it asserts the UHPI_HRDY signal. This mode allows the host to randomly access a 64K-byte page in the C672x address space. The upper bits of the C672x address are set by the DSP (only) through the CFGHPIAMSB and CFGHPIAUMB registers (see Table 4-15 and Table 4-16 Two host address lines or host GPIO if address lines are not available. Not used in this mode. Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write enable pins. Only required if needed for strobe timing. Not required if CS meets strobe timing requirements. Figure 4-17. UHPI Non-Multiplexed Host Address/Data Fullword Mode CAUTION The EMIF data bus and UHPI HA inputs share the EM_D[31:16]/UHPI_HA[15:0] pins. When using Non-Multiplexed mode, make sure the EMIF does not drive EM_D[31:16]; otherwise, a drive conflict with the external host MCU may result. Normally, the EMIF will begin to drive the EM_D[31:16] lines immediately after it completes the SDRAM initialization sequence, which occurs automatically after RESET is released. To avoid a drive conflict then, the boot software must set CFGHPI.NMUX to '1' before the EMIF drives EM_D[31:16]. Setting CFGHPI.NMUX to '1' forces these pins to be input pins. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.12.2 UHPI Peripheral Registers Description(s) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-13 is a list of the UHPI registers. Table 4-13. UHPI Configuration Registers BYTE ADDRESS REGISTER NAME

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The UHPI has several device-level configuration registers which affect its behavior. Figure 4-18 Figure 4-19 and Figure 4-20 show the bit layout of these registers. Table 4-14 Table 4-15 and Table 4-16 contain a registers. Reserved Reserved BYTEAD FULL NMUX PAGEM ENA R/W, R/W, R/W, R/W, R/W, LEGEND: R/W Read/Write; R Read only; n value after reset Figure 4-18. CFGHPI Register Bit Layout (0x4000 0008) Table 4-14. CFGHPI Register Bit Field (0x4000 0008) RESET READ BIT NO. NAME 31:5 Reserved N/A N/A Reads are indeterminate. Only should be written to these bits. BYTEAD R/W UHPI Host Address Type Host Address is a word address Host Address is a byte address FULL R/W UHPI Multiplexing Mode (when NMUX Half-Word (16-bit data) Multiplexed Address and Data Mode Fullword (32-bit data) Multiplexed Address and Data Mode NMUX R/W UHPI Non-Multiplexed Mode Enable Multiplexed Address and Data Mode Non-Multiplexed Address and Data Mode (utilizes optional UHPI_HA[15:0] pins). Host data bus is bits in Non-Multiplexed mode. Setting this bit prevents the EMIF from driving data out or 'parking' the shared EM_D[31:16]/UHPI_HA[15:0] pins. PAGEM R/W UHPI Page Mode Enable (Only for Multiplexed Address and Data Mode). Full 32-bit DSP address specified through host port. Only lower bits of DSP address are specified through host port. Upper bits are restricted to the page selected by CFGHPIAMSB and CFGHPIAUMB registers. ENA R/W UHPI Enable UHPI is disabled UHPI is enabled. Set this bit to '1' only after configuring the other bits in this register. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Reserved HPIAMSB R/W, LEGEND: R/W Read/Write; R Read only; n value after reset Figure 4-19. CFGHPIAMSB Register Bit Layout (0x4000 000C) Table 4-15. CFGHPIAMSB Register Bit Field (0x4000 000C) RESET READ BIT NO. NAME 31:8 Reserved N/A N/A Reads are indeterminate. Only should be written to these bits. 7:0 HPIAMSB R/W UHPI most significant byte of DSP address to access in Non-Multiplexed mode and in Multiplexed Address and Data mode when PAGEM Sets bits [31:24] of the DSP internal address as accessed through UHPI. Reserved HPIAUMB R/W, LEGEND: R/W Read/Write; R Read only; n value after reset Figure 4-20. CFGHPIAUMB Register Bit Layout (0x4000 0010) Table 4-16. CFGHPIAUMB Register Bit Field (0x4000 0010) RESET READ BIT NO. NAME 31:8 Reserved N/A N/A Reads are indeterminate. Only should be written to these bits. 7:0 HPIAUMB R/W UHPI upper middle byte of DSP address to access in Non-Multiplexed mode and in Multiplexed Address and Data mode when PAGEM Sets bits [23:16] of the DSP internal address as accessed through UHPI. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.12.3 UHPI Electrical Data/Timing TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 4.12.3.1 Universal Host-Port Interface (UHPI) Read and Write Timing Table 4-17 and Table 4-18 assume testing over recommended operating conditions (see Figure 4-21 through Figure 4-24 Table 4-17. UHPI Read and Write Timing Requirements (1) (2) NO. MIN MAX UNIT t su(HASL-DSL) Setup time, UHPI_HAS low before DS falling edge ns t h(DSL-HASL) Hold time, UHPI_HAS low after DS falling edge ns t su(HAD-HASL) Setup time, HAD valid before UHPI_HAS falling edge ns t h(HASL-HAD) Hold time, HAD valid after UHPI_HAS falling edge ns t w(DSL) Pulse duration, DS low ns t w(DSH) Pulse duration, DS high ns t su(HAD-DSL) Setup time, HAD valid before DS falling edge ns t h(DSL-HAD) Hold time, HAD valid after DS falling edge ns t su(HD-DSH) Setup time, HD valid before DS rising edge ns t h(DSH-HD) Hold time, HD valid after DS rising edge ns t su(HCSL-DSL) Setup time, UHPI_HCS low before DS falling edge ns t h(HRDYH-DSL) Hold time, DS low after UHPI_HRDY rising edge ns (1) P SYSCLK2 period (2) DS refers to HSTROBE HD refers to UHPI_HD[31:0]. HDS refers to UHPI_HDS[1] or UHPI_HDS[2] HAD refers to UHPI_HCNTL[0], UHPI_HCNTL[1], UHPI_HHWIL, and UHPI_HR W Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-18. UHPI Read and Write Switching Characteristics (1) (2) NO. PARAMETER MIN MAX UNIT Case HPIC or HPIA read Case HPID read with no (3) auto-increment Case HPID read with t d(DSL-HDV) Delay time, DS low to HD valid ns auto-increment and read FIFO (3) initially empty Case HPID read with auto-increment and data previously prefetched into the read FIFO t dis(DSH-HDV) Disable time, HD high-impedance from DS high ns t en(DSL-HDD) Enable time, HD driven from DS low ns t d(DSL-HRDYH) Delay time, DS low to UHPI_HRDY high ns t d(DSH-HRDYH) Delay time, DS high to UHPI_HRDY high ns Case HPID read with no (3) auto-increment Delay time, DS low to UHPI_HRDY t d(DSL-HRDYL) ns Case HPID read with low auto-increment and read FIFO (3) initialy empty t d(HDV-HRDYL) Delay time, HD valid to UHPI_HRDY low ns Case HPIA write (3) Delay time, DS high to Case HPID read with t d(DSH-HRDYL) ns UHPI_HRDY low auto-increment and read FIFO (3) initially empty Delay time, DS low to UHPI_HRDY low for HPIA write and FIFO not t d(DSL-HRDYL) (3) ns empty t d(HASL-HRDYH) Delay time, UHPI_HAS low to UHPI_HRDY high ns (1) H 0.5 SYSCLK2 period (2) DS refers to HSTROBE HAD refers to UHPI_HCNTL[0], UHPI_HCNTL[1], UHPI_HHWIL, and UHPI_HR W (3) Max delay is a best case, assuming no delays due to resource conflicts between UHPI and dMAX or CPU. UHPI_HRDY should always be used to indicate when an access is complete instead of relying on these parameters. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 3 2 17 18 UHPI_HCS UHPI_HDSx UHPI_HRW UHPI_HA[15:0] UHPI_HD[31:0] (Read) UHPI_HD[31:0] (Write) UHPI_HRDY Valid Valid Read data W rite data Read Write 37 37 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Depending on the type of write or read operation (HPID or HPIC), transitions on UHPI_HRDY may or may not occur. Figure 4-21. Non-Multiplexed Read/Write Timings Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com UHPI_HCS UHPI_HAS UHPI_HRW UHPI_HHWIL HSTROBE (A) UHPI_HD[15:0] UHPI_HRDY 1337 UHPI_HCNTL[1:0] TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 See Figure 4-14 Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. Figure 4-22. Multiplexed Read Timings Using UHPI_HAS Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL HSTROBE (A) UHPI_HD[15:0] UHPI_HRDY 1 2 1 2 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 See Figure 4-14 Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. Figure 4-23. Multiplexed Read Timings With UHPI_HAS Held High Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL HSTROBE (A) UHPI_HD[15:0] UHPI_HRDY 54 38 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 See Figure 4-14 Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. Figure 4-24. Multiplexed Write Timings With UHPI_HAS Held High Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.13 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) Receive Logic Clock/Frame Generator State Machine Clock Check and Serializer 0 Serializer 1 Serializer y GIO Control DIT RAM 384 C 384 U Optional Transmit Formatter Receive Formatter Transmit Logic Clock/Frame Generator State Machine McASPx (x = 0, 1, 2) Peripheral Configuration Bus McASP DMA Bus (Dedicated) AHCLKRx ACLKRx AFSRx AMUTEINx AMUTEx AFSXx ACLKXx AHCLKXx AXRx[0] AXRx[1] AXRx[y] Pins Function Receive Master Clock Receive Bit Clock Receive Left/Right Clock or Frame Sync Transmit Master Clock Transmit Bit Clock Transmit Left/Right Clock or Frame Sync Transmit/Receive Serial Data Pin Transmit/Receive Serial Data Pin Transmit/Receive Serial Data Pin Error Detection The McASPs DO NOT have dedicated AMUTEINx pins. TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The McASP serial port is specifically designed for multichannel audio applications. Its key are: Flexible clock and frame sync generation logic and on-chip dividers Up to sixteen transmit or receive data pins and serializers Large number of serial data format options, including: TDM Frames with to time slots per frame (periodic) or slot per frame (burst). Time slots of 8,12,16, 20, 24, 28, and bits. First bit delay or clocks. MSB or LSB first bit order. Left- or right-aligned data words within time slots DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers. Extensive error-checking and mute generation logic All unused pins GPIO-capable Figure 4-25. McASP Block Diagram Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The three McASPs on C672x have different configurations (see Table 4-19 NOTE: McASP2 is not available on the C6722B and C6720. Table 4-19. McASP Configurations on C672x DSP McASP DIT CLOCK PINS DATA PINS COMMENTS McASP0 No AHCLKX0/AHCLKX2, ACLKX0, AFSX0 Up to AHCLKX0/AHCLKX2 share pin. AHCLKR0/AHCLKR1, ACLKR0, AFSR0 AHCLKR0/AHCLKR1 share pin. McASP1 No AHCLKX1, ACLKX1, AFSX1, ACLKR1, AFSR1 Up to AHCLKR0/AHCLKR1 share pin McASP2 Yes ACLKX2, AFSX2, AHCLKR2, ACLKR2, AFSR2 Up to Full functionality on C6727B. On (Only available on the C6727B.) C6726B, functions only as DIT since only AHCLKX0/AHCLKX2 is available. Not available on the C6722B and C6720. NOTE: The McASPs do not have dedicated AMUTEINx pins. Instead they can select one of the pins listed in Table 4-21 Table 4-22 and Table 4-23 to use as a mute input. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.13.1 McASP Peripheral Registers Description(s) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-20 is a list of the McASP registers. For more information about these registers, see the TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU878). Table 4-20. McASP Registers Accessed Through Peripheral Configuration Bus McASP0 McASP1 McASP2 REGISTER BYTE BYTE BYTE (reads) Read returns: Pin data input register PDSET (writes) Writes affect: Pin data set register (alternate write address: PDOUT) 0x4400 0020 0x4500 0020 0x4600 0020 PDCLR Pin data clear register (alternate write address: PDOUT) 0x4400 0044 0x4500 0044 0x4600 0044 GBLCTL Global control register 0x4400 0048 0x4500 0048 0x4600 0048 AMUTE Audio mute control register 0x4400 004C 0x4500 004C 0x4600 004C DLBCTL Digital loopback control register 0x4400 0050 0x4500 0050 0x4600 0050 DITCTL DIT mode control register 0x4400 0060 0x4500 0060 0x4600 0060 RGBLCTL Receiver global control register: Alias of GBLCTL, only receive bits are affected allows receiver to be reset independently from transmitter 0x4400 0064 0x4500 0064 0x4600 0064 RMASK Receive format unit bit mask register 0x4400 0068 0x4500 0068 0x4600 0068 RFMT Receive bit stream format register 0x4400 006C 0x4500 006C 0x4600 006C AFSRCTL Receive frame sync control register 0x4400 0070 0x4500 0070 0x4600 0070 ACLKRCTL Receive clock control register 0x4400 0074 0x4500 0074 0x4600 0074 AHCLKRCTL Receive high-frequency clock control register 0x4400 0078 0x4500 0078 0x4600 0078 RTDM Receive TDM time slot 0-31 register 0x4400 007C 0x4500 007C 0x4600 007C RINTCTL Receiver interrupt control register 0x4400 0080 0x4500 0080 0x4600 0080 RSTAT Receiver status register 0x4400 0084 0x4500 0084 0x4600 0084 RSLOT Current receive TDM time slot register 0x4400 0088 0x4500 0088 0x4600 0088 RCLKCHK Receive clock check control register 0x4400 008C 0x4500 008C 0x4600 008C REVTCTL Receiver DMA event control register 0x4400 00A0 0x4500 00A0 0x4600 00A0 XGBLCTL Transmitter global control register. Alias of GBLCTL, only transmit bits are affected allows transmitter to be reset independently from receiver 0x4400 00A4 0x4500 00A4 0x4600 00A4 XMASK Transmit format unit bit mask register 0x4400 00A8 0x4500 00A8 0x4600 00A8 XFMT Transmit bit stream format register 0x4400 00AC 0x4500 00AC 0x4600 00AC AFSXCTL Transmit frame sync control register 0x4400 00B0 0x4500 00B0 0x4600 00B0 ACLKXCTL Transmit clock control register 0x4400 00B4 0x4500 00B4 0x4600 00B4 AHCLKXCTL Transmit high-frequency clock control register 0x4400 00B8 0x4500 00B8 0x4600 00B8 XTDM Transmit TDM time slot 0-31 register 0x4400 00BC 0x4500 00BC 0x4600 00BC XINTCTL Transmitter interrupt control register 0x4400 00C0 0x4500 00C0 0x4600 00C0 XSTAT Transmitter status register 0x4400 00C4 0x4500 00C4 0x4600 00C4 XSLOT Current transmit TDM time slot register Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-20. McASP Registers Accessed Through Peripheral Configuration Bus (continued) McASP0 McASP1 McASP2 REGISTER BYTE BYTE BYTE (1) Transmit buffer register for serializer 0x4400 0204 0x4500 0204 0x4600 0204 XBUF1 (1) Transmit buffer register for serializer 0x4400 0208 0x4500 0208 XBUF2 (1) Transmit buffer register for serializer (1) Writes to XRBUF originate from peripheral configuration bus only when XBUSEL in XFMT. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-20. McASP Registers Accessed Through Peripheral Configuration Bus (continued) McASP0 McASP1 McASP2 REGISTER BYTE BYTE BYTE (1) Transmit buffer register for serializer 0x4400 0210 0x4500 0210 XBUF4 (1) Transmit buffer register for serializer 0x4400 0214 0x4500 0214 XBUF5 (1) Transmit buffer register for serializer 0x4400 0218 XBUF6 (1) Transmit buffer register for serializer 0x4400 021C XBUF7 (1) Transmit buffer register for serializer 0x4400 0220 XBUF8 (1) Transmit buffer register for serializer 0x4400 0224 XBUF9 (1) Transmit buffer register for serializer 0x4400 0228 XBUF10 (1) Transmit buffer register for serializer 0x4400 022C XBUF11 (1) Transmit buffer register for serializer 0x4400 0230 XBUF12 (1) Transmit buffer register for serializer 0x4400 0234 XBUF13 (1) Transmit buffer register for serializer 0x4400 0238 XBUF14 (1) Transmit buffer register for serializer 0x4400 023C XBUF15 (1) Transmit buffer register for serializer 0x4400 0280 0x4500 0280 0x4600 0280 RBUF0 (2) Receive buffer register for serializer 0x4400 0284 0x4500 0284 0x4600 0284 RBUF1 (2) Receive buffer register for serializer 0x4400 0288 0x4500 0288 RBUF2 (2) Receive buffer register for serializer 0x4400 028C 0x4500 028C RBUF3 (2) Receive buffer register for serializer 0x4400 0290 0x4500 0290 RBUF4 (2) Receive buffer register for serializer 0x4400 0294 0x4500 0294 RBUF5 (2) Receive buffer register for serializer 0x4400 0298 RBUF6 (2) Receive buffer register for serializer 0x4400 029C RBUF7 (2) Receive buffer register for serializer 0x4400 02A0 RBUF8 (2) Receive buffer register for serializer 0x4400 02A4 RBUF9 (2) Receive buffer register for serializer 0x4400 02A8 RBUF10 (2) Receive buffer register for serializer 0x4400 02AC RBUF11 (2) Receive buffer register for serializer 0x4400 02B0 RBUF12 (2) Receive buffer register for serializer 0x4400 02B4 RBUF13 (2) Receive buffer register for serializer 0x4400 02B8 RBUF14 (2) Receive buffer register for serializer 0x4400 02BC RBUF15 (2) Receive buffer register for serializer (2) Reads from XRBUF originate on peripheral configuration bus only when RBUSEL in RFMT. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-26 shows the bit layout of the CFGMCASP0 register and Table 4-21 contains a bits. Reserved Reserved AMUTEIN0 R/W, LEGEND: R/W Read/Write; R Read only; n value after reset Figure 4-26. CFGMCASP0 Register Bit Layout (0x4000 0018) Table 4-21. CFGMCASP0 Register Bit Field (0x4000 0018) RESET READ BIT NO. NAME 31:3 Reserved N/A N/A Reads are indeterminate. Only should be written to these bits. 2:0 AMUTEIN0 R/W AMUTEIN0 Selects the source of the input to the McASP0 mute input. 000 Select the input to be a constant '0' 001 Select the input from AXR0[7]/SPI1_CLK 010 Select the input from AXR0[8]/AXR1[5]/SPI1_SOMI 011 Select the input from AXR0[9]/AXR1[4]/SPI1_SIMO 100 Select the input from AHCLKR2 101 Select the input from SPI0_SIMO 110 Select the input from SPI0_SCS /I2C1_SCL 111 Select the input from SPI0_ENA /I2C1_SDA Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-27 shows the bit layout of the CFGMCASP1 register and Table 4-22 contains a bits. Reserved Reserved AMUTEIN1 R/W, LEGEND: R/W Read/Write; R Read only; n value after reset Figure 4-27. CFGMCASP1 Register Bit Layout (0x4000 001C) Table 4-22. CFGMCASP1 Register Bit Field (0x4000 001C) RESET READ BIT NO. NAME 31:3 Reserved N/A N/A Reads are indeterminate. Only should be written to these bits. 2:0 AMUTEIN1 R/W AMUTEIN1 Selects the source of the input to the McASP1 mute input. 000 Select the input to be a constant '0' 001 Select the input from AXR0[7]/SPI1_CLK 010 Select the input from AXR0[8]/AXR1[5]/SPI1_SOMI 011 Select the input from AXR0[9]/AXR1[4]/SPI1_SIMO 100 Select the input from AHCLKR2 101 Select the input from SPI0_SIMO 110 Select the input from SPI0_SCS /I2C1_SCL 111 Select the input from SPI0_ENA /I2C1_SDA Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-28 shows the bit layout of the CFGMCASP2 register and Table 4-23 contains a bits. Reserved Reserved AMUTEIN2 R/W, LEGEND: R/W Read/Write; R Read only; n value after reset Figure 4-28. CFGMCASP2 Register Bit Layout (0x4000 0020) Table 4-23. CFGMCASP2 Register Bit Field (0x4000 0020) (1) RESET READ BIT NO. NAME 31:3 Reserved N/A N/A Reads are indeterminate. Only should be written to these bits. 2:0 AMUTEIN2 R/W AMUTEIN2 Selects the source of the input to the McASP2 mute input. 000 Select the input to be a constant '0' 001 Select the input from AXR0[7]/SPI1_CLK 010 Select the input from AXR0[8]/AXR1[5]/SPI1_SOMI 011 Select the input from AXR0[9]/AXR1[4]/SPI1_SIMO 100 Select the input from AHCLKR2 101 Select the input from SPI0_SIMO 110 Select the input from SPI0_SCS /I2C1_SCL 111 Select the input from SPI0_ENA /I2C1_SDA (1) CFGMCASP2 is reserved on the C6722B and C6720. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.13.2 McASP Electrical Data/Timing TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 4.13.2.1 Multichannel Audio Serial Port (McASP) Timing Table 4-24 and Table 4-25 assume testing over recommended operating conditions (see Figure 4-29 and Figure 4-30 Table 4-24. McASP Timing Requirements (1) (2) NO. MIN MAX UNIT Cycle time, AHCLKR external, AHCLKR input t c(AHCKRX) ns Cycle time, AHCLKX external, AHCLKX input Pulse duration, AHCLKR external, AHCLKR input 7.5 t w(AHCKRX) ns Pulse duration, AHCLKX external, AHCLKX input 7.5 Cycle time, ACLKR external, ACLKR input greater of or ns t c(ACKRX) ns Cycle time, ACLKX external, ACLKX input greater of or ns Pulse duration, ACLKR external, ACLKR input t w(ACKRX) ns Pulse duration, ACLKX external, ACLKX input Setup time, AFSR input to ACLKR internal Setup time, AFSX input to ACLKX internal Setup time, AFSR input to ACLKR external input t su(AFRXC-ACKRX) ns Setup time, AFSX input to ACLKX external input Setup time, AFSR input to ACLKR external output Setup time, AFSX input to ACLKX external output Hold time, AFSR input after ACLKR internal Hold time, AFSX input after ACLKX internal Hold time, AFSR input after ACLKR external input t h(ACKRX-AFRX) ns Hold time, AFSX input after ACLKX external input Hold time, AFSR input after ACLKR external output Hold time, AFSX input after ACLKX external output Setup time, AXRn input to ACLKR internal t su(AXR-ACKRX) Setup time, AXRn input to ACLKR external input ns Setup time, AXRn input to ACLKR external output Hold time, AXRn input after ACLKR internal t h(ACKRX-AXR) Hold time, AXRn input after ACLKR external input ns Hold time, AXRn input after ACLKR external output (1) ACLKX internal ACLKXCTL.CLKXM PDIR.ACLKX ACLKX external input ACLKXCTL.CLKXM PDIR.ACLKX ACLKX external output ACLKXCTL.CLKXM PDIR.ACLKX ACLKR internal ACLKRCTL.CLKRM PDIR.ACLKR ACLKR external input ACLKRCTL.CLKRM PDIR.ACLKR ACLKR external output ACLKRCTL.CLKRM PDIR.ACLKR (2) P SYSCLK2 period Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-25. McASP Switching Characteristics (1) NO. PARAMETER MIN MAX UNIT Cycle time, AHCLKR internal, AHCLKR output Cycle time, AHCLKR external, AHCLKR output t c(AHCKRX) ns Cycle time, AHCLKX internal, AHCLKX output Cycle time, AHCLKX external, AHCLKX output Pulse duration, AHCLKR internal, AHCLKR output (AHR/2) 2.5 (2) Pulse duration, AHCLKR external, AHCLKR output (AHR/2) 2.5 (2) t w(AHCKRX) ns Pulse duration, AHCLKX internal, AHCLKX output (AHX/2) 2.5 (3) Pulse duration, AHCLKX external, AHCLKX output (AHX/2) 2.5 (3) Cycle time, ACLKR internal, ACLKR output greater of or ns (4) Cycle time, ACLKR external, ACLKR output greater of or ns (4) t c(ACKRX) ns Cycle time, ACLKX internal, ACLKX output greater of or ns (4) Cycle time, ACLKX external, ACLKX output greater of or ns (4) Pulse duration, ACLKR internal, ACLKR output (AR/2) 2.5 (5) Pulse duration, ACLKR external, ACLKR output (AR/2) 2.5 (5) t w(ACKRX) ns Pulse duration, ACLKX internal, ACLKX output (AX/2) 2.5 (6) Pulse duration, ACLKX external, ACLKX output (AX/2) 2.5 (6) Delay time, ACLKR internal, AFSR output Delay time, ACLKX internal, AFSX output Delay time, ACLKR external input, AFSR output Delay time, ACLKX external input, AFSX output Delay time, ACLKR external output, AFSR output Delay time, ACLKX external output, AFSX output t d(ACKRX-FRX) ns Delay time, ACLKR internal, AFSR output Delay time, ACLKX internal, AFSX output Delay time, ACLKR external input, AFSR output Delay time, ACLKX external input, AFSX output Delay time, ACLKR external output, AFSR output Delay time, ACLKX external output, AFSX output Delay time, ACLKX internal, AXRn output t d(ACLKX-AXRV) Delay time, ACLKX external input, AXRn output ns Delay time, ACLKX external output, AXRn output Disable time, ACLKX internal, AXRn output t dis(ACKX-AXRHZ) Disable time, ACLKX external input, AXRn output ns Disable time, ACLKX external output, AXRn output (1) ACLKX internal ACLKXCTL.CLKXM PDIR.ACLKX ACLKX external input ACLKXCTL.CLKXM PDIR.ACLKX ACLKX external output ACLKXCTL.CLKXM PDIR.ACLKX ACLKR internal ACLKRCTL.CLKRM PDIR.ACLKR ACLKR external input ACLKRCTL.CLKRM PDIR.ACLKR ACLKR external output ACLKRCTL.CLKRM PDIR.ACLKR (2) AHR Cycle time, AHCLKR. (3) AHX Cycle time, AHCLKX. (4) P SYSCLK2 period (5) AR ACLKR period. (6) AX ACLKX period. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data In/Receive) ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 For CLKRP CLKXP the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). For CLKRP CLKXP the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). Figure 4-29. McASP Input Timings Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 131313 1313 1211 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data Out/Transmit) ACLKR/X (CLKRP = CLKXP = 0)(B) ACLKR/X (CLKRP = CLKXP = 1)(A) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 For CLKRP CLKXP the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). For CLKRP CLKXP the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). Figure 4-30. McASP Output Timings Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.14 Serial Peripheral Interface Ports (SPI0, SPI1) 4.14.1 SPI Device-Specific Information Peripheral Configuration Bus Interrupt and DMA Requests 16-Bit Shift Register 16-Bit Buffer 16-Bit Emulation Buffer C672x SPI Module GPIO Control (all pins) State Machine Clock Control SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_SCS SPIx_CLK TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-31 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many data formatting options. Figure 4-31. Block Diagram of SPI Module The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and SPIx_SOMI) and two optional pins SPIx_SCS SPIx_ENA The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are other slave devices on the same SPI port. The C672x will only shift data and drive the SPIx_SOMI pin when SPIx_SCS is held low. In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the same SPI bus. In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts SPIx_ENA The addition of this handshake signal simplifies SPI communications and, on average, increases SPI bus throughput since the master does not need to delay each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer can begin as soon as both the master and slave have actually serviced the previous SPI transfer. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com Optional − Slave Chip Select Optional Enable (Ready) SLA VE SPIMASTER SPI SPIx_SIMOSPIx_SIMO SPIx_SOMI SPIx_SOMI SPIx_CLK SPIx_CLK SPIx_ENA SPIx_ENA SPIx_SCS SPIx_SCS TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-32. Illustration of SPI Master-to-SPI Slave Connection Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.14.2 SPI Peripheral Registers Description(s) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-26 is a list of the SPI registers. Table 4-26. SPIx Configuration Registers SPI0 SPI1 REGISTER NAME (Pin Function) 0x4700 0018 0x4800 0018 SPIPC1 Pin Control Register (Pin Direction) 0x4700 001C 0x4800 001C SPIPC2 Pin Control Register (Pin Data In) 0x4700 0020 0x4800 0020 SPIPC3 Pin Control Register (Pin Data Out) 0x4700 0024 0x4800 0024 SPIPC4 Pin Control Register (Pin Data Set) 0x4700 0028 0x4800 0028 SPIPC5 Pin Control Register (Pin Data Clear) 0x4700 002C 0x4800 002C Reserved Reserved Do not write to this register 0x4700 0030 0x4800 0030 Reserved Reserved Do not write to this register 0x4700 0034 0x4800 0034 Reserved Reserved Do not write to this register 0x4700 0038 0x4800 0038 SPIDAT0 Shift Register (without format select) 0x4700 003C 0x4800 003C SPIDAT1 Shift Register (with format select) 0x4700 0040 0x4800 0040 SPIBUF Buffer Register 0x4700 0044 0x4800 0044 SPIEMU Emulation Register 0x4700 0048 0x4800 0048 SPIDELAY Delay Register 0x4700 004C 0x4800 004C SPIDEF Default Chip Select Register 0x4700 0050 0x4800 0050 SPIFMT0 Format Register 0x4700 0054 0x4800 0054 SPIFMT1 Format Register 0x4700 0058 0x4800 0058 SPIFMT2 Format Register 0x4700 005C 0x4800 005C SPIFMT3 Format Register 0x4700 0060 0x4800 0060 TGINTVECT0 Interrupt Vector for SPI INT0 0x4700 0064 0x4800 0064 TGINTVECT1 Interrupt Vector for SPI INT1 Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.14.3 SPI Electrical Data/Timing TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 4.14.3.1 Serial Peripheral Interface (SPI) Timing Table 4-27 through Table 4-34 assume testing over recommended operating conditions (see Figure 4-33 through Figure 4-36 Table 4-27. General Timing Requirements for SPIx Master Modes (1) NO. MIN MAX UNIT greater of or t c(SPC)M Cycle Time, SPIx_CLK, All Master Modes 256P ns 100 ns t w(SPCH)M Pulse Width High, SPIx_CLK, All Master Modes greater of or ns ns t w(SPCL)M Pulse Width Low, SPIx_CLK, All Master Modes greater of or ns ns Polarity Phase to SPIx_CLK rising Polarity Phase 0.5t c(SPC)M Delay, initial data bit valid to SPIx_CLK rising t d(SIMO_SPC)M on SPIx_SIMO to initial ns Polarity Phase edge on SPIx_CLK (2) to SPIx_CLK falling Polarity Phase 0.5t c(SPC)M to SPIx_CLK falling Polarity Phase from SPIx_CLK rising Polarity Phase Delay, subsequent bits from SPIx_CLK falling t d(SPC_SIMO)M valid on SPIx_SIMO after ns Polarity Phase transmit edge of SPIx_CLK from SPIx_CLK falling Polarity Phase from SPIx_CLK rising Polarity Phase 0.5t c(SPC)M from SPIx_CLK falling Polarity Phase Output hold time, 0.5t c(SPC)M from SPIx_CLK rising SPIx_SIMO valid after t oh(SPC_SIMO)M ns receive edge of SPIxCLK, Polarity Phase 0.5t c(SPC)M except for final bit (3) from SPIx_CLK rising Polarity Phase 0.5t c(SPC)M from SPIx_CLK falling Polarity Phase 0.5P to SPIx_CLK falling Polarity Phase 0.5P Input Setup Time, to SPIx_CLK rising t su(SOMI_SPC)M SPIx_SOMI valid before ns Polarity Phase receive edge of SPIx_CLK 0.5P to SPIx_CLK rising Polarity Phase 0.5P to SPIx_CLK falling Polarity Phase 0.5P from SPIx_CLK falling Polarity Phase 0.5P Input Hold Time, from SPIx_CLK rising t ih(SPC_SOMI)M SPIx_SOMI valid after ns Polarity Phase receive edge of SPIx_CLK 0.5P from SPIx_CLK rising Polarity Phase 0.5P from SPIx_CLK falling (1) P SYSCLK2 period (2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPIx_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIx_SOMI. (3) The final data bit will be held on the SPIx_SIMO pin until the SPIDAT0 or SPIDAT1 register is written with new data. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-28. General Timing Requirements for SPIx Slave Modes (1) NO. MIN MAX UNIT greater of or t c(SPC)S Cycle Time, SPIx_CLK, All Slave Modes 256P ns 100 ns greater of or t w(SPCH)S Pulse Width High, SPIx_CLK, All Slave Modes ns ns greater of or t w(SPCL)S Pulse Width Low, SPIx_CLK, All Slave Modes ns ns Polarity Phase to SPIx_CLK rising Setup time, transmit data Polarity Phase written to SPI and output to SPIx_CLK rising t su(SOMI_SPC)S onto SPIx_SOMI pin before ns Polarity Phase initial clock edge from to SPIx_CLK falling master. (2) (3) Polarity Phase to SPIx_CLK falling Polarity Phase from SPIx_CLK rising Polarity Phase Delay, subsequent bits from SPIx_CLK falling t d(SPC_SOMI)S valid on SPIx_SOMI after ns Polarity Phase transmit edge of SPIx_CLK from SPIx_CLK falling Polarity Phase from SPIx_CLK rising Polarity Phase 0.5t c(SPC)S from SPIx_CLK falling Polarity Phase Output hold time, 0.5t c(SPC)S from SPIx_CLK rising SPIx_SOMI valid after t oh(SPC_SOMI)S ns receive edge of SPIxCLK, Polarity Phase 0.5t c(SPC)S except for final bit (4) from SPIx_CLK rising Polarity Phase 0.5t c(SPC)S from SPIx_CLK falling Polarity Phase 0.5P to SPIx_CLK falling Polarity Phase 0.5P Input Setup Time, to SPIx_CLK rising t su(SIMO_SPC)S SPIx_SIMO valid before ns Polarity Phase receive edge of SPIx_CLK 0.5P to SPIx_CLK rising Polarity Phase 0.5P to SPIx_CLK falling Polarity Phase 0.5P from SPIx_CLK falling Polarity Phase 0.5P Input Hold Time, from SPIx_CLK rising t ih(SPC_SIMO)S SPIx_SIMO valid after ns Polarity Phase receive edge of SPIx_CLK 0.5P from SPIx_CLK rising Polarity Phase 0.5P from SPIx_CLK falling (1) P SYSCLK2 period (2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPIx_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPIx_SIMO. (3) Measured from the termination of the write of new data to the SPI module, as evidenced by new output data appearing on the SPIx_SOMI pin. In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the SPI module by either the DSP CPU or the dMAX. (4) The final data bit will be held on the SPIx_SOMI pin until the SPIDAT0 or SPIDAT1 register is written with new data. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-29. Additional (1) SPI Master Timings, 4-Pin Enable Option (2) (3) NO. MIN MAX UNIT Polarity Phase to SPIx_CLK rising Polarity Phase 0.5t c(SPC)M Delay from slave assertion of to SPIx_CLK rising t d(ENA_SPC)M SPIx_ENA active to first ns Polarity Phase SPIx_CLK from master. (4) to SPIx_CLK falling Polarity Phase 0.5t c(SPC)M to SPIx_CLK falling Polarity Phase 0.5t c(SPC)M from SPIx_CLK falling Polarity Phase Max delay for slave to deassert from SPIx_CLK falling SPIx_ENA after final SPIx_CLK t d(SPC_ENA)M ns edge to ensure master does not Polarity Phase 0.5t c(SPC)M begin the next transfer. (5) from SPIx_CLK rising Polarity Phase from SPIx_CLK rising (1) These parameters are in addition to the general timings for SPI master modes Table 4-27 (2) P SYSCLK2 period (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPIx_ENA assertion. (5) In the case where the master SPI is ready with new data before SPIx_ENA deassertion. Table 4-30. Additional (1) SPI Master Timings, 4-Pin Chip Select Option (2) (3) NO. MIN MAX UNIT Polarity Phase to SPIx_CLK rising Polarity Phase 0.5t c(SPC)M to SPIx_CLK rising Delay from SPIx_SCS active to t d(SCS_SPC)M ns first SPIx_CLK (4) (5) Polarity Phase to SPIx_CLK falling Polarity Phase 0.5t c(SPC)M to SPIx_CLK falling Polarity Phase 0.5t c(SPC)M from SPIx_CLK falling Polarity Phase Delay from final SPIx_CLK edge from SPIx_CLK falling t d(SPC_SCS)M to master deasserting SPIx_SCS ns Polarity Phase (6) (7) 0.5t c(SPC)M from SPIx_CLK rising Polarity Phase from SPIx_CLK rising (1) These parameters are in addition to the general timings for SPI master modes Table 4-27 (2) P SYSCLK2 period (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPIx_SCS assertion. (5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0]. (6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain asserted. (7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0]. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-31. Additional (1) SPI Master Timings, 5-Pin Option (2) (3) NO. MIN MAX UNIT Polarity Phase 0.5t c(SPC)M from SPIx_CLK falling Max delay for slave to Polarity Phase deassert SPIx_ENA after from SPIx_CLK falling final SPIx_CLK edge to t d(SPC_ENA)M ns ensure master does not Polarity Phase 0.5t c(SPC)M begin the next from SPIx_CLK rising transfer. (4) Polarity Phase from SPIx_CLK rising Polarity Phase 0.5t c(SPC)M from SPIx_CLK falling Polarity Phase Delay from final from SPIx_CLK falling SPIx_CLK edge to t d(SPC_SCS)M ns master deasserting Polarity Phase 0.5t c(SPC)M SPIx_SCS (5) (6) from SPIx_CLK rising Polarity Phase from SPIx_CLK rising Max delay for slave SPI to drive SPIx_ENA valid t d(SCSL_ENAL)M after master asserts SPIx_SCS to delay the 0.5P ns master from beginning the next transfer. Polarity Phase to SPIx_CLK rising Polarity Phase 0.5t c(SPC)M Delay from SPIx_SCS to SPIx_CLK rising t d(SCS_SPC)M active to first ns Polarity Phase SPIx_CLK (7) (8) (9) to SPIx_CLK falling Polarity Phase 0.5t c(SPC)M to SPIx_CLK falling Polarity Phase to SPIx_CLK rising Polarity Phase 0.5t c(SPC)M Delay from assertion of to SPIx_CLK rising t d(ENA_SPC)M SPIx_ENA low to first ns Polarity Phase SPIx_CLK edge. (10) to SPIx_CLK falling Polarity Phase 0.5t c(SPC)M to SPIx_CLK falling (1) These parameters are in addition to the general timings for SPI master modes Table 4-27 (2) P SYSCLK2 period (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPIx_ENA deassertion. (5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain asserted. (6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0]. (7) If SPIx_ENA is asserted immediately such that the transmission is not delayed by SPIx_ENA (8) In the case where the master SPI is ready with new data before SPIx_SCS assertion. (9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0]. (10) If SPIx_ENA was initially deasserted high and SPIx_CLK is delayed. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-32. Additional (1) SPI Slave Timings, 4-Pin Enable Option (2) (3) NO. MIN MAX UNIT Polarity Phase P from SPIx_CLK falling Polarity Phase 0.5t c(SPC)M P 0.5t c(SPC)M Delay from final from SPIx_CLK falling t d(SPC_ENAH)S SPIx_CLK edge to slave ns Polarity Phase deasserting SPIx_ENA P from SPIx_CLK rising Polarity Phase 0.5t c(SPC)M P 0.5t c(SPC)M from SPIx_CLK rising (1) These parameters are in addition to the general timings for SPI slave modes Table 4-28 (2) P SYSCLK2 period (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. Table 4-33. Additional (1) SPI Slave Timings, 4-Pin Chip Select Option (2) (3) NO. MIN MAX UNIT Required delay from SPIx_SCS asserted at slave to first t d(SCSL_SPC)S P ns SPIx_CLK edge at slave. Polarity Phase 0.5t c(SPC)M P from SPIx_CLK falling Polarity Phase P Required delay from final from SPIx_CLK falling t d(SPC_SCSH)S SPIx_CLK edge before ns Polarity Phase SPIx_SCS is deasserted. 0.5t c(SPC)M P from SPIx_CLK rising Polarity Phase P from SPIx_CLK rising Delay from master asserting SPIx_SCS to slave driving t ena(SCSL_SOMI)S P ns SPIx_SOMI valid Delay from master deasserting SPIx_SCS to slave 3-stating t dis(SCSH_SOMI)S P ns SPIx_SOMI (1) These parameters are in addition to the general timings for SPI slave modes Table 4-28 (2) P SYSCLK2 period (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-34. Additional (1) SPI Slave Timings, 5-Pin Option (2) (3) NO. MIN MAX UNIT Required delay from SPIx_SCS asserted at slave to first t d(SCSL_SPC)S P ns SPIx_CLK edge at slave. Polarity Phase 0.5t c(SPC)M P from SPIx_CLK falling Polarity Phase P Required delay from final from SPIx_CLK falling t d(SPC_SCSH)S SPIx_CLK edge before ns Polarity Phase SPIx_SCS is deasserted. 0.5t c(SPC)M P from SPIx_CLK rising Polarity Phase P from SPIx_CLK rising Delay from master asserting SPIx_SCS to slave driving t ena(SCSL_SOMI)S P ns SPIx_SOMI valid Delay from master deasserting SPIx_SCS to slave 3-stating t dis(SCSH_SOMI)S P ns SPIx_SOMI Delay from master deasserting SPIx_SCS to slave driving t ena(SCSL_ENA)S ns SPIx_ENA valid Polarity Phase from SPIx_CLK falling Polarity Phase Delay from final clock receive from SPIx_CLK rising edge on SPIx_CLK to slave t dis(SPC_ENA)S ns 3-stating or driving high Polarity Phase SPIx_ENA (4) from SPIx_CLK rising Polarity Phase from SPIx_CLK falling (1) These parameters are in addition to the general timings for SPI slave modes Table 4-28 (2) P SYSCLK2 period (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. (4) SPIx_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to Otherwise it is 3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) 4 5 5 6 MASTER MODE POLARITY = 0 PHASE = 0 MASTER MODE POLARITY = 0 PHASE = 1 MASTER MODE POLARITY = 1 PHASE = 0 MASTER MODE POLARITY = 1 PHASE = 1 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-33. SPI Timings Master Mode Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SPIx_CLK SPI_SIMO SPI_SOMI SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) 1110 SLA VE MODE POLARITY = 0 PHASE = 0 SLA VE MODE POLARITY = 0 PHASE = 1 SLA VE MODE POLARITY = 1 PHASE = 0 SLA VE MODE POLARITY = 1 PHASE = 1 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-34. SPI Timings Slave Mode Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com MASTER MODE 4 PIN WITH CHIP SELECT SPIx_CLK SPI_SIMO SPI_SOMI SPIx_ENA SPIx_CLK SPI_SIMO SPI_SOMI SPIx_SCS SPIx_CLK SPI_SIMO SPI_SOMI SPIx_ENA SPIx_SCS MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MASTER MODE 4 PIN WITH ENABLE MASTER MODE 5 PIN A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) DESEL (A) DESEL (A) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-35. SPI Timings Master Mode (4-Pin and 5-Pin) Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com SPIx_CLK SPI_SOMI SPI_SIMO SPIx_ENA SPIx_CLK SPI_SOMI SPI_SIMO SPIx_SCS SPIx_CLK SPI_SOMI SPI_SIMO SPIx_ENA SPIx_SCS SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SLA VE MODE 4 PIN WITH ENABLE SLA VE MODE 4 PIN WITH CHIP SELECT SLA VE MODE 5 PIN DESEL (A) DESEL (A) A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 4-36. SPI Timings Slave Mode (4-Pin and 5-Pin) Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) 4.15.1 I2C Device-Specific Information Peripheral Configuration Bus Noise Filter Noise Filter Clock Prescaler I2CPSCx Prescaler Register Bit Clock Generator I2CCLKHx Clock Divide High Register I2CCLKLx Clock Divide Low Register Control I2CCOARx Own Address Register I2CSARx Slave Address Register I2CCMDRx Mode Register I2CEMDRx Extended Mode Register I2CCNTx Data Count Register I2CPID1 Peripheral ID Register 1 I2CPID2 Peripheral ID Register 2 Transmit I2CXSRx Transmit Shift Register I2CDXRx T ransmit Buffer Receive I2CDRRx Receive Buffer I2CRSRx Receive Shift Register I2Cx_SCL I2Cx_SDA C672x I2C Module Control Interrupt/DMA I2CIERx Interrupt Enable Register I2CSTRx Interrupt Status Register I2CSRCx Interrupt Source Register Control I2CPFUNC Pin Function Register I2CPDIR Pin Direction Register I2CPDIN Pin Data In Register I2CPDOUT Pin Data Out Register I2CPDSET Pin Data Set Register I2CPDCLR Pin Data Clear Register Interrupt DMA Requests TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Having two I2C modules on the C672x simplifies system architecture, since one module may be used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to implement a user interface. Figure 4-37 is block diagram of the C672x I2C Module. Each I2C port supports: Compatible with Philips I2C Specification Revision 2.1 (January 2000) Fast Mode up to 400 Kbps (no fail-safe I/O buffers) Noise Filter to Remove Noise ns or less Seven- and Ten-Bit Device Addressing Modes Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality Events: DMA, Interrupt, or Polling General-Purpose I/O Capability if not used as I2C CAUTION The C672x I2C pins use a standard mA LVCMOS buffer, not the slow I/O buffer defined in the I2C specification. Series resistors may be necessary to reduce noise at the system level. Figure 4-37. I2C Module Block Diagram Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.15.2 I2C Peripheral Registers Description(s) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-35 is a list of the I2C registers. Table 4-35. I2Cx Configuration Registers I2C0 I2C1 REGISTER NAME

www.ti.com 4.15.3 I2C Electrical Data/Timing TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 4.15.3.1 Inter-Integrated Circuit (I2C) Timing Table 4-36 and Table 4-37 assume testing over recommended operating conditions (see Figure 4-38 and Figure 4-39 Table 4-36. I2C Input Timing Requirements NO. MIN MAX UNIT Standard Mode t c(SCL) Cycle time, I2Cx_SCL μ s Fast Mode 2.5 Standard Mode 4.7 Setup time, I2Cx_SCL high before I2Cx_SDA t su(SCLH-SDAL) μ s low Fast Mode 0.6 Standard Mode t h(SCLL-SDAL) Hold time, I2Cx_SCL low after I2Cx_SDA low μ s Fast Mode 0.6 Standard Mode 4.7 t w(SCLL) Pulse duration, I2Cx_SCL low μ s Fast Mode 1.3 Standard Mode t w(SCLH) Pulse duration, I2Cx_SCL high μ s Fast Mode 0.6 Standard Mode 250 t su(SDA-SCLH) Setup time, I2Cx_SDA before I2Cx_SCL high ns Fast Mode 100 Standard Mode t h(SDA-SCLL) Hold time, I2Cx_SDA after I2Cx_SCL low μ s Fast Mode 0.9 Standard Mode 4.7 t w(SDAH) Pulse duration, I2Cx_SDA high μ s Fast Mode 1.3 Standard Mode 1000 t r(SDA) Rise time, I2Cx_SDA ns Fast Mode 0.1C b 300 Standard Mode 1000 t r(SCL) Rise time, I2Cx_SCL ns Fast Mode 0.1C b 300 Standard Mode 300 t f(SDA) Fall time, I2Cx_SDA ns Fast Mode 0.1C b 300 Standard Mode 300 t f(SCL) Fall time, I2Cx_SCL ns Fast Mode 0.1C b 300 Standard Mode Setup time, I2Cx_SCL high before I2Cx_SDA t su(SCLH-SDAH) μ s high Fast Mode 0.6 Standard Mode N/A t w(SP) Pulse duration, spike (must be suppressed) ns Fast Mode Standard Mode 400 C b Capacitive load for each bus line pF Fast Mode 400 Table 4-37. I2C Switching Characteristics (1) NO. PARAMETER MIN MAX UNIT Standard Mode t c(SCL) Cycle time, I2Cx_SCL μ s Fast Mode 2.5 Standard Mode 4.7 Setup time, I2Cx_SCL high before I2Cx_SDA t su(SCLH-SDAL) μ s low Fast Mode 0.6 Standard Mode t h(SDAL-SCLL) Hold time, I2Cx_SCL low after I2Cx_SDA low μ s Fast Mode 0.6 (1) I2C must be configured correctly to meet the timings in Table 4-37 Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 6 14 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL 11 9 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL 26 24 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-37. I2C Switching Characteristics (continued) NO. PARAMETER MIN MAX UNIT Standard Mode 4.7 t w(SCLL) Pulse duration, I2Cx_SCL low μ s Fast Mode 1.3 Standard Mode t w(SCLH) Pulse duration, I2Cx_SCL high μ s Fast Mode 0.6 Standard Mode 250 Setup time, I2Cx_SDA valid before I2Cx_SCL t su(SDAV-SCLH) ns high Fast Mode 100 Standard Mode t h(SCLL-SDAV) Hold time, I2Cx_SDA valid after I2Cx_SCL low μ s Fast Mode 0.9 Standard Mode 4.7 t w(SDAH) Pulse duration, I2Cx_SDA high μ s Fast Mode 1.3 Standard Mode Setup time, I2Cx_SCL high before I2Cx_SDA t su(SCLH-SDAH) μ s high Fast Mode 0.6 Standard Mode Capacitive load on each bus line from this C b pF device Fast Mode Figure 4-38. I2C Receive Timings Figure 4-39. I2C Transmit Timings Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com 4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog 4.16.1 RTI/Digital Watchdog Device-Specific Information McASP0,1,2 Transmit/Receive DMA Events McASP0,1,2 Transmit/Receive DMA Events Counter 0 32-Bit + 32-Bit Prescale (Used by DSP BIOS) Capture 0 32-Bit + 32-Bit Prescale Counter 1 32-Bit + 32-Bit Prescale Capture 1 32-Bit + 32-Bit Prescale Compare 0 32-Bit RTI Interrupt 0 SYSCLK2 RTI Interrupt 1Compare 1 32-Bit RTI Interrupt 2Compare 2 32-Bit RTI Interrupt 3Compare 3 32-Bit RESET (Internal Only) Digital Watchdog 25-Bit Counter W atchdog Key Register 16-Bit Key Controlled by CFGRTI Register TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 C672x includes an RTI timer module which is used to generate periodic interrupts. This module also includes an optional digital watchdog feature. Figure 4-40 contains a block diagram of the RTI module. Figure 4-40. RTI Timer Block Diagram The RTI timer module consists of two independent counters which are both clocked from SYSCLK2 (but may be started individually and may have different prescaler settings). The counters provide the timebase against which four output comparators operate. These comparators may be programmed to generate periodic interrupts. The comparators include an adder which automatically updates the compare value after each periodic interrupt. This means that the DSP only needs to initialize the comparator once with the interrupt period. The two input captures can be triggered from any of the McASP0, McASP1, or McASP2 DMA events. The device configuration register which selects the McASP events to measure is defined in Table 4-39 Measuring the time difference between these events provides an accurate measure of the sample rates at which the McASPs are transmitting and receiving. This measurement can be useful as a hardware assist for a software asynchronous sample rate converter algorithm. Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.16.2 RTI/Digital Watchdog Registers Description(s) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A followed by 0xA35C in two separate writes) must be continually written to the key register before the watchdog counter counts down to zero; otherwise, the DSP will be reset. This feature can be used to provide an added measure of robustness against a software failure. If the application fails and ceases to write to the watchdog key; the watchdog will respond by resetting the DSP and thereby restarting the application. Note that Counter and Compare are used by DSP BIOS to generate the tick counter it requires; however, Capture is still available for use by the application as well as the remaining RTI resources. Table 4-38 is a list of the RTI registers. Table 4-38. RTI Registers BYTE ADDRESS REGISTER NAME event. RTI Internal Registers 0x4200 0000 RTIGCTRL Global Control Register. Starts stops the counters. 0x4200 0004 Reserved Reserved bit. 0x4200 0008 RTICAPCTRL Capture Control. Controls the capture source for the counters. 0x4200 000C RTICOMPCTRL Compare Control. Controls the source for the compare registers. 0x4200 0010 RTIFRC0 Free-Running Counter Current value of free-running counter 0x4200 0014 RTIUC0 Up-Counter Current value of prescale counter 0x4200 0018 RTICPUC0 Compare Up-Counter Compare value compared with prescale counter 0x4200 0020 RTICAFRC0 Capture Free-Running Counter Current value of free-running counter on external event. 0x4200 0024 RTICAUC0 Capture Up-Counter Current value of prescale counter on external event. 0x4200 0030 RTIFRC1 Free-Running Counter Current value of free-running counter 0x4200 0034 RTIUC1 Up-Counter Current value of prescale counter 0x4200 0038 RTICPUC1 Compare Up-Counter Compare value compared with prescale counter 0x4200 0040 RTICAFRC1 Capture Free-Running Counter Current value of free-running counter on external event. 0x4200 0044 RTICAUC1 Capture Up-Counter Current value of prescale counter on external event. 0x4200 0050 RTICOMP0 Compare Compare value to be compared with the counters. 0x4200 0054 RTIUDCP0 Update Compare Value to be added to the compare register value on compare match. 0x4200 0058 RTICOMP1 Compare Compare value to be compared with the counters. 0x4200 005C RTIUDCP1 Update Compare Value to be added to the compare register value on compare match. 0x4200 0060 RTICOMP2 Compare Compare value to be compared with the counters. 0x4200 0064 RTIUDCP2 Update Compare Value to be added to the compare register value on compare match. 0x4200 0068 RTICOMP3 Compare Compare value to be compared with the counters. 0x4200 006C RTIUDCP3 Update Compare Value to be added to the compare register value on compare match. 0x4200 0070 Reserved Reserved bit. 0x4200 0074 Reserved Reserved bit. 0x4200 0080 RTISETINT Set Interrupt Enable. Sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation. 0x4200 0084 RTICLEARINT Clear Interrupt Enable. Clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation. 0x4200 0088 RTIINTFLAG Interrupt Flags. Interrupt pending bits. Submit Documentation Feedback Peripheral and Electrical Specifications

www.ti.com TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-38. RTI Registers (continued) BYTE ADDRESS REGISTER NAME Control. Enables the Digital Watchdog. 0x4200 0094 RTIDWDPRLD Digital Watchdog Preload. Sets the experation time of the Digital Watchdog. 0x4200 0098 RTIWDSTATUS Watchdog Status. Reflects the status of Analog and Digital Watchdog. 0x4200 009C RTIWDKEY Watchdog Key. Correct written key values discharge the external capacitor. 0x4200 00A0 RTIDWDCNTR Digital Watchdog Down-Counter Figure 4-41 shows the bit layout of the CFGRTI register and Table 4-39 contains a bits. Reserved Reserved CAPSEL1 Reserved CAPSEL0 R/W, R/W, LEGEND: R/W Read/Write; R Read only; n value after reset Figure 4-41. CFGRTI Register Bit Layout (0x4000 0014) Table 4-39. CFGRTI Register Bit Field (0x4000 0014) RESET READ BIT NO. NAME 31:7,3 Reserved N/A N/A Reads are indeterminate. Only should be written to these bits. 6:4 CAPSEL1 R/W CAPSEL0 selects the input to the RTI Input Capture function. CAPSEL1 selects the input to the RTI Input Capture function. 2:0 CAPSEL0 R/W The encoding is the same for both fields: 000 Select McASP0 Transmit DMA Event 001 Select McASP0 Receive DMA Event 010 Select McASP1 Transmit DMA Event 011 Select McASP1 Receive DMA Event 100 Select McASP2 Transmit DMA Event 101 Select McASP2 Receive DMA Event Other values are reserved and their effect is not determined. Peripheral and Electrical Specifications 100 Submit Documentation Feedback

www.ti.com 4.17 External Clock Input From Oscillator or CLKIN Pin OSCV DD C 5 C 7 C 8 R S R B OSCIN OSCOUT C 6 OSCV SS CLKIN Clock Input From OSCIN to PLL On-Chip 1.2-V Oscillator (a) External 3.3-V LVCMOS-Compatible Clock Source (b) OSCV DD OSCIN OSCOUT OSCV SS CLKIN Clock Input From CLKIN to PLL CV DD (1.2 V) NC TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x device includes two choices to provide an external clock input, which is fed to the on-chip PLL to generate high-frequency system clocks. These options are illustrated in Figure 4-42 Figure 4-42 (a) illustrates the option that uses an on-chip 1.2-V oscillator with external crystal circuit. Figure 4-42 (b) illustrates the option that uses an external 3.3-V LVCMOS-compatible clock input with the CLKIN pin. Note that the two clock inputs are logically combined internally before the PLL so the clock input that is not used must be tied to ground. Figure 4-42. C672x Clock Input Options If the on-chip oscillator is chosen, then the recommended component values for Figure 4-42 (a) are listed in Table 4-40 Table 4-40. Recommended On-Chip Oscillator Components FREQUENCY XTAL TYPE X C (1) C (1) C C R B R S 22.579 AT-49 KDS 1AF225796A 470 pF 470 pF pF pF M Ω Ω 22.579 SMD-49 KDS 1AS225796AG 470 pF 470 pF pF pF M Ω Ω 24.576 AT-49 KDS 1AF245766AAA 470 pF 470 pF pF pF M Ω Ω 24.576 SMD-49 KDS 1AS245766AHA 470 pF 470 pF pF pF M Ω Ω (1) Capacitors C and C are used to reduce oscillator jitter, but are optional. If C and C are not used, then the node connecting capacitors C and C should be tied to OSCV SS and OSCV DD should be tied to CV DD Submit Documentation Feedback Peripheral and Electrical Specifications 101

www.ti.com 4.17.1 Clock Electrical Data/Timing TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-41 assumes testing over recommended operating conditions. Table 4-41. CLKIN Timing Requirements NO. MIN MAX UNIT f osc Oscillator frequency range (OSCIN/OSCOUT) MHz t c(CLKIN) Cycle time, external clock driven on CLKIN ns t w(CLKINH) Pulse width, CLKIN high 0.4t c(CLKIN) ns t w(CLKINL) Pulse width, CLKIN low 0.4t c(CLKIN) ns t t(CLKIN) Transition time, CLKIN ns f PLL Frequency range of PLL input MHz Peripheral and Electrical Specifications 102 Submit Documentation Feedback

www.ti.com 4.18 Phase-Locked Loop (PLL) 4.18.1 PLL Device-Specific Information PLLEN (PLL_CSR[0]) Divider (/1 to /32) PLLREF PLL x4 to x25 PLLOUT Divider (/1 to /32) SYSCLK1 CPU and Memory Divider (/1 to /32) SYSCLK2 Peripherals and dMAX Divider (/1 to /32) SYSCLK3 EMIF AUXCLK McASP0,1,2 Clock Input from CLKIN or OSCIN TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL. The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the CLKIN pin. The PLL outputs four clocks that have programmable divider options. Figure 4-43 illustrates the PLL Topology. The PLL is disabled by default after a device reset. It must be configured by software according to the allowable operating conditions listed in Table 4-42 before enabling the DSP to run from the PLL by setting PLLEN Figure 4-43. PLL Topology Submit Documentation Feedback Peripheral and Electrical Specifications 103

www.ti.com BOARD DV DD (3.3 V) EMI Filter 10 /C0109F 0.1 /C0109F PLLHV Place Filter and Capacitors as Close to DSP as Possible EMI Filter: TDK ACF451832−333, −223, −153, or −103, Panasonic EXCCET103U, or Equivalent TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-42. Allowed PLL Operating Conditions ALLOWED SETTING OR RANGE PARAMETER DEFAULT VALUE MIN MAX PLLRST assertion time during initialization N/A 125 ns Lock time before setting PLLEN After changing D0, PLLM, or N/A 187.5 µ s input clock. PLL input frequency (PLLREF after (1) MHz MHz PLL multiplier values (PLLM) x13 x25 PLL output frequency (PLLOUT before dividers D1, D2, D3) (2) N/A 140 MHz 600 MHz SYSCLK1 frequency (set by PLLM and dividers D0, D1) PLLOUT/1 Device Frequency Specification SYSCLK2 frequency (set by PLLM and dividers D0, D2) PLLOUT/2 /2, /3, or of SYSCLK1 SYSCLK3 frequency (set by PLLM and dividers D0, D3) PLLOUT/3 EMIF Frequency Specification (1) Some values for the divider produce results outside of this range and should not be selected. (2) In general, selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter. CAUTION SYSCLK1, SYSCLK2, SYSCLK3 must be configured as aligned by setting ALNCTL[2:0] to '1'; and the PLLCMD.GOSET bit must be written every time the dividers D1, D2, and are changed in order to make sure the change takes effect and preserves alignment. CAUTION When changing the PLL parameters which affect the SYSCLK1, SYSCLK2, SYSCLK3 dividers, the bridge BR2 in Figure 2-4 must be reset by the CFGBRIDGE register. See Table 2-7 The PLL is an analog circuit and is sensitive to power supply noise. Therefore it has a dedicated 3.3-V power pin (PLLHV) that should be connected to DV DD at the board level through an external filter, as illustrated in Figure 4-44 Figure 4-44. PLL Power Supply Filter 104 Peripheral and Electrical Specifications Submit Documentation Feedback

www.ti.com 4.18.2 PLL Registers Description(s) TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 4-43 is a list of the PLL registers. For more information about these registers, see the TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU879). Table 4-43. PLL Controller Registers BYTE ADDRESS REGISTER NAME

www.ti.com Application Example 256K Bytes RAM Bytes ROM 384K Memory Controller C67x+ DSP Core Program Cache Crossbar Switch EMIF UHPIdMAX McASP0 SPI1 McASP1 I2C0 I2C1 RTI SPIO McASP2 PLL OSC ASYNC FLASH

133 MHz

Control (optional) Audio Zone 2 Audio Zone 3 CODEC, DIR, ADC, DAC, DSD, Network Network ADC, DAC, DSD, CODEC, DIR, TDM Port Digital Out, High Speed Parallel Data DSP Control SPI or I2C

6 Independent Audio

Zones (3 TX + 3 RX)

16 Serial Data Pins

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Figure 5-1 illustrates a high-level block diagram of the device and other devices to which it may typically connect. See Section 1.2 for an overview of each major block. UHPI is only available on the C6727B. McASP2 is not available on the C6722B and C6720. Figure 5-1. TMS320C672x Audio DSP System Diagram 106 Application Example Submit Documentation Feedback

www.ti.com Revision History TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 This revision history highlights the technical changes made to the SPRS370B device-specific data sheet to make it an SPRS370C revision. Scope: Updated Table 4-10 EMIF Asynchronous Interface Switching Characteristics. ADDS/CHANGES/DELETES Table 4-10 EMIF Asynchronous Interface Switching Characteristics: t c(EM_CLK) Added MIN value for 133-MHz EMIF frequency Submit Documentation Feedback Revision History 107

www.ti.com Mechanical Data 7.1 Package Thermal Resistance Characteristics TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Table 7-1 and Table 7-2 provide the thermal characteristics for the recommended package types used on the TMS320C672x DSP. Table 7-1. Thermal Characteristics for GDH/ZDH Package AIR FLOW NO. C/W (m/s) Two-Signal, Two-Plane, 101.5 x 114.5 x 1.6 mm 2-oz Cu. EIA/JESD51-9 PCB R θ JA Thermal Resistance Junction to Ambient R θ JB Thermal Resistance Junction to Board 14.5 R θ JC Thermal Resistance Junction to Top of Case Ψ JB Thermal Metric Junction to Board Ψ JT Thermal Metric Junction to Top of Case 0.39 Table 7-2. Thermal Characteristics for RFP Package THERMAL PAD CONFIGURATION AIR NO. C/W FLOW VIA TOP BOTTOM (m/s) ARRAY Two-Signal, Two-Plane, 76.2 x 76.2 mm PCB (1) (2) (3) R θ JA Thermal Resistance Junction to Ambient 10.6 x 10.6 mm 10.6 x 10.6 mm x 7.5 x 7.5 mm 7.5 x 7.5 mm x Ψ JP Thermal Metric Junction to Power Pad 10.6 x 10.6 mm 10.6 x 10.6 mm x 0.39 Double-Sided 76.2 x 76.2 mm PCB (1) (2) (4) R θ JA Thermal Resistance Junction to Ambient 10.6 x 10.6 mm 10.6 x 10.6 mm x 10.6 x 10.6 mm 38.1 x 38.1 mm x 10.6 x 10.6 mm 57.2 x mm x 10.6 x 10.6 mm 76.2 x 76.2 mm x Ψ JP Thermal Metric Junction to Power Pad 10.6 x 10.6 mm 10.6 x 10.6 mm x 0.39 (1) PCB modeled with oz/ft Top and Bottom Cu. (2) Package thermal pad must be properly soldered to top layer PCB thermal pad for both thermal and electrical performance. Thermal pad is V SS (3) Top layer thermal pad is connected through via array to both bottom layer thermal pad and internal V SS plane. (4) Top layer thermal pad is connected through via array to bottom layer thermal pad. Mechanical Data 108 Submit Documentation Feedback

www.ti.com 7.2 Supplementary Information About the 144-Pin RFP PowerPAD Package 7.2.1 Standoff Height Standoff Height TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 This section highlights a few important details about the 144-pin RFP PowerPAD package. Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) should be consulted before designing a PCB for this device. As illustrated in Figure 7-1 the standoff height specification for this device (between 0.050 mm and 0.150 mm) is measured from the seating plane established by the three lowest package pins to the lowest point on the package body. Due to warpage, the lowest point on the package body is located in the center of the package at the exposed thermal pad. Using this definition of standoff height provides the correct result for determining the correct solder paste thickness. According to TI's PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002), the recommended range of solder paste thickness for this package is between 0.152 mm and 0.178 mm. Figure 7-1. Standoff Height Measurement on 144-Pin RFP Package Submit Documentation Feedback Mechanical Data 109

www.ti.com 7.2.2 PowerPAD PCB Footprint Thermal Pad on Top Copper should be as large as Possible. Soldermask opening should be smaller and match the size of the thermal pad on the DSP. 7.3 Packaging Information TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors SPRS370C SEPTEMBER 2006 REVISED OCTOBER 2007 Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) should be consulted when creating a PCB footprint for this device. In general, for proper thermal performance, the thermal pad under the package body should be as large as possible. However, the soldermask opening for the PowerPAD should be sized to match the pad size on the 144-pin RFP package; as illustrated in Figure 7-2 Figure 7-2. Soldermask Opening Should Match Size of DSP Thermal Pad The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document. On the 144-pin RFP package, the actual size of the Thermal Pad is 5.4 mm 5.4 mm. Mechanical Data 110 Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TMS320C6720BRFP200 ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TMS320C6722BRFP200 ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TMS320C6722BRFP250 ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TMS320C6726BRFP266 ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TMS320C6727BGDH275 ACTIVE BGA GDH 256 90 TBD Call TI Call TI TMS320C6727BGDH300 ACTIVE BGA GDH 256 90 TBD SNPB Level-3-220C-168 HR TMS320C6727BGDH350 ACTIVE BGA ZDH 256 90 TBD Call TI Call TI TMS320C6727BZDH275 ACTIVE BGA ZDH 256 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TMS320C6727BZDH300 ACTIVE BGA ZDH 256 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TMS320C6727BZDH350 ACTIVE BGA ZDH 256 90 TBD Call TI Call TI TMSDC6722BRFPA225 ACTIVE HTQFP RFP 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TMSDC6726BRFPA225 ACTIVE HTQFP RFP 144 60 TBD Call TI Call TI TMSDC6727BGDHA250 ACTIVE BGA GDH 256 90 TBD SNPB Level-3-220C-168 HR TMSDC6727BZDHA250 ACTIVE BGA ZDH 256 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 17-Oct-2007 Addendum-Page 1

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 17-Oct-2007 Addendum-Page 2

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