TMSC6701 TI | Alldatasheet
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/C0067 /C0070/C0065. /C0065 /C0065 /C0067 SPRS067E – MAY 1998 – REVISED MAY 2000 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701 – 8.3-, 6.7-, 6-ns Instruction Cycle Time – 120-, 150-, 167-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 1 GFLOPS – TMS320C6201 Fixed-Point DSP Pin-Compatible VelociTI Advanced Very Long Instruction Word (VLIW) ’C67x CPU Core – Eight Highly Independent Functional Units: – Four ALUs (Floating- and Fixed-Point) – Two ALUs (Fixed-Point) – Two Multipliers (Floating- and Fixed-Point) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional Instruction Set Features – Hardware Support for IEEE Single-Precision Instructions – Hardware Support for IEEE Double-Precision Instructions – Byte-Addressable (8-, 16-, 32-Bit Data) – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization 1M-Bit On-Chip SRAM – 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) – 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM and SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM – 52M-Byte Addressable External Memory Space Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel 16-Bit Host-Port Interface (HPI) – Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial-Peripheral-Interface (SPI) Compatible (Motorola ) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible 352-Pin Ball Grid Array (BGA) Package (GJC Suffix) 0.18-mm/5-Level Metal Process – CMOS Technology 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz) 3.3-V I/Os, 1.9-V Internal (167-MHz Only) Copyright 2000, Texas Instruments Incorporated /C0067 /C0065/C0065 !$ $) ( % *)( %$ %’# )% (& !)!%$( & ’ ) ’#( % ,( $()’*# $)( ()$ +’’$)- ’% *)!%$ &’% ((!$ ( $%) $ ()!$ % "" &’# Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 126 GJC (352-PIN BGA) PACKAGE (BOTTOM VIEW) VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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absolute maximum ratings over operating case electrical characteristics over recommended ranges of supply voltage and operating case temperature 28. . . .
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description
The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000 DSP platform. The TMS320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. device characteristics Table 1 provides an overview of the ’C6701 DSP . The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. Table 1. Characteristics of the ’C6701 Processors TMS320C6000 is a trademark of Texas Instruments. Windows is a registered trademark of Microsoft Corporation.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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functional block and CPU diagram Program Control Logic Test ’C67x CPU Data Path B B Register File Program Access/Cache Controller Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File Data Access Controller Power- Down Logic ROM/FLASH SRAM I/O Devices Timer 0 Timer 1 External Memory Interface (EMIF) Multichannel Buffered Serial Port 0 Multichannel Buffered Serial Port 1 Direct Memory Access Controller (DMA) (4 Channels)Host Port Interface (HPI) Internal Program Memory
1 Block Program/Cache
(64K Bytes) Control Registers Internal Data Memory (64K Bytes)
2 Blocks of 8 Banks
Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs DMA Buses Data Bus ’C6701 Digital Signal Processor PLL (x1, x4) Bus SBSRAM SDRAM HOST CONNECTION MC68360 Glueless MPC860 Glueless PCI9050 Bridge + Inverter MC68302 + PAL MPC750 + PAL MPC960 (Jx/Rx) + PAL † These functional units execute floating-point instructions.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the Functional and CPU Block diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all registers on the other side, by which the two sets of functional units can access data from the register files on opposite sides. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The ’C67x CPU executes all TMS320C62x DSP fixed-point instructions. In addition to the ’C62x DSP floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The ’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. TMS320C62x is a trademark of Texas Instruments.
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† These functional units execute floating-point instructions. Figure 1. TMS320C67x CPU Data Paths
Figure 2. CPU and Peripheral Signals
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Figure 3. Peripheral Signals
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Signal Descriptions SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION CLOCK/PLL CLKIN C10 I Clock Input CLKOUT1 AF22 O Clock output at full device speed CLKOUT2 AF20 O Clock output at half of device speed CLKMODE1 C6 I Clock mode select CLKMODE0 C5 I • Selects whether the output clock frequency = input clock frequency x4 or x1 PLLFREQ3 A9 PLL f (3 2 d 1)PLLFREQ2 D11 I PLL frequency range (3, 2, and 1)
- The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQpins PLLFREQ1 B10 I • The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins. PLLV ‡ D12 A§ PLL analog VCC connection for the low-pass filter PLLG ‡ C12 A§ PLL analog GND connection for the low-pass filter PLLF A11 A§ PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS L3 I JTAG test-port mode select (features an internal pullup) TDO W2 O/Z JTAG test-port data out TDI R4 I JTAG test-port data in (features an internal pullup) TCK R3 I JTAG test-port clock TRST T1 I JTAG test-port reset (features an internal pulldown) EMU1 Y1 I/O/Z Emulation pin 1, pullup with a dedicated 20-kW resistor¶ EMU0 W3 I/O/Z Emulation pin 0, pullup with a dedicated 20-kW resistor¶ CONTROL RESET K2 I Device reset NMI L2 I Nonmaskable interrupt
- Edge-driven (rising edge) EXT_INT7 U3 EXT_INT6 V2 I External interrupts EXT_INT5 W1 I External interru ts
- Edge-driven (rising edge) EXT_INT4 U4 g( g g ) IACK Y2 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 AA1 INUM2 W4 O Active interrupt identification number
- Valid during IACK for all active interrupts (not just external)INUM1 AA2 O • Valid during IACK for all active interrupts (not just external)
- Encoding order follow s the interrupt-service fetch-packet ordering INUM0 AB1
- Encoding order follows the interru t-service fetch- acket ordering LENDIAN H3 I If high, LENDIAN selects little-endian byte/half-word addressing order within a word If low, LENDIAN selects big-endian addressing PD D3 O Power-down mode 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kW resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kW resistor.
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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION HOST-PORT INTERFACE (HPI) HINT H26 O Host interrupt (from DSP to host) HCNTL1 F23 I Host control – selects between control, address, or data registers HCNTL0 D25 I Host control – selects between control, address, or data registers HHWIL C26 I Host half-word select – first or second half-word (not necessarily high or low order) HBE1 E23 I Host byte select within word or half-word HBE0 D24 I Host byte select within word or half-word HR/W C23 I Host read or write select HD15 B13 HD14 B14 HD13 C14 HD12 B15 HD11 D15 HD10 B16 HD9 A17 HD8 B17 I/O/Z Host port data (used for transfer of data address and control)HD7 D16 I/O/Z Host-port data (used for transfer of data, address, and control) HD6 B18 HD5 A19 HD4 C18 HD3 B19 HD2 C19 HD1 B20 HD0 B21 HAS C22 I Host address strobe HCS B23 I Host chip select HDS1 D22 I Host data strobe 1 HDS2 A24 I Host data strobe 2 HRDY J24 O Host ready (from DSP to host) BOOT MODE BOOTMODE4 D8 BOOTMODE3 B4 BOOTMODE2 A3 I Boot mode BOOTMODE1 D5 I Boot mode BOOTMODE0 C4 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 AE22 O/Z CE2 AD26 O/Z Memory space enables CE1 AB24 O/Z • Enabled by bits 24 and 25 of the word address CE0 AC26 O/Z • Only one asserted during any external data access BE3 AB25 O/Z Byte-enable control BE2 AA24 O/Z • Decoded from the two lowest bits of the internal address BE1 Y23 O/Z • Byte-write enables for most types of memory BE0 AA26 O/Z • Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF – ADDRESS EA21 J26 EA20 K25 EA19 L24 EA18 K26 EA17 M26 EA16 M25 EA15 P25 EA14 P24 EA13 R25 EA12 T26 O/Z External address (word address)EA11 R23 O/Z External address (word address) EA10 U26 EA9 U25 EA8 T23 EA7 V26 EA6 V25 EA5 W26 EA4 V24 EA3 W25 EA2 Y26 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION EMIF – DATA ED31 AB2 ED30 AC1 ED29 AA4 ED28 AD1 ED27 AC3 ED26 AD4 ED25 AF3 ED24 AE4 ED23 AD5 ED22 AF4 ED21 AE5 ED20 AD6 ED19 AE6 ED18 AD7 ED17 AC8 ED16 AF7 I/O/Z External dataED15 AD9 I/O/Z External data ED14 AD10 ED13 AF9 ED12 AC11 ED11 AE10 ED10 AE11 ED9 AF11 ED8 AE14 ED7 AF15 ED6 AE15 ED5 AF16 ED4 AC15 ED3 AE17 ED2 AF18 ED1 AF19 ED0 AC17 EMIF – ASYNCHRONOUS MEMORY CONTROL ARE Y24 O/Z Asynchronous memory read enable AOE AC24 O/Z Asynchronous memory output enable AWE AD23 O/Z Asynchronous memory write enable ARDY W23 I Asynchronous memory ready input † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION EMIF – SYNCHRONOUS BURST SRAM CONTROL SSADS AC20 O/Z SBSRAM address strobe SSOE AF21 O/Z SBSRAM output enable SSWE AD19 O/Z SBSRAM write enable SSCLK AD17 O SBSRAM clock EMIF – SYNCHRONOUS DRAM CONTROL SDA10 AD21 O/Z SDRAM address 10 (separate for deactivate command) SDRAS AF24 O/Z SDRAM row-address strobe SDCAS AD22 O/Z SDRAM column-address strobe SDWE AF23 O/Z SDRAM write enable SDCLK AE20 O SDRAM clock EMIF – BUS ARBITRATION HOLD AA25 I Hold request from the host HOLDA A7 O Hold-request-acknowledge to the host TIMERS TOUT1 H24 O Timer 1 or general-purpose output TINP1 K24 I Timer 1 or general-purpose input TOUT0 M4 O Timer 0 or general-purpose output TINP0 K4 I Timer 0 or general-purpose input DMA ACTION COMPLETE DMAC3 D2 DMAC2 F4 O DMA action completeDMAC1 D1 O DMA action complete DMAC0 E2 MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 E25 I External clock source (as opposed to internal) CLKR1 H23 I/O/Z Receive clock CLKX1 F26 I/O/Z Transmit clock DR1 D26 I Receive data DX1 G23 O/Z Transmit data FSR1 E26 I/O/Z Receive frame sync FSX1 F25 I/O/Z Transmit frame sync † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 L4 I External clock source (as opposed to internal) CLKR0 M2 I/O/Z Receive clock CLKX0 L1 I/O/Z Transmit clock DR0 J1 I Receive data DX0 R1 O/Z Transmit data FSR0 P4 I/O/Z Receive frame sync FSX0 P3 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 T2 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV1 G2 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV2 C11 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV3 B9 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV4 A6 I Reserved for testing, pulldown with a dedicated 20-kW resistor RSV5 C8 O Reserved (leave unconnected, do not connect to power or ground) RSV6 C21 I Reserved for testing, pullup with a dedicated 20-k resistor RSV7 B22 I Reserved for testing, pullup with a dedicated 20-k resistor RSV8 A23 I Reserved for testing, pullup with a dedicated 20-k resistor RSV9 E4 O Reserved (leave unconnected, do not connect to power or ground) SUPPLY VOLTAGE PINS A10 A15 A18 A21 A22 D17 G24 DV DD G25 S 3.3-V supply voltageDV DD H25 S 3.3V su ly voltage J25 L25 N23 R26 T24 U24 W24 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) AB3 AB4 AB26 AC6 AC10 AC19 AC21 AC22 DV DD AC25 S 3.3-V supply voltageDV DD AD11 S 3.3V su ly voltage AD13 AD15 AD18 AE18 AE21 AF5 AF6 AF17 A12 A16 A20 B11 B12 B25 CV S 1.8-V supply voltage (for ’6701-120, -150)CV DD C15 S 1.8V su ly voltage (for 6701 120, 150) 1.9-V supply voltage (for ’6701-167 only) C20 yg ( y ) C24 D14 D18 D20 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) D23 J23 K23 M24 N25 P23 CV S 1.8-V supply voltage (for ’6701-120, -150)CV DD V4 S 1.8V su ly voltage (for 6701 120, 150) 1.9-V supply voltage (for ’6701-167 only) V23 yg ( y ) AC4 AC9 AC12 AC13 AC18 AC23 AD3 AD8 AD14 AD24 AE2 AE8 AE12 AE25 AF12 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION GROUND PINS A13 A14 A25 A26 B24 B26 C13 C16 C17 C25 D13 VSS D19 GND Ground pinsVSS GND Ground ins E24 F24 G26 L23 L26 M23 N24 N26 P26 R24 T25 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION GROUND PINS (CONTINUED) U23 Y25 AA3 AA23 AB23 AC2 AC5 AC7 AC14 AC16 AD2 AD12 AD16 AD20 VSS AD25 GND Ground pinsVSS AE1 GND Ground ins AE3 AE7 AE9 AE13 AE16 AE19 AE23 AE24 AE26 AF1 AF2 AF8 AF10 AF13 AF14 AF25 AF26 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Signal Descriptions (Continued) SIGNAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION REMAINING UNCONNECTED PINS D10 D21 NC G1 Unconnected pinsNC Unconnected ins † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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TI offers an extensive line of development tools for the TMS320C6000/C0116 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000/C0116 DSP-based applications: Software Development Tools: Code Composer Studio/C0116 Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS ) Emulator (supports C6000/C0116 DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320/C0116 DSP family member devices, including documentation. See this document for further information on TMS320/C0116 DSP documentation or any TMS320/C0116 DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320/C0116 DSP-related products from other companies in the industry. To receive TMS320/C0116 DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000/C0116 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under “Development T ools”, select “Digital Signal Processors”. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
(TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). of the device have been demonstrated fully. TI’s standard warranty applies. expected end-use failure rate still is undefined. Only qualified production devices are to be used. Table 2. TMS320C6701 Device P/Ns and Ordering Information
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100 MHz
120 MHz
150 MHz
167 MHz
200 MHz
233 MHz
250 MHz
300 MHz
Figure 4. TMS320 DSP Device Nomenclature (Including TMS320C6701) MicroStar BGA is a trademark of Texas Instruments.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 23POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the ’C6x devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x devices, associated development tools, and third-party support. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
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bypasses the PLL to become the internal CPU clock. Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. Table 3. CLKOUT1 Frequency Ranges† of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved. Table 4. ’C6701 PLL Component Selection Table typical lock time is specified as 100 ms, the maximum value may be as long as 250 ms.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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absolute maximum ratings over operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT CV Supply voltage Core‡ ’6701-120, -150 1.71 1.8 1.89 V CV DD Supply voltage, Core‡ ’6701-167 only 1.81 1.9 1.99 V DV DD Supply voltage, I/O‡ 3.14 3.30 3.46 V VSS Supply ground 0 0 0 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IOH High-level output current –12 mA IOL Low-level output current 12 mA TC Case temperature Default 0 90 /C0095C TC Case temperature A Version –40 105 /C0095C ‡ TI DSP’s do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long term reliability of the device. System-level concerns such as bus contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. For additional power supply sequencing information, see the Power Supply Sequencing Solutions For Dual Supply Voltage DSPs application report (literature number SLVA073).
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 27POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage DV DD = MIN, I OH = MAX 2.4 V VOL Low-level output voltage DV DD = MIN, I OL = MAX 0.6 V II Input current† VI = VSS to DVDD ±10 uA IOZ Off-state output current VO = DVDD or 0 V ±10 uA I Supply current CPU CPU memory access‡ CV DD = NOM, CPU clock = 150 MHz 470 mAIDD2V Supply current, CPU + CPU memory access‡ CV DD = NOM, CPU clock = 120 MHz 380 mA I Supply current peripherals‡ CV DD = NOM, CPU clock = 150 MHz 250 mAIDD2V Supply current, peripherals‡ CV DD = NOM, CPU clock = 120 MHz 200 mA I Supply current I/O pins‡ DV DD = NOM, CPU clock = 150 MHz 85 mAIDD3V Supply current, I/O pins‡ DV DD = NOM, CPU clock = 120 MHz 70 mA C i Input capacitance 10 pF C o Output capacitance 10 pF † TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. ‡ Measured with average activity (50% high / 50% low power). For more detailed information on CPU/peripheral/I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486).
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† Typical distributed load circuit capacitance. All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements
NO. CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 UNITNO. † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ‡ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. NO. CLKMODE = x4 CLKMODE = x1 UNITNO. † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ‡ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. Figure 8. CLKIN Timings
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† P = 1/CPU clock frequency in nanoseconds (ns). ‡ PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. Figure 9. CLKOUT1 Timings § P = 1/CPU clock frequency in ns. Figure 10. CLKOUT2 Timings
SDCLK timing parameters are the same as CLKOUT2 parameters. Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 12 and Figure 13) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 6 tsu(EDV-CKO1H) Setup time, read EDx valid before CLKOUT1 high 4.5 ns 7 th(CKO1H-EDV) Hold time, read EDx valid after CLKOUT1 high 1.5 ns 10 tsu(ARDY-CKO1H) Setup time, ARDY valid before CLKOUT1 high 3.5 ns 11 th(CKO1H-ARDY) Hold time, ARDY valid after CLKOUT1 high 1.5 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics for asynchronous memory cycles‡ (see Figure 12 and Figure 13) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 1 td(CKO1H-CEV) Delay time, CLKOUT1 high to CEx valid –1.0 4.5 ns 2 td(CKO1H-BEV) Delay time, CLKOUT1 high to BEx valid 4.5 ns 3 td(CKO1H-BEIV) Delay time, CLKOUT1 high to BEx invalid –1.0 ns 4 td(CKO1H-EAV) Delay time, CLKOUT1 high to EAx valid 4.5 ns 5 td(CKO1H-EAIV) Delay time, CLKOUT1 high to EAx invalid –1.0 ns 8 td(CKO1H-AOEV) Delay time, CLKOUT1 high to AOE valid –1.0 4.5 ns 9 td(CKO1H-AREV) Delay time, CLKOUT1 high to ARE valid –0.5 4.5 ns 12 td(CKO1H-EDV) Delay time, CLKOUT1 high to EDx valid 4.5 ns 13 td(CKO1H-EDIV) Delay time, CLKOUT1 high to EDx invalid –1.0 ns 14 td(CKO1H-AWEV) Delay time, CLKOUT1 high to AWE valid –1.0 4.5 ns ‡ The minimum delay is also the minimum output hold after CLKOUT1 high.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 14) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . MIN MAX MIN MAX UNIT 7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 2.0 2.0 ns 8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 2.9 2.1 ns switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 14 and Figure 15) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . PARAMETER MIN MAX MIN MAX UNIT 1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high 0.5P – 1.3 0.5P – 1.3 ns 2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P – 2.9 0.5P – 2.3 ns 3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high 0.5P – 1.3 0.5P – 1.6 ns 4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P – 2.9 0.5P – 2.3 ns 5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high0.5P – 1.3 0.5P – 1.7 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high0.5P – 2.9 0.5P – 2.3 ns 9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high 0.5P – 1.3 0.5P – 1.3 ns 10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 0.5P – 2.9 0.5P – 2.3 ns 11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high 0.5P – 1.3 0.5P – 1.3 ns 12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high 0.5P – 2.9 0.5P – 2.3 ns 13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high0.5P – 1.3 0.5P – 1.3 ns 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high0.5P – 2.9 0.5P – 2.3 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 0.5P – 1.3 0.5P – 1.3 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.9 0.5P – 2.3 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 3.6 ns 8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 16 and Figure 17) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . PARAMETER MIN MAX MIN MAX UNIT 1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high 1.5P – 4.5 1.5P – 4.5 ns 2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P – 2.5 0.5P – 2 ns 3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high 1.5P – 4.5 1.5P – 4.5 ns 4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P – 2.5 0.5P – 2 ns 5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high1.5P – 4.5 1.5P – 4.5 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high0.5P – 2.5 0.5P – 2 ns 9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high 1.5P – 4.5 1.5P – 4.5 ns 10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 0.5P – 2.5 0.5P – 2 ns 11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high 1.5P – 4.5 1.5P – 4.5 ns 12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high 0.5P – 2.5 0.5P – 2 ns 13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high1.5P – 4.5 1.5P – 4.5 ns 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high0.5P – 2.5 0.5P – 2 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P – 4.5 1.5P – 4.5 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.5 0.5P – 2 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
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timing requirements for synchronous DRAM cycles (see Figure 18) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 7 tsu(EDV-SDCLKH) Setup time, read EDx valid before SDCLK high 1.8 ns 8 th(SDCLKH-EDV) Hold time, read EDx valid after SDCLK high 3 ns switching characteristics for synchronous DRAM cycles† (see Figure 18–Figure 23) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . PARAMETER MIN MAX MIN MAX UNIT 1 tosu(CEV-SDCLKH) Output setup time, CEx valid before SDCLK high 1.5P – 4 1.5P – 4 ns 2 toh(SDCLKH-CEV) Output hold time, CEx valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns 3 tosu(BEV-SDCLKH) Output setup time, BEx valid before SDCLK high 1.5P – 4 1.5P – 4 ns 4 toh(SDCLKH-BEIV) Output hold time, BEx invalid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns 5 tosu(EAV-SDCLKH) Output setup time, EAx valid before SDCLK high1.5P – 4 1.5P – 4 ns 6 toh(SDCLKH-EAIV) Output hold time, EAx invalid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 9 tosu(SDCAS-SDCLKH) Output setup time, SDCAS valid before SDCLK high 1.5P – 4 1.5P – 4 ns 10 toh(SDCLKH-SDCAS) Output hold time, SDCAS valid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 11 tosu(EDV-SDCLKH) Output setup time, EDx valid before SDCLK high1.5P – 4 1.5P – 4 ns 12 toh(SDCLKH-EDIV) Output hold time, EDx invalid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 13 tosu(SDWE-SDCLKH) Output setup time, SDWE valid before SDCLK high 1.5P – 4 1.5P – 4 ns 14 toh(SDCLKH-SDWE) Output hold time, SDWE valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns 15 tosu(SDA10V-SDCLKH) Output setup time, SDA10 valid before SDCLK high1.5P – 4 1.5P – 4 ns 16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns 17 tosu(SDRAS-SDCLKH) Output setup time, SDRAS valid before SDCLK high 1.5P – 4 1.5P – 4 ns 18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high0.5P – 1.9 0.5P – 1.5 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low.
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Figure 20. SDRAM ACTV Command Figure 21. SDRAM DCAB Command
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† HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1. ¶ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE , SDA10, SDRAS, SDCAS, and SDWE. † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE , SDA10, SDRAS, SDCAS, and SDWE. Figure 24. HOLD/HOLDA Timing
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 RESET TIMING timing requirements for reset (see Figure 25) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 1 tw(RESET) Width of the RESET pulse (PLL stable)† 10 CLKOUT1 cycles1 tw(RESET) Width of the RESET pulse (PLL needs to sync up)‡ 250 ms † This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. ‡ This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 ms to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. switching characteristics during reset§¶ (see Figure 25) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 2 tR(RESET) Response time to change of value in RESET signal 1 CLKOUT1 cycles 3 td(CKO1H-CKO2IV) Delay time, CLKOUT1 high to CLKOUT2 invalid –1 ns 4 td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 valid 10 ns 5 td(CKO1H-SDCLKIV) Delay time, CLKOUT1 high to SDCLK invalid –1 ns 6 td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK valid 10 ns 7 td(CKO1H-SSCKIV) Delay time, CLKOUT1 high to SSCLK invalid –1 ns 8 td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK valid 10 ns 9 td(CKO1H-LOWIV) Delay time, CLKOUT1 high to low group invalid –1 ns 10 td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group valid 10 ns 11 td(CKO1H-HIGHIV) Delay time, CLKOUT1 high to high group invalid –1 ns 12 td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group valid 10 ns 13 td(CKO1H-ZHZ) Delay time, CLKOUT1 high to Z group high impedance –1 ns 14 td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group valid 10 ns § Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HINT. Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE , SDA10, SDRAS, SDCAS, SDWE , HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. ¶ HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group.
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
† Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HINT. SDWE , HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. ‡ HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. Figure 25. Reset Timing
be connected to asynchronous inputs. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. Figure 26. Interrupt Timing
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 1 tsu(SEL-HSTBL) Setup time, select signals§ valid before HSTROBE low 4 ns 2 th(HSTBL-SEL) Hold time, select signals§ valid after HSTROBE low 2 ns 3 tw(HSTBL) Pulse duration, HSTROBE low 2P ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 2P ns 10 tsu(SEL-HASL) Setup time, select signals§ valid before HAS low 4 ns 11 th(HASL-SEL) Hold time, select signals§ valid after HAS low 2 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 3 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 2 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inacti- vated until HRDY is active (low); otherwise, HPI writes will not complete properly. 1 ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § Select signals include: HCNTRL[1:0], HR/W, and HHWIL. switching characteristics during host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 5 td(HCS-HRDY) Delay time, HCS to HRDY¶ 1 12 ns 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 1 12 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 4 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low P – 3 P + 3 ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 12 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 1 12 ns 20 td(HASL-HRDYH) Delay time, HAS low to HRDY high 3 12 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. ||This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 29. HPI Write Timing (HAS Not Used, Tied High) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 30. HPI Write Timing (HAS Used)
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 49POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 31) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 1¶ ns 5 t Setup time external FSR high before CLKR low CLKR int 13 ns5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 4 ns 6 t Hold time external FSR high after CLKR low CLKR int 7 ns6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 4 ns 7 t Setup time DR valid before CLKR low CLKR int 10 ns7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 1 ns 8 t Hold time DR valid after CLKR low CLKR int 4 ns8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4 ns 10 t Setup time external FSX high before CLKX low CLKX int 13 ns10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 4 ns 11 t Hold time external FSX high after CLKX low CLKX int 7 ns11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. § The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the McBSP communicates to is a slave. ¶ The minimum CLKR/X pulse duration is either (P–1) or 9 ns, whichever is larger. For example, when running parts at 167 MHz (P = 6 ns), use 9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P–1) = 11.5 ns as the minimum CLKR/X pulse duration.
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP†‡ (see Figure 31) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNIT MIN MAX 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 3 15 ns 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1# C + 1# ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –4 4 ns 9 t Delay time CLKX high to internal FSX valid CLKX int –4 5 ns9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 16 ns 12 t Disable time, DX high impedance following last data bit fromCLKX int –3 2 ns12 tdis(CKXH-DXHZ) Disable time, DX high im edance following last data bit from CLKX high CLKX ext 2 9 ns 13 t Delay time CLKX high to DX valid CLKX int –2 4 ns13 td(CKXH-DXV) Delay time, CLKX high to DX valid. CLKX ext 3 16 ns 14 t Delay time, FSX high to DX valid. FSX int –2 4 ns14 td(FXH-DXV) Delay time, FSX high to DX valid. ONLY applies when in data delay 0 (XDATDLY = 00b) mode.FSX ext 2 10 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit.
Figure 31. McBSP Timings
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Figure 32. FSR Timing When GSYNC = 1
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 53POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 33) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 – 3P ns 5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 33) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . PARAMETER MASTER § SLAVE UNIT MIN MAX MIN MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ T – 4 T + 4 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# L – 4 L + 4 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid –4 4 3P + 1 5P + 17 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low L – 2 L + 3 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high P + 4 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
† P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 35) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 – 3P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 35) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . PARAMETER MASTER § SLAVE UNIT MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ T – 4 T + 4 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# H – 4 H + 4 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid –4 4 3P + 1 5P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high H – 2 H + 3 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high P + 4 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000
58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 36) NO. ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 – 3P ns 5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 36) NO. PARAMETER ’C6701-120 ’C6701-150 ’C6701-167 UNITNO . PARAMETER MASTER § SLAVE UNIT MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ H – 4 H + 4 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# T – 4 T + 4 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid –4 4 3P + 1 5P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high –2 4 3P + 4 5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L – 2 L + 3 2P + 1 4P + 13 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Figure 37. DMAC Timing † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. Figure 38. Timer Timing
Figure 39. Power-Down Timing
62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Figure 40. JTAG Test-Port Timing
/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0048/C0049 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS067E – MAY 1998 – REVISED MAY 2000 63POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA GJC (S-PBGA-N352) PLASTIC BALL GRID ARRAY 31,75 TYP 0,635 AF AD AB AC Y V W AA AE R T N P L M J K G E F B C A D H U 2622 19 211715 1612 14 1810 Seating Plane 4173506-2/D 07/99 SQ35,20 34,80 SQ33,20 32,80 21,00 NOM See Note EHeat Slug 0,90 0,60 1,00 NOM 0,50 MIN 3,50 MAX 0,635 21,00 NOM 1,27 0,15 1,27 M∅ 0,10 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Thermally enhanced plastic package with heat slug (HSL). D. Flip chip application only E. Possible protrusion in this area, but within 3,50 max package height specification F. Falls within JEDEC MO-151/BAR-2 thermal resistance characteristics (S-PBGA package) NO °C/W Air Flow LFPM† 1 R Q JC Junction-to-case 0.74 N/A 2 R Q JA Junction-to-free air 11.31 0 3 R Q JA Junction-to-free air 9.60 100 4 R Q JA Junction-to-free air 8.34 250 5 R Q JA Junction-to-free air 7.30 500 † LFPM = Linear Feet Per Minute
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