TMS9995

TMS9995NL-12 TI | Alldatasheet

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1. TMS 9995 PIN DESCRIPTION 2 4. TMS 9995 INSTRUCTION SET Pence n eee nent ete e eect neeeneees 3F 4.1 Definition 6... eee eee ee res

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451 Dual Operand Instructions with Multiple Addressing for Source

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4.5.2 Dual Operand Instructions with Multiple Addressing Modes for the Source

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4.6.3 Instruction Execution Times 6 eee tee eeeeeeeeeeeeee 48

Table 1 Dedicated Workspace Registers... cece eee eect ete e eee e neces 6 Table2 Interrupt Level Data... eect eeeeeees 16 Table3 Flag Register Bit Definitions 2... eect eect eee terres 26 Tabled TMS 9995 External Instruction Codes 0... cece eee eee ee eee eeeeseeveese. 26 Table6 Definition of Terminology 0... ooo eee eect e eee ett e eee tt eee e eee 85 Table7 Status Register Bit Definitions eee e eee e este ee tet teeeees 36 Table8 Execution Sequence Example 0... coe c cece cece cette eect tee eeeseeeeeses 48 TableQ Instruction Execution Times... cece eee cece eee e eee eeeeeeeeeeeeess 50 Table 10 Operation Address Derivation 02.2000. e eect eect eee eeeteteeneeees 52 Table 11 Instruction Execution Time Examples... eee eee cece cece eset eeeeeeees 58 v

1. INTRODUCTION

11 DESCRIPTION

The TMS 9995 microcomputer is a single-chip 16-bit central processing unit (CPU) with 256 bytes of on-chip random access memory (RAM). A member of the TMS 9900 family of microprocessor and peripheral circuits, the TMS 9995 is fabricated using N-channel silicon-gate MOS technology. The rich instruction set of the TMS 9995 is based upon a unique memory-to-memory architecture that features multiple register files resident in memory. Memory-resident register files allow faster response to interrupts and increased programming flexibility. The inclu- sion of RAM, timer function, clock generator, interrupt interface, and a flexible flag register on-chip facilitates support of small system implementations. All members of the TMS 9900 family of peripheral circuits are compatible with the TMS 9995. Providing a per- formance upgrade to the TMS 9900 microprocessor, the TMS 9995 instruction set is an opcode-compatible super- set of the TMS 9900 processor family. 12 KEY FEATURES. © 16:Bit instruction word © Memory-to-Memory architecture © 65,536 byte/32,768 word directly addressable memory address space © — Minicomputer instruction set including signed multiply and divide instructions © — Multiple 16-word register files (Workspaces) residing in memory © 256 bytes of on-chip RAM =~ Separate memory and interrupt bus structures © 8-Bit memory data bus © 7 prioritized hardware interrupts © 16 software interrupts (XOPS) @ =~ Programmed and DMA I/O capability © Serial 1/0 via communication register unit (CRU) © On-chip time/event counter © On-chip programmable flags (16) © — Macro instruction detection (MID) feature © — Automatic first wait state generation feature © Single 5-volt supply © — 40-pin package © N-Channel silicon gate MOS technology ® On-chip clock generator 2. ARCHITECTURE

21 MEMORY ALLOCATION

The basic word of the TMS 9995 architecture is 16 bits in length. These 16 bits are divided into 8-bit bytes for external memory in the manner shown in Figure 1. A word is, therefore, defined as two consecutive 8-bit bytes in memory. All words (instruction opcodes, operand addresses, word-length data, etc.) are restricted to even address boundaries, i.e., the most significant half, or 8 bits, resides at an even address and the least significant half resides at the subsequent odd address. Any memory access involving a full word that is directed by software to utilize an odd address will result in the word starting with this odd address minus one to be accessed.

EVEN ADORESS + 1) ise ms on SIGN ar se FIGURE 1 — WORD AND BYTE FORMATS The instruction set of the TMS 9995 allows both word and byte operations, Byte instructions may address either byte as necessary, A byte access of this type will not affect the other byte of the word involved since the other byte will not be accessed during the execution of the byte instruction. The TMS 9995 memory map is shown in Figure 2. Shown are the locations in the memory address space for the Reset, NMI, other interrupt and XOP trap vectors, and the dedicated address segments for the on-chip RAM and the on-chip memory-mapped 1/O. od no Lee a eves meses eo [———} i. a cos Fd irermuer wor Fd oe =f exrennat Cs ee] con [Od one wos [hf ™ oes oe ES wef veers om PS +00 Bis Linc: INTERNAL (ow.

1 INTERNAL ar ‘CHIP MEMORY

wren (7 Leal inteawar[ ADORESS SPACE ree CT Aye fp ves LOZZAS 3D NOTE: Addresses are byte addresses in hex FIGURE 2 — TMS9995 MEMORY MAP

2.2 TMS 9995 ORGANIZATION

The block diagram of the TMS 9995 is shown in Figure 3, A flow chart, representative of the TMS 9995 functional operation, is shown in Figure 4. : < rr 0007 [= Err > 7 feet oan 1 1AQ/HOLDA Loaic nd cLocKk XTAL2/CLKIN FIGURE 3 — TMS9995 BLOCK DIAGRAM

IE — 9» ner

2.2.1 Arithmetic Logic Unit

The arithmetic logic unit (ALU) is the computational component of the TMS 9996. It performs all arithmetic and logic functions required to execute instructions. The functions include addition, subtraction, AND, OR, exclusive OR, and complement. A separate comparison circuit performs the logic and arithmetic comparisons to control bits 0 through 2 of the status register. The ALU is arranged in two 8-bit halves to accommodate byte operations. Each half of the ALU operates on one byte of the operand. During word operand operations, both halves of the ALU function in conjunction with each other. However, during byte operand processing, results from the least significant half of the ALU are ignored. The most-significant half of the ALU performs all operations on byte operands so that the status circuitry used in word operations is also used in byte operations

2.2.2 Internal Registers

The following three (3) internal registers are accessible to the user (programmer): © Program Counter (PC) . Status Register (ST) @ ~~ Workspace Pointer (WP)

2.2.2.1 Program Counter

The program counter (PC) is a 15-bit counter that contains the word address of the next instruction following the instruction currently executing, The microprocessor references this address to fetch the next instruction from memory and increments the address in the PC when the new instruction is executing. If the current instruction in the microprocessor alters the contents of PC, then a program branch occurs to the location specified by the altered affect the contents of PC.

2.2.2.2 Status Register

The status register (ST) is a fully implemented 16-bit register that reports the results of program comparisons, indi- cates program status conditions, and supplies the arithmetic overflow enable and interrupt mask level to the inter- rupt priority circuits. Each bit position in the register signifies a particular function or condition that exists in the microprocessor. Figure 5 illustrates the bit position assignments. Some instructions use the status register to check for a prerequisite condition; others affect the values of the bits in the register; and others load the entire status register with a new set of parameters. Interrupts also modify the status register. The description of the instruction set later in this document details the effect of each instruction on the status register (see Section 3). ° 1 2 3 4 5 6 7 8 8 10 1" 12 13 445 sto | st» | st2 | st3 | sta | sts | ste | stz | sts | sto | stio | stra | STI2 | stt3 | stra | sis > . ‘ : . ov . v * Fo © ov | oF * eNt INTERRUPT MASK *ST7, STB, STS, and $T11 are not used in the TMS9995, but still physically exist in the register. These bits could therefore be used as flag bits, but software transportability should be kept in mind when doing so as these bits are defined in other 9900 microprocessor family and 990 minicomputer family products, * Do not allow the overflow Interrupt Enable bit (ST10 OV EN) to be set to 1 as the arithmetic overflow is not functional on current devices, This will be corrected at a later date. Le Logical Greater Than c Carry Our x XOP In Progress A> Arithmetic Greater Than ov Overtiow OVEN Overtiow Interrupt Enable EQ Equal/TB Indicator oP Parity (Odd No. of Bits) FIGURE 5 ~ STATUS REGISTER BIT ASSIGNMENTS

2.2.2.3 Workspace

The TMS 9995 uses blocks of memory words called workspaces for instruction operand manipulation. A work- space occupies 16 contiguous words in any part of memory that is not reserved for other use. The individual workspace registers may contain data or address, or function as operand registers, accumulators, address registers, or index registers. Some workspace registers take on special significance during execution of certain instructions. Table 1 lists each of these dedicated workspace registers and the instructions that use them. Figure 6 defines the workspace registers that are allowed to be used as index registers.

: TABLE 1 — DEDICATED WORKSPACE REGISTERS ———. i REGISTER NO. CONTENTS USED DURING o Shift count (optional) Shift instructions (SLA, SRA, SRC, and SLC) Multiplicand and MSW Signed Multiply of result MSW of dividend and Signed Divide quotient 1 | ESW of rout Signed Multiply | LSW of dividend and Signed Divide remainder " Return Address Branch and Link Instruction (BL) Effective Address Extended Operation (XOP)

12 CRU Base Address CRU instructions (SBO, SBZ, TB,

LOCR, and STCR) | 13 Saved WP register Context switching (BLWP, TWP, XOP, interrupts)

14 Saved PC register Context switching (BLWP, RTWP,

XOP, interrupts)

15 Saved ST register Context switching (BLWP, TWP,

XOP, interrupts) WORKSPACE REGISTERS. [sti DATA cn _ —_— [| Iwoex po NOTE: The WP register contains the address of workspace register zero. FIGURE 6 ~ WORKSPACE REGISTERS USABLE AS INDEX REGISTERS

2.2.2.3.1 Workspace Pointer

To locate the workspace in memory, a hardware register called the workspace pointer (WP) is used. The workspace pointer is a 16-bit register that contains the memory address of the first word in the workspace. The address is leftjustified with the 16th bit (LSB) hardwired to logic zero. The TMS 9995 accesses each register in the work- space by adding twice the register number to the contents of the workspace pointer and initiating a memory re- quest for that word. Figure 7 illustrates the relationship between the workspace pointer and its corresponding workspace in memory WORKSPACE POINTER WORKSPACE WORKSPACE (we) ADDRESS REGISTERS erg | | werone ne | 2 | MICROPROCESSOR ADDS WORKSPACE POINTER REGISTER NUMBER TO DERIVE ACTUAL + —_——- wees —_ wee tns as wee — wrenene — | | FIGURE 7 — WORKSPACE POINTER AND REGISTERS For instructions performing byte operations, use of the workspace register addressing mode (see Section 3.2) will result in the most significant byte of the workspace register involved to be used as the operand for the operation. Since the workspace is also addressable as a memory address, the least significant byte may be directly addressed using any one of the general memory addressing modes. The workspace concept is particularly valuable during operations that require a context switch, which is a change from one program environment to another, as in the case of a subroutine or an interrupt service routine. Such an operation using a conventional multi-register arrangement requires that at least part of the contents of the register

file be stored and reloaded using a memory cycle to store or fetch each word. The TMS 9995 accomplishes this operation by changing the workspace pointer. A context switch requires only three store cycles and two fetch cycles, exchanging the program counter, status register and workspace pointer. After the switch, the workspace pointer contains the starting address of a new 16-word workspace in memory for use in the new routine. A corre- sponding time saving occurs when the original context is restored. Instructions in the TMS 9995 that result in a context switch include: Call subroutine (BLWP), Return from Subroutine (RTWP) and the Extended Operation (XOP) instruction. All interrupts also cause a context switch by forcing the TMS 9995 to trap to a service sub- routine.

2.3 TMS 9995 INTERFACES

Each TMS 9995 system interface uses one or more of the signals from one or more of the signal groupings given in the pin description list in Section 3. Each interface is described in detail in the following paragraphs.

2.3.1 TMS 9995 Memory Interface

The signals used in the TMS 9995 interface to system memory are shown in Figure 8. A0-A14, A18/CRUOUT MEMORY SYSTEM AND/OR DMA WE/CRUCLK EAD IAQ/HOLDA AND LAQ/HOLDA REQUIRED FOR SIMPLE MEMORY HOLD SYSTEMS BUT WILL BE USED BY DMA CONTROLLERS FIGURE 8 ~ TMS9995 MEMORY INTERFACE

23.1.1 External Memory Address Space

The details of memory accesses that are external to the TMS 9995 (off-chip accesses) are given in the following paragraphs. (See Figure 2 for the addresses that are in the external memory-address space.)

2.3.1.1.1 Memory Read Operations

To perform a memory read operation, the TMS 9995 first outputs the appropriate address on AO-A14 and A15/ CRUOUT, and asserts MEMEN. The TMS 9995 then places its data bus drivers in the high impedance state, asserts DBIN, and then reads in the data byte. Completion of the memory read cycle and/or generation of Wait states is determined by the READY input as detailed in Section 2.3.1.3. Timing relationships of the memory read sequence are shown in Figure 9. Note that MEMEN remains active (low) between consecutive memory operations.

the least-significant (odd) byte. Figure 9. Note that since an instruction opcode is a word in length, |AQ/HOLDA remains asserted between the two byte read operations involved when an instruction opcode is read from the external memory address space.

2.3.1.1.2 Memory Write Operations

sequence are shown in Figure 10, Note that MEMEN remains active (low) between consecutive memory operations.

cLKouT { ll d l ate | I i 1 | ewe SR a | | ] | i | rr | iT" iT" WE/CRUCL | | ] a | l | \\AQIHOLDA {9} ! | MEMORY WRITE MEMORY WRITE Notes NO WAIT STATE ONE WAIT STATE © Varia asaress Valid memory write deta 1AQ/HOLDA will never be asserted during a memory write cycle FIGURE 10 — TMS9995 MEMORY WRITE CYCLE Writing a word (two 8-bit bytes) to external memory requires two memory write cycles that occur back-to-back. {A Hold state request will not be granted between cycles.) If an instruction directs that a byte write to external memory is to be performed, only the byte specifically addressed will be written (one memory write cycle). External words are accessed most-significant (even) byte first followed by the least-significant (odd) byte.

2.3.1.1.3 Direct Memory Access

The TMS 9995 Hold state allows both external devices and the TMS 9995 to share a common external memory. To gain direct memory access (DMA) to the common memory, the external device first requests the TMS 9995 to enter a Hold state by asserting (taking low) the HOLD input. The TMS 9995 will then enter a Hold state following completion of the cycle (either memory, CRU, external Instruction, or internal ALU cycles) that it is currently performing. Note, however, that a Hold state is not entered between the first and second byte accesses of a full word in the external memory address space, and a Hold state is not entered between the first and second clock cycles of a CRU cycle. Upon entry of a Hold state, the TMS 9995 puts its address, data, DBIN, and WE/CRUCLK drivers in the high impedance mode, and asserts |AQ/HOLDA. The external device can then utilize these signal lines to communicate with the common memory. After the external device has completed its memory transactions, it releases HOLD, and the TMS 9995 continues instruction execution at the point where it had been suspended, Timing relationships for this sequence are shown in Figure 11.

|ctxour cvctes} ‘LKOUT 1 a t rT I~ | | i | | -L-J ooo co) $2 E rT 1 | i a 1 a i 1 1 i} i am OR es i 1 1 __—t | . 1 \\ —_—e ig | UO) I i] T | i ee © crete betore the hold state could have been memory (with any number of wait states), CRU, external instruction, or internal ALU @ FOLD must de valid at test tow-to-high CLKOUT transition of a cycle for next low-to:high CLKOUT transition to begin a hold ©® In high-impedance made (ourput drivers) ® Noxt cycle will begin after first low-to:high CLKOUT transition at which HOLD is high FIGURE 11 — TMS9995 HOLD STATE To allow DMA loading of external memory on power-up, the TMS 9995 does not begin instruction execution after a Reset state until HOLD has been removed if HOLD was active (low) at the time RESET was taken from low to high RESET released). External devices cannot access the internal (on-chip) memory address space of the TMS 9995 when it is in the Hold state. Since 1AQ (Instruction Opcode Acquisition) and HOLDA (Hold Acknowledge) are multiplexed on a single signal, IAQ/HOLDA, this signal must be gated with MEMEN using external logic to separate 1!AQ and HOLDA. When MEMEN = 0, |AQ/HOLDA can indicate |AQ, and when MEMEN = 1, 1{AQ/HOLDA can indicate HOLDA.

2.3.1.2 Internal Memory Address Space

Access of the internal (on-chip) memory address space is transparent to the TMS 9998 instruction set. That is, operands can be read from and written into locations in the internal memory space simply by using the appro- priate addresses via any of the addressing modes in the TMS 9995 instruction set, and instructions can even be executed from the internal memory space by loading the appropriate address into the program counter of the TMS 9995. WwW

The TMS 9995 indicates to the external world when these internal memory address space accesses are occurring by asserting the same signals used for accessing external memory (see Figure 8) in a manner very similar to an ex- ternal memory address space access. There are a few differences in these cycles, however, and these differences are detailed in the following paragraphs. When performing an internal memory address space access, the TMS 9995 outputs the same signals that it would for an external memory space access, with the same timing (see Figures 9 and 10) except for the following: (1) A single cycle (read or write) is output as both internal bytes are accessed simultaneously. (Externally, it appears as though a single byte memory access cycle to an internal address is occurring.) (2) The cycle always has no Wait states, and the READY input is ignored by the TMS 9995 (see Section 2.3.2.3). (3) During read cycles, the data bus (D0-D7) output drivers are put in the high-impedance mode. During write cycles, the data bus outputs non-specific data, During read cycles to the internal memory address space, the TMS 9995 does not make the read data available to the external world. If an instruction is executed from the internal memory address space, |AQ/HOLDA is still asserted, but only during the one read cycle shown externally while the full word is read internally. When in a Hold state, external devices are not able to access the internal memory address space. The 256 bytes of internal random-access read/write memory (RAM), the memory addresses of which are shown in Figure 2, are organized internally as 128 16-bit words. Since the TMS 9995 has 16-bit interna! data paths, two. 8-bit bytes are accessed each time a memory access is made to the internal RAM. Byte accesses are transparent to the internal RAM. That is, when an instruction addresses a byte in the internal RAM, the TMS 9995 will: (1) read the entire word but only use the byte specifically addressed for a read opera- tion and, (2) only write to the specifically addressed byte and not alter the contents of the other byte in the word during a write operation.

2.3.1.2.2 Decrementer (Timer/Event Counter)

Accessible via one of the word addresses (see Figure 2) of the internal memory-mapped I/O address space is the de- crementer. The on-chip decrementer logic can function as a programmable real-time clock, an event timer, or as an external event counter. A block diagram of the decrementer that is representative of its functional operation (but not necessarily representative of its specific logic implementation) is shown in Figure 12. Tb D = 0 a Whit. St=D unto our | > TOUT OF eye soar imrennat eaves ‘REQUEST LATCH DATA PATH NOTE: FLAGO and FLAGI are bits in the Flag Reghiter FIGURE 12 — DECREMENTER FUNCTIONAL BLOCK DIAGRAM

The decrementer is configured as either a timer or an event counter using bit FLAGO of the internal Flag register. tails of the Flag register and accessing the bits in it.) When FLAGO is set to zero, the decrementer will function as a timer. When FLAGO is set to one, the decrementer will function as an event counter. When FLAG1 is set to zero, the decrementer is disabled and will not be allowed to decrement and request level 3 interrupt traps. When FLAG1 is set to one, the decrementer is enabled and will decrement and request level 3 interrupt traps. It should be noted that when the decrementer is configured as a timer, INT4/EC will_be usable as an external interrupt level 4 trap request. When the decrementer is configured as an event counter, INT4/EC is the input for the “event counter” pulses, and an interrupt level 4 trap request input is no longer available externally or internally. The general operation of the decrementer is as follows. FLAGO of the Flag register is first set to select the desired mode of operation. The desired start count is then loaded into the Starting Count Storage Register by performing a memory write of the count word to the dedicated internal memory mapped 1/O address of the decrementer. (This also loads the Decrementing Register with the same count.) The decrementer is then enabled and allowed to start decrementing by setting FLAG1 of the Flag Register to one. (Both FLAGO and FLAG1 are set to zero when level 3 internal interrupt request latch is set (see Section 2.3.2.2.3), the Decrementing Register is reloaded from the Starting Count Storage Register, and decrementing continues. Note that writing a start count of 00004g to the decrementer will disable it. When configured as a timer, the decrementer functions as a programmable real-time clock by decreasing the count in the Decrementing Register by one for each fourth CLKOUT cycle. Loading the decrementer with the appro- priate start count causes an interrupt to be requested every time the count in the Decrementing Register reaches zero. The decrementer can also be used as an event timer when configured as a timer by reading the decrementer (which is accomplished by performing a memory read from the dedicated internal memory mapped I/O address of the decrementer) at the start and stop points of the event of interest and comparing the two values. The dif ference will be a measurement of the elapsed time. When configured as an event counter, operation is as previously discussed except that each high-to-low transition on INT4/EC will cause the Decrementing Register_to decrement. These INT4/EC high-to-low transitions can be asynchronous with respect to CLKOUT. Note that INT4/EC can function as a negative edge-triggered interrupt by loading a start count of one. The decrementer should always be accessed as a full word (two 8-bit bytes). Reading a byte from the decrementer does not present a problem since only the byte specifically addressed will be read. Writing a single byte to either of the bytes of the decrementer will result in the data byte being written into the byte specifically addressed and random bits being written into the other byte of the decrementer.

23.1.3 Wait State Generation

Wait states can be generated for external memory cycles, external CRU cycles and external instruction cycles for the TMS 9995 using the READY input. A Wait state is defined as extension of the present cycle by one CLKOUT cycle. The timing relationships of the READY input to the memory interface and the CRU interface signals are shown in Figure 13, Note that Wait states cannot be generated for memory cycles that access the internal memory address space or for CRU cycles that access the internal CRU address space, as the READY input will be ignored during these cycles. The Automatic First Wait State Generation feature of the TMS 9995 allows a Wait state to be inserted in each ex- ternal memory cycle, regardless of the READY input, as shown in Figure 13. The Automatic First Wait State Generation feature can be invoked when RESET is asserted. If READY is active (high) when RESET goes through a low-to-high transition, the first Wait state in each external memory cycle will be automatically generated. If READY is inactive (low) when RESET goes through a low-to-high transition, no Wait state will be inserted auto- matically in each external memory cycle. There is a one and one-half CLKOUT cycle time minimum setup time requirementon READY before the RESET low-to-high transition. The recommended external circuitry for invoking or inhibiting the Automatic First Wait State Generation feature is shown in Figure 14, Note that this feature does not apply to internal memory address space accesses, external instruction cycles, or any CRU cycles. Wait states cannot be generated during internal ALU/other operation cycles. The READY input is ignored during these cycles.

2.3.2. TMS 9995 Interrupts The TMS 9995 implements seven prioritized, vectored interrupts, some of which are dedicated to predefined func- tions and the remaining are user-definable. Table 2 defines the source (internal or external), assignment, priority level, trap vector location in memory, and enabling/resulting status register interrupt mask values for each interrupt. TABLE 2— INTERRUPT LEVEL DATA VECTOR MASK VALUES. MASK Va PRIORITY LOCATION TO ENABLE AMER vain SOURCE AND LEVELS (Memory ACCEPTING THE INTERRUPT ASSIGNMENT (in Order of Priority) Address, ‘THE INTERRUPT (eri minuets) In Hex) (S12 THRU ST15) 0 04g thru F External: R . 0000 16 te w16 0000 —aternal: Reset (Highest Priority) (see Note 1) (RESET signal)

008 O16 thru F4g 0001

| om | (see Note 2) (see Note 1) (see Note 2) {overnal: MID External:_User- O46 thru F _Use FFFC 16 thre P16 0000 defined (NM (see Note 1) Signal) External: User- 0004 tig thru Fig 0000 defined (NTT Signal) > 008 24g thru Fag 0001 Internal (see Note §) (see Note 2) (see Note 3) (see Note 2) Arithmetic Overflow Internal oooc 34 thru F 002 P| om | or External: User- 0010 446 thru Fag defined (INTA/EC Signal; see Note 4). NOTES: 1. Level 0, MID, and NMI cannot be disabled with the interrupt Mask. 2. MID and Leve! 2 use the same trap vector and change the Interrupt Mask to the same value, 3. Generation of a Level 2 request by an Arithmetic Overflow condition (ST4 set to 1) is also enabled/disablad by bit ST10 of the Status Resister 4, INTA/EC is not on input for Level 4 interrupt trap requests (Level 4 is not usable) when the Decrementer is configured as an Event Counter. 5. Priority Level 2 Internal Arithmetic Overtlow should not be used as the arithmetic overflow is not functional on current devices, This will be corrected at a later dete. The TMS 9995 will grant interrupt requests only between instructions (except for Level 0 Reset), which will be granted whenever it is requested, i.e., in the middle of an instruction). The TMS 9995 performs additional func- tions for certain interrupts, and these functions will be detailed in subsequent sections. The basic sequence that the TMS 9995 performs to service all interrupt requests is as follows: (1) Prioritize all pending requests and grant the request for the highest priority interrupt that is not masked by the current value of the interrupt mask in the status register or the instruction that has just been executed. (See Section 4.5 for these instructions.) (2) Make a context switch using the trap vector specified for the interrupt being granted. (3) Reset ST7 through ST11 in the status register to zero, and change the interrupt mask (ST12 through ST15) as appropriate for the level of the interrupt being granted. (4) Resume execution with the instruction located at the new address contained in the PC, and using the new WP. All interrupts will be disabled until after this first instruction is executed, unless: (a) RESET is requested, in which case it will be granted, or (b) the interrupt being granted is the MID request and the NMI interrupt is requested simultaneously (in which case the NMI request will be granted before the first instruction indicated by the MID trap vector is executed.)

This sequence has several important characteristics. First of all, for those interrupts that are maskable with the interrupt mask in the status register, the mask will get changed to a value that will permit only interrupts of higher priority to interrupt their service routines. Secondly, status bit ST10 (overflow interrupt enable) is reset to zero by the servicing of any interrupt so that overflow interrupt requests cannot be generated by an unrelated program segment. Thirdly, the disabling of other interrupts until after the first instruction of the service routine is executed permits the routine to disable other interrupts by changing the interrupt mask with the first instruction. (The ex- TMS 9995 permits interrupts to be automatically nested in most cases. If a higher priority interrupt occurs while in an interrupt service routine, a second context switch occurs to service the higher priority interrupt. When that routine is complete, a return instruction (RTWP) restores the saved context to complete processing of the lower priority interrupt. Interrupt routines should, therefore, terminate with the return instruction to restore original program parameters. Additional details of the TMS 9995 interrupts are supplied in the following paragraphs.

23.2.1 External Interrupt Requests

Each of these interrupts is requested when the designated signal is supplied to the TMS 9995.

2.3.2.1.1 Interrupt Level 0 (RESET)

Interrupt Level 0 is dedicated to the RESET input of the TMS 9995. When active (low), RESET causes the TMS 9995 to stop instruction execution and to inhibit (take to logic level high) MEMEN, DBIN, and WE/CRUCLK. The TMS 9995 will remain in this Reset state as long as RESET is active. When RESET is released (low-to-high transition), the TMS 9995 performs a context switch with the Level 0 inter- rupt trap vector (WP and PC of trap vector are in memory word addresses 000016 and 000216, respectively.) Note that the old WP, PC and ST are stored in registers 13, 14, and 15 of the new workspace. The TMS 9995 then of these latches), Flag Register bits FLAGO and FLAG1 (see Section 2.3.3.2.1 for details of the Flag Register), If HOLDA is active (high) due to HOLD being active (low) when RESET becomes active, RESET will cause HOLDA to be released (taken low) at the same time as MEMEN, OBIN, and WE/CRUCLK are taken inactive (high). HOLD can remain active as long as RESET is active and HOLDA will not be asserted. If HOLD is active when RESET is released (low-to-high transition), HOLDA will be asserted before the RESET context switch occurs and the TMS 9995 will remain in this hold state until HOLD is released. This RESET and HOLD priority scheme facilitates DMA loading of external RAM upon power-up. Timing relationships of the RESET signal are shown in Figure 15. Release of the RESET signal is also the time at which the Automatic First Wait State function of the TMS 9995 can be invoked (see Section 2.3.1.3)

and its associated interrupt level are named “LOAD” in previous 9900 family products. Table 2. Note that the TMS 9995 will always grant a request for the NMI level interrupt immediately after execu- execution characteristic of certain instructions and also the current value of the interrupt mask.

2.3.2.2 Internally Generated Interrupts

Each of these interrupts is requested when the designated condition has occurred in the TMS 9995.

2.3.2.2.1 Macro Instruction Detection (MID) Interrupt

after encountering an MID opcode. code in future processors and software will then be directly transportable to these future processors. Reset is a complete initialization of the system. flow interrupt ST10 should not be enabled, This will be corrected at a later date. Table 7. for those conditions that set ST4 to one), can cause the Level 2 interrupt to be requested. Note that this location, and enabling/resulting status register interrupt mask values as defined in Table 2.

It should also be noted that the Level 2 arithmetic overflow interrupt shares its trap vector with the MID inter- the cause of the interrupt. The occurrence of an interrupt request by the decrementer (see Section 2.3.1.2.2) will cause the Level 3 internal interrupt request latch to get set. This latch is similar to those for Levels 1 and 4 in that it is reset by servicing a Reset interrupt or when the context switch for its associated interrupt level occurs (Figure 17). The Level 3 internal interrupt request latch being set constitutes a request for a Level 3 interrupt, and the TMS 9995 services this request exactly according to the basic sequence previously described with the priority level, trap vector location, and enabling/resulting status register interrupt mask values as defined in Table 2.

2.3.3 Communication Register Unit Interface

The TMS 9995 accomplishes bit 1/O of varying field width through the use of the Communications Register Unit (CRU). In applications demanding 2 bit-oriented 1/0 interface, the CRU performs its most valuable act: transferring @ specified number of bits to or from memory and a designated device. Thus, the CRU is simply a linking mechanism between memory and peripherals. Acting as a shift register, the CRU is a separate hardware structure of the TMS 9995 microprocessor. This structure can serially transfer up to 16 bits of data between the CPU and a specified device in a single operation. The 32768-bit CRU address space may be divided into any combination of devices, each containing any number of input or output bits. When given the bit address of a device, the CRU can test or modify any bit in that unit. Several consecutive addresses can be occupied by a device. These CRU applications are controlled by single and multiple-bit 9995 instructions. Single-bit instructions facilitate the testing or modification of a particular bit in a device. The device in which a bit is to be tested (TB), set to zero (SBZ), or set to one (SBO) is designated by the sum of the value in Register 12 and an 8-bit signed displacement value included as an operand of that instruction. Details of these instructions are given in Section 4.5.7. Multiple-bit instructions control the serial transfer of up to 16 bits between memory and peripherals. The device with which communication is to take place is addressed by Register 12, The memory address to or from which data is to be transferred, as well as the number of bits to be transferred are included as operands of the multiple- bit instruction. Details of these instructions are given in Section 4.5.6. The signals used in the TMS 9995 interface to the CRU are shown in Figure 18. The CRU address map is shown in Figure 19. [eee | [ee wore FIGURE 18 — TMS9995 CRU INTERFACE

GENERAL Use EXTERNAL (OFF CRU ADDRESS cuir cru SPACE ADDRESS SPACE 1e08 -e eee 1ee0 FLAGO vee FLacy lees FLaGe rete FLAaG3 rece FLaGa teen FLAGS eee FLAGe 1e8e FLAG? rung INTERNAL (ON.

1 Hip) cRU

1eP0 FLAGE REGISTER ADDRESS SPACE tere FLAGS rere FLAGA reF6 FLace tere Face era FLAGD tere FLAGE FLAGE rere i ane 1600 GENERAL USE EXTERNAL (OFF. CRU ADDRESS cle) cA space ADDRESS SPACE a Ste nnat (on 1A morse > Sirens pp = = 2 ones space Foe GENERAL USE EXTERNAL (OFF chu aDORESS Hip) cau SPACE ADDRESS SPACE rere NOTE: These hex addresses are the software base addresses and are obtained by placing the 15-bit Address Bus CRU bit address in a 16-bit field, left justifying the 15 bits in the field, and setting the LSB of the field to zero, FIGURE 19 — CRU ADDRESS MAP The concept of “CRU space” is the key to CRU operations. An ideological area exists in which peripheral devices reside in the form of an address. The CRU space is this ideological area; it has monotonically increasing bit addresses. Each bit represents a bistable I/O point which can be read from or written to. CRU address space and memory address space are independent of each other. Memory space is byte-addressable, and CRU space is bit addressable. Therefore, a desired device is accessed by placing its software base address in Register 12 and exercis- ing the CRU commands. CRU nomenclature is built around the four address types involved in its operation. The software base address, hardware base address, address displacement, and CRU bit address interact to link memory to peripherals in bit-serial communication via the CRU. The software base address consists of the entire 16 bits of R12. In R12, the programmer loads twice the value of the CRU hardware address of the device with which he wishes to communicate. Because only bits 0 through 14 of Register 12 are placed on the address bus, the programmer needs to shift the hardware base address left one Position (equivalent to multiplying by two). Bits 0 through 14 of Register 12 form the hardware base address. For the single-bit instructions, the hardware base address is added to the address displacement to obtain the CRU bit address, For multiple-bit instructions the hardware base address is the CRU bit address.

2.3.3.1 External CRU Devices

To input a data bit from an external (off-chip) CRU device, the TMS 9995 first outputs the appropriate address on A0-A14, The TMS 9995 leaves MEMEN high, outputs logic zeroes on DO-D2, strobes DBIN, and reads in the data bit on CRUIN. Completion of each CRU input cycle and/or generation of Wait states is determined by the READY wow SUL SUU UL SLL ‘ tt ' ut i ! it coor =-X® LX =-Xo i LYE: =Xo on i i i it it H i H it H it Mm H i om LIX i Ly LIT i \\ TNX ' 7 in 7! v4 in 4 H i i Ha i H in H rm { i it ! i ' ut ' tt Lt H ia ' Ma H vy +: H ¥) Notes cmv neu, @ vetia address successive irs, ® 10-07 each ourput logic zero © Non-specific output bit @® CAU input bit must be valid on CRUIN at CLKOUT edge indicated FIGURE 20 — TMS9995 CRU INPUT CYCLE To output a data bit to an external (off-chip) CRU device, the TMS 9995 first outputs the appropriate address on A0-A14, The TMS 9995 leaves MEMEN high, outputs logic zeroes on DO-D2, outputs the data bit on A15/ CRUOUT, and strobes WE/CRUCLK. Completion of each CRU output cycle and/or generation of Wait states is determined by the READY input as detailed in Section 2.3.1.3, Timing relationships of the CRU output cycle are . shown in Figure 21. For multiple-bit transfers, these input and output cycles are repeated until transfer of the entire field of data bits specified by the CRU instruction being executed has been accomplished.

y 1 t y ‘ 1 ‘ voor Xo A on “Xo ' D =Xo D ' ' ' ! : ' ' H ! i i ' t { om iY ' i \\ \\ "\\ t : i \\ H i j in ' ' 1 1 1 ' A @ i a) ! ! aC) I ——~ ee ee —a a Notes Nt @® vatia address cau ourPur, ® 00-07 each output tosic zero NO WAITS @ Valid CAU output bit for address being output ® Don't care FIGURE 21 — TMS9995 CRU OUTPUT CYCLE

2.3.3.1.1 Single-Bit CRU Operations

The TMS 9995 performs three single-bit CRU functions: Test Bit (TB), Set Bit to One (SBO), and Set Bit to Zero (SBZ). The SBO instruction performs a CRU output cycle with logic one for the data bit, and the SBZ instruction performs a CRU output cycle with logic zero for the data bit. A TB instruction transfers the addressed CRU bit from the CRUIN input line to bit 2 of the status register (bit ST2, the EQUAL bit) The TMS 9995 develops a CRU bit address for the single-bit operations from the CRU base address contained in workspace register 12 and the signed displacement count contained in bits 8 through 15 of the instruction. The dis- placement allows two’s complement addressing from base minus 128 bits through base plus 127 bits. The base address from WR12 is added to the signed displacement specified in the instruction and the result is placed onto the address bus. Figure 22 illustrates the development of a single-bit CRU address.

MSB O 1 2 3 4 5 6 7 8 9 10 Ww 12 13 14 15 LSB LITTTTTTTTTIIIT[ QW wars t i 8 9 10 W 12 13, 14 15 H

1 SIGNED

i 1 2 3 4 5 6 7 8 9 10 W 12 13 14 ! CITTTTITIIIILIIL1 mponess BUS EFFECTIVE CRU BIT ADDRESS FIGURE 22 — SINGLE BIT CRU ADDRESS DEVELOPMENT

2.3.3.1.2 Multiple Bit CRU Operations

The TMS 9995 performs two muitiple-bit CRU operations: store communications register (STCR) and load com- munications register (LDCR), Both operations perform a data transfer from the CRU-to-memory or from memory- to-CRU as illustrated in Figure 23, Although the figure illustrates a full 16-bit transfer operation, any number of bits from 1 through 16 may be involved. CRU INPUT BITS CRU OUTPUT BITS N 1 N NH t es OUTPUT (LDCR) ! N+14 N+15, | N+15 N BIT SPECIFIED BY CRU BASE REGISTER (WR12) FIGURE 23 — LDCR/STCR DATA TRANSFERS

The LDCR instruction fetches a word from memory and right shifts it to serially transfer it to CRU output bits. If the LDCR involves eight or fewer bits, those bits come from the right-justified field within the addressed byte of the memory word. If the LDCR involves nine or more bits, those bits come from the right-justified field within the whole memory word. Register 12, bits 0 through 14, defines the starting bit address. When transferred to the CRU interface, each successive bit receives an address that is sequentially greater than the address for the previous bit. This addressing mechanism results in an order reversal of the bits; that is, bit 15 of the memory word (or bit 7) becomes the lowest addressed bit in the CRU and bit 0 becomes the highest bit in the CRU field, A STCR instruction transfers data from the CRU to memory. If the operation involves a byte or less transfer, the transferred data will be stored right-justified in the memory byte with leading bits set to zero. If the operation in- volves from nine to 16 bits, the transferred data is stored right-justified in the memory word with leading bits set to zero. When the input from the CRU device is complete, the lowest addressed bit from the CRU is in the least- significant bit position in the memory word or byte.

2.3.3.2 Internal CRU Devices

Access of internal (on-chip) CRU devices is transparent to the TMS 9995 CRU instructions. Data can be input from and output to the bits of the internal CRU devices simply by using the appropriate CRU addresses to access these bits. The TMS 9995 will indicate to the external world when these internal CRU bit accesses are occurring by asserting the same signals used for accessing external CRU devices (see Figure 18). The timing of these signals for internal CRU input and output cycles will be identical to the timing for external CRU input and output cycles (see Figure 20 and 21) except that during internal CRU cycles, the READY input is ignored, i.e., Wait states cannot be generated, and, during internal CRU input cycles, the TMS 9995 will ignore the CRUIN input signal. The internal bit being input will not be available to the external world on CRUIN. The functional characteristics of the internal CRU devices are described in the following paragraphs.

2.3.3.2.1 Flag Register

Accessible via CRU input and output instructions that are executed to dedicated internal CRU bit addresses (see Figure 19} is the internal Flag Register, The 16-bit Flag Register contains both predefined TMS 9995 systems flags and user-definable flags as detailed in Table 3. The predefined system flags are the configuration bit for the Decrementer, the Decrementer enable bit, and the internal interrupt request latch CRU inputs. Note that CRU out- put operations to the internal interrupt request latch Flag addresses will not cause these latches to be either set or reset. These Flag bits are input only and allow the presence of these interrupt requests to be detected when the occurrence of the interrupts themselves is inhibited by the value of the interrupt mask in the status register.

2.3.3.2.2 MID Flag

Accessible via CRU input and output instructions that are executed to a dedicated internal CRU bit address (see Figure 19) is the MID Flag. The MID Flag is set to one by a MID interrupt, and reset to zero by the software of will not cause the MID interrupt to be requested,

2.3.4 External Instructions

The TMS 9995 has five external instructions (see Table 4) that allow user-defined external functions to be initiated under program control. These instructions are CKON, CKOF, RSET, IDLE, and LREX. These mnemonics, except for IDLE, relate to functions implemented in the 990 minicomputer and do not restrict use of the instructions to initiate various user-defined functions. Execution of an IDLE instruction causes the TMS 9995 to enter the Idle state and remain in this state until a request occurs for an interrupt level that is not masked by the current value of the interrupt mask in the status register, (Note that the Reset and NMI interrupt levels are not masked by any interrupt mask value.) When any of these five instructions are executed by the TMS 9995, the TMS 9995 will use the CRU interface (see Figure 18) to perform a cycle that is identical to a single-bit CRU output cycle (see Figure 21) except for the following: (1) the address being output will be non-specific, (2) the data bit being output will be non-specific, (3) a code, specified in Table 4, will be output on DO-D2 to indicate the external instruction being executed, (4) during CRU and external instruction cycles, D3-D7 are all zeroes. Note that completion of each external instruction and/or generation of Wait states is determined by the READY input as detailed in Section 2.3.1.3,

TABLE 3 — FLAG REGISTER BIT DEFINITIONS CRU BIT

DESCRIPTION

ADORESST | enero | FLAGO Set to 0: Decrementer configured as cs Settot Decrementer configured as mts FLAG1 1EE2 Set to 0: Decrementer not enabled Setto1 Decrementer enabled (wili corres se level 3 interrupt). FLAG2 Level 1 Internal Interrupt Request Latch CRU Input (Input-only). veer mr ee FLAG3 Levet 3 Internal Interrupt Request Latch CRU Input (Input-only). 0: Level 3 request not present 1: Level 3 request present FLAG4 1EES Level 4 Internal Interrupt Request Latch CRU Input (input-only). 0: Level 4 request not present nines FLAGS 1EEA ce < FLAG7 1EEE FLAGB 1EFO FLAGO 1EF2 FLAGA 1EF4 User Defined nt fs FLAGC 1EFS FLAGD 1EFA FLAGE 1EFC FLAGF 1EFE t These hex numbers are those obtained by Placing the 15-bit Address Bus CRU address in a 16-bit field, left justifying the 15 bits in the field, terete erred TABLE 4 — TMS 9995 EXTERNAL INSTRUCTION CODES NG CYCLE INSTRUCTION ee a DUR L ee CRU: SBO, SBZ, TB, LDCR or STCR a a i 0 a er a A

When the TMS 9995 is in the Idle state, cycles with the Idle code will occur repeatedly until a request for an inter- rupt level that is not masked by the interrupt mask in the status register occurs. A Hold state can occur during an Idle state, with entry to and return from the Hold state occurring at the Idle code cycle boundaries, (See Section 2.3,1.1.3 for details of entry to and return from the Hold state.)

2.3.5 TMS 9995 Internal ALU/Other Operation Cycles

When the TMS 9995 is performing an operation internally and is not using the memory, CRU, or external instruc- tion interfacest or is not in the Hold state, the TMS 9995 will, for as many CLKOUT cycles as needed, do the following with its interface signals: (1) Output a non-specific address on AO-A14 and A15/CRUOUT (2) Output all ones on DO-D7 (3) Output logic levet high on MEMEN, DBIN, and WE/GRUCLK (4) Output logic level low on |AQ/HOLDA, and (5) Ignore the READY and CRUIN inputs. The HOLD input is still active, however, as the TMS 9995 can enter a Hold state while performing an internal ALU/other operation. Also, all interrupt inputs are still active. t Internat memory space and internal CRU device accesses are defined as using the memory and CRU interfaces, 3. TMS 9995 PIN DESCRIPTION Table 5 defines the TMS 9995 pin assignments and describes the function of each pin. Figure 24 illustrates the TMS 9995 pin assignment information. XTAL1 1 40 A15/CRUOUT XTAL2/CLKIN 2 39 A14 CLKOUT 3 38 A13 D7 4 37 A12 De 5 36 A11 DS 6 35 A10 D4 7 34° «AG D3 8 33 AB D2 9 32 «AT Veco 10 31 Vss DI ot 30 AG Do 12 29° «AS CRUIN 13 28 AA INT4/EC 14 27) A3 iNT 15 26 A2 1AQ/HOLDA 16 25 «Al DBIN 17 24 AO HOLD 18 23 READY WE/CRUCLK 19 22 RESET MEMEN 20 21 NMI FIGURE 24 — PIN ASSIGNMENTS

TABLE 5 ~ TMS 9995 PIN DESCRIPTION SIGNAL PIN vo DESCRIPTION POWER SUPPLIES Vee 10 ‘Supply voltage (+5 V Nom) Vss 31 Ground reference clocks XTAL2/CLKIN 2 IN Crystal input pin for internal oscillator. Also input pin for external oscillator. XTALI 1 IN Crystal input pin for internal oscillator, cLKOUT 3 out Clock output signal. The frequency of CLKOUT is one fourth the oscillator input {external oscillator) or crystal (internal oscil- lator) frequency. ADDRESS BUS AO 24 ouT Address Bus. AQ is the most significant bit of Al 25 our the 16 bit memory address bus and the 15 bit A2 26 our CRU address bus. A14 is the 2nd least signifi- Ag 27 our cant bit of the 16 bit memory address bus and Aa 28 out the LSB of the 15 bit CRU address bus. The AS 29 our address bus assumes the high impedance state AS 30 our when the TMS 9995 is in the Hold state, ar 32 our a8 33 our Ag 34 our 10 36 our ait 36 ouT | Al2 37 our Al3 38 out Ala 39 out A15/CRUQUT 40 our Address bit 15/CRU output data, A15/ CRUOUT is the LSB of the 16 bit memory address bus and the output data line for CRU output instructions. A15/CRUOUT assumes the high impedance state when the TMS 9995 is in the Hold state. DATA BUS bo 12 ie) Data Bus. During memory cycles (MEMEN o1 " Tc) active) DO (the MSB) through D7 (the LSB) 2 9 v0 are used to transfer data to/from the external D3 8 0 memory system. During non-memory cycles D4 7 ie) (MEMEN inactive) D0, D1 and D2 are used ps 6 vo to indicate whether the TMS 9995 is perform- D6 5 i) ing a CRU cycle or an external instruction. 07 4 vo The data bus assumes the high impedance state when the TMS 9995 is in the Hold state. cRU RUIN 13 CRU input data. During CRU cycles, CRUIN is the input data line for CRU input data,

TABLE 5 — TMS 9995 PIN DESCRIPTION (Continued) CONTROL MEMEN 20 our Memory enable. When active (low) MEMEN. indicates that WE/CRUCLK, DBIN, and the address and data buses are being used for a | memory cycle, When inactive (high) MEMEN indicates that WE/CRUCLK, DBIN and the address and data buses are being used for a CRU cycle, or are indicating that the | TMS 9995 is performing an external instruc- tion. MEMEN does not assume the high im- | pedance state when the TMS 9995 js in the Hold state. Dein v7 ouT Data bus in. During memory read cycles, DBIN is active (low) to indicate that the | TMS 9995 has disabled its data bus output | buffers to allow external memory to enable 3.state drivers that output data onto the data bus. During CRU input cycles, DBIN is also active to indicate that the CRU eyele is an input cycle. DBIN assumes the high im- pedance state when the TMS 9995 is in the Hold state. WE/CRUCLR 19 ouT Write enable/inverted CRU clock. When active (iow), WE/GRUCLK indicates that memory write data is available on the data bus (when MEMEN = 0); or that CRU data out is available on A15/CRUOUT (when MEMEN = 1 and DO = D1 = D2 = 0); or that an external inter- face should decode External instructions (when MEMEN = 1 and 00, D1, and D2 are not all equal to 0). WE/CRUCLK assumes the high impedance state when the TMS 9995 is in the Hold state. READY 23 In | Ready. When active (high), READY indicates | that the present external memory, CRU, or ex: ternal instruction cycle is ready to be completed. | When not ready is indicated, a Wait state (defined | | as extension of the present cycle by one CLKOUT READY is examined to determine if another | Wait state is to be generated or if the cycle is to be completed.

TABLE 5 — TMS 9995 PIN DESCRIPTION (Continued) SIGNAL PIN DESCRIPTION CONTROL (Cont‘d) Horo 18 IN Hold state request. When active (low), HOLD indicates to the TMS 9995 that an external controller desires to use the address and data i buses. Upon sensing @ Hold request, the TMS 9995 will enter a Hold state (defined as suspension of instruction execution) after it has completed its present cycle (see Section 2.3.1.1.3 for details of entry into a Hold state), At the beginning of the Hold state, the TMS 9995 places DBIN, WE/CRUCLK, and the address and data buses in the high imped- lance state, and then responds by asserting IAQ/HOLDA. When HOLD is removed, the ‘TMS 9995 returns to normal operation. IAQ/HOLDA, 16 out Instruction acquisition/hold acknowledge. If 'AQ/HOLDA is active (high) when MEMEN = 0, the TMS 9995 is indicating that the memory read cycle in progress is that of reading an instruction opcode. If !AQ/HOLDA is active when MEMEN = 1, the TMS 9995 is indicating that it is in the Hold state and that DBIN, WE/ ERUCLK, and the address and data buses are | in the high impedance state, INTERRUPTS RESET 22 IN Reset. When active (low) RESET causes the TMS 9995 to enter a RESET state (see Section | 2.3.2.1.1) and inhibit MEMEN, DBIN, and WE/ | CRUCLK. When RESET is released, the TMS 9995 initiates a level zero interrupt se- quence that acquires WP and PC from memory word addresses 0000 and 0002, and begins i execution using this vector. RESET will ter- minate an Idle state. RESET is a Schmitt- { trigger input. Nw 2 IN Non-maskable Interrupt. When active (low), 'NMi causes the TMS 9995 to execute a non: maskable interrupt sequence with the trap vector (WP and PC) in memory word ad- dresses FFFC and FFFE, NMI will terminate an Idle state. NMI is recognized only once for each high-to-low transition, (NMi must be taken inactive before it will be recognized again.) INT? 18 IN Interrupt one, When active (low), INTT will cause the TMS 9995 to execute a level one interrupt trap if level one is not masked by the status register.

TABLE 5 — TMS 9995 PIN DESCRIPTION (Concluded) INTA/EC 4 In Interrupt four/event counter. When either the decrementer is not enabled or the decrementer is enabled and configured as an interval timer, INTA/EC being active (low) will cause the ‘TMS 9995 to execute a level four interrupt trap if level four is not masked by the status register. When the decrementer is enabled and configured as an event counter, a high-to-low | transition on INT4/EC will cause the count in i the decrementer to be decremented by one. | (See Section 2.3.1.2.2 for details of enabling and configuring the decrementer.) 4, TMS 9995 INSTRUCTION SET

44 DEFINITION

Each TMS 9995 instruction performs one of the following operations: © Arithmetic, logical, comparison, or manipulation operations on data e Loading or storage of internal registers (program counter, workspace pointer, or status) © Data transfer between memory and external devices via the CRU © Control functions

4.2 ADDRESSING MODES

The TMS 9995 instructions contain a variety of available modes for addressing random memory data, e.g., pro- gram parameters and flags, or formatted memory data (character strings, data lists, etc.). These addressing modes are: © — Workspace Register Addressing © — Workspace Register Indirect Addressing © — Workspace Register Indirect Auto Increment Addressing e Symbolic (Direct) Addressing © Indexed Addressing © Immediate Addressing © Program Counter Relative Addressing e CRU Relative Addressing

The following figures graphically describe the derivation of effective address for each addressing mode. The applica- bility of addressing modes to particular instructions is described in Section 4.5 along with the description of the operations performed by each instruction. The symbols following the names of the addressing modes (R, *R, *R+, @LABEL or @TABLE (R) are the general forms used by TMS 9995 assemblers to select the addressing modes for register R.

4.2.1 Workspace Register Addressing, R

Workspace Register R contains the operand REGISTER R wome[wsrauerion [= (wes2R OPERAND The Workspace Register addressing mode is specified by setting the two-bit T-field (Tg or Tp) of the instruction word equal to 00.

4.2.2 Workspace Register Indirect Addressing, *R

Workspace Register R contains the address of the operand REGISTER R The Workspace Register Indirect addressing mode is specified by setting the two-bit T-field (Tg or Tp) in the instruction word equal to 01

4.2.3 Workspace Register Indirect Auto Increment Addressing, *R+

Workspace Register R contains the address of the operand. After acquiring the address of the operand, the con- tents of Workspace Register R are incremented. REGISTER R 1 (BYTE) or 2 (WORD) The Workspace Register Indirect Auto Increment addressing mode is specified by setting the two-bit T-field (Tg or Tp) in the instruction word equal to 11,

4.2.4 Symbolic (Direct) Addressing, @LABEL

The word following the instruction contains the address of the operand. The Symbolic addressing mode is specified by setting the two-bit T-field (Tg or Tp) in the instruction word equal to 10 and setting the corresponding $ or D field equal to 0.

4.25 Indexed Addressing, @TABLE (R)

The word following the instruction contains the base address. Workspace Register R contains the index value, The sum of the base address and the index value results in the effective address of the operand, REGISTER R The indexed addressing mode is specified by setting the two-bit T-field (Tg or Tp) of the instruction word equal to 10 and setting the corresponding S or D field not equal to 0. The value in the S or D field is the register which con- tains the index value.

4.26 Immediate Addressing

The word following the instruction contains the operand.

4.2.7 Program Counter Relative Addressing

The eight-bit signed displacement in the right byte (bits 8 through 15) of the instruction is multiplied by 2 and added to the updated contents of the program counter. The result is placed in the PC. JUMP INSTRUCTION ADDRESS NEXT MEMORY WORD +

428 CRU Relative Addressing

The eight-bit signed displacement in the right byte of the instruction is added to the CRU base address (bits 0 through 14 of workspace register 12). The result is the CRU address of the selected CRU bit. INSTRUCTION oO 78 15 (+) CRU BIT REGISTER 12 ADDRESS (WP)+2-12. CRU BASE ADD. | i) 1415

43 DEFINITION OF TERMINOLOGY

The terminology used in describing the instructions of the TMS 9995 is defined in Table 6.

44 STATUS REGISTER MANIPULATION

Various TMS 9995 machine instructions affect the status register. Figure 5 shows the status register bit assignments. Table 7 lists the instructions and their effect on the status register.

45 INSTRUCTIONS

4.5.1 Dual Operand Instructions with Multiple Addressing for Source and Destination Operand

General oO 1 2 3 4 5 6 7 8 c:) 10 WwW 12 13 14 15 If B = 1, the operands are bytes and the operand addresses are byte addresses. If B = 0, the operands are words and the LSB of the operand address is ignored. The addressing mode for each operand is determined by the T-field of that operand. o1 0,1...15 Workspace register indirect 10 0 Symbolic 4 10 1,2 15 Indexed 2,4 4 0,1...15 Workspace register indirect 3 tions (bit 3 = 0).

TABLE 6 — DEFINITION OF TERMINOLOGY TERM DEFINITIONS

8 Byte Indicator (1 = byte; 0 = word)

D Destination address register DA Destination address lop Immediate operand LSB (n) Least-significant (right most) bit of (n) MSB (n) Most-significant (left most) bit of in) N Don't care Pc Program Counter Result Result of operation performed by instruction s Source address register SA Source address st Status register stn Bit n of status register TO Destination address modifier Ts Source address modifier w Workspace register WRn Workspace register n (n} Contents of n aob aiis transferred to b nl Absolute value of 0 + Arithmetic addition - Arithmetic subtraction AND Logical AND oR Logical OR © Logical exclusive OR a Logical complement of n . Arithmetic multiplication

TABLE 7 — STATUS REGISTER BIT DEFINITIONSt CONDITION TO SET BIT TO 1, OTHERWISE INSTRUCTION “ OE SS ALSO, THE EFFECT OF OTHER INTERRUPT INSTRUCTIONS AND INTERRUPTS | sto Logical c,cB If MSB (SA) = 1 and MSB (DA) = 0, or Greater If MsB (SA) = MSB (DA) and MSB of | Than (OA) ~ (SA}] = 1 cl If MSB (W) = 1 and MSB of IOP = 0, or if MSB (W) = MSB of IOP and MSB of (op — (w)) = 14. | ust If bit (0) of selected WR ist | | A, AB, Al, ANDI, result #0 DEC, DECT, LI, MOV, MOVB, NEG, ORI, S, SB, | DIVS, MPYS, INC, INCT, INV, SLA, SOC, SOCB, SRA, SRC, SRL, STCR, SZC, $2CB, XOR Uncondivionally sets status Bit to 0 All other instructions Do not affect the status bit (see Note 1) and interrupts sT1 Arithmetic c,cB Hf MSB (SA) = 0 and MSB (DA) = 1, or Greater If MSB (SA) = MSB (DA) and MSB of Than (OA) — {SAN} = 1 cl If MSB (W) = 0 and MSB of IOP = 1, or if MSB (W) = MSB of 1OP and MSB of or — (wi) = 1, If MsB (SA) = 0 and (SA) # 0 A, AB, Al, ANDI, If MSB of result = 0 and result ¥ 0 DEC, DECT, Li, MOV, MOVB, NEG, ORI, S, $B, DIVS, MPYS, INC, INCT, INV, SLA, SOC, SOCB, SRA, SRC, SRL, STCR, SZC, SZCB, XOR Unconditionally sets status bit to 0 All other instructions Do not affect the status bit (see Note 1) t See Table 6 for definitions of terminology used in this table,

TABLE 7 — STATUS REGISTER BIT DEFINITIONS (Continued) CONDITION TO SET BIT TO 1, OTHERWISE INSTRUCTION SET TO 0 FOR INSTRUCTION LISTED. sr NAME nee ALSO, THE EFFECT OF OTHER INSTRUCTIONS AND INTERRUPTS ci 1 (W) = 10P. coc _ If (SA) and (DA) = 0 czc If (SA) and (DA) = 0

18 If CRUIN = 1 for addressed CRU bit i

ABS, LOCR 1 (SA) = 0 RTWe If bit (2) of WRI5 is 1 If bit (2) of selected WR is 1 A, AB, Al, ANDI, Wresult = 0 DEC, DECT, LI, MOV, MOVB, NEG, | ori,s,s8, o1vs, MPYS, INC, INCT, | INV, SLA, SOC, SOCB, SRA, SRC, SRL, STCR, SZC, SZCB, XOR ~~ Gnconaitionally ets tama BR to 0 ‘All other instructions Do not affect the status bit (see Note 1) and interrupts sT3 Carry A, AB, ABS, Al, If CARRY OUT = 1 DEC, DECT, INC, INCT, NEG, S, $8 SLA, SRA, SRL, Tf last bit shifted out = 1 SRC RTWP - If bit (3) of WARIS is 1 If bit (3) of selected WR is? Unconditionally sets status bit to Alll other instructions Do not affect the status bit (see Note 1) and interrupts sT4 Overtlow A,AB If MSB (SA) = MSB (DA) and MSB of result # MSB (DA) Al If MSB (W) = MSB of 1OP and MSB of resuit + MSB (W) 5,88 - If MSB (SA) # MSB (DA) and MSB of result # MSB (DA) If MSB (SA) = 1 and MSB of result = 0 ING, INCT If MSB (SA) = 0 and MSB of result = 0 SLA If MSB changes during shift DIV If MSB (SA) = 0 and MSB (DA) = 1, or if MSB (SA) = MSB (DA) and MSB of (OA) — (Sad) = 0 Divs If the quotient cannot be expressed as a signed 16 bit quantity (80001 is a valid negative number) ABS, NEG If (SA) = 800016 RTWP and interrupts

TABLE 7 — STATUS REGISTER BIT DEFINITIONS (Conciuded) CONDITION TO SET BIT TO 1, OTHERWISE INSTRUCTION SET TO 0 FOR INSTRUCTION LISTED. BIT AND/OR INTERRUPT ALSO, THE EFFECT OF OTHER INSTRUCTIONS AND INTERRUPTS Parity LDCR If 1 < C < 8 and (SA) has odd number of 1's, STCR if 1 <C <B and the stored bits have an add number of 1's. If C = 0 or 9< C< 15, does If result has odd number of 1's, All other instructions Do not affect the status bit (see Note 1) [oom | emmeeetieneey | All other instructions Do not affect the status bit (see Note 1) ae sT9 XOP, Any Unconditionally sets each of these status st st10 Arithmetic Enable XOP, Any Unconditionally sets status bit to 0 a sT13 Mask and RST, Reset and Unconditionally sets each of these status All other interrupts If ST12 — ST15 = 0, no change Do rot affect these status bits (see Note 1)

OP CODE [=| RESULT | STATUS COMPARED} BITS DESCRIPTION A 10 1/0} ada Yes 04 (SA) + (DA) = (DA) AB 10 111] Add bytes Yes 05 (SA) + (DA) = (DA) c 1 0 0 |0| Compare No 0.2 Compare (SA) to (DA) and set appropriate status bits ce 1 0 0 |1] Compare bytes No 0-25 | Compare (SA) to (DA) and set appropriate status bits s 0 1 1 [0] Subtract Yes 04 (DA) — (SA) + (DA) sB 0 1 1] 1| Subtract bytes Yes 05 (DA) — (SA) + (DA) soc 1 1. 1 | 0] Set ones corresponding Yes 0.2 (DA) OR (SA) ~> (DA) soc8 | 1 1 1 | 1] Setones corresponding bytes Yes 0-2,5 | (DA) OR (SA) + (DA) szc © 1 0 | 0} Set zeroes corresponding Yes 02 (DA) AND (SA) + (DA) szcB 0 1 0 | 1] Set zeroes corresponding bytes Yes 0-25 (DA) AND (SA) ~ (DA) mov |i 1 0/0] Move Yes 02 (SA) > (DA) move [1 1 0 |1{ Move bytes Yes 0.25 (SA) = (DA) 45.2 Dual Operand Instructions with Multiple Addressing Modes for the Source Operand and Workspace Register Addressing for the Destination General o 1 2 3 4 5 6 7 8 9 0 4 12 13 14 15 Forma: oP CODE a ee The addressing mode for the source operand is determined by the Ts field. 00 0,1...15 Workspace register 01 0,1...15 Workspace register indirect 10 0 Symbolic 10 1,2...15 Indexed W 0,1...15 Workspace register indirect auto increment NOTES: 1, Workspace register 0 may not be used for indexing. 2, The workspace register is incremented by 2.

RESULT | sTATUS COMPARED| BITS. DESCRIPTION jorzaas| Too |aFFecteD | coc © © 1 0 0 O| Compare ones No 2 Test (D) to determine if 1's are in each bit | corresponding position where 1’s are in (SA). If so, set ST2. czc_ |0 0 1 0.0 1|Compare zeroes] No 2 Test (D) to determine if 0's are in each bit corresponding position where 1’s are in (SA). If so, set ST2. | XOR |0 01 01 Of Exclusive OR Yes 02 (DA) ® (Sa)-- (D) | mey |0 0 1 1 1 0/ Multiply No - Multiply unsigned (D) by unsigned (SA) and | place unsigned 32-bit product in D (most significant) and D+1 Uleast-significant). If WR15, is D, the next word in memory after WR15 will be used for the least significant half of the product. Div 00111 1]Divide No 4 If unsigned (SA) is less than or equal to unsigned {D), perform no operation and set ST4. Otherwise, divide unsigned (D) and (D+1) by unsigned (SA) Quotient + (D), remainder + (D+1). If D = 18, the next word in memory after WR15 will be used for the remainder.

45.3 Signed Multiply and Divide Instructions

General o 1 2 3 4 5 6 7 8 9 0 1 12 13° 14 15 The addressing mode for the source operand is determined by the Ts field. 00 0,1...15 Workspace register 1 o1 0,1...15 Workspace register indirect 1

10 C) Symbolic 1

10 1,2...15 Indexed 12 "1 0.1.2.5 Workspace register indirect 13 auto increment NOTES: 1. Workspace registers 0 and 1 contain operands used in the signed multiply and divide operations, 2. Workspace register 0 may not be used for indexing. 3. The workspace register is incremented by 2.

OP CODE RESULT | STATUS COMPARED] BITS. DESCRIPTION

0123456789 TOO | AFFECTED

mPYs |0 0 0 0 0 0 0 1 1 1] Signed Yes 0.2 Multiply signed two's com- Multiply plement integer in WRO by signed two's complement integer (SA) and place signed 32-bit product in WRO (most- significant) and WA1 least- significant. Divs |0 0 0 0 0 0 0 1 1 O} Signed Yes 0-24 | If the quotient cannot be ex- Divide pressed as a signed 16 bit quantity (8000 (hex) is a valid negative number), set ST4. Otherwise, divide signed, two's complement integer in WRO and WR1 by the signed two's complement integer (SA) and place the signed quotient in WRO and the signed remainder in WR1. The sign of the quo- tient is determined by algebraic rules. The sign of the remainder is the same as the sign of the dividend and | REMAINDER _ < |DIVISOR!

45.4 Extended Operation (XOP) Instruction

General o 1 2 3 4 5 6 7 8 9 0 1% 12 13 4 15 The Ts and§ fields provide multiple mode addressing capability for the source operand. When the XOP is executed, the following transfers occur: SA—*> (new WR11) (old WP) ————> (new WR 13) (old PC) ——+ (new WR114) After these transfers have been made, ST6 is set to one, and ST7, ST8, ST9, ST10 (Overflow Interrupt Enable), and ST11 are all set to zero. The TMS 9995 does not service interrupt trap requests (except for the Reset and NMI Requests) at the end of the XOP instruction. at

455 Single Operand Instructions

General o 41 2 3 4 5 6 7 8B 9 0 1 12 13 14 15 The Ts and S fields provide multiple mode addressing capability for the source operand, OP CODE RESULT | STATUS compareD | BITS DESCRIPTION 0123456789 TOZERO | AFFECTED! B 0 0 0 0 0 1 0 0 0 1] Branch No - SA (PC) BL 0 0 0 0 0 41 1 0 1 0} Branch No - (PC) + (WR11); SA (PC) and link BLWP 0 0 0 0 0 1 0 0 0 0} Branch No - (SA) = (WP); (SA + 2) (PC); and load (old WP) > (new WR13); workspace {old PC) + (new WR14); pointer (old ST) + (new WR18); The TMS 9995 does not ser- vice interrupt trap requests (except for the Reset and NMI Requests) at the end of the BLWP instruction cLR 0 0 00014 0 0 1 11) Clear No - 0- (SA) Operand SETO 0 0 0 0 0 4 4 1 0 0] Sette No - FRFF 16 ~ (SA) ones INV 0 0 0 0 0 1 0 1 0 4 }F Invert Yes 0-2 (SA) + (Sa) NEG 0 0 0 0 0 1 0 4 0 Of Negate Yes 04 (SA) ~ (SA) aBs 0 0 0 0 0 1 4 1 0 1] Absolute No 04 HSA)|— (Sa) value’ SWPB 0 0 0001 1 0 4 1} Swap No - (SA), bits O thru 7 ~ (SA) bytes bits 8 thru 15; (SA), bits 8 thru 15+ (SA), bits 0 thru 7. INC 0 0 0 0 0 4 0 4 14 Of Increment Yes 04 (SA) +1 (SA) INCT © 0 0 0 0 4 O 4 4 1] Increment Yes 04 (SA) + 2= (SA) by two DEC © 0 0 0 0 1 4 0 0 O| Decrement Yes 04 (SA) — 1 -+ (SA) DECT © 0 0 0 0 1 1 0 0 1] Decrement Yes o4 (SA) — 2 (sa) by two xee 0 © 0 0 0 1 0 0 1 Of Execute No - Execute the instruction at sa + Operand is compared to zero for status bit, ** If additional memory words for the execute instruction are required to define the operands of the instruction located at SA, these words will be accessed from PC and the PC will be updated accordingly. The instruction acquisition signal (1AQ) will not be true when the TMS 9995 accesses the instruction at SA. Status bits are affected in the normal manner for the instruction executed,

45.6 CRU Multiple-Bit Instruction

General i) 1 2 3 4 5 6 7 8 9 10 W 12 13 14 15 The C field specifies the number of bits to be transferred. If C = 0, 16 bits will be transferred. The CRU base register (WR12, bits 0 through 14} defines the starting CRU bit address. The bits are transferred serially and the CRU address is incremented with each bit transfer, although the contents of WR12 are not affected. Ts and S pro- vide multiple mode addressing capability for the source operand. If eight or fewer bits are transferred (C = 1 through 8), the source address is a byte address. If nine or more bits are transferred (C = 0, 9 through 15), the source address is a word address. If the source is addressed in the workspace register indirect auto increment mode, the workspace register is incremented by one if C = 1 through 8, and is incremented by two otherwise. If the source is addressed in the register mode, and if the transfer is eight bits or tess, bits 8 - 15 are unchanged. OP CODE RESULT STATUS COMPARED BITS DESCRIPTION LDCR 0 0 1 1 oO oO Load Yes 0-2,5* Beginning with communication, LSB of (SA), specified number of bits from (SA) sTCR ie) oO 1 1 oO 1 Store Yes 0-2,5* Beginning with communication LSB of (SA), of bits from the CRU to (SA). Positions with 0.

457 CRU Single-Bit Instructions

General oO 1 2 3 4 5 6 7 8 9 10 any 12 13 14 15 Format: OP CODE SIGNED DISPLACEMENT The signed displacement is added to the contents of WR12 (bits 0-14) to form the address of the CRU bit to be selected.

sBO 0 °o oO 1 1 1 oO 1 Set bit to Set the selected one ouput bit to 1 S$BZ o oO oO 1 1 1 1 0 Set bit to Set the selected zero, output bit to 0, TB o oO ie) 1 1 1 1 1 Test bit If the selected CRU input bit = 1, set ST2; if the selected CRU in- put = 0, set ST2 =0.

45.8 Jump Instructions

General oO 1 2 3 4 5 6 7 8 9 10 W 12 13 14 15 Jump instructions cause the PC to be loaded with the value selected by PC relative addressing if the bits of ST are at specified values. Otherwise, no operation occurs and the next instruction is executed since the PC points to the next instruction. The signed displacement field is a word count to be added to PC. Thus, the jump instruction has a range of —128 to 127 words from memory-word address following the jump instruction. No ST bits are affected by jump instructions. OP CODE JEQ oO oO 0 1 oO oO 1 1 Jump equal sT2=1 JGT © 0 0 1 0 4 0 1 | Jump greater than sTi=1 JH o oO oO 1 1 i) 1 1 Jump high STO= 1 andST2=0 JHE oO oO oO 1 i) 1 oO i) Jump high or equal STO=1 or ST2=1 Ju oO oO oO 1 1 oO 1 oO Jump low STO =OandST2=0 JLE oO i) oO 1 oO 0 1 oO Jump low or equal STO=OorST2=1 JLT co) Oo oO 1 oO oO oO 1 Jump less than ST1=OandST2-0 JMP o oO oO 1 o oO Oo oO Jump unconditional Unconditional JNC oO oO oO 1 i) 1 1 1 Jump no carry ST3=0 JNE oO oO oO 1 0 1 1 0 Jump not equal ST2=0 JNO oO 0 oO 1 1 oO oO 1 Jump no overflow ST4=0 Joc © 0 0 41 1 6 0 0} Jump oncary sT3=1 JOP oO 0 0 1 1 1 oO ce) Jump odd parity ST5=1 Cd

45.9 Shift Instructions

General oO 1 2 3 4 5 6 7 8 9 10 a 12 13 14 18 If C = 0, bits 12 through 15 of WRO contain the shift count. If C = 0 and bits 12 through 15 of WRO = 0, the shift count is 16. OP CODE RESULT STATUS MNEMONIC MEANING COMPARED BITS DESCRIPTION SLA oO oO i) oO 1 oO 1 oO Shift left Yes 0-4 Shift (W) left. arithmetic Fill vacated bit positions with 0. SRA oO ie) oO oO 1 oO i) oO Shift right Yes 0-3 Shift (W) right. original MSB of (W). SRC i 0 oO oO 1 ie) 1 1 Shift right Yes 03 Shift (W) right. LSBintoMSB. | SRL 0 0 oO oO 1 oO oO 1 Shift right Yes 0-3 Shift (W) right. | O's.

45.10 Immediate Register Instructions

i) 1 2 3 4 5 6 7 8 9 10 11 12 13, 14 16 OP CODE RESULT STATUS MNEMONIC COMPARED BITS DESCRIPTION o 14723 45 67 8 9 10 TOO AFFECTED Al 000000 1000 14 Add immediate Yes 0-4 (W) + LOP > (W) ANDI 000000 10 0 1 0 AND immediate Yes 0-2 (W) AND IOP ~ (w) cl 000000 10 1 0 0 Compare imme- Yes 0-2 Compare {W) to ut o0000008100%0 0 Load immediate Yes 0-2 JOP = (w) OR! o 00000100 1 1 OR immediate Yes 0-2 (W) OR IOP = (Ww)

45.11 Internal Register Load Immediate Instructions

oO 1 2 3 4 5 6 7 8 9 10 any 12 13 14 15 General OP CODE oO oO i) oO oO OP CODE LWP! oO oO 0 i) oO oO 1 0 1 1 1 Load workspace 1OP — (WP), no ST bits LIM oO oO oO i) oO oO 1 1 0 0 oO Load interrupt JOP, bits 12 thru 15 >

45.12 Internal Register Load and Store Instructions

General 0 1 2 3 4 5 6 7 8 9 10 WW 12 13 14 15 MNEMONIC Bits DESCRIPTION o 1 2 3 4 5 6 7 8 9 10 a AFFECTED STST oO oO oO oO i) oO 1 oO 1 1 oO oO Store status (ST) + (Ww) ust oO i) 0 oO oO [) oO o 1 oO oO oO Load status (W) ~ (ST) Register STWP oO 0 oO oO oO 0 1 oO 1 O 1 0 Store work- (WP) = (W) LWP oO oO oO oO oO oO O oO 1 0 0 1 Load work- (W) + (WP)

45.13 Return Workspace Pointer (RTWP) Instruction

General oO 1 2 3 4 5 6 7 8 9 10 W 12 43 14 15 Format: 0 oO oO o oO oO 1 1 1 0 oO oO oO ° oO oO The RTWP instruction causes the following transfers to occur: (WR15) *(ST) (WR14) (PC) (WR13) »(WP)

45.14 External Instructions

General oO 1 2 3 4 5 6 7 8 9 10 W 12 13 14 15 External instructions cause three data lines (DO through D2) to be set to the levels described below, and the WE/ CRUCLK line to be pulsed, allowing external control functions to be initiated. BITS DESCRIPTION DATA BUS 0123465 678 9 10 AFFECTED [ bo [oi] 52 | IOLE 000 0001 4 01 0 Idle - Suspend TMS 9995, L H L instruction execution until an unmasked interrupt level request occurs. RSET ooo00000%08~«UTvUChUOUUTD Reset 12.15 Set ST12-ST15 L H H to 2er0, CKOF o 000001 11 40 User defined - - H H t CKON oo 0 0 0 80 1404 0 4 User defined - - H L H LREX oo 0 0 0 0 14°44 4 User defined - - H H H

45.15 MID Interrupt Opcodes

The instruction opcodes that will cause an MID interrupt request (see Section 2.3.2.2) are (hex numbers): 0000-007F 0301-033F 00A0-017F 0341-035F 0210-021F 0361-037F 0230-023F 0381-039F 0250-025F 03A1-03BF 0270-027F 03C1-03DF 0290-029F 03€1-03FF 02B80-02BF 0780-07FF 02D0-020F 0C00-OF FF 02E1-02FF

46 INSTRUCTION EXECUTION

4.6.1 Microinstruction Cycle

Each TMS 9995 instruction is executed by a sequence of machine states (microinstructions) with the length of each sequence depending upon the specific instruction being executed, Each microinstruction is completed in one CLKOUT cycle unless Wait states are added to a memory or CRU cycle. (Also, each external memory space access of a word and each external CRU cycle requires at least two CLKOUT cycles but will be accomplished with a single microinstruction),

4.6.2 Execution Sequence

The TMS 9995 incorporates an instruction prefetch scheme which minimizes, and in some cases eliminates, the time required to fetch the instruction from memory. Without the prefetch, a typical instruction execution sequence is as follows: (1) Fetch instruction (2) Decode instruction (3) Fetch source operand, if needed (4) Fetch destination operand, if needed (5) Process the operands (6) Store the results, if required The TMS 9995 makes use of the fact that during Step 5 the memory interface is not required; therefore, the fetch of the next instruction can be accomplished in this time. This instruction is then decoded during the state(s) that is(are) required to store the results of the previous instruction, which creates even more execution overlap. Table 8 illustrates the case of maximum efficiency for an Add instruction (instruction opcodes and operands are located in the internal RAM). Note that it effectively takes only four machine states to perform all six steps, TABLE 8 — EXECUTION SEQUENCE EXAMPLE STEP STATE MEMORY CYCLE INTERNAL FUNCTION COUNT = 2 A i It should be noted that the instruction prefetch scheme employed by the TMS 9995 can cause self-modifying software to execute incorrectly. Incorrect execution will result when an instruction is supposed to generate the opcode of the very next instruction to be executed. (The TMS 9995 will begin the fetch of the opcode of the next instruction before the currently executing instruction stores the results of its execution.)

46.3 TMS 9995 Instruction Execution Times

Instruction execution times for the TMS 9995 are a function of: (1) Machine state time, te2. (2) The location of the instruction opcode (internal or external memory). (3) The location of the workspace and the operand(s) (internal or external memory). (4) Addressing mode used where operands can be fetched via multiple addressing modes, (5) Number of Wait states introduced, as appropriate.

Table 9 lists the number of clock cycles required to execute each TMS 9995 instruction for various combinations of on-chip/off-chip location of instruction opcodes, operands, and workspace. (Other combinations can be ex tropolated from the ones listed.) For instructions with multiple addressing modes for either or both operands, Table 9 lists CLKOUT cycles and associated off-chip memory accesses with all operands addressed in the work- space register mode. To determine the total number of CLKOUT cycles and associated off-chip memory accesses required for other addressing modes, the appropriate values from Table “A’ (Table 10) are added to the base amounts for that instruction. The total execution time for an instruction is: T = teg (C1 +C2+W (XM1 + XM2)] where T = total instruction execution time te2 = CLKOUT cycle time C1 = base CLKOUT cycles C2 = additional CLKOUT cycles for operand address derivation (values in Table“‘A” are for one operand only) W = number of Wait states per off-chip (byte length) memory cycle XM1 = base off-chip (byte length) memory cycles XM2 = additional off-chip (byte length) memory cycles for operand address derivation (values in Table “A’" are for one operand only) Several examples are listed in Table 11.

TABLE 9 — INSTRUCTION EXECUTION TIMES Opcodes & Opcodes & Operands Off Immediate Chip; Source INSTRUCTION. ‘Operands Off Operand Off Opcodes & Chip; All Other | Chip; Destination. ‘Opcodes & Operand All Operands Operands On Operand On All Operands ‘Address On Chip Chip Chip. Off Chip Derivation © @ [Ter [oan [er [oan [ex _[own [er [xem | Source [oo | [ae os pe pe ps pe ep a fa [ape os ae ts pps tos a a SO [aa oe fe fe ee a [pa oo a fe pe fe ep ep [es oe fe pe a fe eum ee ee a [ere ee oe a ea [ee os pe pf ep a OO [exon fe fe fe fe fe pe} 2 fea fe ee os pe fe pe a [coo a oo os te Te fw Tar fT ef] a KC [eo a fo se pe ef ef a [oe fo ee ef ee fe fp a a [owsreaed Pe fo | 7 fe psf «po 8] [‘oivistaierewig | ae fo [ae] 2} a0 | «|e | a] a [owvsisraiseo «dof of Pe fe pe |e fa [bis ta wel as fo | ee fs fe fe | a | ZT A [wer fo a fe fe fe ef a [wy a ee ee ee a [swe tar vonpvecton) [3 [0 | «| 2 [+ | 2 ~«] 2] -} [Koon a fo ae fe fe fe | ep a [coor nccetay) «a2 [0 [iene | 2 anata freee] e | af] a A a a [ewer ao ee fe a fe a [wove aoe ea ae a a a OO [wevs as 0 a fa a poof 0 [veg so ee fe pe pe pe ad [oa eo ae pe pe pe a a a + These values will apply to future parts following Revision 8. (Revision 6 parts are identifiable by a “B“ in the date code of the symbolization + These values apply up to and including Revision B,

TABLE 9 — INSTRUCTION EXECUTION TIMES (Concluded) Opcodes & Penn Opcodes & Operands Off Immediate Chip; Source INSTRUCTION Operands Off Operand Off Opcodes & Chip; All Other | Chip; Destination Opcodes & Operand All Operands: Operands On Operand On All Operands Address On Chip Chip Chip Off Chip Derivation © @ [ex [xmr| er [vans | eff oon [er [xm | Source [Bon —| [see os a Ps fs Pst sta ta [sso fof 2 fe | 2 po fe fT [sex fo fe fe fe | 2 fol «| te [sero oe ae os pe pe pe [swericay ee fo [eee Pe fe eee fT [swieric-0,eustatsorwao-o [2 | o | a [2 [a | 2 [a |e] ]- 1 [SHIFT (6-0, 6 1248 ofwao-Neo) [TN [o-| ew [2 | ew] 2 [ion] ef a [socs a os Pes pe ps oe fm a [stor (eons oe ae ea a ES 0 a [sronecceis) fave | 0 [are aoe [6 pane] a | a [srt oe a pe pe ps Pe a [s2¢ a os a oe oe pe ee [see aos ae ps fe ep ep apa a a [xor iso | is | ef ef ie a a | interrupt, including Reset, NMI, MID, | 14@ o® 17@ | 6© | 176 6© | 2@| 120 and overflow) @ Additional cycles to be added, if appropriate, are listed in @ Trap vector off chip; New workspace on chip. Table "A" (Table 11). © Registers for register-only instructions are on chip (Shift @ Execution time is dependent upon the partial quotient sfter instructions, STST, LST, STWP, LWP) and registers for @® Will remain in Idle state until an unmasked interrupt re- TB, Shift instructions) quest occurs (1 = number of CLKOUT cycles until request @ Workspace on chip occurs) @® Trap vector on chip; New workspace on chip (NMI only) @® Execution time shown does not include execution time of @© Trap vector and New workspace on chip

TABLE 10 — OPERAND ADDRESS DERIVATION (TABLE “A”) Workspace Registers, Workspace Registers Workspace Registers Workspace Registers, Base Address For On Chip; Base Off Chip; Base Base Address For Index-Addressed ‘Address For Index- Address For Index- Index-Addressed ADDRESSING MODE Operands, And Addressed Operands Addressed Operands Operands, And Symbolic (Direct) And Symbolic (Direct) || And Symbolic (Direct) Symbolic (Direct) Addresses On Chip Addresses Off Chip Addresses On Chip Addresses Off Chip wR (Ts or Tp = 00) WR Indirect (Ts or Tp = 01) WR Indirect Auto Increment 4 (Tg or Tp = 11) ‘Symbolic (Tg or Tp = 10, 2 SorD=0) Indexed (Tg or Tp = 10, 2 SorD #0)

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1. TMS 9995 PRELIMINARY ELECTRICAL SPECIFICATIONS

51 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS

OTHERWISE NOTED)t Supply voltage, VOC cece ene te ete tee eee sees —0.3t07V All input voltages 6... eee eee cece ete tees eee eeeeee es 0.3 to 20V Output voltage teva ee teenssnanene er bee eee eee ee -0.3to7V Continuous power dissipation oe eee eee eevee ee teeeeeeeeeee TW Storage temperature range 6. ee eee eee ees 55°C to +150°C ‘Tstresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device celiability tall voltage values are with respect to Vss.

5.2 RECOMMENDED OPERATING CONDITIONS

[PARAMETER TO MIN NOM MAX UNIT | | Supply voltage Veg Cd High-level input voltage Vix (all inputs except XTAL1, XTAL2/CLKIN) | Low-level clock input voltage, Vig OCS | | High-ievel output current, Igy (alloutputs) TOA |

53 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED FREE-AIR TEMPERATURE (UNLESS

OTHERWISE NOTED) [Vou High-level output voltage Vec=MIN,ign=MAX | 24s |v [Vou Lowievel ourputvottage TVec=MIN Tou=MAX [soa [vo=24v 20 ea] aa ed ee ee [1 teputecureent TT vieVsstoveg Tw [toc Supply current Vg MAX 180180 ma Cc Input Cay itance Dota Bus V pur Capac All others f= 1 MHz, All Data Bus other pins OV Cy Output Cz i en id +All typical values are at Voc ™ 5 V, Ta = 25°C

5.4 CLOCK CHARACTERISTICS

The TMS 9995 can use either its internal oscillator or an external frequency source for a clock

5.4.1 Internat Clock Option

The internal oscillator is enabled by connecting a crystal across XTAL1 and XTAL2/CLKIN. (See Figure 25). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. TMs 9995 XTALI XTAL2/CLKIN CRYSTAL T . T ° NOTE: Cy and C2 represent the total capacitance on these pins including strays and parasitics, FIGURE 25 — INTERNAL OSCILLATOR PARAMETER TEST CONDITIONS [win [now | wax [owe] a A A BT

5.4.2 External Clock Option

An external frequency source can be used by injecting the frequency directly into XTAL2/CLKIN with XTAL1 left unconnected. (See Figure 26). The external frequency must conform to the following specifications. The frequency of CLKOUT is one-fourth that of the frequency injected. 2 mss] w | OR TWH Input oscillator pulse width high [Fermtar sd A 2 wut Input oscillator pulse width low ee

‘TMs 9995 XTAL2/CLKIN XTAL1 NO CLKIN CONNECTION OSCILLATOR FIGURE 26 — EXTERNAL OSCILLATOR

5.5 TIMING REQUIREMENTS OVER RECOMMENDED OPERATING CONDITIONS

Po ramamerer wom max tuners] [aq Sep i, READY ptr | CLKOUT mamory eye 00 | [m1 Hola tie, READY afer CLKOUT (memory ena CRU evs) SS] [ug “Setup tine, OataorontorcuKOUT i | [ing Hold tine, Outer OUT [ing Hola time, CRUIN priorte s CLKOUT | [ig Setup tine, READY prior to CLROUT GRU aes) 00] Tus, Setup time, HOLD prior tof CLKOUT [2s ids tsu6 Setup time, RESET and NMI prior to | CLKOUT [aos | Fwea Pulse width, Interrupt inputs [ig aie FAC nove Si | [wig lee wid, EC input [wis Pu width Cinergy ce] [eg etme, FE input ep]

5.6 SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS (See Figure 34)

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