TMS9918A

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TMS9918A/TMS9928A/TMS9929A Video Display Processors . MICROPROCESSOR SERIES”

Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible. TI cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement. Copyright © 1982 Texas Instruments Incorporated

TABLE OF CONTENTS (continued) SECTION PAGE LIST OF APPENDICES APPENDIX PAGE iv

v

LIST OF ILLUSTRATIONS (continued) FIGURE PAGE LIST OF TABLES TABLE PAGE vi

1. INTRODUCTION

441 Description

The TMS9918A/9928A/9929A video display processors (VDP) are N-channel MOS LSI devices used in video systems where data display on a raster-scanned home color television set or color monitor is desired. These devices generate all necessary video, control, and synchronization signals and also control the storage, retrieval, and refresh of display data in the dynamic screen refresh memory. The interfaces to the microprocessor, refresh memory, and the TV require a minimum of additional electronics for the TMS9918A. In Section 1.4, there is a list of acronyms and a glossary of terms used in this manual. The TMS9928A/9929A VDPs are functionally identical to the TMS9918A except that the NTSC color encoding circuitry has been removed and replaced with luminance and color difference signals. The TMS9918A is pin-for-pin compatible with the TMS9928A/9929A, except for three pins, the composite video output, the external video input and the CPU Clock output. These pins are replaced with the Black/White luminance and composite sync (Y) output and two color dif- ference pins, Blue (B-Y) and Red (R-Y) outputs, respectively. The color difference outputs allow the user to generate Red- Green-Blue (R-G-B8) drive for direct color gun control, or composite video for use with NTSC or PAL video color monitor. However, to connect these three outputs to a R-G-B or monitor requires additional R-G-B or encoder circuitry. The TMS9918A/9928A have a 525-line format for U.S. televisions while the TMS9929A has a 625-line format for use with the European PAL system. The VDP has four video display modes: Graphics |, Graphics II, Multicolor and Text mode. The Text mode provides twenty- four 40-character rows in two colors and is intended to maximize the capacity of the TV screen to display alphanumeric character. The Multicolor mode provides an unrestricted 64 x 48 color-dot display employing 15 colors plus transparent. The Graphics | mode provides a 256 x 192 pixel display for generating pattern graphics in 15 colors plus transparent. The Graphics II mode is an enhancement of Graphics | mode, allowing it to generate more complex color and pattern displays. The four video display modes are described in detail in Section 2.4. The video display consists of 35 planes: external VDP, backdrop, pattern plane, and 32 Sprite Planes. The planes are ver- tically stacked with the external VDP being the bottom or innermost plane. The backdrop plane is the next plane followed by the pattern plane that contains Graphics | and Graphics I! patterns with the 32 Sprite Planes as the top planes. The TMS9918A/9928A/9929A VDPs use either a 4K, 8K, or 16K-type low-cost dynamic memory (TMS4027, TMS4108, TMS4116) for storage of the display parameters. The TMS9918A, TMS9928A, and TMS9929A interface identically to the host microprocessor making them software compatible. Thus, all references to VDP in this document apply to all three devices, except where noted.

12 FEATURES

© _ Single-chip solution for interfacing color TVs (excluding Random-Access Memory (RAM) and Radio Frequency (RF) modulator (TMS9918A only) @ =256 x 192 resolution on TV screen @ 15 unique colors plus transparent ©@ — General 8-bit bidirectional interface to Central Processor Unit (CPU) © Direct wiring to 4K, 8K, or 16K dynamic RAM memories @ — Automatic and transparent refresh of dynamic RAMs © — Multiple VOP systems capability e External VDP input capability (TMS9918A only) e Composite video output (TMS9918A only) e Unique planar representation for 3D simulation @ = Standard 40-pin package © — Color difference outputs allow RGB drive — TMS9928A/9929A

1.3 TYPICAL APPLICATIONS

© — Color computer terminals @ Home computers e Drafting/design aids @ Teaching aids © Industrial process monitoring e Home educational systems e Animation aids e European 625-line TV (TMS9929A only) The following example of a typical application may help introduce the user to the TMS9918A VDP. Figure 1-1 is a block diagram of a typical application. Each of the concepts presented in the example is described more fully in later sections of this manual. TMS9918A, } ORIVE - CIRCUITRY L, ; — VIDEO MONITOR ‘TMS9918A/ = HOME TV WITH VIDEO INPUT ADDRESS BUS SELECT LOGIC [ i r= TT] VIDEO IN =| ‘TMS9928A/99294 we VIDEO ENCODER — Sha 2 m g S's eo cpu cpu ~ VIDEO MONITOR RAM ROM TMS9918A/ = HOME TV WITH VIDEO INPUT voP R russezenrszen | Syl DATA BUS RGB ENCODER _—ms a FS . — RGB MONITOR DYNAMIC TMS9918A/ — RAM 9928A/ RE (vRAM) 99298 - DRIVE/VIDEO MODULATOR iL, ENCODER —-_ ~ HOME TV WITHOUT VIDEO INPUT FIGURE 1-1 — SYSTEM BLOCK DIAGRAM The VDP basically has three interfaces: CPU, color monitor, and dynamic refresh RAM (VRAM), the contents of which define the TV image. The TMS9918A also has eight write-only registers and a read-only status register. The VDP communicates with the CPU via an 8-bit bidirectional data bus. Three control lines, decoded from the CPU address and enable lines, determine interpretation of the bus. Through the bus, the CPU can write to VRAM, read from VRAM, write to VDP registers, and read the VDP status. The VDP also generates an interrupt signal after every refresh of the TV display. The dynamic RAM interface consists of direct wiring of eight 4K x 1, 8K x 1, or 16K x 1 dynamic RAS/CAS-type RAMs to the VDP. The amount of RAM required is dependent upon the features selected for use in the application. The interface to the monitor can consist of either wiring the TMS9918A's composite video output pin (suitably buffered) to the input of a color or black-and-white monitor, or using an appropriate RF modulator to feed the signal into a TV anten- na terminal. The TMS9928A/9929A require additional encoder circuitry to interface to a RGB or to a composite video monitor. 1-2

The VDP operates in four modes, and each one can affect the way the VRAM is mapped onto the television screen. In Graphics | and II modes, characters are mapped onto the screen in 8 x 8 pixel blocks, yielding 24 lines of 32 blocks (pat- tern positions) each. In Text mode, there are 24 lines of 40 blocks, each of which is6 x 8 pixels. In Multicolor mode, there are 48 lines of 64 blocks, each of which is composed of 4 x 4 picture elements (pixels), all of one solid color. In addition to these, sprites can be superimposed onto the television image in Graphics |, II, and Multicolor mode. Furthermore, signals entering the TMS9918A through the external VDP input can be used as a background to the TMS9918A. ACRONYMS AND GLOSSARY , B-Y Blue color difference output CIMVID Contains luminance, chrominance and all sync pulse necessary for horizontal and vertical timing {Composite Video) CAS Column Address Strobe CPU Central Processor Unit CSR CPU from VDP read select csw CPU to VDP write select CPUCLK XTAL — 3 GROMCLK XTAL — 24 LSB Least Significant Bit Ls Large Scale Integration MOS Metal Oxide Semiconductor MHz Megahertz MSB Most Significant Bit NTSC National Television Standards Committee which specifies television signal standards for the USA PAL Phase Alternating Line Pixel Picture Element — the smallest point on the TV screen that can be independently controlled. RAM Random-Access Memory RAS Row-Address Strobe RASTER The area in which an image is reproduced RF Radio Frequency R-G-B Red-Green-Biue ROM Read-Only Memory R/W Read/Write R-Y Red color difference output Sprite An object whose pattern is relative to a specified X,Y coordinate and whose position can therefore be controlled by that coordinate with a positional resolution of one pixel VDP Video Display Processor VRAM Video RAM; refers to the dynamic RAMs that connect to the VDP and whose contents define the TV image Y Black/white luminance and composite sync

1. ARCHITECTURE The TMS9918A video display processor (VDP) is designed to provide a simple interface between a microprocessor and a raster-scanned color television. The TMS9928A/9929A VDPs are designed as a simple interface between a microprocessor, and R-G-B monitor or video encoder which produces the video for a video monitor. Figure 2-1 is a block diagram of the major portions of the VDP architecture interfaces to the VDP, CPU, VRAM, and color television.

2.1 CPU INTERFACE

The VDP interface to the CPU using an 8-bit bidirectional data bus, three control lines, and an interrupt is shown in Figure 2-2. Through this interface the CPU can conduct four operations: (1) Write data bytes to VRAM (2) Read data bytes from VRAM (3) Write to one of the eight VDP write-only registers (4) Read the VDP Status Register. Each of these operations requires one or more data transfers to take place over the CPU/VDP data bus interface. The interpretation of the data transfer is determined by the three control lines of the VDP. NOTE The CPU can communicate with the VDP simultaneously and asynchronously with the VDP’s TV screen refresh operations. The VDP performs memory management and allows Periodic intervals of CPU access to VRAM even in the middle of a raster scan.

2.1.1 CPU Interface Control Signals

The type and direction of data transfers are controlled by the CSW, CSR, and MODE inputs. CSW is the CPU to VDP write select. When it is active (low), the eight bits on CD0-CD7 are strobed into the VDP. CSR is the CPU from VDP read select. When it is active (low), the VDP outputs eight bits on CD0-CD7 to the CPU. CSW and CSR should never be simultaneous- ly low at the same time. If both are low, the VDP outputs data on CD0-CD7 and latches in invalid data. MODE determines the source or destination of a read or write data transfer. MODE is normally tied to a CPU low order address line (A14 for TMS9900).

2.1.2 CPU Write to VDP Register

The VDP has eight write-only registers and one read-only status register. The write-only registers control the VDP opera- tion and determine the way in which VRAM is allocated. The status register contains interrupt, sprite coincidence and fifth sprite status flags. Each of the eight VDP write-only registers can be loaded using two 8-bit data transfers from the CPU. Table 2-1 describes the required format for the two bytes. The first byte transferred is the data byte, and the second byte transferred controls the destination. The MSB of the second byte must be a 1. The next four bits are Os, and the lowest three bits make up the destination register number. The MODE input is high for both byte transfers. To rewrite the data in an internal register after a byte of data has already been loaded, the status register must be read so that internal CPU interface logic is reinitialized and will accept the next byte as data and not as a register destination. This situation may be encountered in interrupt-driven program environments. Whenever the status of VDP write parameters is in question, this procedure should be used. NOTE The CPU address is destroyed by writing to the VDP register. 241

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ADDRESS & CONTROL REGISTERS DATA cru Do: D7 ADDRESS REGISTER vRAM READ DATA REGISTER WRITE DATA REGISTER CSR cw CONTROL MODE FIGURE 2-2 — VDP TO CPU INTERFACE 2.1.3. CPU Write to VRAM The CPU transfers data to the VRAM through the VDP using a 14-bit autoincrementing address register. The address register setup requires 2-byte transfers. A 1-byte transfer is then required to write the data to the addressed VRAM byte. The address register is then autoincremented. Sequential VRAM writes require only 1-byte transfers since the address register is already set up. During setup of the address register, the two MSBs of the second address byte must be 0 and 1 respectively. MODE is high for both address transfers and low for the data transfer. CSW is used in all transfers to strobe the 8 bits into the VDP. See Table 2-1. TABLE 2-1 — CPU/VDP DATA TRANSFERS, oPeRATI BIT RATION C) 1 2 3 4 5 6 7 WRITE TO VOP REGISTER BYTE 1 DATA WRITE Op Dy Dz Dg Dg Dg Dg dz 0 1 BYTE 2 REGISTER SELECT 1 () () ° oO RSg RS} RS2 oO 1 WRITE TO VRAM BYTE 1 ADDRESS SETUP Ae Az AB. AQAA ANDAR ° 1 BYTE 2 ADDRESS SETUP ° 1 Ao Ay A2 A3 Ag AS 0 1 BYTE 3 DATA WRITE Do 0; Dz 03 Dg Dg 6 D7 o o READ FROM VDP REGISTER BYTE 1 DATA READ Do Dy Dz D3 04 Ds 06 07 1 1 READ FROM VRAM BYTE 1 ADDRESS SETUP AS AZ Ag Ag Aro Ain AI2- AN ° 1 BYTE 2 ADDRESS SETUP oO tC) Ao Ay A2 AZ Aa As o 1 BYTE 3 DATA READ Do Dy D2 D3 Dg Ds 0g D7 1 0 2-3

2.1.4 CPU Read from VDP Status Register

The CPU can read the contents of the status register with a single-byte transfer. MODE is high for the transfer. CSR is used to signal the VDP that a read operation is required.

2.1.5 CPU Read from VRAM

The CPU reads from the VRAM through the VDP using the autoincrementing address register. A 1-byte transfer is then re- quired to read the data from the addressed VRAM byte. The address register is then autoincremented. Sequential VRAM data reads require only a 1-byte transfer since the address register is already set up. During setup of the address register, the two MSBs of the second address byte must be 0. By setting up the address this way, a read cycle to VRAM is initiated and read data will be available for the first data transfer to the CPU. (See Table 2-1). MODE is high for the address byte transfers and low for the data transfers. The VDP requires approximately 8 microseconds to fetch the VRAM byte follow- ing the last data transfer and 2 microseconds following address setup. The CPU interacts with VRAM memory through the VDP. The amount of time necessary for the CPU to transfer a byte of data to or from VRAM memory can vary from 2 to 8 microseconds. Once the VDP has been told to read or write a byte of data to or from VRAM it takes approximately 2 microseconds until the VDP is ready to make the data transfer. In addition to this 2 microsecond delay, the VDP must wait for a CPU access window; i.e., the period of time when the VDP is not occupied with memory refresh or screen display and is available to read or write data. The worst case time between windows occurs during the Graphics | or Graphics Il mode when sprites are being used. Dur- ing the active display, CPU windows occur once every 16 memory cycles giving a maximum delay of 6 microseconds (a memory cycle takes about 372 nanoseconds). In the Text mode the CPU windows occur at least once out of every three memory cycles or a worst case delay of about 1.1 microseconds. Finally, in the Multicolor mode, CPU windows occur at least once out of every four memory cycles. If the user needs to access memory in 2 microseconds, two situations occur where the time waiting for an access window is effectively zero. Both of these are independent of the display mode being used. The first situation occurs when the blank bit of register 1 is 0. With this bit low, the entire screen will show only border color and the VDP does not have to wait for a CPU access window at any time. The second situation occurs when the VDP is in the vertical refresh mode. The VDP issues an interrupt output at the end of each active area. This signal indicates that the VDP is entering the vertical refresh mode and that for the next 4.3 milliseconds there is no waiting for an access window. If the user wants the CPU to access memory during this interval, itis necessary for the controlling CPU to monitor the interrupt output of the VDP (the CPU can either poll this output or use it as an interrupt input). The program that monitors the interrupt output must allow for its own delays in responding to the interrupt signal and recognize how much time it has left during the 4300 microsecond refresh period. The CPU must write a 1 to the interrupt enable bit of Register 1 in order to enable the interrupt for each frame, and then read the status register each time an inter- rupt is issued to clear the interrupt output. A summary of these delay times is presented in Table 2-2. TABLE 2-2 — MEMORY ACCESS DELAY TIMES VDP TIME WAITING FOR TOTAL CONDITION DELAY AN ACCESS WINDOW TIME Active Display Area Graphics 2us 0 - 5.95 us 2-8ys Lu 4300 ys after Vertical 2us O us 2us Interrupt Signal Register | All 2ys Ops 2us Blank Bit 0 paiva Bepiay As | wuticawr | 2m [0-18 =

2.1.6 9 VDP Interrupt The VDP INT output pin is used to generate an interrupt at the end of each active-display scan, which is about every 1/60 second for the TMS9918A/9928A and 1/50 second for the TMS9929A. The INT output is active when the Interrupt Enable bit (IE) in VDP Register 1 is a 1 and the F bit of the status register is a 1. Interrupts are cleared when the status register is read.

2.1.7 VDP Initialization

The VDP is externally initialized whenever the RESET input is active (low) and must be held low for a minimum of 3 microseconds. The external reset synchronizes all clocks with its falling edge, sets the horizontal and vertical counters to known states, and clears VDP registers 0 and 1. The video display is automatically blanked since the BLANK bit in VDP . register 1 becomes a 0. The VDP, however, continues to refresh the VRAM even though the display is blanked. While the RESET line is active, the VDP does not refresh the VRAM.

2.2 WRITE-ONLY REGISTERS

The eight VDP write-only registers are shown in Figure 2-3. They are loaded by the CPU as described in Section 2.1.2. Registers 0 and 1 contain flags to enable or disable various VOP features and modes. Registers 2 through 6 contain values that specify starting locations of various sub-blocks of VRAM. The definitions of these sub-blocks are described in Section 2.4. Register 7 is used to define backdrop and text colors. Each register is described in the following paragraphs.

2.2.1 Register 0

Register 0 contains two VDP option control bits. All other bits are reserved for future use and must be Os. BIT6 M3 (mode bit 3) (see Section 2.3.2 for table and description) BIT7 External VDP enable/disable 0 disables external VOP input 1 enables external VDP input NOTE Enabling bit 7 in the TMS9928A/9929A causes A-Y and B-Y to go to the sync level only when all planes in front of the pixel under question are transparent.

2.2.2 Register 1 (contains 8 VDP option control bits)

0 selects 4027 RAM operation 1 selects 4108/4116 RAM operation BIT1 BLANK enable/disable 0 causes the active display area to blank 1 enables the active display Blanking causes the display to show border color only BIT2 1E (Interrupt Enable) 0 disables VDP interrupt 1 enables VDP interrupt BIT 3,4 M1, M2 (mode bits 1 and 2) M1, M2 and M3 determine the operating mode of the VDP: Mi M2 M3 0 0 0 Graphics | mode 0 i) 1 Graphics I! mode 0 1 0 Multicolor Mode

1 O i} Text mode

BIT6 Size (sprite size select) 0 selects Size 0 sprites (8 x 8 bit) 1 selects Size 1 sprites (16 x 16 bits) BIT7 MAG (Magnification option for sprites) 0 selects MAGO sprites (1X) 1 selects MAG1 sprites (2X) REGISTER SB sB > Fede fe fe | wan Tees ise ous:

3 COLOR TABLE BASE ADDRESS

5 Le | SPRITE ATTRIBUTE TABLE BASE ADDRESS

6 GENERATOR BASE

’ reer cot enoroncnononeones STATUS FIFTH SPRITE NUMBER (READ-ONLY) FIGURE 2-3 — VDP REGISTERS 2-6

2.2.3 Register 2

Register 2 defines the base address of the Name Table sub-block. The range of its contents is from 0 to 15. The contents of the register form the upper 4 bits of the 14-bit Name Table addresses; thus the Name Table base address is equal to (Register 2) *400(hex).

2.2.4 Register 3

Register 3 defines the base address of the Color Table sub-block. The range of its contents is from 0 to 255. The contents of the register form the upper 8 bits of the 14-bit Color Table addresses; thus the Color Table base address is equal to (Register 3) *40(hex).

22.5 Register 4

Register 4 defines the base address of the Pattern, Text or Multicolor Generator sub-block. The range of its contents is 0 through 7. The contents of the register form the upper 3 bits of the 14-bit Generator addresses; thus the Generator base address is equal to (Register 4) *800(hex).

2.2.6 Register 5

Register 5 defines the base address of the Sprite Attribute Table sub-block. The range of its contents is from 0 through 127. The contents of the register form the upper 7 bits of the 14-bit Sprite Attribute Table addresses; thus the base address is equal to (Register 5) *80(hex). 2.2.7. Register 6 Register 6 defines the base address of the Sprite Pattern Generator sub-block. The range of its contents is 0 through 7. The contents of the register form the upper 3 bits of the 14-bit Sprite Pattern Generator addresses; thus the Sprite Pattern Generator base address is equal to (Register 6) *800(hex).

2.2.8 Register 7

The upper 4 bits of Register 7 contain the color code of color 1 in the Text mode. The lower 4 bits contain the color code for color 0 in the Text mode and the backdrop color in all modes. 2.2.9 Setup Values for VDP Registers 2 through 6. VRAM TABLE ADDRESSING Register 2 in the VDP contains the starting address for the Name Table sub-block. R2 * 400(16) = START ADDRESS R2 ADDRESS 00 0000 01 0400 02 0800

03 OCOO — MAXIMUM NUMBER FOR 4K RAMS

OF 3C00 — MAXIMUM NUMBER

Register 3 in the VDP contains the starting address for the Color Table. (R3) * 40(16) STARTING ADDRESS START START START ADDRESS ADDRESS ADDRESS 00 0000 28 OA00 50 7400 01 0040 29 0A40 51 1440 02 0080 2A o0A8o 52 1480 03 ooco 28 oAco 53 14C0 04 0100 2c oBoo 54 1500 05 0140 2D B40 55 1540 06 0180 2E 0B80 56 1580 07 010 2F oBco 57 15CO 08 0200 30 ocoo 58 1600 09 0240 31 oc4o 59 1640 0A 0280 32 ocso 5A 1680 0B 02co 33 occo 5B 16CO oc 0300 34 op00 5C 1700 oD 0340 35 oD40 5D 1740 OE 0380 36 oD8o 5E 1780 OF 03co 37 opco 5F 1760 10 0400 38 0E00 60 1800 " 0440 39 0E40 61 1840 12 0480 3A 0E80 62 1880 13 04co 3B ECO 63 18C0 14 0500 3c oFoo 64 1900 15 0540 3D oF40 65 1940 16 0580 3E oF80 66 1980 7 05co 3F OFCo* 67 19C0 18 0600 40 1000 68 1A00 19 0640 41 1040 69 1A40 1A 0680 42 1080 6A 180 1B o6co 43 10C0 6B 1ACO 1c 0700 44 1100 6c 1800 1D 0740 45 1140 6D 1840 1E 0780 46 1180 6E 1B80 1F 07co 47 1160 6F 1BCO 20 0800 48 1200 70 1c00 21 0840 49 1240 1 1040 22 0880 4A 1280 72 1C80 23 o8co 4B 12C0 73 1¢co 24 0900 4c 1300 74 1D00 25 0940 4D 1340 75 1D40 26 0980 4 1380 76 1D80 27 o9co 4 1300 7 190 ‘*Maximum number for 4K RAMS 2-8

(R3)* 40(16) STARTING ADDRESS (Concluded) ze | ee ee ADDRESS ADDRESS ADDRESS 78 1E00 A6 2980 D3 34CO 79 1€40 AT 29C0 D4 3500 7A 1E80 AB 2A00 DS 3540 7B 1ECO Ag 2A40 D6 3580 7c 1F00 AA 2A80 D7 35C0 7D 1F40 AB 2ACO Ds 3600 JE 1F80 AC 2800 De 3640 7F 1FCO AD 2B40 DA 3680 80 2000 AE 2B80 DB 36C0 81 2040 AF 2BC0 pc 3700 82 2080 80 2c00 DD 3740 83 20c0 B1 2c40 DE 3780 84 2100 B2 2c80 DF 37C0 85 2140 B3 2cco EO 2800 86 2180 B4 2D00 —1 3840 87 21C0 B5 2D40 E2 3880 88 2200 B6 2D80 €3 38CO 89 2240 B7 2000 E4 3900 8A 2280 B8 2E00 ES 3940 8B 22C0 Bo 2E40 E6 3980 8c 2300 BA 2E80 &7 39c0 8D 2340 BB 2ECO Es 3A00 8E 2380 BC 2F00 EQ 1A40 8F 23C0 BD 2F40 EA 3A80 90 2400 BE 2F80 EB 3ACO PH 2440 BF 2FCO EC 3800 92 2480 co 3000 ED 3840 93 24CO C1 3040 EE 3B80 94 2500 c2 3080 EF 3BCD 95 2540 c3 30Co FO 3C00 96 2580 ca 3100 FA 3c40 97 25C0 cs 3140 F2 3c80 9 ane ce 3180 F3 3cco oA 2680 C7 3100 F4 2D00 9B 26c0 ce 3200 F5 3040 9c 2700 co 3240 F6 3080 9D 2740 cA 3280 F7 3DC0 9E 2780 cB 32C0 FB 3£00 oF 2700 cc 3300 F9 3E40 ‘a0 2800 co 3340 FA 3€80 A 2840 CE 3380 FB 3eCo AQ 2880 CF 33C0 FC 3F00 A3 28C0 Do 3400 FD 3F40 A4 2900 D1 3440 FE 3F80 AS 2940 D2 3480 FF 3FCO

Register 4 in the VDP contains the starting address for the Pattern Generator Sub-block. (R4) * 800(16) = START ADDRESS START R4 ADDRESS 00 0000 01 0800 — Max # for 4K RAMS 02 1000 03 1800 04 2000 05 2800 06 3000 07 3800 — Max #for 16K RAMS Register 5 in the VDP contains the starting address for the Sprite Attribute Table. (RS) * 80(16) = START ADDRESS a a a ADDRESS | as | ADDRESS ADDRESS ADDRESS 00 0000 21 7080 40 2000 60 3000 01 0080 22 1100 a 2080 61 3080 02 0400 23 1180 42 2100 62 3100 03 0180 24 1200 43 2180 63 3180 04 0200 25 1280 44 2200 64 3200 ° aes 26 1300 45 2280 65 3280 07 0380 27 1380 46 2300 66 3300 08 0400 28 1400 47 2380 67 3380 09 0480 29 1480 48 2400 68 3400 0A 0500 2A 1500 49 2480 69 3480 0B 0580 28 1580 4A 2500 6A 3500 oc 0600 2c 1600 4B 2580 6B 3580 oD 0680 2D 1680 4c 2600 6c 3600 OE 0700 2E 1700 4D 2680 6D 3680 OF 0780 2F 1780 4E 2700 6E 3700 10 0800 30 1800 4F 2780 6F 3780 n 0880 31 1880 50 2800 70 3800 12 0900 51 2880 1 3880 13 0980 2 oe 52 2900 72 3900 14 oA00 uu 1A00 53 2980 73 3980 15 oA8o 54 2A00 74 3A00

16 B00 36 1A80 55 2A80 75 3A80

17 OB80 36 1800 56 2B00 76 3B00

18 ocoo 37 1880 57 2B80 77 3B80 19 ocso 38 1c00 58 2c00 78 3c00 1A op00 39 180 59 2C80 79 3¢80 1B opso 3A 1000 5A 2D00 7A 3D00 1c E00 3B 1080 5B 2080 7B 3D80 1D 0E80 3c 1€00 5C 2E00 7c 3E00 1E OFOO 3D 1€80 5D 2E80 7D 3E80 1F OF80* 3 1F00 5E 2F00 7E 3F0O 20 1000 3F 1F80 5F 2F80 7F 3F80 ‘*Meximum number for 4k RAMS 2-10

Register 6 contains the value for the starting address of the Sprite Pattern Generator sub-block. STARTING ADDRESS = R6 *<800 START R6 ADDRESS 00 0000 01 0800 — Max # for 4K DRAMS 02 1000 03 1800 04 2000 05 2800 06 3000 07 3800 — Max # for 16K RAMS

2.3 STATUS REGISTER

The VDP has a single 8-bit status register that can be accessed by the CPU. The status register contains the interrupt pend- ing flag, the sprite coincidence flag, the fifth sprite flag, and the fifth sprite number, if one exists. The format of the status register is shown in Figure 2-3 and is discussed in the following paragraphs. The status register may be read at any time to test the F, C, and 5S status bits. Reading the status register will clear the interrupt flag, F. However, asynchronous reads will cause the frame flag (F) bit to be reset and therefore missed. Conse- quently, the status register should be read only when the VDP interrupt is pending.

2.3.1 Interrupt Flag (F)

The F status flag in the status register is set to 1 at the end of the raster scan of the last line of the active display. It is reset to a 0 after the status register is read or when the VDP is externally reset. If the Interrupt Enable bit in VDP Register 1 is active (1), the VDP interrupt output (INT) will be active (low) whenever the F status flag is a 1. Note that the status register needs to be read frame by frame in order to clear the interrupt and receive the new interrupt of the next frame.

2.3.2 Coincidence Flag (C)

The C status flag in the status register is set to a 1 if two or more sprites coincide. Coincidence occurs if any two sprites on the screen have one overlapping pixel. Transparent colored sprites, as well as those that are partially or completely off the screen, are also considered. Sprites beyond the Sprite Attribute Table terminator (D016) are not considered. The C flag is Cleared to a 0 after the status register is read or the VDP is externally reset. The status register should be read immediately upon powerup to ensure that the coincidence flag is reset. The VDP checks each pixel position for coincidence during the generation of the pixel regardless of where it is located on the screen. This occurs every 1 /60th of a second for the TMS9918A and TMS9928A and every 1/50th of a second for the TMS9929A. Thus, when moving sprites more than one pixel position during these intervals, it is possible for the sprites to have multiple pixels overlapping or even to have passed completely over one another when the VDP checks for coin- cidence.

2.3.3 Fifth Sprite Flag (5S) and Number

The 5S status flag in the status register is set to a 1 whenever there are five or more sprites on a horizontal line (lines 0 to 192) and the frame flag is equal to a 0. The 5S status flag is cleared to a 0 after the status register is read or the VDP is externally reset. The number of the fifth sprite is placed into the lower 5 bits of the status register when the 5S flag is set and is valid whenever the 5S flag is 1. The setting of the fifth sprite flag will not cause an interrupt. 2-11

24 VIDEO DISPLAY MODES

The VDP displays an image on the screen that can best be envisioned as a set of display planes sandwiched together. Figure 2-4 shows the definition of each of the planes. Objects on planes closest to the viewer have higher priority. In cases where two entities on two different planes are Occupying the same spot on the screen, the entity on the higher priority plane will show at that point. For an entity on a specific plane to show through, all planes in front of that plane must be transparent at that point. The first 32 planes (Figure 2-5) each may contain a single sprite, The areas of the Sprite Planes, outside of the sprite itself, are transparent. Since the coordinates of the sprite are in terms of pixels, the sprite can be posi- tioned and moved about very accurately. Sprites are available in three sizes: 8 x 8 pixels, 16 x 16 pixels, and 32 x 32 pixels. Behind the Sprite Planes is the Pattern Plane. The Pattern Plane is used for textual and graphics images generated by the Text, Graphics |, Graphics Il, or Multicolor modes. Behind the Pattern Plane is the backdrop, which is larger in area than the other planes so that it forms a border around the other planes. The last and lowest priority plane is the External VDP. Plane. Its image is defined by the external VDP input pin which allows the TMS9918A to mix the external video signal internal to the chip. This mixing must occur outside of the chip for the TMS9928A and TMS9929A. This is achieved through the color dif- ference outputs swinging to a special level (sync level is shown in Figure 2-6) not used by the color difference signals in normal operation. This occurs when bit 7 of Register 0 is set high. External mixing circuitry is required to detect this change in the level of the color difference signals and then switch from the VDP signals to an external source’s signals (see Figures 2-7 and 2-8). ——— a BLACK F vorcuie Me} EXTERNAL 0 4k VDP INPUT 4 |B e' [OA | BE wo BACKDROP (SOLID COLOR) 7 , PATTERNS ' , (CHARACTER-ORIENTED) 1 ! BACKDROP ; ; SPRITES (OBJECT-ORIENTED)* FIGURE 2-4 — VDP DISPLAY PLANES (DEFINITION) 2-12

is] RY [ii oe © 5 qh oh 5 Y oe itiees j han 2-13

1 | ! ' | V WHITE ——— Y | V BLACK | H 1 VsYNC = | ! ! ! ' ! 1 | | VWHITE —— I f ! I R-Y 1 iy V BLACK — 1 vsync —— \\ LEVEL 1 | ! V WHITE —— ’ | BY | * | | \\ VBLACK —— vsync —— 1 k LEVEL | ' NORMAL OPERATIONS | REGISTER olor seLecTed EXT VIDEO SIGNALS 1BIT7HIGH 'REGIsTeRO | SELECTED REGISTER O, \\ Isit7Low =! BIT7 HIGH { ' * ONLY PRESENT IN TMS9929A ; 1 os FIGURE 2-6 — TMS9928A/9929A SIGNAL WAVEFORMS FOR MULTIPLE VDP OPERATION 2-14

The backdrop consists of a single color used for the display borders and as the default color for the active display area. The default color is stored in the VDP Register 7. When the backdrop color register contains the transparent code, the backdrop automatically defaults to black if the external VDP mode is not selected. The 32 Sprite Planes are used for the 32 sprites in the Multicolor and Graphics modes. They are not used in the Text mode and are automatically transparent. Each of the sprites can cover an8 x 8, 16 x 16, or32 x 32 pixel area on its plane. Any part of the plane not covered by the sprite is transparent. All or part of each sprite may also be transparent. Sprite 0 is on the outside or highest plane, and sprite 31 is on the plane immediately adjacent to Pattern Plane. Whenever a pixel in a Sprite Plane is transparent, the color of the next plane can be seen through that plane. If, however, the sprite pixel is non- transparent, the colors of the lower planes are automatically replaced by the sprite color. There is also a restriction on the number of sprites on a line. Only four sprites can be active on any horizontal line. Addi- tional sprites on a line will be automatically made transparent for that line. Only those sprites that are active on the display will cause the coincidence flag to set. The VDP status register provides a flag bit and the number of the fifth sprite whenever this occurs. The Pattern Plane is used in the Text, Multicolor, and Graphics modes for display of the graphic pat- terns of characters. Whenever a pixel on the Pattern Plane is nontransparent, the backdrop color is automatically replaced by the Pattern Plane color. When a pixel in the Pattern Plane is transparent, the backdrop color can be seen through the Pattern Plane. The VDP has four video color display modes that appear on the Pattern Plane: Graphics | mode, Graphics I! mode, Text mode, and Multicolor mode. Graphics | and Graphics || modes cause the Pattern Plane to be broken up into groups of 8 x 8 pixels, called pattern positions. Since the full image is 256 x 192 pixels, there are 32 x 24 pattern positions on the screen in the Graphics modes. In Graphics | mode, 256 possible patterns may be defined for the 768 pattern positions with two unique colors allowed for each line of a pattern definition. Thus, all 15 colors plus transparent may be used in a single pattern position. In Text mode, the Pattern Plane is broken into groups of 6 x 8 pixels, called text positions. There are 40 x 24 text posi- tions on the screen in this mode. In Text mode, sprites do not appear on the screen and two colors are defined for the entire screen by VDP Register 7. In Multicolor mode, the screen is broken into a grid of 64 x 48 positions, each of which is a4 x 4 pixel. Within each posi- tion, one unique color is allowed. The VDP registers define the base addresses for several sub-blocks within VRAM. These sub-blocks form tables which are used to produce the desired image on the TV screen. The Sprite Pattern Generator Table and the Sprite Attribute Table are used to form sprites. The contents of these tables must ail be provided by the microprocessor. Animation is achieved by altering the contents of VRAM in real time. The VDP can display the 15 colors shown in Table 2-3. The VDP colors also provide eight different gray levels for displays on monochrome television; the luminance value in the table indicates these levels, 0.00 being black and 1.00 being white. All other values in the table are expressed as percentages of the white/black voltage swing. NOTE The gray levels differ slightly for the TMS99184 when compared to the TMS9928A/9929A. Whenever ail planes are of the transparent color at a given point, and external video is not selected, the color shown at that point will be black. 2-16

TABLE 2-3 — COLOR ASSIGNMENTS . TMS9918A TMS9828A /3929A, COLOR COLOR LUMINANCE CHROMINANCE COLOR HEX (DC) (AC VALUE) DIFFERENCE VALUE Y R-Y B-Y 0 TRANSPARENT 0.00 - - - - 1 BLACK 0.00 - 0.00 47 47 2 MEDIUM GREEN 53 53 53 .07 .20

3 LIGHT GREEN 67 40 67 17 27

4 DARK BLUE 40 60 -40 A 1.00

5 LIGHT BLUE 53 53 53 AB 93

6 DARK RED 7 47 47 83 .30 7 CYAN 67 60 73 0.00 70 8 MEDIUM RED 53 60 53 93 .27 9 LIGHT RED 67 .60 67 93 27 A DARK YELLOW 73 7 73 57 07 B LIGHT YELLOW 80 33 80 57 7 Cc DARK GREEN 46 AT 7 13 23 D MAGENTA 53 40 53 73 67 E GRAY 80 - 80 47 47 F WHITE 1.00 - 1.00 47 47 - BLACK LEVEL 0.00 - 0.00 7 47 - COLOR BURST 0.00 40 0.00 47(28A) -1(28A) 73(29A) .2(29A) - SYNC LEVEL ~0.40 - -.46 47 7 - EXTERNAL VIDEO - - 0.00 47 47

2.4.1 Graphics | Mode

The VDP is in Graphics | mode when M1, M2, and M3 bits in VDP registers 1 and 0 are zero. When in this mode the Pat- tern Plane is divided into a grid of 32 columns by 24 rows of pattern positions as shown in Figure 2-9). Each of the pattern Positions contains 8 x 8 pixel. The tables in VRAM used to generate the Pattern Plane are the Pattern Generator, Name, and Color Tables which require 2848 VRAM bytes. Figure 2-9 illustrates the mapping of these tables into the Pattern Plane. Less memory is required if all 256 possible pattern definitions are not required. The tables can be overlapped to reduce the amount of VRAM needed for pattern generation. Examples of VRAM memary allocation are provided in Section 3.3. ROW 0 cee eee a P= | > | Le fe | e ° hd ACTIVE DISPLAY AREA bd . . row Pm |= | Lm | = | eee ROW 23 7377 | @ @ o@ | 76 | 767 FIGURE 2-9 — PATTERN GRAPHICS NAME TABLE MAPPING 2-17

BASE ADDRESS =O PATTERN POSITION 1 ; 32 POSITIONS roaeoN

2 POSITION 31

° pol J J LI J

2 BASE PATTERN

N 8M PATTERN =! 24 POSITIONS am +7 (8 8YTES) | 766 767 [J PATTERN 2046 PATTERN PLANE PATTERN NAME TABLE 2047 POSITION PATTERN 767 GENERATOR TABLE (w/e) uv | | PATTERN CULOR TABLE FIGURE 2-10 — GRAPHICS | MODE MAPPING The Pattern Generator Table contains a library of patterns that can be displayed in the pattern positions. It is 2048 bytes long and is arranged into 256 patterns, each of which is 8 bytes long, yielding 8 x 8 bits. All of the 1s in the 8-byte pattern can designate one color (color 1), while all the Os can designate another color (color 0). The full 8-bit pattern name is used to select one of the 256 pattern definitions in the Pattern Generator Table. The table is a 2048-byte block in VRAM beginning on a 2-kilobyte boundary. The starting address of the table is determined by the generator base address in VDP Register 4. The base address forms the three MSBs of the 14-bit VRAM address for each Pattern Generator Table entry. The next 8 bits indicate the 8-bit name of the selected pattern definition. The lowest 3 bits of the VRAM address indicate the row number within the pattern definition. There are 8 bytes required for each of the 256 possible unique 8 x 8 pattern definitions. The first byte defines the first row of the pattern, and the second byte defines the second row. The first bit of each of the eight bytes defines the first column ‘of the pattern. The remaining rows and columns are similarly defined. Each bit entry in the pattern definition selects one of the two colors for that pattern. A 1 bit selects the color code (color 1) contained in the most significant 4 bits of the cor- responding color table byte. A 0 bit selects the other color code (color 0). An example of pattern definition mapping is pro- vided in Figure 2-11. COLUMN BIT YTE ROw/e (PATTERN) (PATTERN DEFINITION) po 123 4 5 [oo 41234 5 67 O c ccce o44.t1t144 00 1 c 000001 0 0 2 c 00000 1 0 0 3 ccce oo 1 17 1:1 0 0 4 c 0000081 0 0

5 Cc 00000 10 0

6 cc cc ¢ o141 1 1 1 14 0 0 7 00900000 0 NOTES: VDP register 7 entry: 7146. Color code 7 is cyan (signified above by ‘C’). Color code 1 is black (signified above by a space). Bit 0 is the most significant bit of each data byte. FIGURE 2-11 — PATTERN DISPLAY MAPPING 2-18

The color of the 1s and Os is defined by the Pattern Color Table that contains 32 entries, each of which is 1 byte long. Each entry defines two colors: the most significant 4 bits of each entry define the color of the 1s, and the least significant 4 bits define the color of the Os. The first entry in the color table defines the colors for patterns 0 to 7; the next entry for patterns 8 to 15, and so on. (See Table 2-4 for assignments.) Thus, 32 different pairs of colors may be displayed simultaneously. The Pattern Name Table is located in a contiguous 768-byte block in VRAM beginning on a 1-kilobyte boundary. The start- ing address of the Name Table is determined by the 4-bit Name Table base address field in VDP Register 2. The base address forms the upper 4 bits of the 14-bit VRAM address. The lower 10 bits of the VRAM address are formed from the row and column counters. An example of pattern name table addressing is given in Section 3.3. TABLE 2-4 — GRAPHICS | MODE COLOR TABLE [_srene. | raremno,[] even | rerun 0 0.7 16 128..135 1 8.15 v7 136..143 2 16.23, 18 144..151 3 24.31 19 152..159 4 32.39 20 160..167 5 40.47 21 168.175 6 48.55 22 176..183 7 56..63 23 184.191 8 64.71 24 192.199 9 72.79 25 280..207 10 80..87 26 208.215 "1 88..95 27 216.223 12 96.103 28 224.231 13 104..111 29 232..239 14 112.119 30 240..247 15 120.127 31 248-255 Each byte entry in the Name Table is either the name of or the pointer to a pattern definition in the Pattern Generator Table. The upper 5 bits of the 8-bit name identify the color group of the pattern. There are 32 groups of 8 patterns. The same two colors are used for all eight patterns in a group; the color codes are stored in the VDP Color Table. The Color Table is located in a 32-byte clock in VRAM beginning on a 64-byte boundary. The table starting address is determined by the 8-bit Color Table base address in VDP Register 3. The base address forms the upper 8 bits of the 14-bit Color Table entry VRAM address. The next bit is a 0 and the lowest 5 bits are equal to the upper 5 bits of the corresponding Name Table entries. Since the tables in VRAM have their base addresses defined by the VDP registers, a complete switch of the values in the tables can be made by simply changing the values in the VDP registers. This is especially useful when one wishes to time- slice between two or more screens of graphics. When the Pattern Generator Table is loaded with a pattern set, manipulation of the Pattern Name Table contents can change the appearance of the screen. Alternatively, a dynamically changing set of patterns throughout the course of a graphics session is easily accomplished since all tables are in VRAM. A total of 2848 VRAM bytes are required for the Pat- tern, Name, Color and Generator tables. Less memory is needed if all 256 possible pattern definitions are not required; the tables can be overlapped to reduce the amount of VRAM needed for pattern generation. Examples of VRAM memory allocation are provided in Section 3.3.

2.4.2 Graphics Il Mode

The VDP is in the Graphics Il mode bits (M1 = 0, M2 = 0 and M3 = 1). The Graphics Il mode is similar to Graphics | mode except it allows a larger library of patterns so that a unique pattern generator entry may be made for each of the 768 (32 24) pattern positions on the video screen. Additionally, more color information is included in each 8 = 8 graphics pattern. Thus, two unique colors may be specified for each byte of the 8 x 8 pattern. A larger amount of VRAM (12 kilobytes) is required to implement the full usage of the Graphics II mode. Like Graphics | mode, the Graphics Il mode Pattern Name Table contains 768 entries which correspond to the 768 pattern Positions on the display screen. Because the Graphics | mode pattern names are only 8 bits in length, a maximum of 256 Pattern definitions may be addressed using the addressing scheme discussed in Section 2.4.10. Graphics I! mode, however, segments the display screen into three equal parts of 256 pattern positions each and also segments the Pattern 219

Generator Table into three equal blocks of 2048 bytes each. Pattern definitions in the first third of the display screen cor- respond to pattern positions in the upper third. Likewise, pattern definitions in the second and third blocks of the Pattern Generator Table correspond to the second and third areas of the Pattern Plane. The Pattern Name Table is also segmented into three blocks of 256 names each so that names found in the upper third reference pattern definitions are found in the upper 2048 bytes in Pattern Generator Table. Similarly, the second and third blocks reference pattern definitions in the second 2048-byte block and third-2048 byte block, respectively. Thus, if 768 patterns are uniquely specified, an 8-bit pattern name will be used three times, once in each segment of the Pattern Name Table. The Pattern Generator Table falls on 8-kilobyte boundaries and may be located in the upper or lower half of 16K memory based on the MSB of the pattern generator base in VDP Register 4. The LSBs must be set to all 1s. The Color Table is also 6144 bytes long and is segmented into three equal blocks of 2048 bytes. Each entry in the Pattern Color Table is 8 bytes which provides the capability to uniquely specify color 1 and color 0 for each of the 8 bytes of the corresponding pattern definition. The addressing scheme is exactly like that of the Pattern Generator Table except for the location of the table in VRAM. This is controlled by the loading of the MSB of the color base in VDP Register 3. The LSBs must be set to all 1s. Figure 2-12 illustrates the Graphics I! mode mapping scheme. Note that pattern names, P1, P2, and P3, correspond to pat- tern generator entries in the three blocks of the Pattern Generator Table. Note also how these three names map to the display screen. Figure 2-13 is an example of a Pattern Generator and Pattern Color Table entry. ‘Td {2 BYTES) PATTERN POSITION 0 = 4 ° (eayTEs) | — ° — he eee uw (oA | POSITION

4 TanvEnn aa [Pattern rosirion me 25

Ce ee [he Position PATTERN GENERATOR (J rartean rosnion si 51 TABLE on 1} Sire PATTERN PosiTiON wn ° ~_ PATTERN: PL) Cp tenon « (= cd | | — PATTERN PLANE 767 a _ PATTERN NAME fears TABLE oe (eeyTes) oal___J PATTERN COLOR TABLE FIGURE 2-12 — GRAPHICS 11 MODE MAPPING : 2-20

o 3.4 7 ROWO 01000001 B 1 8 B B B B 1 | 1 (BLACK) B (LT. YELLOW)| 0 ROW 1 8B 8 7 8 B B 7B |7 (CYAN) B (LT. YELLOW] 1 3 00001000 B 8 8 B E B B B_ |E (GRAY) B (LT. YELLOW] 3 4 [9 9 6 0 1 0 o o| 8 8 8 Be BB B [8 (MED. RED) |B LT. YELLOW] 4 6 8 B B B 6 B B B_ |6 (DK.RED) | B (LT. YELLOW] 6 7 0 000%1000 8 B B B D B B B_ | D (MAGENTA)] B (LT. YELLOW)] 7 PATTERN GENERATOR PATTERN COLOR PATTERN TABLE ENTRY TABLE ENTRY FIGURE 2-13 — PATTERN DISPLAY MAPPING 2.4.3. Multicolor Mode The VDP is in Multicolor mode when mode bits M1 = 0, M2 = 1, and M3 = 0. Multicolor mode provides an unrestricted 64 x 48 color square display. Each color square contains a4 x 4 block of pixels. The color of each of the color squares can be any one of the 15 video display colors plus transparent. Consequently, all 15 colors can be used simultaneously in the Multicolor mode. The Backdrop and Sprite Planes are still active in the Multicolor mode. The Multicolor Name Table is the same as that for the graphics modes, consisting of 768 name entries, although the name no longer points to a color list. Color is now derived from the Pattern Generator Table. The name points to an 8-byte seg- ment of VRAM in the Pattern Generator Table. Only 2 bytes of the 8-byte segment are used to specify the screen image. These 2 bytes specify four colors, each color oc- cupying a4 x 4-pixel area. The 4 MSBs of the first byte define the color of the upper left quarter of the multicolor pattern; the LSBs define the color of the upper right quarter. The second byte similarly defines the lower left and right quarters of the multicolor pattern. The 2 bytes thus map into an 8 x 8-pixel multicolor pattern. (See Figure 2-14). COLORC | COLORD

2 BYTES FROM |

FIGURE 2-14 — MULTICOLOR LIST MAPPING 2-21

The location of the 2 bytes within the 8-byte segment pointed to by the name is dependent upon the screen position where the name is mapped. For names in the top row (names 0-31), the 2 bytes are the first two within the groups of 8-byte segments pointed to by the names. The next row of names (32-63) uses the bytes 3 and 4 within the 8-byte segments. The next row of names uses bytes 5 and 6 while the last row of names uses bytes 7 and 8. This series repeats for the remainder of the screen. For example, referring to Figure 2-15 if Name Table entry 0 (pattern position 0) multicolor block #N (name = N), the multicolor pattern displayed will be an 8 x 8-pixel block consisting of colors A, B, C, and D which comprise the first two bytes of the Multicolor Table. If, however, name #N is located in Name Table entry 33, (Pattern position 33), the colors displayed will be colors E, F, G, and H as specified by bytes 3 and 4 of the multicolor block pointed to by the name. Likewise, pattern positions which lie in rows 2 and 3 would cause colors |, J, K, L and colors M, N, O, P, respectively, to be displayed. Thus, it can be seen that the color displayed from the multicolor generator block is dependent upon pattern Position on the screen. Figure 2-16 illustrates the Multicolor mode mapping scheme. VIDEO DISPLAY VRAM COLOR JcoLoR

0 A 8

ROWS 0, 4, 8, 12, 16, 20 1 lcoLor D ROWS 1,5, 9, 13, 17, 21 COLOR r) 4 1 ROWS 2, 6, 10, 14, 18, 22 COLOR |coLoR

5 K L

6 COLOR

N ROWS 3, 7, 11, 15, 19, 23 7 |cotor fcotor ° P msB LSB MULTICOLOR BLOCK #N GENERATOR BLOCK #N

2 SQUARES WIDE

8 SQUARES HIGH S BYTES

FIGURE 2-16 — MULTICOLOR BLOCK DISPLAY 2-22

(a Te | Rowo fe To | [ays] ROWO [| HELE ows [ETE pow, Poe4 FEE Eon [MINT ows lo[P | 767 | now 2s _| 2047 re Tx o7] rome PATTERN NAME PATTERN GENERATOR Cc. TABLE TABLE VIDEO DISPLAY ns BYTES POINTED TO BY NAMES FIGURE 2-16 — MULTICOLOR MODE MAPPING The mapping of VRAM contents to screen image is simplified by using duplicate names in the Name Table since the series of bytes used within the 8-byte segment specifies a 2 x 8 color square pattern on the screen as a straightforward transla- tion from the 8-byte segment in VRAM pointed to by the common name. When used in this manner, 768 bytes are still used for the Name Table and 1536 bytes are used for the color information in the Pattern Generator Table (24 rows x 32 columns x 8 bytes/pattern position). Thus, a total of 1728 bytes in VRAM are required. It should be noted that the tables begin on even 1K and 2K boundaries and are therefore not contiguous. An ex- ample of multicolor VRAM memory allocation is given in Section 3.3.

2.4.4 Text Mode

The VOP is in Text mode when mode bits M1 = 1, M2 = 0, and M3 = 0. tn this mode, the screen is divided into a grid of 40 text positions across and 24 down. (See Figure 2-17). Each of the text positions contains 6 pixels across and 8 pixels down. The tables used to generate the Pattern Plane are the Pattern Name Table and the Pattern Generator Table. There can be up to 256 unique patterns defined at any time. The pattern definitions are stored in the Pattern Generator Table in VRAM and can be dynamically changed. The VRAM contains a Pattern Name Table which maps the pattern definition into each of the 960 pattern cells on the Pattern Plane (Figure 2-18), Sprites are not available in Text mode. eee eee : . ° ° oe ACTIVE DISPLAY AREA oe oe oe Pe [efit fel =| 921 eae FIGURE 2-17 — TEXT MODE NAME TABLE PATTERN POSITIONS 2-22

As with the Graphics modes, the Pattern Generator Table contains a library of text patterns that can be displayed in the text positions, It is 2048 bytes long and is arranged in 256 text patterns, each of which is 8 bytes long. Since each text position on the screen is only 6 pixels across, the least significant 2 bits of each text pattern are ignored, yielding 6 x 8 bits in each text pattern. Each 8-byte block defines a text pattern in which all the 1s in the text pattern take on one color when displayed on the screen, while all the Os take on another color. These colors are chosen by loading VDP Register 7 with the color 1 and color 0 in the left and right nibbles. respectively (see Section 2.2), o TEXT POSITION 0 1 | 40 POSITIONS —= TEXT POSITION 39

0 CJ L]

N ——+] oN" 24 POSITIONS m+? TEXT

068 PATTERN

969 M [)

2046 TEXT POSITION 959

FIGURE 2-18 — MAPPING OF VRAM INTO THE PATTERN PLANE IN TEXT MODE In the Text mode, the Pattern Name Table determines the position of the text pattern on the screen as shown in Figure 2-18. There are 960 entries in the Pattern Name Table, each 1 byte long. There is a one-to-one correspondence between text pattern positions on the screen and entries in the Pattern Name Table (40 x 24 = 960). The first 40 entries corre- spond to the top row of text pattern positions on the screen, the next 40 to the second row, and so on. The value of an entry in the Pattern Name Table indicates which of the 256 text patterns is to be placed at that spot on the Pattern plane. The Pattern Name Table is located in a contiguous 960-byte block in VRAM, beginning on a 1-kilobyte boundary. The starting address of the name table is determined by the 4-bit name table base address field in VDP Register 2. The base address forms the upper 4 bits of the 14-bit VRAM address. The lower 10 bits of the VRAM address point to 1 of 960 pat- tern cells. The name table is organized by rows. An example of Pattern Name Table addressing is given in Section 4. Each byte entry in the name table is the pointer to a pattern definition in the Pattern Generator Table. The same two colors are used for all 256 patterns; the color codes are stored in VDP Register 7. As the name implies, the Text mode is intended mainly for textual applications, especially those in which the 32 patterns- per-line in Graphics modes is insufficient. The advantage is that eight more patterns can be fitted onto one line; the disad- vantages are that sprites cannot be used, and only two colors are available for the entire screen. With care, the same text pattern set that is used in Text mode can be also used in Graphics | mode. This is done by ensur- ing that the least significant 2 bits of all the character patterns are 0. Thus, a switch from Text mode to Pattern mode results in a stretching of the space between characters, and a reduction of the number of characters per line from 40 to 32. As with the Graphics Modes, once a character set has been defined and placed into the Pattern Generator, updating the Pattern Name Table will produce and manipulate textual material on the screen. The full 8-bit pattern name is used to select 1 of the 256 pattern definitions in the pattern generator table. The table is a 2048-byte block in VRAM, beginning on a 2-kilobyte boundary. The starting address of the table is determined by the generator base address in VDP Register 4. The base address forms the 3 MSBs of the 14-bit VRAM address for each Pat- tern Generator Table entry. The next 8 bits are equal to the 8-bit name of the selected pattern definition. The lowest 3 bits of the VRAM address are equal to the row number within the pattern definition. There are 8 bytes required for each of the 256 possible unique 6 x 8 pattern definitions. The first byte defines the first row of the pattern, and the second byte defines the second row. The least significant 2 bits in each byte are not used. However, it is strongly recommended that these bits be Os. Each bit entry in the pattern definition selects one of the two colors for 2-24

that pattern. A 1 bit selects the color code (color 1) contained in the most significant 4 bits of VDP Register 7. A 0 bit selects the other color code (color 0) which is in the least significant 4 bits of the same VDP Register. Figure 2-18 is an ex- ample of pattern definition mapping. A total of 3008 VRAM bytes are required for the Pattern Name Generator Tables. Less memory is required if all 256 possi- ble pattern definitions are not required; the tables can be overlapped to reduce the amount of VRAM needed for pattern generation. Examples of VRAM memory allocation are provided in Section 3.3.

2.4.5 Sprites

The video display can have up to 32 sprites on the highest priority video planes. The sprites are special animation patterns which provide smooth motion and multilevel pattern overlaying. The location of a sprite is defined by the top left-hand cor- ner of the sprite pattern. The sprite can be easily moved pixel-by-pixel by redefining the sprite origin. This provides a simple but powerful method of quickly and smoothly moving special patterns. The sprites are not active in the Text mode. The 32 Sprite Planes are fully transparent outside of the sprite itself. The sub-blocks in VRAM that define sprites are the Sprite Attribute Table (see Figure 2-19) and the Sprite Generator Table (see Section 4.4). These tables are similar to their equivalents in the pattern realm in that the Sprite Attribute Table ‘specifies where the sprite goes on the screen, while the Sprite Generator Table describes what the sprite looks like. Sprite Pattern formats are given in Table 2-5. BIT ° 1 2 3 4 5 6 7 o VERTICAL POSITION BYTE : Pm

3 EARLY

FIGURE 2-19 — SPRITE ATTRIBUTE TABLE ENTRY TABLE 2-5 — SPRITE PATTERN FORMATS [sce | mac | anea | nesourmon | erresarreny () 8x8 single pixel 8 1 16x 16 single pixel 32 0 16x 16 2x 2pixels 8 1 32 x 32 2x 2 pixels 32 Figure 2-20 illustrates the manner in which the VRAM tables map into the existence of sprites on the display. Since there are 32 sprites available for display, there are 32 entries in the Sprite Attribute Table. Each entry consists of four bytes. The entries are ordered so that the first entry corresponds to the sprite on the sprite 0 plane, the next to the sprite on the sprite 1 plane, and so on. The Sprite Attribute Table is 4 x 32 = 128 and is located in a contiguous 128-byte block in VRAM, beginning on a 128-byte boundary. 2-25

The starting address of the table is determined by the 7-bit Sprite Attribute Table base address in VDP Register 5. The base address forms the upper 7 bits of the 14-bit VRAM address. The next 5 bits of the VRAM address are equal to the sprite number. The lowest 2 bits select 1 of the 4 bytes in Sprite 2 Attribute Table entry for each sprite. Each table entry contains 4 bytes which specify the sprite position, sprite pattern name, and color, as shown in Figure 2-19. vRam a at / SS) pep [YX] “AR Map SPRITE ATTRIBUTE TABLE SPRITE GENERATOR TABLE FIGURE 2-20 — SPRITE MAPPING The first two bytes of each entry of the Sprite Attribute Table determine the position of the sprite on the display. The first byte indicates the vertical distance of the sprite from the top of the screen, in pixels. It is defined such that a value of —1 Puts the sprite butted up at the top of the screen, touching the backdrop area. The second byte describes the horizontal displacement of the sprite from the left edge of the display. A value of 0 butts the sprite up against the left edge of the backdrop. Note that all measurements are taken from the upper left pixel of the sprite. When the first two bytes of an entry position a sprite so it overlaps backdrop, the part of the sprite that is within the backdrop is displayed normally. The part of the sprite that overlaps the backdrop is hidden from view by the backdrop. This allows the animator to move a sprite into display from behind the backdrop. The displacement in the first byte is partially signed, in that values for vertical displacement between —31 and 0 (E116 to 0) allow a sprite to bleed-in from the top edge of the backdrop. Similarly, horizontal displacement values in the vicinity of 255 allow a sprite to bleed-in from the right side of the screen. To allow sprites to bleed-in from the left edge of the backdrop, a special bit in the third byte of the Sprite Attribute Table entry is used. Byte 3 of the Sprite Attribute Table entry contains the pointer to the Sprite Generator Table that specifies what the sprite should look like. This is an 8-bit pointer to the sprite patterns definition, the Sprite Generator Table. The sprite name is similar to that in the Graphics Modes. Byte 4 of the Sprite Attribute Table entry contains the color of the sprite in its lower 4 bits (see Table 2-3 for color assignments). The MSB is the Early Clock (EC) bit. When set to 0, this bit does nothing. When set to 1, the horizontal Position of the sprite is shifted to the left by 32 pixels. This allows a sprite to bleed-in from the left edge of the backdrop. Values for horizontal displacement (byte 2 in the entry) in the range 0 to 32 cause the sprite to overlap with the left-hand border of the backdrop. The Sprite Generator Table is a maximum of 2048 bytes long beginning on the 2-kilobyte boundaries. {t is arranged into 256 blocks of 8 bytes each. The third byte of the Sprite Attribute Table entry, then specifies which 8-byte block to use to specify a sprite’s shape. The 1s in the Sprite Generator cause the sprite to be defined at the point; Os cause the transparent color to be used. The starting address of the table is determined by the sprite generator base address in VDP Register 6. The base address forms the 3 MSB of the 14-bit VRAM address. The next 8 bits of the address are equal to sprite name, and the last 3 bits are equal to the row number within the sprite pattern. The address formation is slightly modified for SIZE, sprites. There is a maximum limit of four sprites that can be displayed on one horizontal line. If this rule is violated, the four highest- Priority sprites on the line are displayed normally. The fifth and subsequent sprites are not displayed on that line. Further- more, the fifth-sprite bit in the VDP status register is set to a 1, and the number of the violating fifth sprite is loaded into the status register (see Section 2.3). 2-26

Larger sprites than 8 x 8 pixels can be used if desired. The MAG and SIZE bits in VDP register 1 are used to select the various options described in the following paragraphs. MAG =0,SIZE=0: No options chosen MAG = 1,SIZE=0 The Sprite Generator Table uses 8 bytes to describe the sprite; however, each bit in the Sprite Generator maps into 2 x 2 pixels on the TV screen, effectively doubling the size of the sprite to 16 x 16. MAG =0,SIZE = 1: The Sprite Generator Table uses 31 bytes to define the sprite shape; the result is a 16 x 16-pixel sprite. The mapping of the 32 bytes into the sprite image is as shown in Figure 2-21. Mapping is still 1 bit to 1 pixel. MAG = 1,SIZE=1: Same as MAG = 0, SIZE = 1 except each bit now maps into a2 x 2-pixel area, yielding a 32 x 32 sprite. The VDP provides sprite coincidence checking. The coincidence status flag in the VDP status register is set to a 1 whenever two active sprites have 1 bits at the same screen location. Sprite processing is terminated if the VDP finds a value of 208 (D016) in the vertical position field of any entry in the Sprite Attribute Table. This permits the Sprite Attribute Table to be shortened to the minimum size required; it also permits the user to blank out part or all of the sprites by simply changing one byte in VRAM. A total of 2176 VRAM bytes are required for the Sprite Name and Pattern Generator Tables. Significantly less memory is required if all 256 possible sprite pattern definitions are not required. The Sprite Attribute Table can also be shortened as described in the preceding paragraph. The tables can be overlapped to reduce the amount of VRAM. required for sprite generation. Examples of VRAM memory allocation are provided in Section 3.3. 2-27

02 PATTERN

03 FOR SCREEN DISPLAY

04 JauaDRANT A

09 QUADRANT | QUADRANT

16x16 (MAGO) 32x32 (MAG1) " PATTERN

12 FOR

13 [QUADRANT C 1A PATTERN 1B FOR 1c [QUADRANT D FIGURE 2-21 — SIZE 1 SPRITE MAPPING 2-28

2.4.6 A Step-by-Step Approach to Create Patterns and Sprites

1. Use an 8 x 8 pattern similar to that in Figure A. Each small square represents one pixel on the screen. LTT TTT TT Seen eee Seeeeeee BREE LT TTT Ty See LITT TT YT) FIGURE A 2. Fill in the blocks to create your text character or graphics pattern. Examples of the letter A and an ARROW are shown in Figures B and C. ae See LTT TTT TT 2 8B Eee TTT TT EEE BEE eee BEE BEB aan OU ann SEB EE | [| | | nn Sen eee 2 LETT) TT Ty | LITT ETT Pt) FIGURE B FIGURE C NOTE If these patterns are to be used in the Text mode, (40 patterns per line), the pattern should be inside a left-justified 6 = 8 block like the A shown in Figure 8. If all of the Text patterns are inside this 6 x 8 block, they can be used for Text and Graphics 1 and 2 modes. 2-23

1. Assign 1s to the filled-in areas and Os to the blanks. Then convert the 1s and Os to their hexadecimal equivalents, as shown in Figure D. TT Tf TT | = 20100000 = 20(16) TW IL] <0 1010000 = 50,16) TT BL] - 10001000 = 88/16) Ct Te | I | = 10001000 = 8816) 1 | tT | [| = 10001000 = sa16) CT TTY = 10001000 = 8816) rE TL TT TTY = c0000000 = 00/16) PTT TT TT TY = ene) PTT TT = 0008) BERSS BER EEEee || = 06,16) = FF(16) ETT |_| = 0616) BERES OBE CELT TTT Tf 006) PT TT TT TJ = 216) Pt tt | = cone PT TT = 20116) PT TT = 6 Pt TTT TY - 2006) PTT TT = con PT TF = 20116) Bn = FC(16) FIGURE D 2-30

1. Now place the eight bytes defining the pattern into the Pattern Generator Table. Assume the Pattern Generator Table sub-biock is located at 800, 6 and the arrow pattern is to be named 00, 6 Then place the eight pattern bytes as follows: wo [4 a a soz [4 a a PATTERN oo a a NAME 00 eos [06d cs es a ws fd Ce on a PATTERN nn NAME 01 Ce a sor [ so =f rs a | Cs go2 [00 | 93 [ oO | PATTERN Cl NAME 20 95 | oo | %6 [oo | 907 {oo os f aos [20 aos [so | AOA PATTERN A0B NAME 41 aoc [Fes | a0D Ane NOTE When using text in your applications, you can place the eight bytes of the text character in its ASCII number location. Example: ASCII SPACE = 2016 ? = 3Fig A= 4146 B= 4216 C = 4346 Ete. This simplifies writing text to the screen. Simply write the ASCII name directly to the Pattern Name Table. A space character is shown in Pattern Generator Table position 20, and A is shown in pattern name 41. 2-31

1. Determine whether to use 8 x 8 or 16 x 16 sprite patterns. Then use the appropriate work pattern, as shown in Figures E and F. LT TTT TTT TTT tt tt LETT Teer rey SRR LETT rte ere ey SRR SERRE Ree LITT eT e SERRE LT TT rT ry LETT TTT Trey SERRE Petr t reer eee SRR PT Te Tt SRS SREEEEEe PTT reer SeeeeeEe SRR eee LEP eet tT PEP Trey LUT TTT Tt | LI TET TT TTT tt tr FIGURE E FIGURE F 2. Fill in the blocks to create your sprite pattern. Examples are shown in Figures G and H. [| | To aan aan 0 6B Ean SRR San SRE Lt Ty | | HH HH Saeeu8 SER an | aT aan =n oo. me coe : San 6 BEEREEREEEEE 6 an 88 88 SEEREREEEEEE 6B @ S8en 8 aan LTT TTT | SaaB FIGUREG FIGURE H 2-32

1. Next encode the sprite patterns as in the Pattern Section. The8 x 8 sprite encodes exactly as the 8 x 8 pattern, but the 16 x 16 sprite encodes as shown in Figure J. o- (TTT) “FF w-T TT = FE so-t Te TT TT -00 [288 SRR 3e-( | ro sr={ [I | | rs 3F= | | |=Fs SEEEEE ii se- [| | || =re | - or- TT «rs Be 88 Be LLL TH = rs Bae BEE oo-[ TTT TTT TT TT) BT] -1 Ban Se, oo-[] TT TT TT TTT iT] - 1 | | oo-L ETT TT Re | | ais S eee Be FE= EBEE;: BEEEEE i FF= BREESE. FIGURE! FIGURE J Break the 16 x 16 block pattern into four 8 x 8 patterns. Next, encode the 8 x 8 patterns starting in the upper left corner, then do the lower left, upper right, and lower right. 2:33

1. Place the 8 bytes for 8 x 8 sprites or 32 bytes for 16 x 16 sprites in the Sprite Generator Table. Assuming the sprite generator table is located at location 0000, Figures K and L show how the tables should look for 8 x 8 and 16 x 16 sprites. 8X8 16X16 000 [31 | 000 [oF | 001 | 42 001 [ 1F | 002 [24 002 [30 | Ce a 004 = [48] NAMEO og = [3 | 005 [24 005 [3F | 006 [42__| 006 [3F | ‘UPPER LEFT 007 [3 i 007 [_3F | CORNER

008 I 008 [3F

009 Cd 009 | 3F |

00a [| SPRITE 00a [| 1F | 008 [| NAME 01 0B | 00 | oc a ooc [00 | 00D | 00D [| 00 | Lower O0E OoE [| FF | LEFT SPRITE OOF [| ooF [FF | CORNER NAME 00 010 010 [| FF 011 | FF 012 [oo | FIGURE K 013 [| 00 | 014 | Fo | 015 | F8 | UPPER 016 [Fs | RIGHT 017 [Fs | CORNER 018 | Fe | O1A | Fs | 018 [ 1 | o1c [18 | Lower 01D [18 | RIGHT O1E [Fe | ~CORNER o1F | Fo | 020 SPRITE NAME 04 FIGUREL 16 x 16 sprite patterns start in the table with the byte from the upper left-hand corner. Then start with the upper right, going toward the lower right. . 2-34

1. VDP INTERFACES AND OPERATION

3.1 VDP/VRAM INTERFACE

The VDP can access up to 16,384 bytes of VRAM using a 14-bit VRAM address. The VDP fetches data from the VRAM in order to process the video image described later. The VDP also stores data in or reads in data from the VRAM during a CPU-VRAM data transfer. The VDP automatically refreshes the VRAM. 3.1.1. VRAM Interface Control Signals The VDP-VRAM interface consists of two 8-bit data buses (RDO-RD7 unidirectional, ADO-AD7 bidirectional) and three control lines, as shown in Figure 3-1. The VRAM outputs data to the VDP on the VRAM read data bus {RDO-RD7}. The VDP outputs both the address and data to the VRAM over the VRAM address/data bus (ADO-AD7). The VRAM row address is output when RAS is active (low). The column address is output when CAS is active (low). Data is output to the VRAM when R/W is active (low). 3.1.2. VRAM Memory Types The VDP can use 4027-type 4K, 4108-type 8K, or 4116-type 16K dynamic RAMs. The 4/16K bit in VDP register 1 is a0 for 4027-type RAMs and a 1 for 4108- and 41 16-type RAMs. There is a minor difference between the way 4027s and 4108s/4116s are wired to the VOP. In the 4027, all CE pins are tied to ground. in the 4108/4116 the AG lines on the 4116 and 4108 (the same pin as CE on 4027's) are all tied to AD1 on the TMS9918A. A jumper can be used to select the VRAM type.

3.1.3 VDP to DRAM Address Connections

The VDP can be easily connected to either the 4027 or 4116 DRAMs. However, due to different pin numbering standards, it is possible to connect the VDP to the DRAMs incorrectly. Table 3-1 shows the recommended way to connect a VDP to either DRAM. Other DRAMs, such as the single +5 V supply type, can also be used by following the 4K or 16K columns in Table 3-1. TABLE 3-1 — VDP TO DRAM ADDRESS CONNECTIONS 4027 VDP or 4K ADO DATA ONLY DATA ONLY ADI AG DATA ONLY AD2 AS AS AD3 A4 A4 AD4 A3 A3 ADS A2 A2 AD6 Al Al AD7 AO AO When connecting the data ports together, ensure that corresponding RAMs (assuming 8 by 1 DRAMs) are properly con- nected to the corresponding input or output of the VDP. For example, ADO of the corresponding input or output D input of the RAM, and RDO of the VDP should connect to the Q output of the same RAM. The same is true for all AD and RD corresponding pins for each of the eight DRAMs. NOTE CDO is the MSB of the CD bus; CD7 is the LSB. ADO is the MSB of the AD bus; AD7 is the LSB. RDO is the MSB of the RD bus; RD7 is the LSB. RAMs have the reverse convention. AD7 is the MSB of the AD bus, and ADO is the LSB. Therefore, AD7 of the VDP connects to AD of the 4116, and AD1 connects to A6. Data coming into the VDP on CDO goes to VRAM on ADO and returns to the VDP on RDO.

eS a OW = ayy (SO 2 RD7 Cl D 5 we PY aoas wc RDS Pd 8 RD4 . g ® RDS : @ 8 RD2 = __ : $ © rp eee ee : @ > RDO gs a HES Zo 08 ™ Ta 8 a a Trico og

5 Os TTT}

on a, AD1 ADO RAS LI} cas Low 5 rTT]> PT TTD aoa ll RAS CAS W g fe) € D = a 1 FIGURE 3-1 — VRAM INTERFACE

3.2 VRAM MEMORY ADDRESS DERIVATION

Table 3-2 summarizes the VRAM address derivation for all VDP modes of operation. Section 4 of this manual contains examples of how typical VRAM addresses are computed by the VDP. TABLE 3:2 — PATTERN GRAPHICS ADDRESS LOCATION TABLES GRAPHICS | MODE ADDRESS LOCATION appress tye [o[s]2]3]«]s[e]7]e[e]tofssfrafia] commeNTs 1) PATTERN PATTERN NAME TABLE BASE (VDP REG2) NAME [Row | PATTERN POSITION ADDRESS 2) PATTERN cOLe PATTERN COLOR TABLE BASE (VDP REGS) COLOR [o| ALWAYS "0" IN BIT 8 ADDRESS NAME (0-4) FIVE MOST SIGNIFICANT BITS OF NAME 3) PATTERN [pce | PATTERN GENERATOR BASE (VDP REG4) GENERATOR [NAME i ALL 8 BITS OF NAME ADDRESS THREE LSB’S FORM PATTERN ROW POSITION GRAPHICS Il MODE ADDRESS LOCATION appress tvee [o[s]2]3]4[s]e]7[ale]iofipzfs] COMMENTS 1) PATTERN PATTERN NAME TABLE BASE (VDP REG2) NAME [Row | PATTERN POSITION ROW ADDRESS [COLUMN | PATTERN POSITION COLUMN 2) PATTERN ] PATTERN COLOR TABLE BASE MSB (VDP REG3) COLOR [xx ] ‘TWO MSB FROM VERTICAL COUNTER ADDRESS ALL 8 BITS OF NAME [ xXxx_] COLOR TABLE BYTE/LINE 3) PATTERN [I PATTERN NAME TABLE BASE MSB (VDP REG4) GENERATOR [xx ] ‘TWO MSB FROM VERTICAL COUNTER ADDRESS [NAME | ALL 8 BITS OF NAME [_xxx_| PATTERN GENERATOR BYTE/LINE NUMBER TEXT MODE ADDRESS LOCATION appress tvee [o]+]2]3]4[s]s[7[s[oftofspapa] comments TEXT MODE PATTERN NAME TABLE BASE (VOP REG2) NAME ADDRESS EQUAL (TEXT POSITION ROW # TIMES 40) PLUS (TEXT POSITION COLUMN NUMBER) TEXT MODE [ PGB | PATTERN GENERATOR BASE (VDP REG4) PATTERN [Name NAME ADDRESS L_xxx_] BYTE/LINE NUMBER

TABLE 3.2 — PATTERN GRAPHICS ADDRESS LOCATION TABLES (CONTINUED) SPRITE ADDRESS LOCATION aporess vee [o[1[2[3[4[s[s[7[s[e[ioffizis] COMMENTS | SPRITE [sAB—i«ds| SPRITE ATTRIBUTE TABLE BASE (VDP REGS) ATTRIBUTE [SPRITE | SPRITE NUMBER ADDRESS Uxx™ ATTRIBUTE NUMBER:

00 FOR VERTICAL POSITION

01 FOR HORIZONTAL POSITION

10 FOR NAME

11 FOR TAG (EARLY CLOCK AND COLOR)

SIZE =0 [ sPGB_ | SPRITE PATTERN GENERATOR BASE (VDP REG4) SPRITE PATTERN [Name NAME ATTRIBUTE OF SPRITE GENERATOR L xxx] THREE LSB’S GIVE BYTE/LINE NUMBER SIZE=1 [seca] SPRITE PATTERN GENERATOR BASE (VDP REG4) SPRITE PATTERN [NAME (0-5) | SIX MSB OF NAME GENERATOR [_XXXxX——_ | SIZE = 1 SPRITE BYTE NUMBER (SEE FIGURE 44) MULTICOLOR ADDRESS LOCATION aopnesstvee [ols [2[s[s[s[s[7[e[o[toffafis[ comments 4) MULTICOLOR NAME TABLE BASE (VDP REG2) NAME [Row its PATTERN POSITION ROW ADDRESS COLUMN PATTERN POSITION COLUMN 5) MULTICOLOR [ PGB | PATTERN GENERATOR BASE (VDP REG4) COLOR [NAME | NAME FROM NAME FETCH GENERATOR [_ Xxx} THREE LSB’S FORM BYTE/SQUARE ROW ADDRESS The TMS9918A/9928A operates at 262 lines per frame and approximately 60 frames per second in a noninterlaced mode of operation. The TMS9929A operates at 313 lines per frame and approximately 50 frames per second in a noninterlaced mode of operation.

3.3 VRAM ADDRESSING EXAMPLE

A typical application might require up to 256 unique 8 x 8 patterns with no more than 2 colors per pattern and up to 32 8 x 8 sprites. These conditions dictate in which mode the VDP is to be used. The sprite requirement and the 8 x 8 pattern blocks eliminate the text and multicolor modes, respectively. This leaves onty the Graphics | and Graphics I! modes, and since two colors per block are all that are necessary, Graphics | is employed due to its ease of use. Figure 3-2 shows a memory map that allows these functions to fit into a 4K memory area. Register values for Figure 3-2 are as follows: Register 0 = 00 External VOP disabled, M3 = 0 Register 1 = CO 16K DRAM selected, Blank = 1, Graphics 1 mode selected, SIZE = 0, MAG = 0 Register 2 = 01 Name Table Start Address @ > 400 Register 3 = 08 Color Table Start Address @ >0200 Register 4 = 01 Pattern Generator Start Address @ > 800 Register 5 = 02 Sprite Attribute Table Start Address > 100 Register 6 = 00 Sprite Pattern Generator Start Address @>0000 Register 7 = XX Determined by user.

0000 If the same application required 16 x 16 bit sprites, then the

SPRITE memory map could be modified as f 5 GENERATOR 32.8 X 8 PATTERNS y map follows: TABLE ooFF 0000

0100 SPRITE 32 18 X 16 SPRITES

SPRITE 32 SPRITES X 4 BYTES GENERATOR 32 SPR X 32 BYTES ATTRIBUTE ='80 BYTES TABLE carr 7 1024 BYTES TABLE ovr PATTERN 0400

0180 NAME 24 LINES X 32 CHAR

TABLE = 768 CHAR O1FF OsFF COLOR ome SPRITE 0700 42 SPRITES X 4 BYTES TABLE 32 BYTES ATTRIBUTE = 128 BYTES 021F TABLE 0736 0220 0740 O3FF COLOR 32 BYTES

0400 TABLE

PATTERN 24 LINES X 32 CHARACTERS O75F ee = 768 BYTES NUSED 0760 O6FF UNUS| | mse | oe ™ UNUSED PATTERN

0800 SUB-BLOCK

PATTERN 256 PATTERNS X 8 BYTES/PATTERN OFFF GENERATOR 048 BYTES -BLOCK SuBB OFFF FIGURE 3:2 — VDP-VRAM MEMORY ALLOCATION

3.4 MONITOR INTERFACES

3.4.1. TMS9918A Monitor Interface The composite video output signal from the TMS9918A drives a color monitor. This signal incorporates all necessary horizontal and vertical synchronization signals as well as tuminance and chrominance information. In monitor applications, the requirements of the monitor should be studied to determine if the VDP can be connected directly to it. The internal out- put buffer device on the composite video pin is a source-follower MOS transistor that requires an external pull-down resistor to Vs: as shown in Figure 3-3. Typically a 330-ohm resistor is recommended to provide a 1.9-volt synchronization level. The lost resistor (RL) defines the sharpness of the edges on the video signals. A lower resistor value gives faster fall times and a sharper picture. In some cases, it may be necessary to provide a simple interface circuit to match the VDP output voltages with the monitor specifications. To drive a standard television that is not outfitted with a composite video input, the signal can be run into the television antenna terminals by using an appropriate RF modulator on the VDP output. Take care to ensure a proper match between VDP, RF modulator, and TV. Vec TMS9918A - VDP — COMPOSITE VIDEO OUTPUT Rext 3302 TYP FIGURE 3-3 — COMPOSITE VIDEO PULL-DOWN CIRCUIT

3.4.2 TMS9928A/9929A Monitor Interface

The Y, R-Y and B-Y output signals require external encoder circuitry to drive a video color monitor; an R-G-B matrix cir- cuitry is required to drive R-G-B color monitors. The Y output signal contains all necessary horizontal and vertical syn- chronization signals as well as luminance while the R-Y and B-Y signals contain the unmodulated chrominance information and are used in the NTSC and PAL systems to modulate two carriers in quadrature. The internal output buffer devices on these pins are source-follower MOS transistors that require an external pull-down resistor to Vgg: as shown in Figure 3-4, A 330 ohm resistor is recommended. VDP CRYSTAL

4 R-Y R

—— tl 470 | G rmseezea/saz0, BY ENCODER/

470 DRIVER ;

SYNC > Oommm | - oy (OPTIONAL) RGB MONITOR 470 \\ BURST CRYSTAL VDP CRYSTAL (4.43 MHz TMS9929A) PAL 10.738 MHz (adjustable) color (3.58 MHz TMS9928A) NTSC R-Y 470 a COMPOSITE

1 VIDEO VIDEO 7

= NCODER/ vpp zm] BY e TMs9928A/99290 DRIVER (NTSC/PAL) al) 470 —— + VIDEO MONITOR a - YY 470 NOTE: The LM18839 is typically used in the video encoder circuitry. FIGURE 3-4 — USE OF TMS9928A/9929A WITH DIFFERENT MONITORS.

3.5 TMS9918A EXTERNAL VDP OPERATION

The external VDP interface allows cascading multiple VDPs. Figures 3-5 and 3-6 illustrate cascading two VDPs. Note that the VDPs must be reset by a common reset source to assure synchronization on an open loop basis. This reset source should have fast edges so that rise and fall times are less than 30 ns. Occasionally, synchronization is not obtained after reset, in which case, reset should be reapplied. The video matching circuit ensures that the video signal of external VDP is biased correctly and of the proper amplitude. This ensures the luminance levels of the external and VDP colors are matched and external VDP video does not bleed through into the composite video output of the first VDP. The internal circuit assures that a perfect match results if the external video is of the same amplitude as the composite video of the VDP and its dc level is increased by a MOS threshold voltage (typically 0.7 volts). This adjustment can be varied to change the relative luminance levels of the two video signals and thus modify the picture appearance. XTAL 10.738635 MHz XTAL1 XTAL2 XTAL1 XTAL2 TMS9918A, TMS9918A MIDEO TO MONITOR COMVID MATCHING EXTVDP COMVID OR RF MONITOR CIRCUIT RESET/SYNC RESET/SYNC FROM RESET SOURCE FIGURE 3-5 — CASCADING TWO TMS9918A VDPs XTAL 10,738635 MHz EXT MODE VvoP vpP MASTER SLAVE BY DETECT BY (EXTERNAL) AND SOURCE LECT RESET/SYNC | RESET/SYNC RY BY Y (SELECTED) FROM RESET SOURCE FIGURE 3-6 — CASCADING TWO TMS9918A/9929A VDPs

For the External VDP input plane to be visible, the External VDP Enable bit in VDP Register 0 (EXVID) should be set to a 1. The backdrop color (VDP Register 7, lower 4 bits) should be set to transparent (0). For the external VDP plane to show through at a given spot on the screen, the pattern color at that spot should be transparent, and all sprites should not be in the way (alternatively, a sprite that was in the way could be made transparent in color). Note that the external VDP feature can be used in either Graphics |, Graphics II, Text, or Multicolor mode.

3.6 OSCILLATOR AND CLOCK GENERATION

The VDP is designed to operate with a 10.738635 (+ 0.005) MHz crystal input to generate the required internal clock signals. A fundamental-frequency parallel-mode crystal is the frequency reference for the internal clock oscillator, which is the master time base for all system operations. This master clock is divided by two to generate the pixel clock (5.3 MHz) and by three to provide the CPUCLK (3.58 MHz for TMS9918A only). The GROMCLK is developed from the master clock frequency divided by 24 (3.58 MHz for TMS9928A only).

3.6.1 TMS9918A Color Phase Generation

The 10.7 + MHz master clock and its complement generate an internal six-phase 3.579545 MHz (+ 10 Hz) clock to pro- vide the video color signals and the color burst reference used in developing the composite video output signal. While the VOP signals are not exact equivalents to the standard NTSC colors, the differences can easily be adjusted with the color and tint controls of the target color monitor.

3.6.2 Video Sync and Control Generation

Decoding the outputs of the horizontal and vertical counters generates the horizontal and vertical control signals. The pixel clock drives the horizontal counter which in turn increments the vertical counter. Table 3-3 gives the relative count values of the screen display parameters. Within the active display area during Graphics | mode, the three LSBs of the horizontal counter address the individual picture element of each pattern displayed. Also, dur- ing the vertical active display period, the three LSBs of the vertical counter address each individual line in the 8 x 8 pat- terns. The Graphics I, Multicolor and Text modes use the counters similarly. The TMS9918A/9929A operates at 262 lines per frame and approximately 60 frames per second in a noninterlaced mode of operation. The TMS9929A operates at 313 lines per frame and approximately 50 frames per second in a noninterlaced mode of operation. TABLE 3:3 — SCREEN DISPLAY PARAMETERS PATTERN OR TEXT MULTICOLOR HORIZONTAL ACTIVE DISPLAY 256 240 RIGHT BORDER 18 25 RIGHT BLANKING 8 8 HORIZONTAL SYNC 2 2 LEFT BLANKING 2 2 COLOR BURST 14 14 LEFT BLANKING 8 8 LEFT BORDER 13 19 342 342 a VERTICAL ACTIVE DISPLAY 192 BOTTOM BORDER 24 BOTTOM BLANKING 3 VERTICAL SYNC 3 TOP BLANKING 13 TOP BORDER 27 262 3-8

37 VDP TERMINAL ASSIGNMENTS

3.7.1 TMS9918A Terminal Assignments

SIGNATURE ] termina | vo | DESCRIPTION XTALI, __ XTAL2 40,39 t 10.7 + MHz crystal inputs* RAS qi 40 f) XTAL2 CAS 2 39 D XTAL1 CPUCLK 38 ° VDP color burst frequency clock. AD7 q 3 38 Pp CPUCLK Typically not used on the AD6qQ4 37 [| GROMCLK TMS9918A, this is the color burst ADS 4 5 36 Pp comviD frequency clock. A04 76 35 DP EXTVOP AD3 G7 34 Pp RESET/SYNC GROMCLK 37 ° VOP output clock = XTAL/24, A02q8 33 p Vec Typically not used. Adl gs 32 DP RDO Apo q 10 31 p ROW COMVID 36 fe) Composite video output for the R/Wd 11 30 P RD2 TMS9918A. Vss 9 12 28 P RDS MODE q 13 28 P RD EXTVDP 35 vo On the TMS9918A, this is the exter- CSW q 14 27 f ROS nal VP input. CSR q 15 26 P RDS INT q 16 25 PRO? RESET/ co7 q 7 24 PcDo SYNC 34 | The RESET pin isa trilevel input pin, CO6 q 18 23 cor When it is below 0.8 volts, RESET C05 q 19 22 pcp2 initializes the VDP. When it is above CD4 q_20 21 pcos 9 volts, RESET is the synchronizing input for external video. Vec 33 ! +65 volt supply RDO MSB 32 1 VRAM read data bus RDI 31 ' RD2 30 ' RDS 29 ' RD4 28 1 RDS 27 1 RD6 26 I RD7 25 ' cDO MSB 24 0 CPU data bus; (CD0) is the most significant bit cot 23 vo cb2 22 vo CD3 21 vo CcD4 20 vo CDS 19 VO cD6 18 vo CO7 LSB 17 Vo INT. 16 ° CPU interrupt output. CSR 15 I CPU-VDP read strobe ctsw 14 ! CPU-VDP write strobe MODE 13 ! CPU interface mode select; usually a processor address line * When driven externally, both inputs must be driven. ** The least significant address bit (AD7) is wired to AQ of the dynamic RAMs. Likewise, AD6 is wired to A1 of the RAMs. Care must be exercised in assuring proper orientation of the TMS 9918A address outputs to the dynamic RAM address in- puts.

TMS9918A Terminal Assignments (continued) SIGNATURE TERMINAL DESCRIPTION Vss 12 ! Ground References RW n [e) VRAM write strobe ADO MSB 10 ° VRAM address/data bus (multiplexed high and low order VRAM address and output data bytes) AD1 9 O° ADO is the most significant bit and is used only for data and not for addressing. ** AD2 8 ° AD3 7 ° AD4 6 ° ADS 5 ° ADE 4 ° AD7 3 ° CAS 2 ° VRAM column address strobe RAS 1 ° VRAM row address strobe * When driven externaily, both inputs must be driven. ** The least significant address bit (AD7) is wired to AQ of the dynamic RAMs. Likewise, AD6 is wired to Al of the RAMs. Care must be exercised in assuring proper orientation of the TMS 9918A address outputs to the dynamic RAM address in- puts. 3-10

3.7.2. TMS992BA/$929A Terminal Assignments SIGNATURE | rermivar | v0 | DESCRIPTION XTAL1, XTAL2 40,39 1 10.7 + MHz crystal inputs* RAS (3 40 P XTAL2 CAS q 2 39 P XTAL1 R-Y 38 fe) VDP color burst frequency clock. On An7 q3 xwbry the TMS9928A/9929A, this is the AD6 g 4 37 b GROMCLK R-Y color difference output. ADS U5 weDpDY AD4 U6 33 P BY GROMCLK 37 ° VDP output clock = XTAL/24, AD3 q 7 34 D RESET/SYNC Typically not used. A028 33 f Vee ADI Q9 32 D RDO Y 36 fe) Composite video output. On the ADO g 10 31 ROW TMS9928A/9929A, this is the Y RW 30 P ROZ (black/white luminance and com- Vssg G 12 23 0 ROS posite sync) output. MODE g 13 28 D RDA CSW q 14 27 DROS B-Y 35 vo External VDP input. On the CSR q 15 26 PROG TMS9928A/9929A, this is the B-Y INT 16 2 PRO? color difference output. co7 g 7 24 D cDo cDé q 18 23 pco1 RESET/ CDS g 19 22 Pco2 SYNC 34 1 The RESET pin is a trilevel input pin. C04 g 20 21 pcp3 When it is below 0.8 volts, RESET initializes the VDP. When it is above 9 volts, RESET is the synchronizing input for external video. Vec 33 1 +65 volt supply RDO MSB 32 i} VRAM read data bus RD1 31 ' RD2 30 ' RD3 29 1 RD4 28 1 RDS 27 1 RDG 26 1 RO7 25 1 CDO MSB 24 vo CPU data bus; (CDO0) is the most significant bit cD1 23 vo cD2 22 vo CD3 21 vo cD4 20 Tie} CDS 19 vo CDé6 18 v0 CD7 LSB 7 vo INT. 16 Le} CPU interrupt output. csr 15 ! CPU-VDP read strobe csw 14 ' CPU-VDP write strobe MODE 13 1 CPU interface mode select; usually a processor address line * When driven externally, both inputs must be driven. ** The least significant address bit (AD7) is wired to AO of the dynamic RAMs. Likewise, AD6 is wired to At of the RAMs. 311

SIGNATURE TERMINAL vo DESCRIPTION Vss 12 1 Ground References R/W 1 ° VRAM write strobe ADO MSB 10 fe) VRAM address/data bus (multiplexed high and low order VRAM address and output data bytes) ADI 9 ° ADO is the most significant bit and is used only for data and not for addressing.** AD2 8 ° AD3 7 fe) AD4 6 fe) ADS 5 ° AD6 4 ° A07 3 [e) cas 2 ° VRAM row address strobe RAS 1 fe) VRam row address strobe * When driven externally, both inputs must be driven. ** The least significant address bit (AD7) is wired to AQ of the dynamic RAMs. Likewise, AD6 is wired to At of the RAMs.

3.7.3 TMS9918A/9928A/9929A Crystals

Crystals for the TMS9918A/9928A/9929A can be purchased from the following: NDK

10080 North Wolfe Rd

Cuppertino, CA 95014 Telephone: (408)255-0831 Telex: 352057 CTS Knights, Inc.

400 Reiman Ave

Sandwich, ill 60548 Telephone: (815)786-8411 312

1. DEVICE APPLICATIONS This section describes the hardware and software interface between a TMS9918A/9928A/9929A VDP and a TMS9900 microprocessor. Some considerations in the use of the VDP for text and graphics applications are also described.

41 VDP TO TMS9900 INTERFACE

The circuit shown in Figure 4-1 illustrates a very simple interface between a TMS9900 microprocessor and a TMS9918A/9928A/9929A. In this circuit, the VDP 8-bit data bus is connected to the 8 MSBs of the TMS9900 16-bit data bus. For mode selection, A14 of the TMS9900 is connected to the mode input pin. Read and write signals to the VDP aie as follows: CSR =A0*A13*DBIN CSW =A0*WE . anne i on _ ats |} csr DBIN TMS9918A VDP TMS9900 CPU FC 87 6] 88 ee nS td 8 8 3 BB 2B? A a ( cDoO cbDOo FIGURE 4-1 — MINIMUM SYSTEM INTERFACE TO TMS9900 DBIN and WE are signals from the TMS9900 which indicate direction flow on the data bus. DBIN is high when the CPU is attempting to do a read data operation, while WE is low when the CPU is outputting data onto the data bus. AQ is used as a VDP select signal. Thus, the VDP is activated whenever the CPU is reading or writing data in the upper half of its address space (> 8000 and above). All addresses above > 8000 then become VOP port addresses. However, in a more sophisticated design, more decoding of the address lines would be done to select only those unique addresses required by the VDP. The purpose of A13 and decoding logic is to generate unique addresses for read and write operations and to block out the read data operation that occurs on the TMS9900 before a write data operation. Without this blockout logic, a pulse on the CSR input would occur before any desired pulsing of the CSW input, thus causing unwanted opera- tion of the VDP. Referring to Table 4-1 and Figure 4-1, the following port addresses can be defined. TABLE 4-1 — VDP PORT ADDRESSES FOR FIGURE 4-1 [operation | caw | CSR | Move | Pont | [Wiedatawoveam [0 | + {0 ‘| >8000_| [Swwvevormee | ° | + | ot | ame | or Write to VOP register [Read deiatromvRAM | 1 | 0 | 0 | >e004 | [Reed vorsaws [| 1 7 o | + | >s008 |

42 TMS9918A /9928A /9929A INTERFACE

Figures 4-2 and 4-3 show the hardware components necessary to make the VDP operate with a typical TM990 16-bit bus application. The CPU can be connected as shown to any general-purpose 8-bit data bus and control signals that work with most microprocessors. The VDP interface timing is similar to that of static memories and occupies eight unique memory address locations within the CPU memory address space. we, pe) noe Les cle AN28 KA ER oy ane 2 fs) oaRO SEU = MEMEN 6 09 fo ae E aoofia tow “s ane MODE PECEEEPEY Ti : tHe Tws99 18a are maf oad = nay i fee inset za v tos 4 ou of Et INTERFACE moss CC tt coe pee Flees 8078 oe et pata zjeos masts | TTT ous yeo8 cas] et a Soe. aa EEE eee ooo —" TTT j MOAT | LUTTE | LAUT a ° Vo RESET MY RESET now 0 anense o 40] xTALY 05 —| nos 20] xrat2 p07] fa comvio ~ 8 m4 ir | COMPOSITE (rSO8YBA ONLY! tot a oy ~ ff tea ---- ey Pe -- ~~ - =~ - - ~~ - 8%¢ 4 ro encooen ios78a/99298 onty) FIGURE 4-2 — TMS9918A/9928A/9829A INTERFACE

vas aa 2) @

58 Al 4 > 5 bw)

ET WE ede = A2 6 7 8 U6 + S or PO ee < Ba 61 > Pwr, | [ac ©2) @ ls at ee pF, | ve Palo; oaRo ea a7 Ss pefis—<o7 | R13}. SELECT a ee oe ay Ag wn, 2 pww'g — us * > fares) @ So ake 67 {> 10 2 [R120 9) @ Au 14K13 bw Als 68 [>

69 Alz 2 > A128

70 Ay A13B

n 6 > Al4B us

78 WE »ry2 WeB

82 BBIN [> DBINE

80 MEMEN M13 MEMENB

35>——po 3B sal s 028 36 48 4alé 3B

13 DIRSEL

38 fo 10] 268 2afa | 5B 39 pow 838 sats | Des 0 fois a 48 sate | 7B Te | FIGURE 4-3 — TM990 (TMS9918A/9928A /9929A) DEMO BOARD

4.2.1 TM990 (TMS9918A/9928A/9929A) Parts List

U1,2,3 74LS367 U4,5 74LS243 U6,7,8 74LS266 ug 74LS138 U10 74LS00 ull TMS9918A/9928A/9929A U12-19 TMS4116 C1,2 33 pF YI 10.738635 MHz Crystal Sw1-3 4-position DIP Switches R1 470 2 5% 1/4 W R2-R13 Bourns XXXX or equivalent NOTE: All power supply pins of each IC should be bypassed with a .1uF capacitor.

4.2.2 Composite Video Output

The TMS9918A composite video output pin (36), is driven by a source-follower MOS transistor that requires an external pull-down resistor to Ygs: A 470-ohm resistor is typically used to provide a 1.9 volt peak-to-peak signal on the output. This output will drive most color directly, although in some cases it may be necessary to provide a simple interface circuit to match the monitor's input requirements. If a color video monitor is not available, an RF modulator can be used to drive the antenna terminals of a standard color television, as shown in Figure 4-4. TMS9918A VIDEO RF TO ANTENNA COMVID IN TERMINALS OF COLOR TV FIGURE 4-4 — RF MODULATOR CONNECTION

4.2.3 Oscillator and Timing

The TMS9918A/9928A/992394 internal timing generation is controlled by a self-contained oscillator and timing circuits. A 10.738635 (+ 0.005%) MHz fundamental-frequency parallel-mode crystal is used to drive the basic oscillator frequency. C1 and C2 are load capacitors for the parallel-resonant crystal. C1 and C2 values may be varied slightly to obtain more accuracy in timing and color generation and also to compensate for stray capacitance on the PC board. Typical values for C1 and C2 range between 15 pF and 39 pF. A trimmer capacitor with a value of 5 pF to 50 pF may also be used instead of C1 and adjusted to provide proper colors to the video monitor. The VDP may also be operated with an external oscillator source. The VDP connections for this external source are shown in Figure 4-5.

+5V 4702 4702 XTAL1 ‘TMS9918A/9928A/9929A XTAL2 FIGURE 45 — EXTERNAL FREQUENCY SOURCE There may be a slight color shift or a complete color loss in applications of RF modulators if there are mismatches in voltages levels or impedances between the VDP and the RF modulator. See Figure 3-4 for the TMS9928A/9929A inter- face.

4.2.4 VRAM Connections

The VRAM used in Figure 4-2 are 4116-type dynamic RAMs that meet the specifications in Section 5. Addressing of the VRAM is done through the address bus and the memory control lines, AD1-AD7 and RAS, CAS, and WR, respectively. Data written to the VRAM is also sent over the address bus. ADO is a MSB, and AD7 is the LSB. Data written from the VRAM is brought into the VDP via the read data bus, RD0-RD7. The TMS9918A automatically refreshes the VRAM with no interaction necessary from the host CPU. Note that address 0 (ADO) and data 0 (DO) are the MSBs for the TMS9918A and all other TMS9900 family members. The VRAM pin designations (AO and DO) referenced in the data manual are shown as being the LSBs to be consistent with 4116-type dynamic RAM data sheets.

43 VDP INITIALIZATION

After powerup and proper reset timing, the VRAM allocation backdrop color and type of dynamic RAM need to be loaded into the VDP registers. The values to be loaded can be calculated by using the examples and tables shown in Appendix A. The following flowchart (Figure 4-6) shows a procedure for loading all eight VDP registers. Setting 4.4 contains a typical TMS9900 software pro- gram designed to work on the demo board, shown in Figure 4-3. SETUP ADDRESS OF VDP IN AND WRITE TO VDP WRITE REGISTER NO. TO vor INCREMENT REGISTER NO. AND INCREMENT TABLE POINTER ALL EIGHT REGISTERS LOADED? CONTINUE FIGURE 46 — VDP REGISTER INITIALIZATION PROCEDURE

44 TYPICAL SOFTWARE PROGRAM

441 General

This program initializes the TMS9918A and loads the Pattern Generator with the upper case character set. It then loads the color table, clears the screen and prints a sign-on message. After initialization, a user program address can be inserted at location 00A4. DEMO9918 SDSMAC 3.4.9 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 9882

9001 IDT 'DEMO9918'

8882 9900 BORG >8989 8083 9888 VRAMW EQU >9889 ADDRESS TO WRITE DATA TO VRAM 0804 9902 VDPW EQU >9882 ADDRESS TO WRITE DATA TO VDP e005 9604 VRAMR EQU »>9884 ADDRESS TO READ DATA FROM VRAM pees 9886 VDPR EQU >9086 ADDRESS TO READ VDP STATUS REGISTER 9B *

0098 FEES IESE IO IOI ITI TEETER TERE EAE

9009 * INITIALIZE THE 9918 WITH THE FOLLOWING: 8818 * 9811 * REG @ = 68 EXT VID OFF, GRAPH 2 OFF 0812 * 0813 * REG 1 = 62 4116, INT DIS, VID ON, GRAPH 1 9014 id SIZE 1, MAG OFF 6015 *

8016 Ld REG 2 = 61 NAME TABLE SUB BLOCK @>400

0617 * gas * REG 3 = 68 COLOR TABLE SUB BLOCK @>288 691.9 * 8820 * REG 4 = 81 PATTERN GEN SUB BLOCK @>880 8621 * 9822 * REG 5 = 86 SPRITE NAME TAB SUB BLK @>308 0923 * 0624 * REG 6 = 86 SPRITE PATT GEN SUB BLK @>008 0625 *

0826 Ld REG 7 = 97 BACKDROP COLOR IS CYAN

0627 *

6828 FEES OEE SII IIE IE IIIT IIIT IIHR REI EE

9829 * 8030 * 9831 * NOTE 9032 * THIS SOFTWARE ASSUMES THAT THE DATA. BUS OF THE 9033 * TMS9918A IS CONNECTED TO THE LEAST SIGNIFICANT 0634 * BYTE OF THE TMS9986, WITH D7 AS THE MOST 9035 * SIGNIFICANT BIT AND D15 AS THE LEAST SIGNIFICANT 0036 * BIT 8037 * 6638 * 0839 6988 6201 INIT LI R1,VDPW VDP WRITE ADDRESS 0682 9062 8040 0004 6262 LI R2,SUTA "SET UP TABLE" ADDRESS 8886 6OBB 8041 0808 6293 LI R3,>80 ADDRESS OF FIRST VDP REGISTER GOGA 0080 @842 860C C472 LPGL MOV *R2+,*R1 GET DATA FROM MEM, SEND TO 9918

9943 BOBE C443 MOV R3,*R1 SEND REG# TO 9918

$944 0819 0583 INC R3 INCRENENT REGISTER COUNT 8845 6612 6283 cr R3,>88 ALL REGS LOADED? 8014 9088 634s 0916 16FA JNE LpPdl NO,GO AGAIN 0048 * 9049 * LOAD PROGRAM LOADS THE TEXT PATTERNS FROM 9058 * A TABLE IN MEMORY TO THE PATTERN GENERATOR @851 * SUB-BLOCK IN VRAM. oes * ASCII >26 TO >SF ARE INCLUDED IN THIS TABLE. 054 * 9855 0018 6281 LPG1 Lr R1,VRAMW ADDRESS TO WRITE DATA TO VRAM 801A 9080

DEMO9918 SDSMAC 3.4.9 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 0003

0956 B81C 0262 LI R2,VDPW ADDRESS TO WRITE TO VDP

@O1E 9002 8057 0020 0203 LI _R3,PATT MEM ADDR OF PATTERNS 0922 o0c0 8058 0624 6204 LI R4,512 64 CHAR X 8 BYTES - 512 BYTES 0626 0200 9959 9028 0205 LI R5,>4908 ADDRESS TO LOAD PATS IN VRAM 002A 4960

0068 B02C C485 MOV R5,*R2 SEND LSB OF VRAN ADDRESS TO VDP

0061 002E 06C5 SWPB R5 REVERSE BYTES 0062 0038 C445 MOV R5,*R1 SEND DATA TO VRAM 0863 0032 D173 LPG2 MOVB *R3+,R5 GET BYTE FROM MEM 0964 0034 B6C5 SWPB RS5 REVERSE BYTES 0065 0036 C445 MOV R5,*R1 SEND DATA TO VRAM 9066 0038 0604 DEC R4 ALL DONE YET? a7 903A 16FB SNE LPG2 NO, GO AGAIN ooce FIO III III III ITI III III IIIT TOT IATA I 8070 * LOAD COLOR TABLE 0071 * 6072 * THIS ROUTINE LOADS THE COLOR TABLE FOR THE 0073 * TEXT PATTERNS JUST ENTERED, 0974 * 0975 * 6076 663C 6261 LI R1,VRAMW ADDRESS TO WRITE DATA TO VRAM 063E 9000 0877 0848 8202 LI R2,VDPW ADDRESS TO WRITE TO VDP 0842 9002 0078 aged #203 LI R3,>4204 START ADDRESS OF TEXT COLOR TABL 46 4204 0079 0048 0204 LI R4,>5F CHARACTERS WILL BE BLUE ON WHITE 004A OO5F

8080 B04C C483 MOV R3,*R2 SEND LSB OF VRAM ADDRESS TO VDP

0081 O04E 0205 LI R5,8 LOAD COUNT VALUE, 64CHAR/8 = 8

0082 0852 C444 LCTL MOV R4,*RI SEND COLOR INFO TO VRAM 0083 8054 0605 DEC RS TABLE LAODED YET? 0084 0056 16FD JNE LCTL NO, GO AGAIN ‘| * ae RRR EERIE ARI RIKER RRR ERREREEEREEREREEREREREKRHEKREK EE 0087 * CLEAR SCREEN 9088 * 8089 * THIS ROUTINE CLEARS THE SCREEN BY WRITING A SPACE 0090 * CHARACTER (ASCII >2@) TO ALL LOCATIONS IN THE 9091 * NAME TABLE. 8092 * 8093 * 6094 0658 0261 LI R1,VRAMW ADDRESS TO WRITE DATA TO VRAM 985A 9000 0095 085C 0202 LI R2,VDPW ADDRESS TO WRITE TO VDP OO5E 9002 0096 9860 0203 LI _R3,>4408 START ADDRESS IN NAME TABLE 0062 4400 0097 0064 C483 MOV R3,*R2 SEND MSB OF VRAM ADDRESS TO VDP 0098 0666 9202 LI R2,768 #OF POSITIONS ON SCREEN 0068 0300 0699 086A 6203 LI R3,>28 ASCII SPACE CHAR 606C 0020

9100 OB6E C443 CSL1 MOV R3,*R1 SEND SPACE TO SCREEN

91081 0070 0602 DEC R2 ARE ALL LOCATIONS CLEAR?

DENO9918 SDSMAC 3.4.9 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 0604 9162 6072 16FD JNE CSL1 NO, GO AGAIN 919 * bibs ERRRERREERRER EERIE ERE RRR AREER ERR EERE EERE RR ER IRE RR ERE 105 * PRINT SIGN ON MESSAGE 9106 * AND BRANCH TO USERS PROGRAM 0107 * 9108 * 9169 9074 6201 LI R1,VRAMW ADDRESS TO WRITE DATA TO VRAM 8076 9900 8119 0878 6202 LI R2,VDPW ADDRESS TO WRITE TO VDP OO7A 9062 111 987C 6203 LI R3,>4409 POSITION OF MESSAGE ON SCREEN BO7E 4400 9112 9080 C483 MOV R3,*R2 SEND MSB OF VRAM ADDRESS TO VDP 6113 8082 86C3 SWPB R3 REVERSE BYTES 6114 9084 C483 MOV R3,*R2 SEND MSB OF VRAM ADDRESS TO VDP 9115 6886 6203 LI R3,MSGB ADDRESS OF SIGN ON MESSAGE

6988 O09E

9116 068A 64C4 PRNT CLR R4 CLEAR RECEPTION REGISTER 9117 668C D113 MOVB *R3,R4 GET A BYTE OF TEXT 9118 OO8E 0284 cr R4,>FFOO IS IT THE EOM CHARACTER?

6090 FFOO

9119 9692 1393 JEQ DONE YES, GOTO NEXT PROGRAM SEGMENT 9126 0894 B6C4 SWPB R4 REVERSE BYTES @121 0096 C444 MOV R4,*R1 SEND CHAR TO VRAM 9122 6698 1oF8 JMP PRNT GET NEXT CHARACTER 9123 009A 6460 DONE B @DONE INSERT BRANCH TO USERS PROGRAM 909C 009A 0124 * AT THIS POINT 0125 689E 54 MSGO TEXT ‘TEXAS INSTRUMENTS TMS9918' OO9F 45 BAG 58 O9Al 41 BOA2 53 O9A3 20 OBA4 49 9OA5 4E OOA6 53 BOAT 54 OOA8 52 9BA9 55 OGAA 4D O9AB 45 QBAC 4E OGAD 54 OOAE 53 GOAF 20 OOBO 54 @OBl 4D OOB2 53 90B3 39 OOB4 39 BOOBS 31 OOB6 38

9126 S0B7 FF BYTE >FF

9128 *

0129 FEI GI I ICISI ICICI IIIS IO ISIIOIIOIIOIIOIIDIIOII III IIIT I

9130 * THIS TABLE CONTAINS THE VALUES FOR 9131 * INITIALIZING THE REGISTERS IN THE 9918A

DEMO9918 SDSMAC 3.4.0 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 8005 0132 * 9133 6988 60 SUTA BYTE >00 0134 96B9 «a2 BYTE >62

0135 OOBA 81 BYTE >01

0136 OOBB 08 BYTE >08

0137 66BC 1 BYTE >01

9138 BBD 06 BYTE >06

9139 QOBE 0B BYTE >66

0140 OOBF 97 BYTE >07

0141 *

0142 FAIS IOIIISIOIO ICICI IIIT IIIT ATI AT OITA IIA:

0143 * 9918A TEXT PATTERNS 0144 * 6145 * THESE PATTERNS FROM A 5X7 CHARACTER IN THE 0146 * 8X8 PATTERN BLOCK THAT IS UPPER AND LEFT 0147 * JUSTIFIED 0148 *

0149 GOCO 8600 PATT DATA >9000 CHARACTER SPACE ASCII 20

8150 00C2 B000 DATA >0000 0151 80c4 9000 DATA >6000 8152 99C6 B00 DATA >6900 0153 o9c8 2020 DATA >2028 CHARACTER ! ASCII 21

9154 BOCA 2020 DATA >2028

8155 o6CC 2000 DATA >2000

0156 GOCE 2000 DATA >2000

0157 98D8 5050 DATA >5058 CHARACTER " ASCII 22 8158 96D2 5000 DATA >5000

8159 GoD4 8000 DATA >6000

8160 90D6 o000 DATA >0000 0161 o0D8 5050 DATA >5059 CHARACTER # = ASCII 23

0162 OODA F850 - DATA >F858

8163 BODC F850 DATA >F856

0164 BODE 5008 DATA >5008

0165 O0Ed 2078 DATA >2078 CHARACTER $ = ASCII 24

9166 O0E2 A070 DATA >A078

0167 O0E4 28F0 DATA >28FG

0168 O8E6 2000 DATA >2000

9169 G0E8 CocB DATA >COC8 CHARACTER § — ASCII 25

8170 OOEA 1020 DATA >1620

9171 BGEC 4098 DATA >4098

0172 OOEE 1809 DATA >1808

0173 OOFO 40A0 DATA >49A0 CHARACTER & ASCII 26

0174 OOF2 AG4O DATA >A040

8175 GOF4 A890 DATA >A890

0176 OOF6 6800 DATA >6800

9177 OOF8 2620 DATA >2020 CHARACTER ' — ASCII_.27

0178 OOFA 2000 DATA >2000

0179 BOFC 0000 DATA >0080

0180 OOFE 0000 DATA >0060

6181 0100 2040 DATA >2048 CHARACTER ( ASCII 28 6182 6102 8080 DATA >8080 0183 6104 8040 DATA >8048 0184 9106 2000 DATA >2000 9185 0108 2910 DATA >2016 CHARACTER ) — ASCII 29 8186 010A 6808 DATA >0868 9187 619C 9810 DATA >6819 9188 0108 2000 DATA >2000 0189 6119 2008 DATA >20A8 CHARACTER * = ASCII 2A 9190 8112 7020 DATA >7028 0191 6114 70a8 DATA >70A8

DEMO9918 SDSMAC 3.4.6 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 0096 0192 96116 2006 DATA >2008 9193 6118 6620 DATA >0028 CHARACTER + ASCII 2B

9194 O11A 26F8 DATA >26F8

8195 B11C 2026 DATA >2626

0196 G11E 0000 DATA >9908

8197 0128 6600 DATA >8589 CHARACTER , ASCII 2C 9198 6122 6600 DATA >8606 6199 0124 2020 DATA >2820 9200 0126 4000 DATA >4006 8201 0128 9900 DATA >9000 CHARACTER - ASCII 2D

9202 G12A OOF8 DATA >8OF8

9203 612C 6000 DATA >9680 9204 812E 6000 DATA >0008 0205 9130 6690 DATA >0980 CHARACTER . ASCII 2E 9206 8132 9000 DATA >8600 0207 0134 6698 DATA >9086 @208 9136 2000 DATA >2008 6209 9138 9608 DATA >9008 CHARACTER / ASCII 2F 0218 913A 1620 DATA >1020 @211 613C 4980 DATA >4080 $212 813E 6000 DATA >8009 9213 6140 7988 DATA >7088 CHARACTER 8 ASCII 30 8214 8142 98A8 DATA >98A8 9215 6144 C888 DATA >C888 9216 8146 7000 DATA >7000 $217 0148 2966 DATA >2066 CHARACTER 1 ASCII 31

9218 G14A 2020 DATA >2020

9219 614C 2620 DATA >2620

0229 B14E 7000 DATA >7900

0221 9150 7088 DATA >7088 CHARACTER 2 ASCII 32 0222 6152 6830 DATA >8830 6223 8154 4080 DATA >4086 6224 8156 F800 DATA >F8998 6225 9158 F808 DATA >F898 CHARACTER 3 ASCII 33

0226 G15A 1636 DATA >1030

9227 B15C 6888 DATA >6888

9228 O15E 7008 DATA >7000

9229 9160 1630 DATA >1039 CHARACTER 4 ASCII 34 9239 8162 5090 DATA >5098 6231 6164 F810 DATA >F819 0232 6166 1008 DATA >1000 0233 6168 F880 DATA >F886 CHARACTER 5 ASCII 35 0234 016A FO08 DATA >F@98 8235 816C 0888 DATA >8888

9236 G16E 7000 DATA >7080

9237 8178 3840 DATA >3848 CHARACTER 6 ASCII 36 6238 6172 8OFO DATA >80FO 6239 6174 8888 DATA >8888 G248 0176 7600 DATA >7688 9241 0178 F898 DATA >F808 CHARACTER 7 ASCII 37 0242 817A 1920 DATA >1020

0243 B17C 4040 DATA >4040

9244 G17E 4000 DATA >4080

9245 0188 7088 DATA >7088 CHARACTER 8 ASCII 38 9246 6182 8870 DATA >8870 9247 0184 8888 DATA >8888 0248 6186 7008 DATA >7000 0249 6188 7088 DATA >7688 CHARACTER 9 ASCII 39 9259 618A 8878 DATA >8878 9251 818C 68190 DATA >0816 410

DEMO9918 SDSMAC 3.4.8 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 9687 $252 O18E EOOO DATA >E@00 9253 6198 9000 DATA >0000 CHARACTER : ASCII 3A 9254 8192 2600 DATA >2008 8255 6194 2000 DATA >2608 8256 8196 0008 DATA >8008 6257 0198 6000 DATA >8608 CHARACTER ; ASCII 3B

6258 G19A 2000 DATA >2000

8259 819C 26208 DATA >2026

9260 G19E 4000 DATA >4006

0261 B1A9 1626 DATA >1928 CHARACTER < ASCII 3c

9262 O1A2 4980 DATA >4880

9263 O1A4 4020 DATA >4626

6264 B1A6 1900 DATA >1960

9265 B1A8 6000 DATA >9008 CHARACTER = ASCII 3D

0266 O1AA F800 DATA >F8008

0267 O1AC F8GO DATA >F860

8268 G1AE 0000 . DATA >0080

0269 G1BO 4620 DATA >4020 CHARACTER > ASCII 3E

0270 91B2 1008 DATA >1008 6271 91B4 1020 DATA >1620 0272 81B6 4006 DATA >4006 9273 61B8 7088 DATA >7688 CHARACTER ? ASCII 3F

9274 G1BA 1620 DATA >1020

9275 @1BC 2000 DATA >2006

6276 G1BE 2600 DATA >2000

0277 61CB 7088 DATA >7688 CHARACTER @ ASCII 46 0278 @1C2 A8B8 DATA >A8B8

8279 B1C4 BOB DATA >BO88

8280 G1C6 7808 DATA >78088

6281 @1C8 2650 DATA >2650 CHARACTER A ASCII 41

9282 G1CA 8888 DATA >8888

9283 @1CC F888 DATA >F888

9284 B1CE 8800 DATA >8860

6285 @1D0 FO88 DATA >FO88 CHARACTER B ASCII 42 0286 61D2 88FO DATA >88FO 6287 91D4 8888 DATA >8888 6288 01D6 FORD DATA >F#06

9289 G1D8 7088 DATA >7088 CHARACTER C ASCII 43

0290 O1DA 8680 DATA >8080

8291 O1DC 8688 DATA >8888

0292 O1DE 7000 DATA >7000

6293 @1E0 FO88 DATA >FO88 CHARACTER D ASCII 44

0294 G1E2 8888 DATA >8888

0295 O1E4 8888 DATA >8888

6296 O1E6 FOOD DATA >FO00

@297 O1E8 F886 DATA >F880 CHARACTER E ASCII 45

6298 O1EA 80FO DATA >80FO

6299 B1EC 8880 DATA >8688

0300 O1EE F800 DATA >F800

9301 O1FO F880 DATA >F880 CHARACTER F ASCII 46

0302 O1F2 86FO DATA >80FO

0303 O1F4 8080 DATA >8680

0304 G1F6é 8000 DATA >8806

8305 O1F8 7880 DATA >7886 CHARACTER G ASCII 47

6306 O1FA 8680 DATA >8888

9307 O1FC 9888 DATA >9888

0308 B1FE 7800 DATA >7860

9309 0200 8888 DATA >8888 CHARACTER H ASCII 48 9319 6262 88F8 DATA >88F8 6311 6264 8888 DATA >8888

DEMO9918 SDSMAC 3.4.8 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 0608 0312 6266 8800 DATA >8808 9313 0208 7626 DATA >7020 CHARACTER I ASCII 49 0314 @26A 2026 DATA >2620 9315 820C 2020 DATA >2028 6316 620E 7008 DATA >7808 $317 82198 6868 DATA >8888 CHARACTER J ASCII 4A 9318 6212 6808 DATA >8868 0319 9214 8888 DATA >9888 8328 9216 7008 DATA >70080 321 8218 8898 DATA >8898 CHARACTER K ASCII 4B

9322 G21A AGCO DATA >AO@CO

8323 621C Ag90 DATA >AG9B

0324 O21E 8808 DATA >8888

9325 0220 8080 DATA >8080 CHARACTER L ASCII 4C 9326 0222 8080 DATA >8888 9327 6224 8080 DATA >8080 9328 6226 F800 DATA >F866 9329 6228 88D8 DATA >88D8 CHARACTER M ASCII 4D 6330 022A A8A8 DATA >A8A8 0331 622c 8888 DATA >8888

9332 O22E 8808 DATA >8886

6333 8236 8888 DATA >8888 CHARACTER N ASCII 4E 0334 0232 C8A8 DATA >C8A8 9335 0234 9888 DATA >9888 6336 0236 8800 DATA >8809 9337 8238 7088 DATA >7688 CHARACTER O ASCII 4F 6338 023A 8888 DATA >8888 6339 023C 8888 DATA >8888

8348 G23E 7608 DATA >7690

9341 6240 Fa88 DATA >FO88 CHARACTER P ASCII 58 0342 0242 88FO DATA >88FO0 9343 8244 8080 DATA >8880 0344 0246 8006 DATA >8000 9345 0248 7088 DATA >7088 CHARACTER Q ASCII 51 9346 024A 8888 DATA >8888 9347 6824C A890 DATA >A890 0348 624E 6800 DATA >6800 9349 6259 FO88 DATA >FO88 CHARACTER R ASCII 52 93508 9252 88FO DATA >88FO 9351 6254 Ag9B DATA >A096 9352 8256 8800 DATA >8860 9353 6258 7088 DATA >7088 CHARACTER S ASCII 53 9354 025A 8070 DATA >8070 9355 925C 0888 DATA >9888 6356 025E 7000 DATA >7686 6357 8260 F829 DATA >F826 CHARACTER T ASCII 54 0358 9262 2020 DATA >2020 0359 9264 2620 DATA >2626 9369 6266 2000 DATA >2008 9361 9268 8888 DATA >8888 CHARACTER U ASCII 55 9362 026A 8888 DATA >8888 9363 826C 8888 DATA >8888

9364 O26E 7000 DATA >7006

0365 0270 8888 DATA >8888 CHARACTER V ASCII 56 0366 0272 8888 DATA >8888 9367 0274 8850 DATA >8859 6368 9276 2000 DATA >2000 0369 0278 8888 DATA >8888 CHARACTER W ASCII 57 6376 627A 88A8 DATA >88A8 0371 627C A8D8 DATA >A8D8 412

DEMO9918 SDSMAC 3.4.0 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 9869

0372 G27E 8809 DATA >8808

0373 6286 8888 DATA >8888 CHARACTER X ASCII 58 0374 6282 5926 DATA >5920 9375 0284 5088 DATA >5888 0376 6286 8800 DATA >88008 9377 6288 8888 DATA >8888 CHARACTER Y ASCII 59 378 828A 5920 DATA >5628

6379 B28C 2928 DATA >2628

0388 628E 2006 DATA >2680 9381 6290 F898 DATA >F868 CHARACTER Z ASCII 5A 8382 8292 1620 DATA >10820 9383 6294 4080 DATA >4088 0384 8296 F800 DATA >F800 9385 9298 F8CO DATA >F8CO CHARACTER [ ASCII 5B 0386 629A COCO DATA >COCO 8387 929C COCO DATA >C6CO

9388 O29E F8G0 DATA >F8068

8389 O2A8 6080 DATA >0088 CHARACTER ASCII 5C

9390 O2A2 4620 DATA >40826

9391 62A4 1998 DATA >1668 392 02A6 0000 DATA >0609 9393 62A8 F818 DATA >F818 CHARACTER ] ASCII 5D

9394 O2AA 1818 DATA >1818

9395 ®2AC 1818 DATA >1818

9396 O2AE F809 DATA >F806

9397 82B6 0900 DATA >8006 CHARACTER ASCII 5E

0398 G2B2 2050 DATA >2856

0399 02B4 8860 DATA >8808 9409 62B6 9006 DATA >6866 9481 82B8 0006 DATA >8990 CHARACTER _ ASCII 5F

9402 O2BA 8000 DATA >8800

9403 62BC 0000 DATA >9000

0494 O2BE F808 DATA >F8008

6405 @2cO 4620 DATA >4026 CHARACTER ASCII 60 9406 62C2 1000 DATA >1800 0487 82Cc4 2000 DATA >8000 8498 02c6 0000 DATA >6000 9409 62C8 0900 DATA >@008 CHARACTER a ASCII 61

8418 G2CA 7688 DATA >7088 ‘

8411 62cC F888 DATA >F888

9412 G2CE 8800 DATA >8866

6413 62D8 0000 DATA >8900 CHARACTER b ASCII 62

6414 G2D2 F048 DATA >F048

8415 62D4 7048 DATA >7648 9416 02D6 FOOD DATA >FOOD 9417 02D8 9008 DATA >6008 CHARACTER c ASCII 63

9418 G2DA 7880 DATA >7880

8419 G2DC 8d8D DATA >8988

0420 B2DE 7800 DATA >7806

421 0250 9990 DATA >8980 CHARACTER d ASCII 64

9422 O2E2 F048 DATA >F048

8423 O2E4 4848 DATA >4848

9424 B2E6 FOBG DATA >FODO

9425 O2E8 9000 DATA >8068 CHARACTER e ASCII 65

$426 O2EA FO80 DATA >FO80

8427 B2EC EBD DATA >E089

9428 O2EE FOOD DATA >FO0B

6429 G2F0 6008 DATA >8006 CHARACTER £ ASCII 66

9430 @2F2 FO8D DATA >F080 0431 62F4 EG8O DATA >E086 413

DEMO9918 SDSMAC 3.4.6 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 9018

0432 O2F6 8000 DATA >8600

0433 O2F8 0608 DATA >6080 CHARACTER g ASCII 67

0434 O2FA 7880 DATA >7886

0435 O82FC B888 DATA >B888

0436 O2FE 7000 DATA >7608

0437 0300 6000 DATA >6668 CHARACTER h ASCII 68 0438 8302 8888 DATA >8888 0439 0304 F888 DATA >F888 @440 0306 8860 DATA >8800 9441 6368 6600 DATA >6608 CHARACTER i ASCII 69 0442 030A F820 DATA >F826 8443 838C 2620 DATA >2628 0444 630E F800 DATA >F886 0445 8318 9000 DATA >6600 CHARACTER j ASCII 6A 9446 6312 7626 DATA >7028 9447 6314 20a DATA >28A0 0448 0316 EO06 DATA >E#08 9449 8318 9000 DATA >8868 CHARACTER k ASCII 6B 8458 631A 90A0 DATA >90A0 @451 631c AbCO DATA >A9CO 9452 931E 9000 DATA >9000 9453 9328 6000 DATA >0608 CHARACTER 1 ASCII 6C 0454 9322 8680 DATA >8088 8455 6324 8080 DATA >8088 0456 6326 F800 DATA >F800 0457 9328 9008 DATA >09606 CHARACTER m ASCII 6D 6458 632A 88D8 DATA >88D8 9459 632C A888 DATA >A888 8460 632E 8800 DATA >8886 6461 6336 0000 DATA >0908 CHARACTER n ASCII 6E 8462 6332 88C8 DATA >88C8 0463 0334 A898 DATA >A898 9464 0336 8800 DATA >8800 9465 6338 6000 DATA >9000 CHARACTER o ASCII 6F @466 033A F888 DATA >F888 8467 633c 8888 DATA >8888 0468 633E F890 DATA >F806 8469 6349 9909 DATA >8086 CHARACTER p ASCII 76 0470 0342 FO88 DATA >FO88 9471 8344 FO8D DATA >FO80 0472 8346 8000 DATA >8009 9473 6348 6000 DATA >0008 CHARACTER q ASCII 71 0474 034A F888 DATA >F888 8475 834C A898 DATA >A899 0476 034E EO09 DATA >E008 9477 8359 6000 DATA >8606 CHARACTER r ASCII 72 9478 0352 F888 DATA >F888 9479 0354 F8A0 DATA >F8A9 9480 0356 9000 DATA >9800 9481 0358 8006 DATA >09000 CHARACTER s ASCII 73 0482 035A 7888 DATA >7880 0483 035C 7008 DATA >7008

0484 O35E FOOO DATA >FO08

0485 6369 0060 DATA >9008 CHARACTER t ASCII 74 8486 6362 F828 DATA >F826 6487 0364 2026 DATA >2620 0488 0366 2006 DATA >2000 8489 6368 9908 DATA >9600 CHARACTER u ASCII 75 0496 036A 8888 DATA >8888 8491 636C 8888 DATA >8888

DEMO9918 SDSMAC 3.4.8 81.117 15:45:22 MONDAY, SEP 27, 1982. PAGE 8611 9492 936E 7000 DATA >7800 9493 9370 8900 DATA >9006 CHARACTER v ASCII 76 8494 8372 8888 DATA >8888 8495 0374 96AB DATA >90AG 0496 0376 4000 DATA >4008 9497 6378 5000 DATA >0608 CHARACTER w ASCII 77 6498 037A 8888 DATA >8888 9499 937C A8D8 DATA >A8D8 0500 0375 8800 DATA >8808 9581 0380 6960 DATA >9889 CHARACTER x ASCII 78 502 0382 8860 DATA >8860 8583 6384 2668 DATA >2860 9504 0386 8800 DATA >8808 0505 0388 0000 DATA >6006 CHARACTER y ASCII 79 6596 938A 8856 DATA >8858 6597 938C 2626 DATA >2620

6508 O38E 2090 DATA >2000

8589 9390 0000 DATA >8896 CHARACTER 2 ASCII 7A 9519 0392 F819 DATA >F819 6511 9394 2040 DATA >2040 9512 0396 F808 DATA >F800 6513 6398 3849 DATA >3848 CHARACTER ASCII 7B 9514 039A 26C0 DATA >20C8 9515 039C 2040 DATA >2048 9516 039E 3800 DATA >3866 9517 03A8 4020 DATA >4026 CHARACTER ASCII 7¢ 9518 93A2 1008 DATA >1098 9519 63A4 1920 DATA >1828

9528 O3A6 4000 DATA >4800

9521 93A8 E910 DATA >EG16 CHARACTER ASCII 7D

6522 O3AA 2618 DATA >2618

@523 @3AC 2610 DATA >2016

0524 O3AE EOOD DATA >EGO8

6525 03B0 40A8 DATA >40A8 CHARACTER ASCII 7E 9526 83B2 1866 DATA >1888 8527 93B4 8000 DATA >6600 6528 03B6 6000 DATA >8060 9529 63B8 A85B DATA >A85B8 CHARACTER ASCII 7F

9539 O3BA A850 DATA >A858

8531 93BC A850 DATA >A850

9532 O83BE A800 DATA >A808

9533 END

NO ERRORS, NO WARNINGS . 415

4.5 TMS9900 SOFTWARE SUBROUTINES

NOTE: Before using any of the line drawing subroutines, the “Load Line Drawing Patterns” subroutine must be executed. PATTERN PATTERN PATTERN 00 01 02 TTTTITTTI-* (CT ggtyi-* CLT yt -~ rit try ty j-%° «CCTM TT =e PPT tT Ty -00 PTT -o «TT TT -3 PPP fT || -00 -ee [TT] Be ee | | | -re sre TTT Be [| -18 |] | | -re PTT TTT TT j-0o CTR TT -:3 |] | Be TT | -1e TTT TTT TT y-o [TTR TT -13 [TT Bat | | | 1 TITTY TTT )-oo CLT RTT )-:3 CCl Be TT J -: PATTERN PATTERN PATTERN 03 04 05 CTT TTT ot) -° CTT TTT )-% (TT) Ty fy - TTT TTT TT) -c COTM TT -2 (TT Bea | Tt rT Try -o [TTR TT -3 [TT Pe fT) = aan =1F rit j-re CTY I =1F aan =1F Pty y-rs tT] =1F Cll Me TT - CET TTT )-o PTT TT TT TY -00 Cl] Me TT) -3 CITT TTT i-o PPT TT TTT | -00 TCT Me CC) -3 CEPT it y-% CET TTT | -0 PATTERN =18 =18 =18 =FF =FF =18 =18 =18 416

SEGMENTS SDSMAC 3.4.9 81.117 13:36:55 TUESDAY, SEP 21, 1982. PAGE 6002

0001 IDT 'SEGHENTS'

0002 IIIT IT TTT TTI TT TT TT TK ITT RTT ITI TTT TI TR TOR RR RIK

6003 * * 6004 * TNS9918A SUBROUTINES * 0005 * *

0066 FI III IIIS III III II III IOI III Tote

0007 9000 VRAMW EQU >9080 ADDRESS TO WRITE DATA TO VRAN 6008 9062 VDPW EQU >9002 ADDRESS TO WRITE DATA TO VDP 0009 9064 VRAMR EQU >9004 ADDRESS TO READ PATA FRO! VRAN 0010 9006 VDPR EQU >9086 ADDRESS TO READ STATUS FRO! VDP

0011 PIT RRR TREK KIRKE KEKE RK KEE KEE RK KE RAE K

0012 * * 6013 * LOAD LINE DRAWING PATTERNS * 0014 * * 9015 * REGISTERS USED: * 9016 * * 6017 * REG 1 = RESERVED * 6018 * REG 2 = RESERVED * 0019 * REG 3 = ADDRESS OF PATTERN GENERATOR * 0020 * REG 4 = PATTERN LOCATION IN NENORY * 0921 * REG 5 = COLORS OF DRAWING PATTERNS * 0022 * (USER DEFINED) *

0023 FERS IIIS IIIS III III II IOI III ICI IIIT IOI TOIT:

0024 * 0025 * 0626 6060 0201 LI R1,VRAMT ADDRESS TO WRITE DATA TO VRAN 0002 9060 0027 9004 G202 LI R2, VDP! ADDRESS TO WRITE TO VDP 0006 9002 0028 0008 0203 LI R3,>4800 ADDRESS IN PATT GEN FOR PATT 0 SGA 4800 0029 000C 0264 LI _R4,PATD DRAWING PATTERNS LOCATED IN NEM O00E O02E' 0036 0616 C483 HOV. R3,*R2 SEND HSB OF VRAN ADDRESS TO VDP 6031 0532 06C3 SVIPB R3 REVERSE BYTES 0032 0014 C483 NOV R3,*R2 SEND LSB OF VRAN ADDRESS TO VDP 6933 9016 0203 LI 23,56 7 PATTERNS X 8 BYTES EACH 9618 0038

0034 OG1A D474 LLD1 MOVB *R4+,*R1 SEND BYTE TO VRAM

€935 O91C 6603 DEC R3 DECRENENT BYTE COUNT

0036 OO1F 16FD SNE LLD1 IF NOT DONE, GET NEXT BYTE

0937 0026 6203 LI _R3,>4200 ADDRESS OF COLOR TABLE 0022 4200 0938 0024 C483 NOV R3,*R2 SEND LSB OF VRAN ADDRESS TO VDP 0639 0026 06C3 SWPB R3 REVERSE BYTES 0040 0628 c4e3 NOV R3,*R2 SEND 1SB OF VRAN ADDRESS TO VDP 0041 002A C445 HOV R5,*R1 SEND COLOR BYTE TO VRAI 0642 092c 045 Bo *Rll RETURN TO CALLING PROGRAM 0043 * 0044 * 0045 * PATTERNS FOR LIND DRAWING 0046 * 6047 * 0048 002E 6006 PATD DATA >GoGC PATTERN 90 6649 0030 OOFF DATA >00FF 0050 0032 FFOO DATA >FFGO 0051 0634 og00 DATA >6006 9052 0636 1818 DATA >1818 PATTERN 01 0053 0038 1818 DATA >1818 6054 003A 1818 DATA >1818 417

SEGNENTS SDSNAC 3.4.0 81.117 13:36:55 TUESDAY, SEP 21, 1982. PAGE 96603 0055 0n3c 1818 DATA >1818 6056 003E 5000 DATA >0006 PATTERN 62 6057 6040 GOOFS DATA >00F8 0058 0042 Fels DATA >F818 6059 6044 1818 DATA >1818 0060 9046 OG00 DATA >6000 PATTERN 63 0061 6048 OO1F DATA >OO01F

6062 SO4A 1F18 DATA >1F18

6063 004C 1818 DATA >1818

0064 O04E 1818 DATA >1818 PATTERN 04

9065 0050 18Fe DATA >18F8 6966 0652 FEO DATA >F809 6067 0054 gN00 DATA >0000 C068 9056 1818 DATA >1818 PATTERN 05 6069 0058 181F DATA >181F

0970 OO5A 1F00 DATA >1FPG60

6071 B805C 6600 DATA >6960

6072 OO5E 1818 DATA >1818 PATTERN 6

6973 0660 18FF DATA >18FF 0074 6062 FF18 DATA >FF18 6075 9964 1818 DATA >1818 9976 * 0677 * 6978 rveretrrtrrtrttittttttttrt ttt ttt titre ti tri rire res eet 09079 * * e086 * LOAD SPRITES SUBROUTINE * CMe * * co82 * REGISVERS USED: * 0083 * * C84 * Rl = RESERVED * C885 * R2 = RESERVED * cose * R3 = ADDRESS OF SPRITE TABLE IN VRAH * 5087 * R4 = MENORY ADDRESS OF SPRITE TABLE (USER DEF) * CO88 * R5 = NUMBER OF BYTES TO TRANSFER (USER DEF) * Goe9 * *

6099 TTrerrrrrrrrrrrrertrtttttttttttttttttttt ttt ttt tit rr tires 7

onSl * G692 6066 6201 LI R1,VRANI ADDRESS TO WRITE DATA TO VRAN 9968 9000 0093 066A 0202 LI -R2,VDPU ADDRESS TO WRITE TO VDP 906C 9062 0994 006E C203 LI _R3,>4000 ADDRESS OF SPRITE TABLE IN VRAI 0976 4000 0995 6072 C483 NOV R3,*R2 SEND LSB OF VRAN ADDRESS TO VDP 9596 0074 06C3 SUPB R3 REVERSE BYTES 9097 6076 C483 NOV R3,*R2 SEND NSB OF VRAl ADDRESS TO VDP 0998 9678 DOF4 LDPL NOVE *R4+,R3 GET BYTE OF DATA FROM NEN

6099 OO7A 06C3 SUPB R3 REVERSE BYTES

9100 G97C C443 HOV R3,*R1 SEND DATA TO VRAN

9191 GO7E G605 DEC RS ARE WE DONE YET? 9192 0086 16Fn JHE LDPL NO, GO AGAIN G103 0082 045B B *R11 YES, RETURN TO CALLING PROGRAI 418

SEGMENTS SDSMAC 3.4.0 81.117 13:36:55 TUESDAY, SEP 21, 1982. PAGE 0004

6105 HORII III IIR FIR IK IK TTI RIT RRR RIK IR RIK RRR RK

6166 * * 6107 * CLEAR SCREEN SUBROUTINE * 6108 * * 0109 * REGISTERS USED: * 6110 * . * 6111 * Rl = RESERVED * 0112 * R2 = RESERVED * 9113 * R3 = START ADDRESS ON SCREEN * 0114 * *

0115 FRI III III III IOI IOI TO ITO TOTTI IOK tte

6116 * 6117 * 6118 9084 0201 CLSC LI R1,VRANW ADDRESS TO WRITE DATA TO VRAH 0086 9000 6119 6988 0202 LI R2,VDPW ADDRESS TO WRITE TO VDP 098A 9002 0120 608C 6203 LI R3,>4400 START LOCATION OF THE NANE TABLE OO8E 4400 9121 0690 C483 HOV. R3,*R2 SEND LSB OF VRAM ADDRESS TO VDP G122 0692 96C3 SWPB R3 REVERSE BYTES 6123 0094 C483 NOV R3,*R2 SEND NSB OF VRAM ADDRESS TO VDP 6124 6096 9202 LI 2,768 #OF POSITIONS ON SCREEN 0098 0300 9125 009A 9203 LI R3,>20 ASCII SPACE CHAR 659C 0926

6126 B09E C443 CSL1 MOV R3,*RL SEND SPACE CHAR TO VRAM

0127 OOAD 0602 DEC R2 ARE ALL LOCATIONS CLEAR?

9128 OOA2 16FD JNE CSL1 NO, GO AGAIN

G129 90A4 945B B *R11 YES, RETURN TO CALLING PROGRAM 0130 * 6131 *

6132 JE IIIOSISI IOI IEI IIIS IEI ISIS ISIS IE EIT ITI IIT IIIT IIIT

6133 * * 0134 * PRINT NESSAGE SUBROUTINE * 6135 * AND BRANCH ‘TO USERS PROGRAM * 6136 * * 6137 * REGISTERS USED: * 0138 * * 0139 * Rl = RESERVED * o149 * R2 = RESERVED * 9141 * R3 = STARTING ADDRESS OF MESSAGE IN NAME * 0142 * TABLE (USER DEFINED) * 0143 * R4 = HEHORY ADDRESS OF MESSAGE (USER DEFINED) * 6144 * * 9145 * NOTE: END NESSAGE STRING WITH A BYTE 00 * * * 0148 * 8149 * 0150 00A6 0201 PRNT LI R1,VRANW ADDRESS TO WRITE DATA TO VRAI DOA8 9000

9151 AHAA 6202 LI _R2,VDPW ADDRESS TO WRITE TO VDP

0152 OOAE C483 MOV. R3,*R2 SEND LSB OF VRAli ADDRESS TO VDP

0153 ONG 06C3 SUPB R3 REVERSE BYTES

0154 OOB2 C483 HOV R3,*R2 SEND HSB OF VRAN ADDRESS TO VDP

0155 GGB4 DOB4 PRL1 HOVB *R4+,R2 GET BYTE OF TEXT FRO! NEM

9156 OOB6 1303 JEQ PRL2 IF ZERO, THEN END OF HESS

6157 OGB8 06C2 SUPR R2 INDEX BYTE INTO POSITION

SEGMENTS SDSMAC 3.4.0 81.117 13:36:55 TUESDAY, SEP 21, 1982. PAGE 0005

6158 BOBA C442 NOV R2,*R1 SEND CHAR TO VRAM

6159 SOBC 1OFB JMP PRL GET NEXT CHAR

6160 OOBE 045B PRL2 B *R11 RETURN TO CALLING PROGRAM

9161 * 0162 * 6163 erverrrrrerrrrerrrrerrr tt tt tttttitittititri tii ri rier lt 6164 * * 6165 * ERASE TO END OF SCREEN SUBROUTINE * 0166 * * 9167 * REGISTERS USED: * 9168 * * 0169 * Rl = RESERVED * 6170 * R2 = RESERVED * 6171 * R3 = ADDRESS IN NAME TABLE TO START ERASURE * 6172 * (USER DEFINED), R3 MUST BE EQUAL TO * 6173 * OR GREATER THAN >4409, AND NUST BE LESS * 6174 * THAN OR EQUAL TO >46FF * 0175 * .

0176 FOI III III III II II III RR IIIT TIA T AIS IIIA TAA IIR:

0177 *

8178 OOCO 0261 FEOS LI R1,VRAMW ADDRESS TO WRITE DATA TO VRAN

9179 60C4 0202 LI -R2,VDPIT ADDRESS TO WRITE TO VDP O0C6 9002 0186 66C8 C483 HOV R3,*R2 SEND LSB OF VRAM ADDRESS TO VDP

9181 GOCA 96C3 SPB R3 REVERSE BYTES

0182 OOCC C483 NOV R3,*R2 SEND NSB OF VRAM ADDRESS TO VDP

6183 OGCE 6202 LI R2,>26 LOAD R2 WITH 'SPACE' CHAR

0184 OOD2 C442 EESl NOV R2,*R1 SEND 'SPACE' TO SCREEN

6185 GOD4 9583 INC R3 INCREMENT CHAR COUNT

0186 OGD6 0283 CI R3,>4700 ARE WE AT THE END OF SCREEN

0187 SODA 1AFB JL EESI IF NOT GO AGAIN

6188 OODC 045B B *R11 YES, RETURN TO CALLING PROGRAM

9189 * 9190 * 6191 III RI ITI RIOR TOT TOR TOTO TT ITT TTI TTI TIO IR IT TTI TTR IRR IRI HT. 9192 * * 9193 * ERASE LINE SUB * €194 * * 6195 * REGISTERS USED: * G196 * * 0197 * Rl = RESERVED * 0198 * R2 = RESERVED * 0199 * R3 = STARTING ADDRESS IN LINE IN NAME * 0206 * TABLE TO BE ERASED (USER DEFINED) *

6261 III III III III III OITA IIIA TAT IA

6202 * 9203 *

6204 OODE 0261 ERLN LI R1,VRANW ADDRESS TO WRITE DATA TO VRAN

COEO 9906 ‘

0205 OGE2 6202 LI -R2,VDPW ADDRESS TO WRITE TO VDP

9206 OSE6 C483 NOV R3,*R2 SEND LSB OF VRAN ADDRESS TO VDP

0207 OOE8 06C3 SUPB R3 REVERSE BYTES

9208 OOEA C483 NOV R3,*R2 SEND NSB OF VRAN ADDRESS TO VDP

9209 OOEC 0202 LI R2,>20 LOAD R2 WITH 'SPACE' CHAR

0210 SOFG 6203 LI R3,32 LOAD R3 WITH # OF POSTIONS

SEGNENTS SDSNAC 3.4.6 81.117 13:36:55 TUESDAY, SEP 21, 1982. PAGE 6606 8OF2 0026

6211 OOF4 C442 ERL1 MOV R2,*R1 SEND 'SPACE' CAHR TO NAME TABLE

8212 OOF6 6603 DEC R3 DECREMENT CHAR COUNT

6213 6OF8 16FD JNE ERL1 IF NOT DONE, GO AGAIN

6214 OOFA 045B B *R11 LONE, RETURN TO CALLING PROG

0215 * 6216 *

0217 III III III IOI III IOI III IOI IOI ISITE

9218 * * 6219 * DRAW A HORIZ LINE * 6220 * * 0221 * REGISTERS USED: * 6222 * * 6223 * R3 = ADDRESS OF UPPER LEFT CORNER * 6224 * R4 = # OF HORIZ POSITIONS * 6225 * R5 = # OF VERT POSITIONS * 6226 * R9 = PATTERN # OFFSET * 6227 * *

0228 FOI IOIII IIIS ISI IIT ITC IIII III III ITI I IIE

0229 * 6230 *

6231 OOFC G201 DBOX LI R1,>9060 ADDRESS OF DATA TO 9918

9232 0106 0202 LI R2,>9002 ADDRESS OF ADDRESSES TO 9918 9162 9602 6233 0104 C483 NOV R3,*R2 SEND LSB OF ADDRESS TO 9918 9234 0106 96C3 SUPB R3 REVERSE BYTES 6235 9108 C483 NOV R3,*R2 SEND NSB OF ADDRESS TO 9918 6236 016A 06C3 SPB R3 REVERSE BYTES

6237 G16Cc C189 HOV R9,R6 GET OFFSET

6238 0160 9226 AI R6,>01 POINT TO UPPER LEFT CORNER PATTE 6110 6001 0239 0112 C446 NOV R6,*R1 SEND IT TO THE 9918 6240 6114 Clc4 NOV R4,R7 STORE I1ORIZ COUNT IN TEMP REG 0241 6116 0647 DECT R7 DETERMINE (LENGTH - CORNERS) €242 6118 1304 JEQ DBL2 NO LENGTH OTHER THAN CORNERS

6243 G11A C189 HOV R9,R6 PATTERN 60 + OFFSET

9244 Sl1C C446 PRBL1 NOV 26,*RIL SEND LINE SEGNENT TO 9918

6245 O11E 0607 DEC R7 DEC LINE COUNT

0246 9120 16FD JNE DBL NOT DONE YET, GO AGAIN 0247 0122 C189 DBL2 NOV R9,RE GET OFFSET 0248 6124 0226 AI -R6,>05 POINT TO UPPER RIGHT CORNER 0126 0605 0249 0128 C446 NOV R6,*R1 SEND IT TO 9918

9250 G12A C203 NOV R3,R8 SEND ADDRESS OF UPPER LEFT TO TE

9251 912c Clc5 NOV R5,R7 SEND VERT COUNT TO TEMP 0252 012E 0647 DECT R7 DETERNINE (HEIGTH ~ CORNERS) 9253 91306 130c JEQ DBL4 NO HEIGTH OTHER TIAN CORNERS 6254 6132 C189 HOV R9,RE GET OFFSET 0255 9134 9226 AI R6,>03 POINT TO VERT LINE PATTERN 6136 9003 0256 0138 6228 DBL3 AI R8,>20 INC VERT POSITION BY 1 CHAR 913A 0026 9257 013c C488 NOV R8,*R2 SEND ADDRESS TO 9918 0258 013E 96C8 SPB R8 REVERSE RYTES

9259 O14e c4ee HOV R8,*R2 SEND ADDRESS TO 9918

6260 0142 H6C8 SUPR RE REVERSE BYTES ©261 0144 CO46 NOV R6,RL SEND VERT LINE SEGNENT 70 9918 6262 0146 0607 DEC R7 DECRENENT VERT COUNT 0263 6148 16F7 INE DBL3 NOT DONE YET, GO AGAIN 421

SEGMENTS SDSNAC 3.4.9 81.117 13:36:55 TUESDAY, SEP 21, 1982. PAGE 0007 6264 014A 6228 DBL4 AI R8,>20 INC VERT POSITION BY 1 CHAR §14c 6026

6265 O14E C488 NOV R8,*R2 SEND ADDRESS TO 9918A

0266 9158 B6CB SUPB R8& REVERSE BYTES 6267 9152 Co88 MOV R8,R2 SEND ADDRESS TO 9918 0268 6154 96C8 SWPB R8 REVERSE BYTES 9269 8156 C189 MOV R9,R6 GET OFFSET 6270 6158 0226 AI R6,>82 POINT TO LOWER LEFT CORNER PATT O15A 8062 0271 615C C446 HOV R6,*R1 SEND IT TO 9918

6272 G15E Clc4 NOV R4,R7 SEND HORIZ COUNT TO TEMP

6273 0160 0647 DECT R7 DETERMINE (HORIZ - CORNERS) 6274 0162 1304 JEQ DBL6 NO HORIZ OTHER THAN CORNERS 0275 0164 C189 HOV R9,RG GET OFFSET 6276 0166 C446 DBLS5 NOV R6,*R1 SEND HORIZ PATTERN TO 9918 9277 6168 9667 DEC R7 DECRENENT HORIZ COUNT 6278 016A 16FD INE DBLS IF NOT DONE, GO AGAIN 9279 516C C189 DBL6 HOV R9I,R6 GET OFFSET

0280 O16E 0226 AI R6,>04 POINT TO LOWER RIGHT PATTERN

9281 6172 C446 HOV R6,*R1 SEND PATTERN TO 9918 9282 9174 C1C5 Nov. R5,R7 STORE VERT COUNT IN TEMP 0283 0176 0647 DECT R7 DECREMENT VERT COUNT 8284 9178 1312 JEQ DBL8 IF NO VERT SEGHENTS, DONE 6285 617A Cl1C4 NOV R4,R7 STORE HORIZ COUNT IN TENP 6286 017C 6607 DEC R7 DECREMENT HORIZ COUNT

0287 G17E C203 NOV R3,R8 STORE ADDRESS OF UPPER LEFT COR

6288 6180 A207 A R7,R8 FIND UPPER RIGHT CORNER LOCATION 6289 0182 C189 HOV R9,R6 GET OFFSET 6298 6184 0226 AI R6,>83 POINT TO VERTICAL LINE PATTERN 9186 0003 9291 9188 C1C5 NOV R5,R7 STORE VERT COUNT IN TEMP 6292 018A 0647 DECY R7 DETERNINE (HEIGHT - CORNERS) 6293 argc 9228 DBL7 AI R8,>20 INCREMENT VERT POSITION BY 1 CHA 618E 6020 6294 9190 C488 NOV R8,*R2 SEND ADDRESS TO 9918 9295 6192 06Cc8 SUIPB R8 REVERSE BYTES 6296 0194 C488 HOV R8,*R2 SEND ADDRESS TO 9918 6297 0196 06C8 SUPB RE REVERSE BYTES 0298 0198 C446 HOV R6,*R1 SEND PATTERN TO 9918 6299 619A 6607 DEC R7 DECRENENT VERT COUNT 0300 019C 16F7 SNE DBL7 IF NOT DONE, GO AGAIN

6301 G19E 645B DBL8 B *R11 SUB DONE RETURN TO CALLING PROG

0302 * 6303 *

0304 FI IIIS IIIS ISI ISIS IDIOT IOI SISISI IOI IGOR TO IGE

0305 * * 0306 * LOAD TEXT COLORS SUBROUTINE * 6307 * * 6308 * REGISTERS USED: * 6309 * * 9310 * R4 = COLORS FOR TEXT CHARACTERS * 6311 * *

6312 JESSIE ISIE EI IIIT ISIE SOI IIE IEICE IIIT IAI III III IAAI

6313 *

6314 O1AD 6201 LDTC LI R1,>9000

9315 G1A4 0202 LI -R2,>9002

9316 61A8 9263 LI R3,>4204 ADDRESS FOR TEXT COLORS IN 9916

SEGMENTS SDSMAC 3.4.6 81.117 13:36:55 TUESDAY, SEP 21, 1982. PAGE 9008 G1AA 4204 6317 @1AC C483 MOV. R3,*R2 SEND ADDRESS TO 9918

9318 B1AE G6C3 SWPB R3 REVERSE BYTES

9319 81BO C483 NOV R3,*R2 8 COLOR CHAR X 8 TEXT/CHAR = 64

0320 G1B2 C444 LCLI MOV R4,*R1 SEND WORD TO 9918

0321 61B4 6602 DEC R2 DECREMENT COUNT 0322 01B6 16FD JNE LCLI IF NOT DONE, GO AGAIN 6323 01B8 9455 B *R11 DONE, RETURN TO CALLING PROG 0324 * 6325 *

0326 FEI III III IO III IIIA IAI IIIT IIIT OTT IATA:

0327 * * 0328 * DRAW A VERTICAL LINE SUB * 6329 * * 0330 * REGISTERS USED: * 9331 * * 0332 * R3 = ADDRESS ON SCREEN * 8333 * R4 = # OF POSITIONS * 0334 * R9 = PATTERN OFFSET * 6335 * *

0336 FEI III III IOI III IIIT III ITO TOT IIA IAA:

9337 *

9338 G1BA C483 DVLN MOV R3,*R2 SEND ADDRESS TO 9918

6339 B1BC 06C3 SWPB R3 REVERSE BYTES

9340 O1BE C483 HOV. R3,*R2 SEND ADDRESS TO 9918 9341 61C0 86C3 SWPB R3 REVERSE BYTES 9342 01C2 C445 MOV R5,*R1 SEND PATTERN TO 9918

0343 END

NO ERRORS, NO WARNINGS 423

1. TMS9918A /9928A /9929A ELECTRICAL SPECIFICATIONS

5.1 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE

(unless otherwise noted)* . Supply voltage, Vg IO <8 P20 *Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions section of this specification is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliabili- ty.

5.2 RECOMMENDED OPERATING CONDITIONS*

Supply voltage, Vcc. 4.75 5.25 Input Voltage, Vj, RESET/SYNC pin High-level input, ViH Input voltage, V}, SYNC level 2.6 Vv EXT VDP pin White level 3.7 v (TMS9918A only) Black level 3 Vv Low-level input voltage, VIL Vv Operating free-air temperature, TA 0 70 °C * All voltage values are with respect to Vss.

5.3 ELECTRICAL CHARACTERISTICS OVER FULL RANGES OF RECOMMENDED OPERATING CONDITIONS

(unless otherwise noted) TMS9918A /992BA /9929A, PARAMETER TEST CONDITIONS | MIN TYPt MAX High-level RAS, CAS, R/W 2.7 3.4 VOH loH = 400 pA Vv output All other voltage outputs VoL v output DRAM lot = 800 pA voltage interface lozH Off-state output current high-level voltage Vo = 5.25 V 1 100 pA applied, D0-D7 outputs Jozi Off-state output current high-level voltage Vo = 0.4V uA applied, D0-D7 outputs hi High-level input current Vy = 5.25 V, all other pins at 10] pA Ov ti Low-level input current Vyp=0V, All other pins at pA ov TMS9918A Only (Figure 5-1) PARAMETER TEST CONDITIONS | min Nom max | UNIT Vwhite Video voltage level of white, COMVID 28 30 32V | | Vplack Video voltage level of black (blank), RL = 4702 COMVID 2.1 23 25V Veyne Video voltage level of sync, COMVID 1.85 20 21Vv | | + All typical values are at Vcc = 5.25 V, Ta = 25°C. 5-2

(unless otherwise noted) (Continued) TMS9928A/9829A Only (Figure 5-1) PARAMETER TEST CONDITIONS | min wom max | UNIT Vwhite Video voltage level of white, Y, R-Y, B-Y 2.5 3 36] Vv outputs Vblack Video voltage level of black (blank), Y, RL = 4702 1.6 2.3 251 v R-Y, B-Y outputs Veyne Video voltage level of sync, Y output 1.2 18 2 TMS9829A Only PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ves Color burst video voltage level with respect R-Y output 0.25 Vv to V no color Vneg Color burst video voltage level with respect B-Y output v to V no color TMS9918A /992BA /9929A (Figure 5-2) PARAMETER TEST CONDITIONS [ min NOM max] UNIT Video voltage difference, white-black, Y, 0.7 1.0 Vv R-Y, B-Y outputs Input unmeasured CG capacitance All other f=11 MHz, pins inputs atoV unmeasured Co Output capacitance f = 11 MHz, pins 20 aroVv + All typical values are at Voc = 5.25 V, T& = 25°C.

5.4 TIMING REQUIREMENTS OVER FULL RANGES OF RECOMMENDED OPERATING CONDITIONS

(TMS9918A /992BA /9929A) CPU - VDP interface (Figures 5-3 and 5-4) ee Ce ee ee Pann Atinenimeecswme [| [nal Ane neers ed [wow omanninnoaeeeswnn [wd | a non Rian coven imi Pewee [tT (requesting memory access) ae a (not requesting memory access) VDP-VRAM Interface (Figure 5-5 and 5-6) ee ee ee [acs _sosaeanmmmncise [ed [cio teatanavineswcarne fe id External Clock Source (Figure 5-7) eC ee ee 10.738635 10.739172 a oem iw Pit eeteriniwoumnan [ew | = | ra ee [> esse [= Ty falling edge to XTAL2 falling edge

5.5 SWITCHING CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED OPERATING CONDITIONS

(TMS9918A /9928A /9829A) CPU-VDP Interface PARAMETER TEST CONDITIONS | MIN TYP MAX UNIT mye we |. 6d | hi onenges C= 300 pF fCPUCLK CPU clock output clock frequency (fext + 3) 3.4 3.58 3.76 fGROMCLK GROM clock output clock frequency (fext + 24) 425.12 447.5 469.88 VDP-VRAM Interface (Figures 5-5 and 5-6) PARAMETER TEST CONDITIONS | MIN TYP MAX UNIT tw Pulse width, CAS high 80 100 120 | ns | twiCL) Pulse width, CAS low 220 230 250 | | twiRH) Pulse width, RAS high 100 125 150 twiRL) Pulse width, RAS low 190 210 230 | ns | tw(W) Pulse width, write pulse 170 190 210 | ns | — CL = 50 pF tCA-CL Delay time, column address to CAS -10 -2 ns low tRA-RL Delay time, row address to RAS low 25 45 65 | ns | tWH-CL Delay time, R/W high to CAS low 25 50 75 | = | tw-CH Delay time, R/Wlowto CAS high 120 140 160 | ns | tW-RH Delay time, R/W low to RAS high 60 75 90 | ns |

55 SWITCHING CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED OPERATING CONDITIONS

(TMS9918A/9928A /9929A) (Continued) TMS9918A Composite video output (Figures 5-8 and 5-9) pes =| = | == =p | see = a0 ae ae | Pose [oe cae Pe = ef = | Pee [=| eee [x0 oo | os |

(TMS9918A /$828A /9929A) (Continued) TMS9918A Composite video output (Figures 5-8 and 5-9) Pe | ce Ce ee [ee R, = 4702 Pee | CL = 150 pF [ee pei | Te syne Hs Lee NOTE: Fall times depend on external pull-down resistor 5-7

(TMS9918A /9928A /9929A) (Continued) TMS9928A/9929A Y, R-Y, B-Y outputs (Figures 5-10 through 5-13) i P= fe | Cs ce ce ee ce a oe [em ee ce ee ce ee ee R_ = 4702 ee ae Cy = 15 pF a ce ce oe ee a ee ace [ae [ae ee | ae NOTE: Fall times depend on external pull-down resistor.

| je—twi — VLE 08 V o—twH —! b-—tpp —o NOTE: All measurements are made at 10% and 90% points. FIGURE 6-7 — EXTERNAL CLOCK TIMING WAVEFORM Ware ‘witB) too tH Ves fr —| beter i tSaeal--—lp 1 1 No roo rN -- a) | taal be tae pal le tusco—e| b— ill ftwicer—ef II tae] FIGURE 6-8 — TMS9918A COMVID HORIZONTAL TIMING ! | ! \\

7 TAAIANMD Iu PY ~

LINENO, 242 243 244245246287 249 250251 wey 1 2 3 1 vertica | | VERTICAL | ENDBoTTOM =| FRONT [VERTICAL | BACK | START TOP BORDER | BLankines | sync | BLANKING* I BORDER *Color burst output suppressed FIGURE 6-9 — TMS9918A VERTICAL TIMING 5-12

“~F = = g a J___4 ; | _ ~S — t= s r—) ==: ¥ ii _ tai F ---.4 3 Z | ps 3 j : ° 5 > : : en oe 13 ; pte Pe ~ aH i 3 ; oT pf 1 2 Pa | pi-¥- F | 3 | f 3 | ae § 1 | 3 3 | tote | : - | fl : 7 => - I | 2 1g l a | | 7 1-2 F Ht 1 | to g 17 I § | : 2 | Z ls Z . 1 g 4 | £ A g og eis gy 5 8 pie gid = $ 5s - 3 ¢ 5-13

_ l £ t * E | | ---4 : a s “ e¢ \\ Ee _-t - §8 J a H & H = a g t < z ' zg = = Fy 1 Sz 7 5 = eSz g z= c4 g gas z g o> 7 @ 2 ] 3 8 4 a = = =] | 3 : 8 5 | att z a—---- | aE _ 3s | o z a <a, @ | Ibs j #3 EE f . | = 4 2 ? i l qt { i = & w oe A ---—- | =~ 2352 Ps n a r | Z 8 . | | 3 2.8 | i abo = Fy 8g See = | | a $ EOXx = 2 cee | fT, 138 ges 1 ¢ 12 g “ | l 3 - ----# \\ < a ! , | s g 5. : | zg, 2 g3 g z ge § | z | 3 g 2° = | 69 4 5 x F w o6g3 x 2 | : w a8 ¥§ o & | 3 F 66 8 g & 1 3 E ofa 5: | . $ S53 FF 514

1. MECHANICAL DATA

6.1 TMS9918 40-PIN PLASTIC DUAL-IN-LINE PACKAGE

2.090 (83,1) max eas oY enone! us Yan Yen Yes TunVontontantontontent ont ont met ston EITHER {__) INDEX ~~ a | & 0600-0010 © (15,24 + 0,26) 0.020 (051) MIN = — SEATING PLANE 105. Ft 0.125 (3,17) MIN 90 0.011 : 0.003 0.018 + 0.003 sity PIN SPACING 0.100 (2,54) T.P. See esa (See Note b) 0.060 (1,52) NOM 088 (1-38) NOTES: a. All linear dimensions are in inches and parenthetically in millimeters. Inch dimensions goven. b. Each pin centerline is located within 0,010 (0.25) of its true longitudinal position,

62 TMS9918 40-PIN CERAMIC DUAL-IN-LINE PACKAGE

yy ~~ 20m0 8131 max iN ao of) HO . Soom ee oe eo eo \\ INDEX por 0.600 - 0.010 C—O carom + FFU FL FN FL FFF Ff 9 Go 018 + 0.003, 0.010 (0.25) NOM PIN SPACING 0.100 (2.54) TP (127 +0511 (See Note b) 0.050 + 0.010 (1.27 + 0.26) NOTES: a. All linear dimensions are in inches and parenthetically in millimeters. inch dimensions goven. b. Each pin centertine is located within 0.010 (0.26) of its true longitudinal position,

Software programs apply to all three VDPs (TMS9918A/9928A/9929A). A-1

This appendix contains the diagrams and software listing of an upper and lower case ASCII character set. The character matrix is 5 X 7 in the 8 X 8 pixel block. These characters are left-justified so they can be used in the text (6 X 8 pixels) mode. PATTERN PATTERN PATTERN PATTERN 20 21 22 Es] [TT TTT TT | -% [TT TTT -2 ae eee <8 Pye t TT TT | = [Te TTT -2 am See hed Perr re rt -o0 (Ta -2 Ce | -2 Fe PPT Tr TT | - 0 Te TT) -20 PEt rr -0 =80 tT TT ey TT | -o OS Seeeee CTT ete TTY -o0 7Fe CETTE TT -00 PT = 00 PT -00 50 PEPE TE Ty | - 00 LT -2 PETE - 0 =50 COTY TT TT) - 0 CYT TTT TT «00 CYT TTT TT - 00 00 PATTERN PATTERN PATTERN PATTERN 24 25 26 27 (Tm Ty TT) -2 PTT TT) -o = Seeeee CT TT TT -2

2 TT] -7 Cm TT] -cs Le -40 [Tee TT TT -2

8 Seeeee aan seek GS sane) an Beeeer

t Pt] -7 Ce TT -20 Le -40 PPT TTT -00 [| eT) -2 SS Seana a 8 eee Py 00 ae See en Ber Gn sees, PPT TT) - 00 Lr -2 eee 6a im 8 6 OE PTT TT Ty - 00 LIT TTT TT - 00 CITT TT TT «00 CET TT TET | - 0 CITT ITT TTY - 0 PATTERN PATTERN. PATTERN PATTERN bd 29 2a 28 mT TT) -2 ae seeee Cm TT) -2 CTP TTT) -» Pe - «0 CT a) - 10 ee as Ca TTT) -2 pip yy -% Bane Beer L] LTT) -7 Pe) TT) -2 PT TT | - 2 PP TT - oe TT TT -2 it Ty -re PTT) - 2% Seen wear = PTT -7 LT ae TT) -20 | TT) «40 enn Beer | TT eas L] eT -2 an Seeeer [Te -20 ee seeenr. PPE TTT TT - 00 CET CEPT TY - 0 CLT TT TTT - 00 CLI TTT TTY - 0 CET TET TTY - 00 PATTERN PATTERN PATTERN PATTERN 2c 20 2 2F CTT TTT TT) -% CTT TT TT) -° [TTT TT yyy -% [TTT Ty fy) - LT TTT Ty -% PP Ty = 2° Pry ety yyy -% Seen Beek CPP rT -% Py yy = LTT TTT yy = een Seeee Pr Ty - 0% yy -Fe Pir ry Ty =o ae Seeee ae See PTT TT TT <0 PPP eT Ty -2 ae Seems [tm TT TT -2 CTT «0 See LTT Ty - 2% Ce TT -40 PPP) - 00 [eT Ty -20 LT - 00 CETTE TTT - 0 CITT TTT) - 0 CIT TT TTT} - 00 CTT er TT - 00 PATTERN PATTERN: PATTERN: PATTERN 30 31 32 33 *70 [TT] -2 = Cy) -7 TTT) -re -88 Hel AHH =60 Lt TT -ss Seen Seah. =98 an Seen SEB8 BSen See see =A8 CCBILL -2 | TT -20 (| ie 20 =o rl mili|j-> we - 40 Seen Sen =88 aS seeee Py | -2 SSn Baek) =70 J TTT] <7 {TT «re |_| LT TT -7 =o CLIT PT Py) - 0 LITTLE T TT | -o CELT ET TT - 00 PATTERN PATTERN PATTERN PATTERN 4 35 36 37 See Bene TTT) -Fe [Ty CTT) = [TT] -re [Tee TT -20 PT TT -% me ey -« eum See Oe eee) PT Fo PT -2 CO - 10 G8 SEeEr Bene Baer PT Ty -r0 ae Seeeee CT - re Ca TT «os Bee Been me TT) - «0 ean eee San seek Gan sear a eee San Seeer a it -7 LJ {TT -7 te TT -40 CITT ETT TY - 00 CLIT TTT - 0 CLIT CT TT - 00 CLE TE TT TY -0 A-2

PATTERN PATTERN PATTERN PATTERN 38 39 3a 3B C] LJ Ty: C] Ly yy) -7 [TTT TT TT) -% (TTT TT TT) -» SEn BER Ene See PTET TT TT) - 0 PP perry = Gan meek G8 SEB on seen) Cry) -» C | CT <7 = PT -7 COTTE - 0 COE «0 She Baan Een SRE ae Seeee Se Seen) En Beek Onn SER PPT TTY -00 Le Try -2 i. LITT] - 7 PTT «eo CTT TET - 0 Car - «0 CLIT EE TTY - 00 CET TPT ry -o0 CECT TY) - 0 CLIP ET Tr) - 0 PATTERN PATTERN PATTERN PATTERN 3c 30 3E oF S88 BeBe CTT TTT TT) -0 SO Seeeeeey CJ CTT: Com Ty -2 COT TT] «0 CU - = aus Been = eeeeee CTT] - rs Co TT) «1 Sen Seen CT - CT - 00 CP TT | -0 Ce Pry -2 = Benes CTT. BEG sane a CCT -2 CTT - 2 PTT TTT - oo ae seeee Pp TY 00 eee see COT) «0 ee 0 on seen) “CETL ET TT) - 00 CEPT TTT - 00 CTT TT ETT | - 0 CTY Ci TTT 4-0 PATTERN PATTERN PATTERN PATTERN 40 at 42 43 *70 an Seeee =FO C Py yy) -7 ad a 8 Bee ~88 SB8 SES -aa Ene Seek ~88 PTT yy -% ~es Ce -s “Fo CTT -% =80 [Ty -re =88 PTT TT - 2

20 Sen Bee = 08 S58 seen

778 TT a TT - 2 =F0 1] {Ty <7

. =00 CETTE TTT) - 0 =00 CLIT TT TT) «0 PATTERN PATTERN PATTERN PATTERN “4 45 46 47 Ly Ty: _T] -F Ty -F Cy [Ty - SEE BER SEUREEER SEEEEEER Sueeeea ann Bak CT «0 TTT -* TTT -% San Seek PTT) -ro TT - ro Py Ty - 2 SEH Beak Petey -2 PIT tty) -2 | a - 2s Gnn Senn Py = 20 TCC = « ans ses PTT - ro [_[) - re TCL ery - 2 | LTT -7 LETT TT TT] - 0 LET TT TTT) - 00 LOCI TH) - 0 CLE LT TTT) - 0 PATTERN PATTERN PATTERN PATTERN 48 49 4a 4B Sn SEeh ‘2 (1 -» anne week Sen Beh Gan sna CT a Tr - 2 Bees eeek Cm TT -% Gms seen) an Sees) Coa CT] -os Cm Ty -~ | [yj -rs a8 Seeeee CPT a TT -os SESEeaR een Been COT - 2 aaen Beer Ss Benen CTT ee TT -ss ae Seer Ens Baer P| MTT -2 GG8 S8nn ] PTT - 2 ] PTT | -7 Gan Seer LETTE TTT | 2 CLI TET TT - 00 CLT TTT TTY - 0 LETT YT TTT | - 00 PATTERN PATTERN PATTERN PATTERN 4c 4D 4 oo 0 smansee San Baek Sn8 BGG LJ - PTT Ty -» a S88 GBS BBRhe Enn BSS CPP - 2 BS 8 meek Ge Saab SEe SEB PTT TTT | - 2 a8 seep a 8 SSee a - 2 PTT - 2 San BEac) T| Met i- SEE S88 TT - 20 [ll mm iii-e TT Md -s ane SeeR TT «es Se ner a - 2 = {| TT) - 7 CEP TE TT TY 00 LEPTT TT) - 0 LITT ETT) -00 CYT TTT TT] 00

PATTERN PATTERN PATTERN PATTERN 50 51 53 Py: Dy TT ty-* [TJ 7): DO euenia SEB BSR nn BBBRY ann BEER CT eT -2 Sen Bene a - S58 Bee, Lt} tT | - PT -F En Benny TTT] «ro J Cy TT -7 PTC Oo 8 Sea |e Ty - 0 euan seek, TTT Ty )-» on seen CT - 2 Ban see TT -» a 8 seeg) gan Seen) LI it -7 CEPT TTT - 0 CEPT Fry - 0 CITT Cr} «oo CLE TTT TT - PATTERN PATTERN awe PATTERN iJ 55 57 rT - ann Seek TTT -« oa - LT me TT -2 Te «= Cr -s TTT] - 2 CC TTT] - 2 Te -% CE - 2 Te -s On Seeeee Te TT -# CT - 2 aS 8 gear ae eeeeery Te -« eT «2s a_8 seen Cre TTT -» ann 2See Le TT] - 5 a see Cay - 2 LI] | TT - 7 on seeeee Tt TT - ss COT TT TTT - 0 CLEETT TT - 0 CTT TTT TT) - COTTE TTT - 0 PATTERN PATTERN PATTERN PATTERN 58 59 5A 5B Ome SRE SEE Beh [TT -re -Fe Gan SEB) San weak Lit Te TT] -% ed | oe a 8 mee Co TT -° ed oe Seen Cem Try -» Com TTT -2 0 Ce TT - 50 [lmtiiii|-» Ce -« ed EGG Seer) an Semee.) PTT Ty TT] -2 =o Gnn See CTT] -2 CTT) «re Fe LOTT TTT - 0 COE -o CIT TT TTT) - 0 -00 PATTERN PATTERN PATTERN PATTERN 5D SE SF CT -~ “Fe CO -~ PAA: SEBEREER, 18 CCC -» SReeeEeee i” See 18 a8 Benee) Se SREReE) CT TT -2 “18 Se seeek) ETT Ty TT -00 LT - 1 -18 Su8 BeBe) CTT TTT - 00 COT i - 8 -18 CTT Ty -« Pe | - 00 COT Ty -o =F8 COT - 00 CO - oo COCCI TT «0 +00 CCOCTTTTLT J - oo [TTI -rs PATTERN PATTERN PATTERN PATTERN 60 61 62 63 oS meen Co: CT T-~ TTT: | «20 Perry yy -° Cy = CoE] = een Sees Cy CT): CT}: C) - PP TT TY - 20 Gun meek = oe eee PTT Tr] H+ =o TT) -F a LT} -7 SRREEEER =o gen meek, Ss oe eee Co -2 CTT - «0 CC eT -» i TTT) - ro tC] TT -7 COTTA 14 - 00 CTTrt Try - 0 CITT TTT 1) -0 CET TT TTT - 0 vaTTERN PATTERN PATTERN PATTERN 65 67 Sennen Citi -~ Sennen Coo -~ Corry Co -« SenneEEe Cor TTT - 00 amen Coy-. anna Cy CTT] - 72 = 28 28 aueneee auennes PTTL TT 20 no 28 268 Ennead) gnnn8 a TT - es = 88 288 suaeneen Snnnen8 Ce | -es nnn TT -ro SBnE5n8 L] PITT «70 CITT Tr rr) LITT Cr rr) -0 Corr rr CLIT TTT - 0

PATTERN PATTERN PATTERN PATTERN 68 69 6A 6B cot -~ COT -~ Coo - codon -» CTT yy] -% Cr] «0 CTT - 0 CTT Ty] -% EBB SEER TT Tj -rs _] TTT -7 Tm ei -% Gan BEER. on Seeeee ae apeeen BS seeeeo CT] «rs Ca TTT) -2 Cm Cr «2 TCH - co gee Beet ae seeeer @ eseeep PT - a0 a -s TT | «re TT «eo ae Seer LIT TT TTT] -00 LL TI TT Tf -o0 LL ETT TTT - 0 LITT TTT TY -00 PATTERN nn PATTERN PATTERN 6c 6E oF CTT TTT -~ (TTT TT TT) -° LTT TTT TT -~ [TT TTT TT Py yt -% Cry Er -° Crt yr PTT -% San Senha CT) -s ann PTT TT | -2 SB sea Gn seek) ann 888 PPT) - 2% B 8 BSS Ce - ann ona PTT - 20 gen week an sua TL CT «re TT -e Ce - ann LiL TT TTT | -0 LITT CTT) - 0 LITT) TTT} «00 CITT Tritt mane rane PATTERN PATTERN 2 Ay CTT - CT -~ CTT TIT TT -* Coo -» Cory -2 Cry Ty]: Py -° Lt | -00 Cr: Ty -F CT): = iT -7 aes Seah aun Seen CL ae TT -s CT rr «2% {tT Ty -r a 8 See | Jy - re 14 Pty -70 PTT TT -» Co] mm | TT] -2% yy -% eune Seek) CCP -» eT - «0 Gn gues LITT -r COTTTTTT - 0 CITT TTT] - LITT TTT -0 CEPT TTT TY] - oo PATTERN PATTERN PATTERN PATTERN “4 75 76 7 TTT Co y)-~ Co) -~ CTT -~ Cyr COTE «00 Lr) -% CO - aan CT -2 CCH - 8 Ce -% an Benes SHB BEER Te TT - CCL] -« oe saeen ann seen Co TT] -% aS 8 seen Com TT ann Sec) me - 10 a ween oe Seeee | (TTT) -7 Li CCT - «0 TCT] - COT TTT) CLL TTT TT) -% CITT TT - 0 LOTTI TIT) -% PATTERN PATTERN PATTERN PATTERN 78 79 7A 78 PITT -~ PTT: CITT TT -~ [Tt [TT]: pe «2° Coy yy -* Potty TT: aT Pry = aan Sen San Seek Tr -r Chm Tr) -2 oe eee = 8 eee LU TT: PTT Ty) - oe a +++ 2 Ge semen, a -2 LL Ty -= eo 8 eee Ca -» S suse So sae ome See Ce Cr -» CT «re Cr TH - LIT TL TTT] -0 COPE TT - 0 LIT TT ETT «0 COT TT TTT] -0 PATTERN PATTERN PATTERN PATTERN 70 7 7 7 i Seeeeeiee (TTT: So Seeeeei a 8 BEeh oe Semen Lt -° S 8 Seat Ty] -s0 aon Seen an eneeee Se epee oe eee oan See CC eT COT ery] -» a 8 Beeee an See CT Py -2 CEPT TT] - = 8 seep Com Cry -» Cm -° CCC] -% CTT «50 eS seenes) PT -e CECT ET «0 (= as CEPT Tr) - CIT TT rT} - COCTTT ET - 0% LOTT TTT} - 0 AS

When choosing the VRAM memory, the user must take into consideration the propagation delay times of the ‘system in addition to the access time of the memory and data setup time of the VDP. After the VDP outputs a low level signal on RAS, there is a delay time (t, (RAS, ) for this low level to reach the VRAM memory; there is a similar delay {tgicas)! for a signal output on the CAS pin to real AAS VRAM memory. Finally, there is a delay \\ta(datay) for data output by the memory to reach the VDP. These delays (shown in Figure B1) depend on the length of the wires between VDP and memory, and on the capacitive load being driven. Valid data appearing on RDO-RD7 is strobed into the VDP when CAS is brought high. Therefore, the memory chosen must have fast enough access times, tar) and tac) so that valid data is present on RDO-RD7 when a positive transition occurs on CAS. For 16-K memories from Texas Instruments (TMS4116-XX), the times, tac and taicy: Can vary, but their sum is equal to tar) (eect + tac) = tap) Thus, when taiRAS) 2 taicas) the limiting access time is tary After the memory receives a negative transition on the RAS input, the memory access time, tary must be fast enough so that valid data is present on RDO-RD7 when CAS goes high (see Figure B2). The equation for this is: truce + ‘wet? tap) * fa(datay + tsu(D-cH) Under worst case conditions, this equation can be used to find out how much time is allowed for system delays using different memories. TABLE B-1 — WORST CASE TIMING FOR VDP. MEMORIES SYSTEM DELAYS twCL 230 ns MIN tRL-CL 40 ns MIN tsu(D-CH) 80 ns MAX If the values from Table B1 are placed in the equation, we find (Ree + twee! VDP MIN > (tyRas) + taidatay) SYS + taipy MEM +ton.cy VOP MAX] 210 ns - tap) MEM MAX 2 [ taRAS) + tyidatay! SYS MAX TABLE B-2 — DRAM SYSTEM DELAYS PaRTNO. [wm eveTem peLave 4116-15 150 ns 60 ns MAX 4116-20 200 ns 10 ns MAX 4116-25 50 ns ~40 ns MAX From the data given here, the VDP will work with both -15 and -20 TMS4116 dynamic RAMs provided the system delays are smal enough. The VDP does not meet the tay ) specifications for the -25 TMS4116 and is unable to use the -25 under worst case condi- tions. The VDP has been verified to aR with both -15 and -20 TMS4116s in a system application. Note that in addition to the equation derived above, that all memory timing requirements must be met as specified in a memory data book. B-1

° | VDP CAS VRAM 9918A/ MEMORY 9928A/ 4116-XX (8 in parallel) 9929A RDO pi RD7 _ | FIGURE B-1 — MEMORY CONFIGURATION SHOWING DELAY TIMES. voP RAS | twiRL} \\ TIMING a es l — | t CAS wc) ———4 | I (] le ALCLO \\ ! i | DATA | ! 1 i ; ot 1 | td(DATA) a tsulD-CH) | | | | \\ nS VRAM RAS I 1 TIMING I | | \\ \\4 | td(RAS) — \\ \\ II \\ oAS | | \\ Vt ' \\ 1 | acs) I fe tnt ct of —§taic—o} | I | FIGURE B-2 — RELATIVE TIMING OF VRAM TO VDP. B-2

PATTERN AND SCREEN WORKSHEETS ci

November 1982 Post Office Box 1443 * Houston, Texas 77001 MPO10A Semiconductor Group Printed in U.S.A.