TMS9900

TMS9901 TI | Alldatasheet

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1. INTRODUCTION

1.1 DESCRIPTION

The TMS 9901 Programmable Systems Interface is a multifunctioned component designed to provide low cost interrupts and 1/0 ports in a 9900/9980 microprocessor system. It is fabricated with N-channel silicon-gate technology and is completely TTL compatible on all inputs and outputs including the power supply (+ 5 V) and single-phase clock. The Programmable Systems Interface provides a 9900/9980 system with interrupt control, 1/0 ports, and a real-time clock as shown in Figure 1.

1.2 KEY FEATURES

© N-channel Silicon-Gate Process © 9900 Series CRU Peripheral © Performs Interrupt and I/O Interface Functions = 6 Dedicated Interrupt Input Lines — 7 Dedicated 1/0 Ports — 9 Ports Programmable as Interrupts or I/O © Easily Stacked for Interrupt and 1/0 Expansion © Interval and Event Timer © Single 5 V Supply 2. FUNCTIONAL DESCRIPTION

2.1 CPU INTERFACE

The TMS 9901 interfaces to the CPU through the Communications Register Unit (CRU) and the interrupt control lines as shown in Figure 2. The CRU interface consists of 5 address select lines (S0-S4), chip enable (CE), and 3 CRU lines (CRUIN, CRUOUT, CRUCLK). When CE becomes active (low), the 5 select lines point to the CRU bit being accessed (see Table 1). In the case of a write, the datum is strobed off the CRUOUT line by the CRUCLK signal. For a read, the datum is sent to the CPU on the CRUIN line. The interrupt control lines consist of an interrupt request line (INTREQ) and 4 code lines (ICO-IC3). The interrupt section of the TMS 9901 prioritizes and encodes the highest priority active interrupt into the proper code to present to the CPU, and outputs this code on the ICO-IC3 code lines along with an active INTREQ. Several TMS 9901's can be used with the CPU by connecting all CRU and address lines in parallel and providing a unique chip select to each device.

2.2 SYSTEM INTERFACE

The system interface consists of 22 pins divided into 3 groups. The 6 pins in Group 1 (INT! — INT6) are normally dedicated to interrupt inputs (active low), but may also be used as input ports (true data in). Group 2 (INT7/P15 — INT15/P7) consists of 9 pins which can be individually programmed as interrupt inputs (active low), input ports (true data in), or output ports (true data out). The remaining 7 pins which comprise Group 3 (PO—P6) are dedicated as individually programmabte I/O ports (true data).

2.3 INTERRUPT CONTROL

A block diagram of the interrupt control section is shown in Figure 3. The interrupt inputs (6 dedicated, 9 programmable) are sampled by @ (active low) and are ANDED with their respective mask bits. If an interrupt input is active (low) and enabled (MASK=1), the signal is passed through to the priority encoder where the highest priority signal is encoded into a 4 bit binary code as shown in Table 2. The code along with interrupt request is then output via the CPU interface on the leading edge of the next G to ensure proper synchronization to the processor 1078 1

° ooo000 CONTROL BIT(1) CONTROL BIT!) 1 oooot INTH/CLK 12) Mask 1/CLK1(3) 2 00010 INT2/CLK2 Mask 2/CLK2 3 00011 INTS/CLK3- Mask 3/CLK3 4 oo1r00 INT4/CLKA Mask 4/CLK4 5 00101 INTS/CLKS Mask SICLKS 6 oo1rre INT6/CLK6 Mask 6/CLK6 7 oornd INT7/CLK7 ‘Mask 7/CLK7 8 o1000 INTS/CLKB Mask 8/CLKB 9 o1001 INT9/CLKO Mask 9/CLK9 10 o1010 INF10/CLK10 Mask 10/CLK10 W o1rond INTH1/CLK11 Mask 11/CLK11 12 o1100 INTI2/CLK12 Mask 12/CLK12 13 orto INTIS/CLK13 Mask 13/CLK13 14 01110 INTI4/CLK14 Mask 14/CLK14 15 orraid INT1S/INTREO Mask 15/RST2(4) 16 10000 PO Input!5) PO Output'6) 7 10001 PA Input P1 Output 18 10010 P2 Input P2 Output 19 rood P3 Input P3 Output 20 10100 P4 Input P4 Output 2 10101 PS Input PS Output 2 10110 P6 Input P6 Output 23 1o1rtd P7 Input P7 Output 24 11000 P8 Input °8 Output 25 11001 P9 Input P9 Output 26 11010 P10 Input P10 Output 2 110114 P11 Input P11 Output 28 11100 P12 Input P12 Output 29 1.1404 P13 Input P13 Output 30 11110 P14 Input P14 Output 3 ra4r4id P15 Input P15 Output NOTES: (1) 0= Interrupt Mode 1 = Clock Mode (2) Data present on INT input pin (or clock value) will be read regardless of mask value. (3) While in the Interrupt Mode (Control Bit ~ 0) writing a “1"" into mask will enable interrupt; a "0" will disable, (4) Writing 2 zeroto bit 15 while in the clock mode (control bit = 1) executes o software reset of the 1/0 pins. (5) Data present on the pin will be read. Output data can be read without affecting the data, (6) Writing data to the port will program the port to the output mode and output the data. ) 3 | 1076

| i oj | I | «fae od | ” | 2 paioninizen i secoven ii 1 1 ge | | | ole oe] a | | ra] cc | J | | C F< | 5 I a ot a FIGURE 3 — INTERRUPT CONTROL LOGIC ‘ 1076

[Lisrennversrare | enonny | co | ter [2 | ca | rao | INT1 1 (HIGHEST) 0 ° 0 1 ° INT 2 2 o °o 1 oO o INT 3/cLock 3 ° o 1 1 0 ints 8 ° 1 0 1 ° INT6 6 ° 1 1 0 C) iNT? 7 o 1 1 1 0 INTs 8 1 0 0 o 0 int 9 9 1 ° ° 1 ° INF 10 10 1 0 1 ° ° int 11 " 1 ° 1 1 ° INT 13 13 1 1 ° 1 o INT 14 14 1 1 1 ° ° iNT 18 15 (LOWEST) 1 1 1 1 ° NO INTERRUPT - 1 1 1 1 1 The output signals will remain valid until the corresponding interrupt input is removed, the interrupt is disabled (MASK-=0), or a higher priority enabled interrupt becomes active. When the highest priority enabled interrupt is removed, the code corresponding to the next highest priority enabled interrupt is output. If no enabled interrupt is active, all CPU interface lines (INTREO, ICO-IC3) are held high, RST! (power-up-reset) will force the output code to {0,0,0,0) with INTREG held high and will reset all mask bits low (interrupts disabled). Individual interrupts can be subsequently enabled (disabled) by programming the appropriate command bits. Unused interrupt inputs may be used as datum inputs by disabling the interrupt (MASK=0).

2.4 INPUT/OUTPUT

A block diagram of the I/O section is shown in Figure 4. Up to 16 individually controlled 1/0 ports are available (7 dedicated, 9 programmable). RST1 or RST2 (a command bit) will program all ports to the input mode. Writing a datum to any port will program that port to the output mode and latch out the datum. The port will then remain in the ‘output mode until either FIST1 or AST2 are executed. Data present on the Group 2 pins can be read by either the Read Interrupt Commands or the Read Input Commands. Group 2 pins being used as input ports should have their respective Interrupt Mask values reset (low) to prevent false interrupts from occurring. In applications where Group 1 pins are not required as interrupt inputs, they may be used as input ports and read using the Read Input commands. As with Group 2 ports, any pins being used as input ports should have their respective Interrupt Masks disabled

2.5 PROGRAMMABLE REAL TIME CLOCK

‘A block diagram of the programmable real time clock section is shown in Figure 5. The clock consists of a 14 bit counter that decrements at a rate of F(¢)/64 (at 3 MHz this results in a maximum interval of 349 ms with a resolution ‘of 21.3 us) and can be used as either an interval timer or as an event timer. The clock is accessed by writing a one into the control bit (address 0) to force CRU bits 1-15 to clock mode. (See Table 1.) Writing a nonzero value into the clock register then enables the clock and sets its frequency. During system set up ‘this entire operation can be accomplished with one additional \\/O instruction (LDCR) as shown in Table 3. The clock functions as an interval timer by decrementing to zero, issuing an interrupt, and restarting at the programmed start 1076 5

it < fH cru cRU | | INTERFACE Locic 1/0 PORTS | (POP15 MAX) v0 | DATA | _ <|H FIGURE 4 - 1/0 INTERFACE 6 1076

FIGURE 5 — REAL TIME CLOCK TABLE 3 SOFTWARE EXAMPLES ASSUMPTIONS = System uses clack at maximum interval = Total of 6 interrupts are used = Bits are used as output port — 8 bits are used as input port = FIST! (power up reset) has already been applied System u R12,PSIBAS ‘Setup CRU Base Address to point to 9901 seen, focr «exo Program Clock with maximum interval Inwrupt [Loc @Y,7 Re-enter interrupt mode and enable top 6 interrupts ‘System ut R12,PSIBAS+ 16 Move CRU Base to point to I/O port oer Locr R18 Move most significant byte of R1 to output port Ports Read im RI2PSIBAS+ 24 Move CRU Base to point to input ports Programmed P froare ster §=— 8 Move input port to most significant byte of R2 (0 ——>F FFF Don't Cares sie cLKVCT Save Interrupt Mask cuKec Lim 0 Disable INTERRUPTS u RIZPSIBAS +1 Setup CRU Base $80 -1 Set 9901 into Clock Mode, Latch Clock Value STCR RA, 14 Store Read Register Latch Value into Ra sBz a Reenter Interrupt Mode and Restarting Clock aTWe Restore Interrupt Mask clKveT DATA —_—_CLKWP, CLKPC 1076 7

value. When the clock interrupt is active, the clock mask (mask bit 3) must be written into (with either a “1” or a“O") to clear the interrupt. If a value other than that initially programmed is required, a new 14-bit clock start value is similarly programmed by executing a CRU write operation to the same locations. During programming the decrementer is restarted with the current start value after each start value bit is written, A timer restart can be easily implemented by writing a single bit to any of the clock bits. The clock is disabled by RST! (power-up-clear) or by writing a zero value into the clock register. Enabling the clock programs the third priority interrupt (INT3) as the clock interrupt and disables generation of interrupts from the INT3 input pin. When accessing the clock all interrupts should be disabled to ensure that system integrity is maintained. The clock can also function as an event timer since whenever the device is switched to the clock mode, by writing a one to the control bit, the current value of the clock is stored in the clock read register. Reading this value, and thus the elapsed event time, is accomplished by executing a 14 bit CRU read operation (addresses 1-14). The software example (Table 3) shows a read of the event timer. The current status of the machine can always be obtained by reading the control (address zero) bit. A “0” indicates the machine is in an interrupt mode. Bits 1 thru 15 would normally be the interrupt input lines in this mode, but if any ere not needed for interrupts they may also be read with a CRU input command and interpreted as normal data inputs. A "1" read on the control bit indicates that the 9901 is in the clock mode. Reading bits 1 thru 14 completes the event timer operation as described above, Reading bit 15 indicates whether the interrupt request line is active. A software reset RST2 can be performed by writing a “1” to the control bit followed by writing a 1” to bit 15, which forces all 1/O ports to the input mode.

2.6 SYSTEM OPERATION

During power up RSTI must be activated (low) for a minimum of 2 clock cycles to force the TMS 9901 into a known state. RST1 will disable all interrupts, disable the clock, program all I/O ports to the input mode, and force ICO-IC3 to (0,0,0,0) with INTREG held high. System software must then enable the proper interrupts, program the clock (if used), and configure the I/O ports as required (See Table 3 for an example). After initial power up, the TMS 9901 will be accessed only as needed to service the clock, enable (disable) interrupts, or read (write) data to the 1/0 ports. The 1/0 ports can be reconfigured by use of the RST2 command bit. Figure 6 illustrates the use of a TMS 9901 with a TMS 9900. The TIM 9904 is used to generate RST to reset the 9900 and the 9901 (connected to RST1). Figure 7 shows a TMS 9980 system using the TMS 9901. The reset function, load interrupt, and 4 maskable interrupts allowed in a 9980 are encoded as shown in Table 4. Connecting the system as shown ensures that the proper reset will be applied to the 9980. TABLE 4

9980 INTERRUPT LEVEL DATA

INTERRUPT VECTOR LOCATION INTERRUPT MASK VALUES CODE FUNCTION (MEMORY ADDRESS DEVICE ASSIGNMENT TO ENABLE (1co-1¢2) IN HEX) (8T12 THROUGH S15)

110 Level 4 0010 External Device 4 Through F

101 Level 3 oooc External Device 3 Through F

100 Level 2 oo08 External Device 2 Through F

o1t Level 1 oo04 External Device 1 Through F oot Reset 0000 Reset Stimulus Don't Care

010 Load 3FFC Load Stimulus Don't Care

ooo Reset oooo0 Reset Stimulus Don't Care

144 No-Op = =

2.7 PIN DEFINITIONS

Table 5 defines the TMS 9901 pin assignments and describes the function of each pin. TABLES ‘TMS 9901 PIN ASSIGNMENTS AND FUNCTIONS signature] Pin] v0] DESCRIPTION INTREG 11 | OUT] INTERRUPT Reauest. When active (low) INTREQ indicates that an enabled interrupt wn 40 Vee hhas been received. INTREO will stay active cnuour 2 aed until all enabled interrupt inputs are re- erucLK 3 PO moved. RUIN & Pa) tco(mss) | 15 | OUT] Interrupt Code tines. 1CO-IC3 output the es = St ier 14 | OUT] binary code corresponding to the highest ire 6 = 2 1c2 13 | OUT| priority enabled interrupt. If no enabled NS 7 “NTS 1c3(LsB) | 12 | OUT| interrupts are active ICO-IC3 = (1,1,1.1). NTs 8 im ree cE 5 | IN_ | Chip Enable. When active (low) data may be na 8 1 ene transferred through the CRU interface to mam oe ne CPU. CE has no effect on the inerups an 2 ae 7 e213 3 NTIS so 39 | IN | Address select lines. The data bit being ae 2 whine si 36 | IN | accessed by the CRU interface is specified ‘co ts a 82 35 | IN | by the S:bit code appearing on SO-S4, vee = 8 St IN ni ma se INTE 2 NTT CRUIN 4 | OUT] CRU deta in (to CPU). Data specified by Ps 19 ia 'S0-S4 is transmitted to the CPU by CRUIN. aang noe When CE is not active CRUIN is in 2 high- impedance state. cRuoUT 2| IN | CRU data out (trom CPU). When CE is active, data present on the CRUOUT input will be sampled during CRUCLK and written into the command bit specified by SO-S4. CRUCLK 3| IN. | CRU Clock (from CPU), CRUCLK specifies that valid data is present on the CRUOUT line. RST 1 | IN | Power Up Reset. When active (low) FST1 resets ali interrupt masks to “0”, disables the clock, and programs all 1/0 ports to inputs. FST1 has a Schmitt-Trigger input to allow implementation with an AC circuit as shown in Figure 6. Vee 40 Supply Voltage. +5 V nominal. Vss 16 Ground Reference 6 10 System clock (#3 in TMS 9900 system, CKOUT in TMS 9980 system). IwT1 17. | IN | Group 1, interrupt inputs. When active. InT2 18 | IN | (Low) the signal is ANDed with its corresponding mask bit and if enabled sent to the interrupt control section INT3 9] IN | INTI has highest priority. iwra a | wn INTS 7 | 1N INTs 6| iN TNT7/ P15 | 34 | 1/0 | Group 2, programmable interrupt (active low) or 1/0 pins (true logic). Each pin is individually programmable as TNTa/ P14 | 33 | 1/0 | an interrupt, an input port, or an output port INT9/ P13 32 | V0 INTio/p12 | 31 | Vo Intiyer1 | 30 | v0 Iti2z/P10 | 29 | V0 TuTi3/e9 | 28 | 1/0 InTiaes. | 27) V0 INTis/e7 | 23] vO Po 38 | 1/0 | Group 3, 1/0 ports (true logic). Each pin is individually programmable as an input port or an output port. Pt 37 | 0 P2 26 | V0 3 22| 1/0 Pa 2] v0 PS 20 | v0 ; °6 19 | v0 ) 10 1076

1. TMS 9901 ELECTRICAL SPECIFICATIONS 3.1. ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)* Supply voltages, Voc and Vgg© ss ee ee 0.3-V to 10V Allinput and outputvoltages . » . -0.3V to 10V Continuous power dissipation = O75 W Operating free-air temperature range : ee oe ee OC 10 70°C Storage temperature range rrr) oe es =65°C to 150°C sserosses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This isa stress rating only anc Tanetional enerstion of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions’ eeeaeicr nie sponitication Is not implied, Exposure to absolute maximum rated conditions for extended period may affect device reliability

3.2 RECOMMENDED OPERATING CONDITIONS

(aot | Supply voltage, Veo a 58S Supply voltage, Vsg_ __ 0 High-level input voltage, VIM [2224 Vee | | [Opeatinteesir emeentews Ta Oe

3.3 ELECTRICAL CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED OPERATING CONDITIONS

(UNLESS OTHERWISE NOTED) [oc panameven ——SSC*dtSCS es conorrions [mn rye max [unit | [i trout eurenttonyinpud | vjs0Veovee | to HOOT uv [Tion=-100wa Te Vou High level output voltage [ion —a00we | Zou cowl oipa varie [Tioe=3ama Ss Lice Supply currenttromveg P| iss Supply current romVss—— | 210200 6, Copacitanee, any input | t= THe, Allother [O_o beeen ony out memo

34 TIMING REQUIREMENTS OVER FULL RANGE OF OPERATING CONDITIONS

PARAMETER [win Nom wax | unit | [ey Sock vse time ts His ———cocktatine [iaiol) lock puletowwieth Twist Glock pulse nigh width | as om Setup time for $0'S4, GE, or CRUOUT before CRUCLK [2007330 os _| Fine Setuptime;inputbetowe vai RUIN || es rap ines nterapretoreiow [iiGRUGLR) CRU clock pubewith ST GT th Address hold time [eo 106 u

3.5 SWITCHING CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED OPERATING CONDITIONS

PARAMETER TEST CONDITIONS MIN TYP MAX _ Propagation delay, 6 low to vatid | CL = 100 pF, ~ twit) tad thor ele Flo f ,robod i: {a teton al | wet + pete ! | + bet oy ke be ty { kp —} & / \\ | I 1 ! ' 4 [twicruet) I em ff I ' KY\\NVYYVV ANINIKIX—vsuronooness OOO vatorooness j S0-s4 1 | 1 | i H | fete WVXWWYVYWWWWVYWYWVVVV VV q ERY vancworoare INTI-INTHS, Po-rrs | ] | i L ' | | YWWVWWWWVYVWWVYWWVV VV VV VV WV VV HANAHAN vstiocrom CRUIN ' ' Wy MYX VVVVVYV VV VV VV XXX vawronra EISOOXRROOOOOOEEOOOOOOOE OOOO RROD CRUOUT NOTE 1: ALL TIMING MEASUREMENTS ARE FROM 10x and 90% POINTS FIGURE 8 — SWITCHING CHARACTERISTICS 12 1076

1. MECHANICAL DATA 4.1. TMS 9901 — 40 PIN CERAMIC PACKAGE yao {\\ > ceavine SU ere gg SUE QUGTETETETPTONQTSVOTgTyig rg —Rmnte ama LUM RAMANA aa ects

4.2 TMS 9901 — 40 PIN PLASTIC PACKAGE

nox ~~] ce & ovo f LK by aiupes Jost max mente Jpeetonon 1076 13