TMS87C257

TMS87C257 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMLS857 — NOVEMBER 1990 * Organization ...32K x 8 J Package {Top View) * Single 5-V Power Supply , © Intergrated Address Latch ASNpp || 1 28t] Voc Al2i}2 arf) A14 * Max Access/Min Cycle Time (Vcc + 5%) A7]3 26]| A13 TMS87C257-150 150ns AG] 4 25]) AB TMS87C257-1 170 ns AS|| 5 2a{) AD TMS87C257-2 200 ns Adie 23] Att TMS87C257 250 ns A3(| 7 22|) G A2(]8 21) A10 ° PRP =| i MOS Technol = lower-Saving CMOS Technology aio rol] E * Very High-Speed SNAP! Pulse Programming AOl}i0 ~—- 19] DQ7 - Dao} 11 —18{] Das. * 3-State Output Buffers pai}i2 ~ 17/] pas * Low Power Dissipation (Vcc = 5.5 V) Daz} 19 16} 004 — Active ...263 mW Worst Case GND} 14 15} DAB — Standby ... 1.4 mW Worst Case (CMOS Input Levels) description AO-A14 Address Inputs The TMS87C257 series are 262 144-bit, ultra- & Supt erate owerdown violet-light erasable, electrically programmable GND Ground read-only memories. NC No Internal Connection These devices are fabricated using power-saving NU Make No Extemal Connection CMOS technology for high speed and simple 0Q0-DQ7 __Inputs (programming)/Outputs interface with MOS and bipolar circuits. Voc 5-V Power Supply All inputs(including program data inputs) can be ASNVpp Aacress SobeltS-V Programming driven by Series 74 TTL circuits without the use of ower Supply external pullup resistors. Each output can drive one Series 74 TTL circuit without external resistors. The data outputs are three-state for connecting multiple devices to a common bus. The TMS87C257 incorporates internal address latches on address inputs AO-A7. The internal address latch allows address and data pins to be tied directly to the processor's multiplexed address/data pins which can simplify design, reduce chip connect, and lower the cost of multiplexed bus systems. The TMS87C257 is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS87C257 is characterized for operation from - 40°C to 85°C (E suffix) These EPROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in microprocessor-based systems. One other 13 V supply is needed for programming . All programming signals are TTL level. These devices are programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse programming algorithm uses a Vpp of 13 V and a Vcc of 6.5 V for a nominal programming time of four seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. urren asf publeston de. Product conform 0 wy ‘necessarily Include testing ofall parameters. INSTRUM ENTS POST OFFICE BOX 1443 * HOUSTON, TEXAS 77001 7-47

TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY ‘SMLS857 — NOVEMBER 1990 operation There are seven modes of operation listed in the following table. The read mode requires a single 5-V supply. ASNpp during programming requires 13 V for SNAP! Pulse and 12 V on A9 for signature mode. OUTPUT PROGRAM SIGNATURE ee [ei [as ee fae x x vi - pao-pa7 DataQut | HEZ HLZ Data Out nz = [MFG | Device | TX can be Vit or Vin. tVy = 12V205V. § Vi latches the address inputs AO-A7, Vi} unlatches those inputs. read/output disable When the outputs of two or more TMS87C257s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All other devices inthe circuit should have their outputs disabled by applying a high-level signal to the G pin while the device is powered up (E is low). Output data is accessed at pins DQO through DQ7. latchup Immunity Latchup immunity on the TMS87C257 is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup without compromising performance or packing density. For more information see application report SMLAQ01, “Design Considerations; Latchup Immunity of the HVCMOS EPROM Family”, available through TI Sales Offices. power down Active Ig supply current can be reduced from 30 mA to 250 yA (CMOS-level inputs) by applying a high-level (CMOS) signal to the E pin. In this mode all outputs are in the high-impedance state, independent of G. Data and address inputs are at static CMOS levels. erasure Before programming, the TMS87C257 EPROM is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV intensity x exposure time) is 15-W-s/om2. A typical 12-mW/cm2, filtertess UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS87C257, the window should be covered with an opaque label. After erasure (all bits in logic high state), logic lows are programmed into the desired locations. A programmed zero low can be erased only by ultraviolet light. nl TEXAS % INSTRUMENTS 7-48 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77001

TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMLS857 — NOVEMBER 1990 SNAP! Pulse programming The 256K latched CMOS EPROM is programmed using the Tl SNAP! Pulse programming algorithm as illustrated by the flowchart in Figure 1, which can reduce time to a nominal of four seconds. Actua! programming time will vary as a function of the programmer used. Data is presented in parallel (eight bits) on pins DQO to DQ7. Once addresses and data are stable, Eis pulsed. The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (us) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-us pulses per byte are provided before a failure is recognized. The programming mode is achieved when AS/Vpp = 13 V, Vcc = 6.5 V, G = Vin, and E = Vi. During the programming mode, the address latch becomes effectively transparent. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with Vcc = Vpp°= 5V. program Inhibit Programming may be inhibited by maintaining a high level input on the E pin. program verify Programmed bits may be verified with AS/Vpp = 13 V when G = Vy and E = Vi: signature mode The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when AQ is forced to 12 V + 0.5 V. Two identifier bytes are accessed by AO; i.e., AO = Vi_ accesses the manufacturer code, which is output on DQ0-DQ7; AO = Vj accesses the device code, which is output on DQO-DQ7. All other addresses must be held at Vi_. Each byte possesses odd parity on bit DQ7. The manufacturer code for these devices is 97, and the device code is C2. memory address lines Fifteen memory address lines (AO-A14) are provided on the device and are used in conjunction with Gand E to select one of 32 768 eight bit locations in the memory array. Addresses AO through A7 are latched on the negative edge of the address strobe signal. address strobe line The address strobe (AS) input is multiplexed with Vpp on pin 1. The negative edge of AS latches the low order address lines (A0-A7) to demultiplex the address/data bus while the positive edge of AS unlatches these address lines. TEXAS * INSTRUMENTS POST OFFICE BOX 1443 ® HOUSTON, TEXAS 77001 7-49

Figure 1. SNAP! Pulse Programming Flowchart

TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMLS857 — NOVEMBER 1990 logic symboit simplified version (programming features not shown) ‘TMS87C257 ‘TMS87C257 EPROM 32K x8 EPROM 32K x8 Aspe —-¢ —\\c20 ASNpp — c20 10 113 V), 21,22¢23 10 a0 2000 40 75 2000 At At a2 © a2 2 a3 a3 = aa 8 Aa . " as $ as $ ay [37 Dat a6 as 3 —— av [3 002 ar 2oo7t, , _0 ars z2op7 |, _0 av |, Dat a 3 8 262 143 as 8 262143 Av | —¢— Das Ao 2 ass av | 18— pas aio 2h aro 2 AV [te _ 206 an 3 ant 2 av | 15 p07 Az Ai2 av pas ais 26 aig 28 Ata 14 ara 2 14 E20 an [PWR DWN] E20 [PWR DWN] 99 {G21 2. G ar 21EN G NS EN NS) G22 Av pao azo 2 ns 437 DO! pT 45 002 TT 7167 203 [ 477 204 jo qe” 005 jo qq” DOS Cd Dav t These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

0 EE OVA ORCEORG

Storage temperature range... 1. cece e eee eter e eee een eters seseee ~ 65°C to 150°C + Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. SS TEXAS %y INSTRUMENTS POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 7-51

TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY ‘SMLS857— NOVEMBER 1990 a recommended operating conditions TMS87G257-150 ‘TMS87C257-1 ‘TMS87C257-2 UNIT ‘TMS87C257 Yoo Supp vonage y ‘SNAP! Pulse programming algorithm 6.25 65 6.75 Vep Supply voltage Read mode (see Note 3) VeC-06 VCC +06 Vv ‘SNAP! Pulse programming algorithm 12.75 13 13.25 Vin High-level input voltage (CMOS) VOC x 0.7 veC +1 Te Low vat inpat voage TEMOS) v NOTES: 2. Vocmustbe applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device mustnotbe inserted into or removed from the board when Vpp or Vcc is applied. 3. Vpp can be connected to Vcc directly (except in the program mode). Vcc supply current in this case would be Icc + Ip. electrical characteristics over full ranges of operating conditions ErEertEa y VoH_ High-level output voltage TOH == 20 nA Voo-o4 [ion=2tma | Vo Low-level output voltage TOL = 20 uA ee xT ty___ Input current (leakage) Vi =0t05.5V es | Tg Output curentfeakago) Vo=9%VeG et] 'pp1__Vpp supply current Vpp = Vcc = 5.5 V loc1 Vee supply current (standby) _[ CMOS-input level Voc = §.5 V,E= Voc Voc =55V,E=ViL, Ioc2 Voc supply current (active) teycle = minimum cycle time, 15 30| mA outputs open tTypical values are at Ta = 25°C and nominal voltages. capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHzt PARAMETER TEST CONDITIONS MIN TyPt MAX] UNIT [Gc__rputeapactaree [inte SSCS ‘Typical values are at Ta = 25°C and nominal voltages. + Capacitance measurements are made on a sample basis only. § AS/Vpp is not included in input capacitance. ooo TEXAS ad INSTRUMENTS 7-52 POST OFFICE BOX 1443 ® HOUSTON, TEXAS 77001

TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMLS857 — NOVEMBER 1990 switching characteristics over full ranges of recommended operating conditions (see Notes 4 and 5) TEST CONDITIONS | @76257-160 ‘Bou mae (BEE NOTES 685) [WN WAX [WIN WAX [WIN MAX [WN wae | ONT ‘ae enable serene ee ‘enl@) on opener ae cs cs CL = 100 pF, Output disable time from tdis Gor E, whichever 1 Series 74 TTL Load, occurs firstt input ty « 20 ns, ‘Output data valid time | putty = 20.ns t after change of address, 'v(A) —_E, or G, whichever occurs firstt Tea Aaron to ASTER a ‘Address strobe pulse 'wAS) width ns Address hold from tValue calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested. switching characteristics for programming: Vcc = 6.5 V and Vpp = 13 V, Ta = 25°C (see Note 4) ten Output enabie time trom G ee ee NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to Vcc x 0.7 V. Timing measurements are made at 3 V for logic high and 0.8 V for logic low. (reference AC Testing Wave Form) 5. Common test conditions apply for the tyis except during programming, TEXAS % INSTRUMENTS POST OFFICE BOX 1443 ® HOUSTON, TEXAS 77001 7-53

Figure 2. AC Testing Output Load Circuit made at 3 V for logic high and 0.8 V for logic low for both inputs and outputs.

TMS87C257 262 144-BIT LATCHED UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMLS857 — NOVEMBER 1990 read cycle timing Vi Vit + tata) —_4 | ! Vin E | l lq——, Vit H a(E) id! t le»! tw(AS) 14> | ' Vin ASNpp / \\ | | h T Vit thas) +> | | i" I ! Vin 6 | | I 1 I tk > VIL | i 1 tena) > t I ais tsu(As) — | | (A) + I ‘ Vi Vit program cycle timing (SNAP! Pulse programming) Program ‘ Verity > v Net h Vit Pi teuay | 4 thay > \\ ! Vin! You | T | | h f Vit! VoH + tsu0) | | | tais(ayt +>

1 Vppt

d I | Veet a a a Vee | | | ! I I ° <> teuey — thio) ' i | \\ ! I | _ Vin E \\ | | | 1 I ! twpam) > ie © tsue) > | i Vi é Ki i Vit T tdis(@) and ten(@) are characteristics of the device but must be accommodated by the programmer. +43-V Vpp and 6.5-V Vcc for SNAP! Pulse programming. el TEXAS ad INSTRUMENTS POST OFFICE BOX 1443 * HOUSTON, TEXAS 77001 7-55