TMS7000

TMS7000 TI | Alldatasheet

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Technical content

Datasheet sections

• 1 Introduction
• 1.1 How to Use this Manual
• 1.2 Updates Added to This Manual
• 2 TMS7000 Family Devices 2-1
• 2.2 TMS70xO, TMS70CxO and TMS70CTxO Devices 2-4
• 2.2.2 TMS70CxO (CMOS) Key Features 2-5
• 2.2.3 TMS70CTxO (CMOS) Key Features 2-6
• 2.3 TMS70x2 and TMS7742 Devices 2-11
• 2.3.2 TMS7742 EPROM (NMOS) Device Key Features 2-12
• 2.5.1 TMS7742 EPROM (NMOS) Prototyping Device Key Features 2-18
• 2.5.2 SE70P162 (NMOS) Piggyback Prototyping Device Key Features 2-19
• 2.6 SE70CP160, SE70CP162 and SE77C42 Prototyping Devices 2-22
• 2.6.1 SE70CP160 (CMOS) Piggyback Prototyping Device Key Features 2-22
• 2.6.2 SE70CP162 (CMOS) Piggyback Prototyping Device Key Features 2-23
• 2.6.3 SE77C42 (CMOS) EPROM Prototyping Device Key Features 2-24

"'" .. TEXAS INSTRUMENlS TAfS7000 Family 1989 1989 8·Bit Microcontroller Family

• TEXAS INSTRUMENTS

Texas Instruments (TI) reserves the right to make changes to or to discontinue any semiconductor product or service identified in this publication without notice. TI advises its customers to obtain the latest version of the relevant in­ formation ·to verify, before placing orders, that the information being relied upon is current. TI warrants performance of its semiconductor products to current specifica­ tions in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Unless mandated by government requirements, specific testing of all parameters of each device is not necessarily performed. TI assumes no liability for TI applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that license, either express or implied, is granted under any patent right, copyright. mask work right, or other intellec­ tual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits for computing devices pursuant to sub­ part J of part 15 of FCC rules, which are designed to provide reasonable pro­ tection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct the interference. Copyright © 1989, Texas Instruments Incorporated

TMS7000 Family Architecture Electrical Specifications The TMS7000 Assembler Assembly Language Instruction Set Linking Program Modules Macro Language Design Aids Development Support Independent Support Customer Information TMS7000 Bus Activity Tables TMS7000 NMOS to CMOS Conversion Guide TMS70x 1 Devices Character Sets Hexadecimal Instruction Table/Opcode Map Instruction Opcode Set CrossWare Installation Glossary

3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.7 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.7.6 3.7.7 3.7.8 3.7.9 3.8 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7 Interrupt Operation Interrupt Control Multiple Interrupt Servicing External Interrupt Servicing External Interrupt Signals . Programmable Timer/Event Counters Control Registers for Timer/Event Counters 1 and 2 Control Registers for Timer/Event Counters 1 and 2 (TMS70Cx2 Timer Start/Stop (Bit 7) and Capture latch Clock Source Control (Bit 6) (See note below.) Idle/Timer Halt Bit (Bit 5) , Timer Output Function (TMS70Cx2 Devices) Serial Port (TMS70x2 and TMS70Cx2 Devices Only) Clock Sources and Serial Port Modes Multiprocessor Communication Serial Port Initialization Initialization Examples Serial Port Interrupts 3-30 3-32 3-35 3-35 3-36 3-38 3-43 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-53 3-65 3-68 3-72 3-73 3-75 3-78

4 Electrical Specifications 4-1

4.1 TMS~OOO, TMS7020, and TMS7040 Specifications 4-2

4.1.1 Application of Ceramic Resonator 4-7

4.2 TMS7002 and TMS7042 Specifications 4-8

4.2.1 Application of Ceramic Resonator 4-14

4.2.2 Serial Port Timing ., 4-15

4.3 TMS7742 Specifications 4-16

4.3.2 Serial Port Timing .. 4-24

4.4 SE70P162 Specifications 4-25

4.4.1 Serial Port Timing ., 4-30

4.5 TMS70COOA, TMS70C20A, and TMS70C40A Specifications (Wide

4.6 TMS70COOA. TMS70C20A. and TMS70C40A Specifications (5V ±10%) 4-38

4.7 TMS70CT20 and TMS70CT40 Specifications (5 V ± 10%) 4-45

4.8 TMS70C02 and TMS70C42 Specifications (Wide Voltage) 4-49

4.9 TMS70C02 and TMS70C42 Specifications (5V ±10%) 4-57

4.10 SE77C42 Specifications 4-65

4.11 SE70CP160A Specifications 4-72

4.12 SE70CP162 Specifications 4-76

5 The TMS7000 Assembler 5-1

5.1 Source Statement Format 5-2

5.1.1 Label Field 5-3

5.1.2 Command Field 5-3

5.1.3 Operand Field 5-3

5.1.4 Comment Field 5-3

5.2 Constants 5-4

5.2.1 Decimal Integer Constants 5-4

5.2.2 Binary Integer Constants 5-4

5.2.3 Hexadecimal Integer Constants 5-5

5.2.4 Character Constants 5-5

5.2.5 Assembly-Time Constants 5-5

5.3 Symbols 5-6

5.3.1 Predefined Symbols 5-6

5.3.2 Terms .. 5-7

5.3.3 Character Strings 5-7

5.4 Expressions .. 5-8

5.4.1 Arithmetic Operators in Expressions 5-8

5.4.2 Logical Operands in Expressions 5-9

5.4.3 Parentheses in Expressions 5-9

5.4.4 Well-Defined Expressions 5-10

5.4.5 Relocatable Symbols in Expressions 5-10

5.4.6 Externally Defined Symbols in Expressions 5-11

5.5 Assembler Directives .. 5-12

5.6 Symbolic Addressing Techniques 5-47

5.7 Assembler Output 5-48

5.7.1 Source Listing 5-48

5.7.2 Normal Completion Error Messages 5-49

5.7.3 Abnormal Completion Error Messages 5-51

5.7.4 Cross-Reference Listing 5-52

5.8 Object Code 5-53

5.8.1 Object Code Format 5-54

6 Assembly Language Instruction Set 6-1

6.1 Definitions 6-2

6.2 Addressing Modes 6-3

6.2.1 Single Register Addressing Mode 6-4

6.2.2 Dual Register Addressing Mode 6-4

6.2.3 Peripheral-File Addressing Mode 6-5

6.2.4 Immediate Addressing Mode 6-6

6.2.5 Program Counter Relative Addressing Mode 6-6

6.2.6 Direct Memory Addressing Mode 6-7

6.2.7 Register File Indirect Addressing Mode 6-7

6.2.8 Indexed Addressing Mode 6-8

6.3 Instruction Set Overview .. 6-9 v

7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 Linking Program Modules Relocation Capability ... . Link Editor Operation ... . Directives Used for Linking . IDT - Program Identifier Directive DEF - External Definition Directive REF and SREF - External Reference Directives

8 Macro Language

8.1.1 Using Macro Libraries

8.2 Strings, Constants, and Operators

8.3.2 Macro Variable Components

8.3.4 Symbol Components

8.4.1 Symbol Attribute Component Keywords

8.4.2 Parameter Attribute Keywords

8.5 Assigning Values to Parameters

8.7 Model Statements

8.8 Macro Examples

8.8.1 Macro I D

8.8.2 Macro GENCMT

8.8.3 Macro FACT

8.8.4 Macro PULSE .

8.9 Macro Error Messages

9 Design Aids

9.1.2 Write Cycle Timing for Microprocessor Mode

9.2.1 Programming the TMS7742 Using a PROM Programmer

9.2.2 Programming the TMS7742 Using the TMS7000 Evaluation Module

9.2.3 Programming the TMS7000 using the TMS7000 XDS

9.3.2 Programming the SE77C42 Using the TMS7000 Evaluation Module

9.3.3 Modify the RTC/EVM7000C Debug Monitor to Enable 12.5 Volt

9.4 Serial Communication with the TMS7000 Family

9.4.2 Software UART (All TMS7000 Devices)

9.5.1 Compare and Jump Instructions

9.5.2 Addition and Subtraction Instructions

9.5.3 Swap and Rotation Instructions

9.6 Subroutine Instructions ..

9.7 Multiplication and Shifting

9.8 The Branch Instruction

9.10 Write-Only Registers

9.11 Sample Routines

9.11.1 Clear RAM

9.11.2 RAM Self Test

9.11.3 ROM Checksum

9.11.4 Binary-to-BCD Conversion

9.11.5 BCD-to- Binary Conversion

9.11.6 BCD String Addition

9.11 .8 Overflow and Underflow 9.11.11 16-Bit Address Stack Operations 9.11.12 16-by-16 (32-Bit) Multiplication

9.11.13 Binary Division, Example 1

9.11.14 Binary Division, Example 2

9.11.15 Binary Division, Example 3

9.11.17 8-Bit Analog-to-Digital Converter

10 Development Support

10.1 The XDS Emulator

10.1.1 Software Development

10.1.2 XDS Memory Map

10.1.3 Communication Capabilities

10.1.4 System Configurations

10.1.5 Breakpoint, Trace, and Timing Functions

10.1.6 Physical Specifications

10.2 Evaluation Modules ...

10.2.1 System Configurations

10.2.2 Communications

10.2.3 Software Development

10.2.4 EPROM Programming Utility

10.3 Prototyping Support

10.3.1 TMS7742 Description

10.3.2 SE70P162 Description

10.3.3 SE70CP160 Description

10.3.4 SE70CP162 Description

10.3.5 SE77C42 Description . 9-37 9-39 9-40 9-41 9-43 9-44 9-44 9-45 9-46 9-47 9-47 9-48 9-49 9-50 9-51 9-52 9-53 9-54 9-55 9-56 9-57 9-58 9-59 9-60 10-1 10-2 10-4 10-6 10-6 10-6 10-7 10-7 10-8 10-8 10-9 10-9 10-10 10-11 10-11 10-11 10-11 10-11 10-11 vii

11.1 11.2 11.3 11.4 11.5 11.6 Independent Support Cybernetic Micro Systems - IBM-PC Crossware and TMS7000 Simulator Software Development Systems, Inc. - UniWare™ TMS7000 Assembler Hewlett-Packard - HP64000 Microcomputer Development System

12 Customer Information

12.1 Mask ROM Prototype and Production Flow

12.3 TMS7000 Family Numbering and Symbol Conventions

12.4 Development Support Tools Ordering Information

12.4.1 TMS7000 Macro Assembler/Linker

12.4.2 TMS7000 XDS Emulators

12.4.3 TMS7000 Evaluation Modules

A B C o E F G H viii TMS7000 Bus Activity Tables TMS7000 NMOS to CMOS Conversion Guide TMS70x1 Devices Character Sets Hexadecimal Instruction Table/Opcode Map Instruction Opcode Set CrossWare Installation Glossary 11-1 11-2 11-4 11-5 11-6 11 -7 11-8 12-1 12-2 12-4 12-6 12-7 12-13 12-13 12-14 12-14 12-16 12-16 12-16 12-16 A-1 B-1 C-1 0-1 E-1 F-1 G-1 H-1

3.,19 Pinouts for TMS7000, TMS7020, TMS7040, TMS70COO, TMS70C20 and Prototyping Devices Available for TMS70xO and TMS70CxO Devices Prototyping Devices Available for TMS70x2 and TMS7742 Devices 8-Bit Programmable Timer/Event Counters - Timer 1 (TMS70xO, TMS70x2, 16-Bit Programmable Timer/Event Counters - Timer 1 (TMS70Cx2) Page 1 -1 2-7 2-7 2-9 2-13 2-13 2-16 2-16 2-20 2-20 2-25 2-25 3-2 3-4 3-4 3-7 3-15 3-15 3-18 3-18 3-20 3-21 3-21 3-23 3-28 3-28 3-31 3-32 3-33 3-34 3-39 3-39 3-20 3-21 Timer 1 Data and Control Registers (TMS70xO, TMS70CxO, TMS70CTxO and 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-40 3-40 3-41 3-41 3-42 3-42 3-52 3-54 3-56 3-58 3-60 3-61 3-62 3-62 IX

x Typical Operating Current vs. Supply Voltage (TMS70CxO, wide voltage) Typical Power-Down Current vs. Oscillator Frequency (TMS70CxO, wide Typical Operating ICC vs. Oscillator Frequency (TMS70CxO, wide voltage) Measurement Points for Switching Characteristics (TMS70CxO, 5V ± 10%) Measurement Points for Switching Characteristics (TMS70CT20 and Typical Operating Current vs. Supply Voltage (TMS70Cx2, wide voltage) Typical Operating ICC vs. Oscillator Frequency (TMS70Cx2, wide voltage) Typical Operating Current vs. Supply Voltage (TMS70Cx2, wide voltage) Measurement Points for Switching Characteristics (TMS70Cx2, 5V ± 1 0%) 3-65 3-66 3-67 3-69 3-70 3-71 3-73 3-73 4-3 4-3 4-4 4-6 4-7 4-9 4-9 4-10 4-13 4-14 4-17 4-17 4-18 4-21 4-23 4-23 4-26 4-26 4-27 4-29 4-33 4-35 4-35 4-36 4-36 4-37 4-37 4-39 4-39 4-41 4-44 4-46 4-46 4-48 4-52 4-53 4-53 4-54 4-54 4-55 4-55 4-58 4-59 4-60 4-63 4-66

Interface Circuit for Programming the TMS7742 with the TMS7000 XDS Driver Program for Programming the TMS7742 with the TMS7000 XDS 12-2 28-Pin Plastic Package, 70-MIL Pin Spacing (Type N2 Package Suffix) .. . 12-3 40-Pin Plastic Package, 100-MIL Pin Spacing (Type N Package Suffix) .. . 12-4 40-Pin Ceramic Package, 100-MIL Pin Spacing (Type JD Package Suffix) 12-5 40-Pin Ceramic Piggyback Package, 100-MIL Pin Spacing (TypeJD Package 12-6 40-Pin N2 Plastic Package, 0.070 "Pin Center Spacing, 0.600" Pin Row 4-67 4-68 4-71 4-75 4-79 5-2 5-52 5-53 6-4 6-4 6-5 6-6 6-6 6-7 6-7 6-8 7-3 9-3 9-8 9-9 9-10 9-11 9-16 9-19 9-20 9-20 9-33 9-35 9-36 9-38 10-3 12-2 12-8 12-9 12-9 12-10 12-11 12-12 12-13 12-14 12-15. 12-15 12-15 A-6 C-3 C-3 xi

Timer Values for Common Baud Rates - TMS70x2 and TMS70Cx2 Absolute Maximum Ratings over Operating Free-Air Temperature Range Electrical Characteristics over Full Range of Operating Conditions Recommended Crystal Operating Conditions over Full Operating Range Page 1-2 1-3 2-2 2-3 2-8 2-10 2-14 2-17 2-21 2-26 3-7 3-8 3-8 3-9 3-11 3-11 3-12 3-12 3-13 3-14 3-24 3-25 3-26 3-30 3-32 3-53 3-74 4-2 4-2 4-3 4-4 Memory Interface Timing at 5 MHz over Full Operating Free-Air Temperature Absolute Maximum Ratings over Operating Free-Air Temperature Range Electrical Characteristics over Full Range of Operating Conditions Recommended Crystal Operating Conditions over Full Operating Range Absolute Maximum Ratings over Operating Free-Air Temperature Range Electrical Characteristics over Full Range of Operating Conditionst 4-5 4-8 4-8 4-9 4-10 4-11 4-12 4-16 4-16

4-15 Recommended Crystal Operating Conditions over Full Operating Range 4-18 Switching Characteristics over Recommended Supply Voltage Range and 4-19 Recommended Conditions for Programming, TA = 25'C (TMS7742) .... 4-22 4-24 Recommended Crystal/Clockin Operating Conditions over Full Operating 4-30 Recommended Crystal/Clockin Operating Conditions over Full Operating 4-36 Recommended Crystal/Clockin Operating Conditions over Full Operating 4-40 Recommended Operating Conditions (TMS70CT20 and TMS70CT40) 4-45 4-44 Recommended Crystal/Clockin Operating Conditions over Full Operating 4-49 Recommended Crystal/Clockin Operating Conditions over Full OJ!lerating xiii

Electrical Characteristics over Full Range of Operating Conditions Recommended Crystal/Clockin Operating Conditions over Full Operating Absolute Maximum Ratings over Operating Free-Air Temperature Range Electrical Characteristics over Full Range of Operating Conditions Recommended Crystal/Clockin Operating. Conditions over Full Operating Absolute Maximum Rating over Operating Free-Air Temperature Range (un- Electrical Characteristics over Full Range of Operating Conditions Recommended Crystal/Clockin Operating Conditions over Full Operating Absolute Maximum Ratings over Operating Free-Air Temperature Range Electrical Characteristics over Full Range of Operating Conditions Recommended Crystal/Clockin Operating Conditions over Full Operating Results of Operations on Absolute and Relocatable Items in Expressions 4-58 4-58 4-59 4-60 4-61 4-62 4-65 4-65 4-66 4-66 4-67 4-68 4-69 4-70 4-72 4-72 4-73 4-74 4-75 4-76 4-76 4-77 4-78 4-79 5-10 5-13 5-49 5-51 5-52 5-54 5-57 6-2 6-3 6-10 6-28 7-4 8-9 8-10 8-11 8-12 8-15 8-29 9-2 9-5 9-6

9-5 SN74AS373, SN74AS138, and SN74AS32 Propogation Delay Times 9-6 A-5 Double Operand Functions - Addressing Modes (ADD,ADC,AND,BT JO,BTJZ,CMP,DAC,DSB,MOV,MPY,OR,SBB,SUB,XOR) A-12 A-6 Double Operand Functions - Functional Modes (ADD,ADC,AND,BT JO,BT JZ,CMP,DAC,DSB,MOV,MPY,OR,SBB,SUB,XOR) A-13 A-7 Miscellaneous Functions - Addressing Modes (DINT,EINT,IDLE,LDSP,NOP,POP ST,PUSH ST,RETI,RETS,SETC,STSP) A-14 A-8 Miscellaneous Functions - Functional Modes (DINT,EINT,IDLE,LDSP,NOP,POP ST,PUSH ST,RETI,RETS,SETC,STSP) A-14 A-9 Long Addressing Functions - Addressing Modes A-10 Long Addressing Functions-Functional Modes (BR,CALL,CMPA,LDA,STA) A-16 A-11 Single Operand Functions, Special-Addressing Modes (CLR.DEC,INC,INV,MOV A B,MOV A RN,MOV B A-12 Single Operand Functions, Special-Functional Modes (CLR,DEC,INC,INV.MOV A B,MOV A RN,MOV B A-13 Single Operand Functions, Normal - Addressing Modes A-14 Single Operand Functions, Normal - Functional Modes A-15 Double Operand Functions, Peripheral - Addressing Modes A-16 Double Operand Functions, Peripheral-Functional Modes A-19 Relative Jumps - Addressing and Functional Modes (JMP,JN/JLT,JZ/JEQ,JC/JHS,JP/JGT,JPZ/JGE,JNZ/JNE,JNC,JL) .... A-22 A-20 Traps - Addressing and Functional Modes (Trap 0 through Trap 23) A-22 xv

This book replaces the following manuals:

• TMS7000 Family Data Manual, SPND001 B
• TMS7000 Assembly Language Programmer's Guide, SPNU002B
• TMS7000 Software Development System Installation Guide, MPB52
• TMS7000 IBM CrossWare Support Reference Guide, MPB10
• TMS7000 VAXNMS CrossWare Support Reference Guide, MPB53 The following table lists related publications. TMS7000 DATA SHEETS AND DATA MANUALS LITERATURE NUMBER TMS7002/7042 Data Sheet SPNS007 TMS7742 Data Sheet SPNS008 TMS70C42/TMS70C02 Data Sheet SPNS009 TMS7000 USER'S GUIDES LITERATURE NUMBER 8051-TMS7041 System Conversion User's Guide SPNU003 TMS7500/TMS75COO Data Encryption Device User's Guide SPNU004 Link Editor User's Guide SPDU037C TMS7000 EVM User's Guide SPNU007 TMS7000 FAMILY DEVELOPMENT SYSTEM SUPPORT LITERATURE NUMBER XDS/7042 User's Guide SPDU047 XDS/22 with the TMS7042 Emulator Pocket Reference SPDF010 TMS7000 FAMILY APPLICATION NOTES LITERATURE NUMBER TMS7000 Bus Activity Tables SPNA002 TMS7000 Keyboard Interface SPNA003 xvii

The TMS7000 is a family1 of 8-bit single-chip microcontrollers. These microcontrollers incorporate a CPU, memory (ROM, RAM, EPROM), bit I/O, serial communications port, timers, interrupts, and external bus interface logic, all on a single chip. The CMOS members of the family provide an outstanding speed/power ratio as a result of the reliable silicon-gate CMOS technology. Eight-bit microcontrollers have the versatility to cover a wide spectrum of ap­ plications. Texas Instruments has two microcontroller families --TMS7000 and TMS370 --which provide reliable alternatives to satisfy the design re­ quirements. P E R F o R M A N C E TI MICROCONTROLLER MIGRATION TMS370Cx5x .' 8·81T CPU

• 200 ns CYCLE TIME
• 0-18K ROM/EEPROM/EPROM TMS370Cx10 • 256/512 RAM
• 8·81T CPU • 256/512 DATA EEPROM
• 200 ns CYCLE TIME • 8 CHANNEL A/D
• 4K ROM/EEPROM • 2 TIMERS + WATCHDOG TMS70Cxx • 128 RAM • SPI..,d SCI (UARTI
• 8-BIT CPU • 256 DATA EEPROM • UP TO 55 I/O LINES
• 333 ns CYCLE TIME • 1 TIMER + WD
• 0·4K ROM • SPI
• 128/256 RAM • UP TO 22 I/O LINES I • TIMERS
• UART
• UP TO 32 I/O LINES I TIME Figure 1-1. TI CMOS 8-bit Microcontroller Spectrum As shown in Figure 1 -1 , the TMS7000 satisfies those applications in the low to mid range. On the other hand, the TM53'70famUy with its on-chip EEPROM, superior performance and other peripheral Sl,!pport futlcti(;lns in- The terms TMS7000 and TMS7000 family refer to ilil TMS7000 devices,'TMS7000, TMS7020, TMS7040, TMS7002, TMS7042, TMS70COO, TMS70C20, TMS70C40, TMS70C02, TMS70C42, TMS70CT20, TMS70CT40, TMS7742 and all future members, unless otherwise stated. ' ' , 1-1

cluding theon-chip analog-to-digital converter addresses the high end appli­ cations. Table 1-1 describes typical applications for eight-bit microcontrollers. Table 1-1. Typical Applications for a-bit Microcontrollers AUTOMOTIVE TELECOM Instrumentation Feature phones Audio entertainment control Autodialers Cruise control Answering machines Anti-skid braking system Modem control Climate control Digital switches Engine control Digital subsets Trip computer COMPUTER INDUSTRIAL Printers and plotters 'Motor control Disk controllers Stepper motors Tape drive control Metering and measurement Keyboards Robotics Touch screen and mouse CONSUMER BUSINESS Home security Cash registers Cable TV systems Automatic bank tellers Appliance control Barcode readers Tl supports the TMS7000 family with a variety of development tools. The Extended Development Systems provide realtime in-circuit emulation, onboard software breakpoints, and reverse assembler. With its extensive de­ bugging features, critical development time is reduced. The evaluation module provides low cost in-circuit emulation for the TMS7000 family members. TI offers a wide range of prototyping devices for the TMS7000 CMOS family members with the SE70CP160 for use with the TMS70C20/40/CT20/CT40 and the SE70CP162 or SE77C42 for use with the TMS70C42. Table 1-2 details the broad TMS7000 CMOS family members.

-Table 1-2. TMS7000 CMOS Family Members TMS70C42 TMS70C40 TMS70CT40 TMS70C02 TMS70C20 TMS70CT20 TMS70COO On-Chip ROM (K bytes) 4/0 4/2/0 4/2 Internal RAM (bytes) 256 128 128 Interrupt levels 6 4 4 Timers: 21-bit 2 - - 13-bit - 1 1 10-bit 1 - - I/O Lines: Bidirectional 24 16 12 Input Only - 8 4 Output Only 8 8 4 Additional I/O: UART - - Package: 40 pin DIP 40 pin DIP 28 pin DIP 44 pin PLCC 44 pin PLCC Prototyping: Piggyback SE70CP162 SE70CP160 SE70CP160 EPROM SE77C42 - - 1-3

Introduction -HowfQ Use this Manual , ,( ';'" ".,' . "\\', " ',' ,

1.1 Ho~ to Use 'this Ma~l;tar

Thisnian~alisdivided'irit() four major parts: 1-4

• 'Hardware iSecti'bn's 2-4)
• "Software (Stfctions5~8)
• Diwelo/;>'n'lent Support (Sections 9-11)
• Customer Infor~ation .(Se~tion 12) The sections and their contents are summarized below. Section 1 -Introduction
• Introduces the TMS7000 family devices.
• Describes the different manual sections and their contents. Section 2 -TMS7000 Family Devices
• Details each TMS7000 family category and their key features.
• Summarizes the categories and compares their features.
• Provides key features, pinouts, and pin descriptions for each category of devices. Section 3 -TMS7000 Family Architecture
• Discusses operation of the microcomputers' hardware features: Registers I/O Memory and memory modes Clock options CMOS low-power modes Interrupts Timer/event counters Serial port (TMS70x2 and TMS70Cx2 devices only) Section 4 -Electrical Specifications Discusses for all device groups:
• Absolute maximum ratings
• Recommended operating characteristics
• Recommended crystal/clockin operating characteristics
• Memory interface timing
• Read and write cycle timing
• Ceramic resonator circuit application (where applicable)
• Serial port timing (where applicable)

Introduction - How to Use this Manual Section 5 -TMS7000 Assembler

• Discusses basic assembler information, including: Source statement format (placement of various fields in code) Constants, symbols, terms, and expressions
• Discusses the various assembler directives, grouped in the fol- lowing categories: Directives that affect the location counter Directives that affect assembler output Directives that initialize constants Directives for linking programs Miscellaneous directives
• Assembler Output ' Explains source listing format and resulting object code. Presents normal completion and abnormal completion er­ ror messages. Shows a sample cross reference listing. Discusses object code and the various fields in object code format, and changing object code. Section 6 -Assembly Language Instruction Set
• Provides general instruction set information, such as symbol definitions.
• Defines eight addressing modes used by the instructions.
• Summarizes the instruction set in table form.
• Presents the TMS7000 assembly language instruction set in alphabetical order. Section 7 -linking Program Modules
• Discusses relocation capability, absolute and relocatable code.
• Discusses the Link Editor and includes a sample link control file.
• Reviews directives needed for linking programs. Section 8 -Macro Language
• Defines the TMS7000 Macro Assembler.
• Tells how to define macros and use macro libraries.
• Shows how strings, constants, and operators are used in inac- ros.
• Discusses variables, parameters, substitution, and keywords.
• Presents the macro definition verbs.
• Provides macro examples. 1-5

Introduction - How to Use this Manual 1-6 Section 9 -Design Aids Includes several examples to help you use the TMS7000 family: de­ vices:

• Interfacing the TMS7000 to peripberal and memory devices such as extra EPROM and RAM
• Programming the TMS7742
• Serial communication using the UART (serial port)
• Instruction set application notes
• Sample routines Section 10 - Development Support Discusses several products manufactured by Texas Instruments that enhance TMS7000 family design development, including:
• XDS (Extended Development Support) Emulator
• EVM (evaluation module)
• Prototyping devices Section 11 - Independent Support Discusses several products manufactured by Texas Instruments that enhance TMS7000 family design development, including assemblers, text editors, simulators, EEROM, and EPROM support. Section 12 - Customer Information
• Discusses quality and reliability.
• Discusses prototype manufacture and production flow, includ­ ing device prefix designators - TMS, TMP, TMX, and SE.
• Illustrates mechanical package information for all TMS7000 fa­ mily members
• Provides ordering information for the TMS7000 microcomput- ers and the Texas Instruments development support products. Appendix A - TMS7000 Bus Activity Tables Appendix B -TMS7000 NMOS to CMOS Conversion Guide Appendix C -TMS70x1 Devices Appendix D - Character Sets Ajlpendix E -Hexadecimal Instruction Table/Opcode Map Appendix F -Instruction Opcode Set Appendix G - CrossWare Installation Appendix H - Glossary Index

Updates Added to This Manual

1.2 Updates Added to This Manual

This manual replaces the previous TMS7000 Family Data Manual #SND001 B. Additional information has been added to the following sections:

• TMS370 Family Devices - Briefly described in Section 1
• TMS70CTxO Devices - New devices added to family:
• SE77C42 EPROM Device - (Replaces the TMS77C82):
• TMS77C82: This device has been' discontinued. and the SE77C42 has been added to handle the prototyping requirements for the TMS70C42.
• NMOS to CMOS Conversion Guide: Appendix B describes the alter­ ations required when converting from a present TMS7000 NMOS design to a CMOS design. 1-7

Updates Added to This Manual 1-8

This section discusses the features of the TMS7000 family2 of microcomput­ ers. All family members are software compatible, allowing easy migration within the TMS7000 family by maintaining a software base, development tools, and design expertise. The TMS7000 family devices are divided into several categories:

• TMS70xO devices include the TMS7000, TMS7020, and TMS7040
• TMS70x2 devices include the TMS7002 and TMS7042
• TMS70CxO devices include the TMS70COO, TMS70C20, and TMS70C40
• TMS70CTxO devices include the TMS70CT20 and the TMS70CT40.
• TMS70Cx2 devices include the TMS70C02 and TMS70C42
• Prototyping devices include the TMS7742 (EPROM), the SE77C42 (EPROiVi) the SE70P162, SE70CP160, and SE70CP162 (piggybacks) This section begins with a summary and comparison of the TMS7000 family devices, and then provides key features, pinouts, and. pin descriptions for the individual categories. Section Page 2.6 SE70CP160, SE70CP162 and SE77C42 Prototyping Devices ... 2-22

2 Throughout this manual, the term TMS7000 or TMS7000 family refers to all members of

the group. 2-1

TMS7000 Famrly Devices - Summary and Device Comparison _2.1 2-2 Summary and Device Comparison The TMS7000 family NMOS devices can be summarized as follows: - The TMS7000 is the basic 8-bit, single-chip microcomputer, containing a CPU, a timer, flexible I/O, and 128 bytes of on-chip RAM, but no on-chip ROM. . - The TMS7020 and TMS7040 have the same basic features as the TMS7000, with the addition of 2K and 4K bytes of on-chip ROM, respectively. - The TMS7002 (ROM less) and TMS7042 (4K bytes on-chip ROM) have the same features as the TMS70xO devices with the addition of a serial port (UART), a 13-bit timer (Timer 2), a 1 O-bit timer (Timer 3), and 256 bytes of on-chip RAM. NMOS prototyping devices include the TMS7742 and the SE70P162. The TMS7742 is an EPROM version of the TMS7042 and contains 4K bytes of on-chip EPROM. The SE70P162 piggyback device is based on the TMS70x2 architecture and operates like a ROM-coded TMS70x2 device. Table 2-1. TMS7000 NMOS Family Feature Summaryt TMS7040 TMS7042 TMS7020 TMS7742 TMS7000 TMS7002 Maximum oscillator frequency 5 MHz 8 MHz 5MHz Voltage 5 V ± 10% 5 V ± 10% 5 V ± 10% Operating temperature O'C to 70'C O'C to 70'C O'C to 70'C On-chip ROM (Kbytes) 4 I 2 I 0 4 I 0 4 (EPROM) Internal RAM (bytes) 128 256 256 Interrupt levels: External I 2 2 2 'Total 4 6 6 Timers/event counters: 13-bit 1 2 2 10-bit - 1 1 I/O lines: Bidirectional 16 22 22 Input only 8 2 2 Output only 8 8 8 Additional features - Serial Port Serial Port Development support: Prototyping: EPROM TMS7742 TMS7742 - Piggyback SE70P162 SE70P162 SE70P162 XDS Yes Yes Yes EVM Yes Yes Yes t The NMOS members of the family are NOT recommended for new deSigns; however, present designs using the NMOS devices are still supported.

TMS7000 Family Devices - Summary and Device Comparison The TMS7000 family CMOS devices can be summarized as follows: - The CMOS TMS70CxO devices have the same features as the TMS70xO de­ vices, adding low power requirements to the list of features. - The CMOS TMS70CTxO devices contain the same basic features as the TMS70CxO devices but are designed with reduced I/O pins and operate in the Single-Chip mode only. (See Table 2-2). - The CMOS TMS70Cx2 devices contain the same features as the TMS70x2 devices with the addition of programmable-sense interrupts and two 21-bit timers. Prototyping devices include the SE70CP160 and SE70CP162 (piggyback) devices, and the SE77C42 EPROM Device which are based on the TMS70Cxx architecture and operate like ROM-coded TMS70CxO, TMS70CTxO, or TMS70Cx2 devices. Table 2-2. TMS7000 CMOS Family Feature Summary. TMS70C40A TMS70C20A TMS70CT40 TMS70C42 TMS70COOA TMS70CT20 TMS70C02 Max osc freq at 5V ± 10 % 5 MHz 5 MHz 6 MHz Voltage 2.5 to 6 V 5 V ± 10% 2.5 to 6 V Operating temperature Industrial -40·C to 85·C - -40·C to 85·C Commercial O·C to 70·C O·C to 70·C O·C to 70·C On-chip ROM (Kbytes) 4 I 2 I 0 4 I 2 4 I 0 Internal RAM (bytes) 128 128 256 Interrupt levels: External 2 2 2 Total 4 4 6 Timers/event counters: 21-bit - - 2 13-bit 1 1 - 10-bit - - 1 I/O lines: Bidirectional 16 12 24 Input only 8 4 - Output only 8 4 8 Additional features - - Serial Port Development support: Prototyping: EPROM - - SE77C42 Piggyback SE70CP160A SE70CP160A SE70CP162 XDS Yes Yes Yes EVM Yes Yes Yes 2-3

TMS7000 Family Devices - TMS70xO, TMS70CxO and TMS70CTxO _ 2.2 TMS70xO, TMS70CxO and TMS70CTxO Devices

2.2.1 TMS70xO (NMOS) Key Features

Timers/event counters: 13-bit . 10-bit I/O lines: Bidirectional Input only Output only Development support: Prototyping: EPROM Piggyback XDS EVM TMS7742 SE70P162 Yes Yes - Register-to-register architecture - . Memory-mapped ports for easy addressing - Eight addressing formats, including: - Register-to-register arithmetic - Indirect addressing - Indexed and indirect branches and calls - Single-instruction binary-coded decimal (BCD) add and subtract - Two external maskable interrupts - Flexible interrupt handling: - Priority servicing of simultaneous interrupts - Software calls through interrupt vectors - Precise timing of interrupts with the capture latch - Software monitoring of interrupt status - Supports all TMS7000 family expansion modes - N-channel silicon-gate MOS technology - 40-pin, 600 mil, dual-inline package

TMS7000 Family Devices - TMS70xO, TMS70CxO and TMS70CTxO

2.2.2 TMS70CxO (CMOS) Key Features

Timers/event counters: 21-bit 13-bit 10-bit I/O lines: Bidirectional Input only Development support: Prototyping: EPROM Piggyback XDS SE70CP160A Yes EVM Yes - Register-to-register architecture - Memory-mapped ports for easy addressing - Eight addressing formats - Single-instruction binary-coded decimal (BCD) add and subtract - Two external maskable interrupts - Flexible interrupt handling - Wide voltage operating range, frequency range: - 2.5 V -0.8 MHz maximum - 6 V - 6.5 M Hz maximum - Two power-down modes: - Wake-Up (160 IJA at 1 MHz typical) - Halt, XTAL/CLKIN=GNO (1 IJA typical) - Silicon-gate CMOS technology - 40-pin, 600 mil, dual-inline package - 44-pin PLCC 2-5

TMS7000 Family Devices - TMS70xO, TMS70CxO and TMS70CTxO. 2-6

2.2.3 TMS70CTxO (CMOS) Key Features

Timerstevent counters: 21-bit 13-bit 10-bit I/O lines: Development support: Prototyping: EPROM Piggyback XDS EVM - Register-to-register architecture - Memory-mapped ports for easy addressing - Eight addressing formats SE70CP160A Yes Yes - Single-instruction binary-coded decim'al (BCD) add and subtract - Two external maskable interrupts - Flexible interrupt handling - Voltage operating range; 5 V ± 10% - Frequency operating range 0.8 MHz to 5.0 MHz - Two power-down modes: - Wake- Up (160 lolA at 1 M Hz typical) - Halt, XTAL/CLKIN=GND (1 lolA tYPical) - Silicon-gate CMOS technology - 28-pin, 400 mil, dual-inline package

TMS7000 Family Devices - TMS70xO, TMS70CxO and TMS70CTxO Table 2-3. TMS70xO and TMS70CxO Pin Descriptions SIGNAL PIN I/O DESCRIPTION PLCC DIP AO LSb 7 6 I Port A. All pins may be used as high-impedance input-only A1 8 7 I lines. Pin A7/EC1 may also be used as the timer/event A2 9 8 I counter input. A3 10 9 I A4 11 10 I A5 18 16 I A6 16 15 I A7/EC1 12 11 I BO 3 3 0 Port B. Bo-B7 are general-purpose output-only pins. B4-B7 B1 4 4 0 become memory-expansion control signals in Peripheral-Expan B2 5 5 0 sion, FullcExpansion, and Microprocessor modes. B3 41 37 0 B4/ALATCH 42 38 0 Data output/Memory interface address latch strobe B5/L 1 1 0 Data output/Memory read/write signal B6/EN E 43 39 0 Data output/Memory interface enable strobe B7/CLKOUT 2 2 0 Data output/Internal clockout CO 31 28 I/O Port C. Co-C7 can be individually selected in software as gen- C1 32 29 I/O eral-purpose input or output pins in Single-Chip mode. Co-C7 C2 33 30 I/O become the LSB address/data bus in Peripheral-Expansion, C3 34 31 I/O Full-Expansion, and Microprocessor modes. C4 35 32 I/O C5 36 33 I/O C6 37 34 I/O C7 38 35 I/O DO 30 27 I/O Port O. 00-07 can be individually selected in software as gen 01 29 26 I/O eral-purpose input or output pins in Single-Chip or Peripheral- 02 27 24 I/O Expansion modes. 00-07 become the MSB address/data bus 03 26 23 I/O in Full-Expansion and Microprocessor modes. 04 25 22 I/O 05 24 21 I/O 06 22 20 I/O 07 21 19 I/O 001 14 13 I Highest priority maskable interrupt 003 13 12 I Lowest priority maskable interrupt RESE"f' 15 14 I Device reset MC 40 36 I Mode control pin, Vee for microprocessor mode XTAL2/CLKIN 19 17 I . Crystal input for control of internal oscillator XTAL1 20 18 0 Crystal output for control of internal oscillator Vee 28 25 Supply voltage (positive) VSS 44 40 Ground reference 2-8

TMS7000 Family Devices - TMS70xO, TMS70CxO and TMS70CTxO Vss AO INT3 INT1 RESET XTAL2/CLKIN XTAL1 N2 PACKAGE (TOPVIEWI MC CO VCC Figure 2-3. Pinout for the TMS70CT20 and TMS70CT40 2-9

TMS7000 Family Devices - TMS70xO, TMS70CxO and TMS70CTxO Table 2-4. TMS70CTxO Pin Descriptions SIGNAL PIN I/O DESCRIPTION AO 4 I Port A. High impedance input only pins. A1 5 I A2 6 I A3 7 I B4 27 0 Port B. General purpose output only pins. B5 2 0 B6 28 0 B7 3 0 CO 18 I/O Port C. Individually selectable in software as general purpose C1 19 I/O input or output pins. C2 20 I/O C3 21 I/O C4 22 I/O C5 23 I/O C6 24 I/O C7 25 I/O 04 16 I/O Port O. Individually selectable in software as general 05 15 I/O purpose input or output pins. 06 14 I/O 07 13 I/O 001 9 I Highest priority Software Maskable interrupt 003 8 I Lowest priority Software Maskable interrupt RESET 10 I Oevice reset MC 26 I VSS for normal operation XTAL2/CLKIN 11 I Crystal input XTAL1 12 0 Crystal output Vee 17 Supply voltage (positive) VSS 1 Ground reference 2-10

TMS7000 Family Devices - TMS70x2 and TMS7742

2.3 TMS70x2 and TMS7742 Devices

2.3.1 TMS70x2 (NMOS) Key Features

Timers/event counters: I/O lines: 13-bit 10-bit Development support: Prototyping: EPROM Piggyback XDS EVM Flexible on-chip serial port: TMS7742 SE70P162 Yes Yes - Asynchronous, Isosynchronous, or Serial I/O modes - Two multiprocessor communication formats Error detection flags - Fully software programmable (bits/character, parity, and stop bits) - Internal or external baud-rate generator - Separate baud-rate timer useable as a third timer Register -to -register arch itectu re Memory-mapped ports for easy addressing Eight addressing formats, including: - Register-to-register arithmetic - Indirect addressing - Indexed and indirect branches and calls Single-instruction binary-coded decimal (BCD) add and subtract Two external maskable interrupts Flexible interrupt handling: - Priority servicing of simultaneous interrupts - Software calls through interrupt vectors - Precise timing of interrupts with the capture latch - Software monitoring of interrupt status Supports all TMS7000 family expansion modes N-channel silicon-gate MOS technology 40-pin, 600 mil, dual-inline package 2-11

TMS7000 Family Devices - TMS70x2 and TMS7742 _ 2.3.2 TMS7742 EPROM (NMOS) Device Key Features 2-12 1/0 lines: Development support: Prototyping: EPROM Piggyback XDS EVM SE70P162 Yes Yes - EPROM programming procedure compatible with the TMS2732 - Flexible on-chip serial port: - Asynchronous, Isosynchronous, or Serial I/O modes - Two multiprocessor communication formats - Error detection flags - Fully software programmable (bits/character, parity, and stop bits) - Internal or external baud-rate generator - Separate baud-rate timer useable as a third timer - Register-to-register architecture - Memory-mapped ports for easy addressing - Eight addressing formats, including: - Register-to-register arithmetic - Indirect addressing - Indexed and indirect branches and calls - Single-instruction binary-coded decimal (BCD) add and subtract - Two external maskable interrupts - Flexible interrupt handling: - Priority servicing of simultaneous interrupts - Software calls through interrupt vectors - Precise timing of interrupts with the capture latch - Software monitoring of interrupt status - Fully compatible with TMS7020, TMS7040, and TMS7042 - Supports all TMS7000 family expansion modes - N-channel silicon-gate MOS technology - 40-pin, 600 mil, dual-inline package

TMS7000 Family Devices - TMS70x2 and TMS7742 Table 2-5. TMS70x2 and TMS7742 Pin Descriptions OPERATION MODES EPROM MODE (TMS7742 ONLY) SIGNAL PIN I/O DESCRIPTION SIGNAL I/O DESCRIPTION AO LSb 6 I/O Ao-A4 and A7 are general-purpose A7 I A3-A7 are A1 7 I/O bidirectional pins. A5 and A6 are A6 I address lines. A2 8 I/O input-only data pins. A5 I A3 9 I/O A4 I A4 10 I/O A3 I A5/RXD 16 I Data input/Serial port receiver A6/SCLK/EC2 15 I/O Data input/Serial port clock/ Timer 2 event counter A7/EC1 11 I/O Data I/O/Timer 1 event counter BO 3 0 Bo-B3 are outputs. B4-B7 are outputs in Single-Chip B1 4 0 mode and memory interface pins in all other modes. B2 5 0 B3/TXD 37 0 Data output/Serial port transmitter B4/ALATCH 38 0 Data output/Memory interface address latch strobe B5/R/W B 1 0 Data output/Memory read/write signal B6/ENA LE 39 0 Data output/Memory interface enable strobe B7/CLKOUT 2 0 Data output/Internal Clockout CO 28 I/O Port C is a bidirectional data port. In 01 I/O 01-08 are C1 29 I/O Microprocessor, Peripheral-Expansion, 02 I/O bidirectional C2 30 I/O and Full-Expansion modes, Port C is 03 I/O data lines. C3 31 I/O a multiplexed low address and data 04 I/O C4 32 I/O bus. 05 I/O C5 33 I/O 06 I/O C6 34 I/O Q7 I/O C7 35 I/O OS I/O DO 27 I/O Port D is a bidirectional data port. In AS I Ao-A2 and 01 26 I/O Microprocessor or Full-Expansion A9 I A8-A11 are D2 24 I/O mode, it is the high address bus. A11 I address lines. D3 23 I/O A10 I 04 22 I/O E I Chip enable D5 21 I/O AO I D6 20 I/O A1 I D7 19 I/O A2 I INT1 13 I Highest priority external maskable interrupt 003 12 I Lowest priority external maskable interrupt RESET 14 I Device reset GND VSS for EPROM mode MC 36 I Mode control pin, Vee for G/Vpp Program enable Microprocessor mode (21 V to program, (0 V to verify) XTAL2/CLKIN 17 I Crystal input for control of internal GND V SS for EPROM oscillator mode XTAL1 18 0 Crystal output for control of internal oscillator Vee 25 Supply voltage (5 V) Vee Supply voltage (5 V) Vss 40 Ground reference GND Ground reference 2-14

TMS7000 Family Devices - TMS70Cx2

2.4 TM S70Cx2 Devices

2.4.1 TMS70Cx2 (CMOS) Key Features

Timers/event counters: I/O lines: 2l-bit l3-bit 10-bit opment support: Prototyping: EPROM Piggyback XDS EVM Flexible on-chip serial port: - Asynchronous, Isosynchronous, or Serial I/O modes - Two mUltiprocessor communication formats - Error detection flags SE77C42 SE70CP162 Yes Yes - Fully software programmable (bits/char, parity, and stop bits) - Internal or external baud-rate generator - Separate baud-rate timer useable as a third timer Memory-mapped ports for easy addressing Eight addressing formats - Two external maskable interrupts and flexible interrupt handling - Wide voltage operating range, frequency range: - 2.5 V - 0.8 M Hz maximum - 6 V - 7.5 MHz maximum - Two power-down modes: - Wake-Up - HALT - Silicon-gate CMOS technology - 40-pin, 600 mil, dual-in line package, 44-pin PLCC 2-15

TMS7000 Family Devices - TMS70Cx2 Table 2-6. TMS70Cx2 Pin Descriptions SIGNAL PIN I/O DESCRIPTION PLCC DIP AO LSb 7 6 I/O Ao-A4 and A7 are general-purpose bidirectional pins. A1 8 7 I/O A2 9 8 I/O A3 10 9 I/O A4/SCLK 11 10 I/O A5/RXD 18 16 I/O Data I/O/Serial port receiver A6/EC2 16 15 I/O Data I/O/Serial port clock/Timer 2 event counter A7/EC1 12 11 I/O Data I/O/Timer 1 event counter 60/T20UT 3 3 a 60-63 are outputs. 64-67 are outputs in Single-Chip mode 61/T10UT 4 4 a and memory interface pins in all other modes. 60 and B1 62 5 5 a also contain the timer output functions. B3/TXD 41 37 a Data output/Serial port transmitter 64/ALATCH 42 38 a Data output/Memory interface address latch strobe 65/~ 1 1 a Data output/Memory interface read/write signal 66/ENABLE 43 39 a Data output/Memory interface enable strobe B7/CLKOUT 2 2 a Data output/Internal clockout CO 31 28 I/O Port C is a bidirectional data port. In Microprocessor. C1 32 29 I/O Peripheral-Expansion. and Full-Expansion modes. Port C is C2 33 30 I/O a multiplexed low address/data bus. C3 34 31 1/0 C4 35 32 I/O C5 36 33 I/O C6 37 34 I/O C7 38 35 I/O DO 30 27 I/O Port 0 is a bidirectional data port. In Microprocessor and Full- 01 29 26 I/O Expansion modes, it is the high address bus. 02 27 24 I/O 03 26 23 I/O 04 25 22 I/O 05 24 21 I/O 06 22 20 I/O 07 21 19 I/O ii'fT1 14 13 I Highest priority external maskable interrupt INT3 13 12 I Lowest priority external maskable interrupt RESET 15 14 I Device reset MC 40 36 I Mode control pin, Vee for Microprocessor mode XTAL2/CLKIN 19 17 I Crystal input for control of internal oscillator XTAL1 20 18 a Crystal output for control of internal oscillator Vrr 28 25 Supply voltage (5 V) Vss 44

40 Ground reference

t For SE70CP160 pin descriptions, refer to the TMS70CxO device pin description table on page 2-7. 2-17

TMS7000 family Devices - TMS7742 and SE70P162 Prototyping Devices _ 2.5 TMS7742 and SE70P162 Prototyping Devices

2.5.1 TMS7742 EPROM (NMOS) Prototyping Device Key Features

The TMS7742 supports prototyping for the TMS7020, TMS7040, and the TMS7042 up to a maximum operational frequency of 5 MHz. - EPROM programming procedure compatible with the TMS2732 - Flexible on-chip serial port: - Asynchronous, Isosynchronous, or Serial I/O mooes - Two multiprocessor communication formats - Error detection flags - Fully software programmable - Internal or external baud-rate generator - Separate baud-rate timer useable as a third timer - Register-to-register architecture - Memory-mapped ports for easy addressing - Eight addressing formats, including: - Register-to-register arithmetic - Indirect addressing - Indexed and indirect branches and calls - Single-instruction binary-coded decimal (BCD) add and subtract - Two external maskable interrupts and flexible interrupt handling - Supports all TMS7000 family expansion modes - N-channel silicon-gate MOS technology - 40-pin, 600 mil, dual-in line package

TMS7000 Family Devices - TMS7742 and SE70P162 Prototyping Devices

2.5.2 SE70P162 (NMOS) Piggyback Prototyping Device Key Features

The SE70P162 supports full-frequency prototyping for the TMS7020, TMS7040, and TMS7042. Uses TMS2764 or TMS27128 EPROMs in a piggyback socket Register-to-register architecture Flexible on-chip serial port: - Asynchronous, Isosynchronous, or Serial I/O modes Two multiprocessor communication formats - Error detection flags - Fully software programmable - Internal or external baud-rate generator - Separate baud-rate timer useable as a third timer Memory-mapped ports for easy addressing Eight addressing formats, including: - Register-to-register arithmetic - Indirect addressing - Indexed and indirect branches and calls - Single-instruction binary-coded decimal (BCD) add and subtract - Two external maskable interrupts Flexible interrupt handling: - Priority servicing of simultaneous interrupts - Software calls through interrupt vectors - Precise timing of interrupts with the capture latch - Software monitoring of interrupt status Fully compatible with TMS7042 at 8 MHz - 40-pin, 600 mil, dual-inline package 2-19

TMS7000 Family Devices - TMS7742 and SE70P162 Prototyping Devices Table 2-7. TMS7742 and SE70P162 Pin Descriptions OPERATION MODES AO LSb 6 A1 7 A2 8 A3 9 A4 10 A5/RXD 16 Data input/Serial port receiver A6/SCLK/EC2 15 Data input/Serial port clock/ Timer 2 event counter A7/EC1 11 I/O Data I/O/Timer 1 event counter BO 3 0 BO-B3 are outputs. B4-B7 are outputs in Single-Chip mode B1 4 0 and memory interface pins in all other modes. B2 5 0 B3/TXD 37 0 Data output/Serial port transmitter B4/ALATCH 38 0 Data output/Memory interface address latch strobe B5/~ 1 0 Data output/Memory read/write signal B6/ENABLE 39 0 Data output/Memory interface enable strobe B7/CLKOUT 2 0 Data Internal clockout CO 28 I/O Port C is a bidirectional data port. In 01 I/O 01-08 are C1 29 I/O Microprocessor, Peripheral-Expansion, 02 I/O bidirectional C2 30 I/O and Full-Expansion modes, Port C is 03 I/O data lines. C3 31 I/O a multiplexed low address and data 04 I/O C4 32 I/O bus. 05 I/O C5 33 I/O 06 I/O C6 34 I/O Q7 I/O C7 35 I/O 08 I/O DO 27 I/O Port D is a bidirectional data port. In A8 Ao-A2 and D1 26 I/O Microprocessor and Full-Expansion A9 A8-A11 are D2 24 I modes, it is the high address bus. A11 address lines. D3 23 I A10 D4 22 I E Chip enable D5 21 I AO D6 20 I A1 D7 19 I A2 MC 36 Mode control pin, Vee for Microprocessor mode XTAL2/CLKIN 17 Crystal input for control of internal GND oscillator XTAL1 18 0 Crystal output for control of internal oscillator Vee 25 Supply voltage (5 V) 2-21

TMS7000 Family Devices - SE70CP160,_ SE70CP162, and SE77C42 _ 2.6 SE70CP160, SE70CP162 and SE77C42 Prototyping Devices

2.6.1 SE70CP160 (CMOS) Piggyback Prototyping Device Key Features

The SE70CP160 supports TMS70C20, TMS70C40, TMS70CT20, - Uses '27C64, '27C128, or compatible EPROMs in a piggyback socket - Register-to-register architecture - Memory-mapped ports for easy addressing - Eight addressing formats, including: - Single-instruction binary-coded decimal (BCD) add and subtract - Two external maskable interrupts and flexible interrupt handling - Wide voltage operating range, frequency range: - 2.5 V -0.8 M Hz maximum - 6 V -6.5 MHz maximum - Two power-down modes: - Wake-up (160 lJA at 1 M Hz typical) - Halt (10 lJA typical) - Fully compatible with TMS70CxO devices and can also be used for prototyping the TMS70CTxO devices - Silicon-gate CMOS technology - 40-pin, 600 mil, dual-inline package 2-22

TMS7000 Family Devices - SE70CP160, SE70CP162,.and SE77C42

2.6.2 SE70CP162 (CMOS) Piggyback Prototyping Device Key Features

The SE70CP162 supports prototyping development for the TMS70C42. - Uses '27C64, '27C128, or compatible EPROMs in a piggyback socket - Flexible on-chip serial port - Asynchronous, Isosynchronous, or Serial I/O modes - Two multiprocessor communication formats Error detection flags - Fu"y software programmable (bits/character, parity, and stop bits) Internal or external baud-rate generator Separate baud-rate timer useable as a third timer - Register-to-register architecture - Memory-mapped ports for easy addressing - Eight addressing formats - Single-instruction binary-coded decimal (BCD) add and subtract - Two external maskable interrupts flexible interrupt handling - Wide voltage oJ)erating range, frequency range: - 2.5 V - 0.8 MHz maximum - 6 V - 7.5 MHz maximum - Two power-down modes: - Wake-Up - HALT - Fu"y compatible with TMS70Cx2 devices - Silicon-gate CMOS technology - 40-pin, 600 mil, dual-inline package 2-23

TMS7000 Family Devices - SE70CP160, SE70CP162, and SE77C42

• . 2.6.3 SE77C42 (CMOS) EPROM Prototyping Device Key Features THE SE77C42 supports full frequency prototyping for the TMS70C42. 2-24 - EPROM programming procedure compatible with '27C64 or '27C128 - Prototyping support for the TMS70C42 - Flexible on-chip serial port: - Asynchronous, Isosynchronous, or Serial I/O modes - Two multiprocessor communication formats Error detection flags - Fully software programmable (bits/char, parity, and stop bits) Internal or external baud-rate generator Separate baud-rate timer useable as a third timer - Memory-mapped ports for easy addressing - Eight addressing formats - Flexible interrupt handling - Priority servicing of simultaneous interrupts - Software calls through interrupt vectors - Precise timing of interrupts with the capture latch - Software monitoring of Interrupt status Two external maskable 'interrupts - Two power-down modes: - Wake-Up - HALT - Silicon-gate CMOS technology, 40-pin, 600 mil, dual-inline package

TMS7000 Family Devices - SE70CP160, SE70CP162, and SE77C42 Table 2-8. SE71C42 and SE70CP162 Pin Descriptionst OPERATION MODES EPROM MODE SE77C42 ONLY) SIGNAL PIN NO I/O DESCRIPTION SIGNAL I/O DESCRIPTION PLCC DIP AO LSb 7 6 I/O Ao-A7 are general-purpose A7 I A3-A7 and A12 A1 8 7 I/O bidirectional pins. A6 I are A2 9 8 I/O A5 I address lines. A3 10 9 I/O A4 I A4/SCLK 11 10 I/O Data I/O/Serial port clock A3 I A5/RXD 18 16 I/O Data I/O/Serial port receiver I A6/EC2 16 15 I/O Data I/O/Timer 2 event counter I Program A7/EC1 12 11 I/O Data I/O/Timer 1 event counter I Output enable BO/T20UT 3- 3 0 Bo-B3 are outputs. B4-B7 are outputs in Single-Chip mode and memory B1/T10UT 4 4 0 interface pins in all other modes. BO and B1 are outputs for Timer 2 B2 5 5 0 and Timer 1. B3/TXD 41 37 0 Data output/Serial port transmitter B4/ALATCH 42 38 0 Data output/Memory interface address latch strobe B5/L 1 1 0 Data output/ Memory read/write signal B6/EN BL 43 39 0 Data'output/Memory interface enable strobe B7/CLKOUT 2 2 0 Data output/Internal clockout CO 31 28 I/O Port C is a bidirectional data port. In 01 I/O Q1-as are C1 32 29 I/O Microprocessor, Peripheral-Expansion, 02 I/O bidirectional C2 33 30 I/O and Full-Expansion modes, Port C is 03 I/O data lines. C3 34 31 I/O a multiplexed low address and data 04 I/O C4 35 32 I/O bus. 05 I/O C5 36 33 I/O 06 I/O C6 37 34 I/O 07 I/O C7 3S 35 I/O as I/O DO 30 27 I/O Port 0 is a bidirectional data port. In A8 I Ao-A2 and 01 29 26 I/O Microprocessor and Full-Expansion A9 I AS-A11 are 02 27 24 I/O modes, it is the high address bus. A11 I address lines. 03 26 23 I/O 810 I 04 25 22 I/O E I Chip enable 05 24 21 I/O AO I 06 22 20 I/O A1 I 07 21 19 I/O A2 I iNT1 14 13 I Highest priority external maskable interrupt INT3 13 12 I Lowest priority external maskable interrupt [Fl'm'f 15 14 I Device reset GND VSS for EPROM moae MC 40 36 I Mode control pin, Vee for V pp Program enable Microprocessor mode (12.5 V to pro- gram, 0 V to verify) XTAL2/CLKIN 19 17 I Crystal input for control of internal GND V Sa for EPROM oscillator mo e XTAL1 20 18 0 Crystal output for control of internal oscillator Vee 28 25 Supply voltage (positive) Vee SU~IY voltage (5 ) Vss 23 40 Ground reference GND Ground reference 2-26

TMS7000 Family Architecture

TMS7000 Family Architecture This section discusses the internal architecture of the TMS7000 family3 de­ vices. Topics in this section include: Section Page Figure 3-1 (page 3-2) shows the major components of the TMS7000 family devices' internal architecture. 3 TMS7000 and TMS7000 family refer to all TMS7000 devices as described in Section 2. 3-1

TMS7000 Family Architecture XTAl 3-2 32 I/O lINES. SERIAL PORT AND TIMER OUTPUT trimer 3, serial port, and timer/event counter 2 available for TMS70x2 and TMS7OCx2 devices only. *Only Port Pins AO~A3, 84-87, Co-C7, and 04-07 available on TMS7OCTxO devices. Figure 3-1. TMS7000 Family Block Diagram

TMS7000 Family Architecture

3.1 On-Chip RAM and Registers

TMS7000 family devices have a 64K-byte maximum memory address space. On-chip and off-chip memory address space varies according to the particular family member used and mode selected (see Section 3.3, Memory Modes). The following sections discuss the Register File (RF), the Peripheral File (PF), and three CPU registers: the Stack Pointer (SP), the Status Register (ST), and the Program Counter (PC).

3.1.1 Register File (RF)

On-chip RAM is called the Register File (RF). Depending upon the device used, the RF has either 128 or 256 bytes of memory treated as registers RO-R127 or Ro-R255. These are located in lower memory as follows: Number of Device TMS70xO TMS70CxO TMS70CTxO TMS70x2 TMS70Cx2 Registers 128 128 128 256 256 Register Range Ro-R127 Ro-R127 RO-R127 Ro-R255 RO-R255 Memory Address >0000 - >007F >0000 - >007F >0000 - >007F >0000 - >OOFF >0000 - >OOFF The first two registers, RO and R1, are also referred to as Register A and Register B, respectively. Several instructions use Register A or B implicitly as either the source or destination register. For example, the STSP instruction stores the contents of the Stack Pointer in Register B. Other instructions may use Registers A or B to save memory or increase execution speed. Unless otherwise indicated, any register in the Register File can be used as a source or destination register.

3.1.2 Peripheral File (PF)

The Peripheral File (PF) is mapped into locations >0100 to >01 FF, which are referred to as Po-P255. These Peripheral-File locations contain the 8-bit PF registers, used for interrupt control, parallel I/O ports, timer control, me­ mory-expansion control, and serial port control. All PF addresses not used onboard the TMS7000 are mapped externally in all modes except Single-Chip. Several instructions, called Peripheral-File instructions, communicate with the PF registers, allowing easy use of externally-mapped peripheral devices. 3-3

TMS7000 Family Architecture - On-Chip RAM and Registers

3.1.3 Stack Pointer (SP)

The Stack Pointer (SP) is an 8-bit CPU register that points to the top of the stack. The stack is physically located in the on-chip RAM, or RF. When the stack is used, the SP points to the last or top entry on the stack. During reset, the SP is loaded with >01. The SP is loaded from Register B (R1-) via the LDSP instruction and initialized to any other value by executing a stack in­ itialization program such as the one illustrated in Figure 3-2. This feature al­ lows the stack to be located anywhere in the Register File. The SP is loaded into Register B via the STSP command. The SP is automatically incremented when data is pushed onto the stack and automatically decremented after data is popped from the stack. INIT MOV LDSP %>60,B >0000 TOP OF STACK ON RESET - >0001 INITIAL TOP OF STACK - >0060 UPPER STACK LIMIT - >007F OR >OOFF INCREMENT THEN STORE FETCH THEN DECREMENT Figure 3-2. Example of Stack Initialization in the Register File

3.1.4 Status Register (ST)

The Status Register (ST) is an 8-bit CPU register that contains three con­ ditional status bits - carry (C), sign (N), zero (Z) - and a global interrupt en­ able bit (I). The C, N, and Z bits are used for arithmetic operations, bit rotating, and conditional branching. M8b78543210L8b IcINlzlll~Eu?EI Figure 3-3. Status Register CST) Carry CC) Bit Used as carry-in/carry-out for most rotate and arithmetic in­ structions. Negative (N) Bit Contains the most significant bit of the destination operand contents after instruction execution. Zero (Z) Bit Contains a 1 when the destination operand equals zero after instruction execution.

TMS7000 Family Architecture - On-Chip RAM and Registers Global Interrupt Enable (I) Bit Enables/disables all interrupts. The EINT (Enable Interrupts) instruction sets this bit to 1; the DINT (Disable Interrupts) instruction clears it. This bit must be set to a 1 for interrupts to be acknowledged. However, the individual interrupt flag bits can be set whether this bit is set to a 1 or a O. Jump-on-condition instructions are also associated with the C, N, and Z sta­ tus bits to provide conditional program-flow options. During reset all bits in the Status Register are cleared. During other interrupts, the Status Register is saved on the stack and can be accessed via the PUSHST and POPST instructions.

3.1.5 Program Counter (PC)

The 16-bit Program Counter (PC) consists of two 8-bit registers in the CPU. These registers contain the MSB and the lSB of a 16-bit address: the Program Counter High (PCH) and Program Counter Low (PCl). The PC acts as the 16-bit address pointer of the opcodes and operands in memory of the currently executing instruction. During reset, the MSB and the lSB of the PC are loaded into Register A and Register B, respectively. 3-5

TMS7000 Family Architecture - On-Chip General Purpose 1/0 Ports

3.2 On-Chip General Purpose I/O Ports

TMS7000 devices have up to 32 I/O pins organized as four 8-bit parallel Ports A. B, C, and D. Port A Port B Port C, Port 0 TMS70xO, TMS70CxO and TMS70CTxO devices - Port A is an input-only port (Only port pins AO-A3 available on TMS70CTxO devices). TMS70x2 devices - AO-A4 and A7 are bidirectional data pins; A5 and A6 are input-only data pins TMS70Cx2 devices - Port A is fully bidirectional All devices - Port B is an output-only port (Only Port pins B4-B7 available on TMS70CTxO devices) All devices - both ports are bidirectional; they are also used as the address/data bus for memory expansion. (The TMS70CTxO devices operate in the Single-chip mode only, and only port pins D4-D7 are available on Port D). Ports A. C, and D are each controlled and accessed via individual Data-Di­ rection Registers and Data Registers in the Peripheral File. Output-only port B has only a Data Register. The Data Register contains the value to be input or output; the Data-Direction Register indicates whether the individual port pin is an input or an output. I/O pins can be individually designated as input or output by writing a 1 or 0 to a corresponding bit in their PF Data­ Direction Register. A 1 makes the pin an output, a 0 makes the pin an input. Writing to the Data-Direction Register does not affect the value in the Data Register. This allows all bidirectional pins to be used for either input or output by only changing the Data-Direction Register. During a hardware reset, all Data-Direction Registers are cleared, forcing all bidirectional ports to their high-impedance input state. It is good practice to load Ports A, C, and D Data Registers before programming any bidirectional bits as outputs. During a hardware reset, Port B is set to all 1 s. Caution: When any port is configured as an output-only port, applying an external potential to its pins may affect system reliability. The value read at the port pins of Ports C or 0 will be the same as the last value internally written to the port. However, read­ ing Port B returns the value at the pins, which can override the data written to the port. Figure 3-4 (page 3-7) shows the logic for each bidirectional I/O line.

TMS7000 Family Architecture - On-Chip General Purpose I/O Ports I/O Port A Port B Port C Port 0 Total I/O Pins Available Total Memory Pins VO PIN ,-----~- t-4-r-----~~~~Q 0 DDR FLIP +-----DDR WRITE FLOP STROBE L--____ --10 OUTPUT OUTPUT 3-STATE DRIVER o DATA FLIP cI-----DATA WRITE FLOP STROBE Figure 3-4. Bidirectional I/O Logic Table 3-1. TMS70xO and TMS70CxO Port Configuration SINGLE-CHIP PERIPHERAL- FULL-EXPANSION MICROPROCESSOR MODE EXPANSION MODE MODE MODE 8 input pins 8 input pins 8 input pins 8 input pins A7=A7/EC1 A7=A7/EC1 A7=A7(EC1 A7=A7/EC1 4 output pins 4 output pins 4 output pins 8 output pins 4 bus control 4 bus control 4 bus control signals signals signals 8-bit 8-bit low 8-bit low

8 I/O pins address/ data bus address/data bus address/ data bus

(LSB) (LSB)

8 I/O pins 8 I/O pins 8-bit high address 8-bit high address

bus (MSB) bus (MSB) 8 input pins 8 input pins 8 input pins 8 input pins 8 output pins 4 output pins 4 output pins 4 output pins

16 I/O pins 8 I/O pins

8 address/data 16 address/data 16 address/data None (multiplexed) 4 memory control 4 memory control 4 memory control 3-7

TMS7000 Family Architecture - On-Chip General Purpose 1/0 Ports i/O Port A Port B Port C Port 0 Total I/O Pins Available Total Memory Pins 3-8 Table 3-2. TMS70CTxO Port Configuration t I/O SINGLE-CHIP MODE Port A 4 Input Pins (AO-A3) Port B 4 Output Pins (B4-87) Port C a I/O Pins Port 0 41/0 Pins (04-D7) Total I/O Pins 4 Input Pins Available 4 Output Pins

12 I/O Pins

t The TMS70CTxO devices operate in the single-chip mode only. Table 3-3. TMS70x2 Port Configuration SINGLE-CHIP PERIPHERAL- FULL-EXPANSION MICROPROCESSOR MODE EXPANSION MODE MODE MODE

6 I/O pins 6 I/O pins 6 I/O pins 6 I/O pins

2 input pins 2 input pins 2 input pins 2 input pins A5=A5/RX A5=A5/RX A5=A5/RX A5=A5/RX A6=A6/SCLK/EC2 A6=A6/SCLK/EC2 A6=A6/SCLKiEC2 A6=A6/SCLK/EC2 A7=A7/EC1 A7=A7/EC1 A7=A7/EC1 A7=A7/EC1 8 output pins 4 output pins 4 output pins 4 output pins B3=B3/TX 4 bus control 4 bus confrol 4 bus control signals signals signals B3=B3/TX B3=B3/TX B3=B3/TX a-bit a-bit low a-bit low 81/0 pins address/data bus address/data bus address/data bus (LSB) (LSB) a-bit high a-bit high

8 I/O pins a I/O pins address bus address bus

(MSB) (MSB) 2 input pins 2 input pins 2 input pins 2 input pins 8 output pins 4 output pins 4 output pins 4 output pins

22 I/O pins 14 I/O pins 6 I/O pins 6 I/O pins

a address/data 16 address/data 16 address/data None (multiplexed) 4 memory control 4 memory control 4 memory control

TMS7000 Family Architecture - On-Chip General Purpose I/O Ports Table 3-4. TMS70Cx2 Port Configuratior. SINGLE-CHIP PERIPHERAL· FULL- EXPANSION MICROPROCESSOR I/O MODE EXPANSION MODE MODE MODE 81/0 pins 8 I/O pins 8 I/O pins 8 I/O pins A4=A4/SCLK A4=A4/SCLK A4=A4/SCLK A4=A4/SCLK -Port A A5=A5/RXD· A5=A5/RXD A5=A5/RXD A5=A5/RXD A6=A6/EC2 A6=A6/EC2 A6=A6/EC2 A6=A6/EC2 A7=A7/EC1 A7=A7/EC1 A7=A7/EC1 A7=A7/EC1 8 output pins 4 output pins 4 output pins 4 output pins Port B B3=B3/TXD 4 bus control 4 bus control 4 bus control B1 =B1 /T1 OUT signals signals signals BO=BO/T20UT B3=B3/TXD B3=B3/TXD B3=B3/TXD B1 =B1/T10UT B1 =B1/T10UT B1 =B1 /T1 OUT BO=BO/T20UT BO= BO/T20UT BO=BO/T20UT 8·bit 8-bit low 8-bit low Port C 81/0 pins address/data bus address/data bus address/data bus (LSB) (LSB) 8-bit high 8-bit high Port D 8 I/O pins 8 I/O pins address bus address bus (MSB) (MSB) Total I/O 8 output pins 4 output pins 4 output pins 4 output pins Pins 24 I/O pins 16 I/O pins 8 I/O pins 8 I/O pins Available Total 8 address/data 1 6 address/data 16 address/data Memory None (multiplexed) 4 memory control 4 memory control Pins 4 memory control 3-9

TMS7000 Family Architecture - On-Chip General Purpose I/O Ports

3.2.1 Port A

On TMS70xO and TMS70CxO parts, Port A is an B-bit high-impedance in­ put-only port, providing eight general-purpose input lines. Pin A7/EC1 may also be used to clock the .on-chip timer/event counter (see Section 3.7, Pro­ grammable Timer/Event Counters). On TMS70CTxO parts, Port A is a 4-bit high impedance input-only port, providing four general-purpose input lines (AO-A3) . On TMS70x2 parts, pins Ao-A4 and pin A7/EC1 of Port A are bidirectional I/O lines. Pins A5 and A6 are general-purpose input-only pins that also have other functions when using the serial port. Pin A5/RXO receives incoming serial data and pin A6/SCLK/EC2 is the serial clock input or output. Pins A6/SClK/EC2 and A7/EC1 may also be used to clock the on-chip timer/event counters, Timer 2 and Timer 1, respectively. . On TMS70Cx2 devices, Port A is a fully-bidirectional I/O port. However, pins A5/RXO and A4/SClK serve as the serial data receive pin and serial clock, respectively, when the serial port is used. Pins A6/EC2 and A7/EC1 may be used to clock the on-chip timer/event counters, Timer 2 and Timer 1, respectively. Note that SCLK has been moved to A4 on the TMS70Cx2 de­ vices from A6 on the TMS70x2 devices. This frees up EC2 to be used at the same time as SClK.

3.2.2 Port B

In Single-Chip mode, Port B is an B-bit general-purpose output port. Reading Port B returns the value written to the pins unless modified by an external value at the pins. (The TMS70CTxO devices contain only pins B4-B7.) In all other memory modes, Port B is split into two parts. The lower nibble (pins Bo-B3) are general-purpose output-only pins. The most significant nibble (pins B4-B7) contains the bus control signals: AlATCH, R/iN, ENABLE, and ClKOUT. (The TMS70CTxO devices operate in single-chip mode only.) On TMS70x2 and TMS70Cx2 devices, pin 83 is also the serial output line (TXO) for the serial port.

3.2.3 Port C

In Single-Chip mode, Port C is an B-bit bidirectional I/O port. Any of its eight PinS may be individually programmed as an input or output line. (The TMS70CTxO devices operate In single-chip mode only.) In all other memory modes, Port C becomes a multiplexed address/data port for the off-chiJl memory bus. In this case, Port C provides the least sig­ nificant byte of a 16-bit address, followed by eight bits of read or write data. (Port 0 provides the most significant byte of the 16-bit address.)

3.2.4 Port 0

In Single-Chip or Peripheral-Expansion mode, Port 0 is an B-bit bidi­ rectional I/O port. Any of its eight pins may be individually programmed as an input or output line under software control. (The TMS70CTxO devices contain four Port 0 pins (04-07) and operate in the single-chip mode only.) In Full-Expansion and Microprocessor modes, Port D becomes a multi­ plexed address/data port for the off-chip memory bus. In this case, Port 0 provides the most significant byte of a 16-bit address. (Port C provides the least significant byte of the 16-bit address.)

TMS7000 Family Architecture - Memory Modes

3.3 Memory Modes

0000 >007F >0080 >OOFF >0100 >010B >010C >01FF >0200 > FOOO >F800 >FFFF The TMS7000 can address up to 64K bytes. Four memory modes can be se- lected by a combination of software and hardware: the Single-Chip, Peri- _ pheral-Expansion, Full-Expansion, and Microprocessor modes. The TMS70CTxO devices operate in the single-chip mode only. . The Mode Control (MC) input pin forces the TMS7000 into Microprocessor mode when set to a VCC. If the MC pin is held at VSS, the remaining memory modes can be selected by bits 6 and 7 of the Peripheral File I/O Control Re­ gister (IOCNTO - PO), as shown in Table 3-5. Table 3-5. Mode Selection Conditions (MC Pin) MODE SELECT CONDITIONS MODE CONTROL IOCNTO MODE PIN (MC) BITS 7.6 Single-Chip VSS 0 0 Peripheral-Expansion VSS 0 1 Full-Expansion VSS 1 0 Microprocessor Vee x x Note: X = Don't Care During reset the 10CNTO register is set to a O. (Refer to Section 3.6 for a de­ tailed description of reset and the initialization procedure for the IOCNTO re­ gister.) Table 3-6 and Table 3-7 summarize the four memory modes. Table 3-6. TMS70xO, TMS70CxO and TMS70CTxO Memory Map SINGlE-CHIPt PERIPHERAl- FUll MICROPROCESSOR EXPANSION EXPANSION Register File Register File Register File Register File Reserved Reserved Reserved Reserved On-Chip 1/0 On-Chip 1/0 On-Chip 1/0 On-Chip 1/0 Peripheral Expansion Peripheral Expansion Peripheral Expansion Not Available Not Available Memory Expansion Memory Expansion 4K ROM 4K ROM 4K ROM 2K ROM 2K ROM 2K ROM t Only operating mode available on the TMS70CTxO devIces 3-11

TMS7000 Family Architecture-Memory Modes Table 3-7. TMS70x2 and TMS70Cx2 Memory Map SINGLE-CHIP PERIPHERAl- FUll MICRO- '70x2 EXPANSION EXPANSION PROCESSOR '70Cx 2 >0000 >0000 Register File Register File Register File ' Register File >OOFF >OOFF >0100 >0100 On-Chip I/O On-Chip I/O On-Chip I/O On-Chip I/O >0117 >0123 >0118 >0124 Peripheral Expansion Peripheral Expansion Peripheral Expansion >OlFF >OlFF ;Q2oO >0200 Not Available Not Available Memory Expansion Memory Expansion >EFFF >EFFF >FOOO ~ 4K ROM 4K ROM 4K ROM >FFFF >FFFF Table 3-8. TMS70xO, TMS70CxO and TMS70CTxO Peripheral Memory Map SINGlE-CHIP:t: PERIPHERAl- I FUll- I MICRO- EXPANSION EXPANSION PROCESSOR PO >0100 IOCNTO I/O Control register P1 >0101 - Reserved P2 >0102 T1DATA Timer 1 data P3 >0103 T1CTL Timer 1 control P4 >0104 APORT Port A data P5 >0105 - Reserved P6 >0106 BPORT Port B Data t P7 >0107 - Reserved P8 >0108 CPORT Port C Data P9 >0109 CDDR Port C Data- Direction Register Peripheral Expansion Pl0 >010A DPORT Port 0 Data J Pll >010B DOOR Port 0 Data-Direction Register I, P12- >010C- Not available Peripheral Expansion P255 >OlFF t In expansion modes, Port B IS referenced In a special manner. See the Port B discussion on page 3-19. :t: Only operating mode available on the TMS70CTxO devices 3-12

TMS7000 Family Architecture - Memory Modes Table 3-9. TMS70x2 Peripheral Memory Map SINGLE-CHIP PERIPHERAL- I FULL- I MICRO- EXPANSION EXPANSION PROCESSOR PO >0100 IOCNTO I/O Control register 0 P1 >0101 - Reserved P2 >0102 T10ATA Timer 1 Data P3 >0103 T1CTL Timer 1 Control P4 >0104 APORT Port A Data P5 >0105 AOOR Port A Data-Direction Register P6 >0106 SPORT Port B Data t P7 >0107 - Reserved P8 >0108 CPORT Port C Data Port C Data-Dir- P9 >0109 COOR ection Register Peripheral Expansion P10 >010A OPORT Port 0 Data I P11 >010B DOOR Port 0 Data-Direction Register I P12- >010C- Not available P15 >010F P16 >0110 IOCNT1 I/O Control Register 1 SMODE First Write after reset - Serial Mode register P17 >0111 SCTLO Write - Serial Control register 0 SSTAT Read - Serial port status register P18 >0112 T2DATA Timer 2 Data P19 >0113 T2CTL Timer 2 Control P20 >0114 T3DATA Timer 3 Data P21 >0115 SCTL1 Serial Control register 1 P22 >0116 RXSUF Receiver Buffer P23 >0117 TXSUF Transmitter Buffer P24- >0118 Not available Peripheral Expansion P225 >01FF t In expansion modes. Port B IS referenced In a special manner. See the Port B discussion on page 3-19. 3-13

TM"S7000 Family Architecture - Memory Modes Table 3-10. TMS70Cx2 Peripheral Memory Map SINGLE·CHIP PERIPHERAL· I FULL· I MICRO· EXPANSION EXPANSION PROCESSOR PO >0100 IOCNTO I/O Control register 0 P1 >0101 IOCNT2 I/O Control register 2 P2 >0102 IOCNTl I/O Control register 1 P3 >0103 - Reserved P4 >0104 APORT Port A Data P5 >0105 AD DR Port A Data·Direction Register P6 >0106 BPORT Port B data t P7 >0107 - Reserved P8 >0108 CPORT Port C Data Port C Data· Dir- P9 >0109 CDDR ection Register Peripheral Expansion P10 >010A DPORT Port 0 Data I P11 >010B DOOR Port 0 Data Direction Register I P12 >010C ~lMSDAT~ Timer 1 MSB decrementer reload register/MSB readout latch P13 >0100 T1LSDATA Timer 1 LSB reload register/LSB decrementer value P14 >010E T1CTL1 Timer 1 control register 1/MSB readout latch P15 >010F T1CTLO Timer 1 control register O/LSB capture latch value P16 >0110 2MSDAH Timer 2 MSB decrementer reload register/MSB readout latch P17 >0111 T2LSDATA Timer 2 LSB reload register/LSB decrementer value P18 >0112 T2CTL1 Timer 2 control register 1/MSB readout latch P19 >0113 T2CTLO Timer 2 control register O/LSB capture latch value P20 >0114 SMODE Serial port mode control register P21 >0115 SCTLO Serial port control register 0 P22 >0116 SSTAT Serial port Status Register P23 >0117 T3DATA Timer 3 reload register /decrementer value P24 >0118 SCTL1 Serial port control register 1 P25 >0119 RXBUF Receiver buffer P26 >011A TXBUF Transmitter buffer P27- >011 B- Reserved P35 >0123 P36- >0124- Not available Peripheral Expansion P255 >01FF t In expansion modes, Port B is referenced in a special manner. See the Port B discussion on page 3-19. 3-14

TMS7000 Family Architecture - Memory Modes

3.3.1 Single-Chip Mode

Single-Chip mode is selected when: MC = VSS and PF Register 10CNTO = OOXX XXXX In Single-Chip mode, the TMS7000 family devices function as standalone microcomputers with no off-chip memory-expansion bus. User memory con­ sists of the RAM register file and ROM. All available I/O lines may be used for various purposes, such as scanning keyboards, driving displays, and con­ trolling other mechanisms. The four ports are configured as shown in Figure 3-5. AO-A7 'J BO-B7 TM670XO CO-C7 ~ 00-07 " j INPUT UNES OUTPUT UNES BIDIRECTIONAL UNES BIDIRECTIONAL UNES Figure 3-5. I/O Ports - Single-Chip Mode Figure 3-6 shows the Single-Chip mode memory map. The unused Peripheral File (PF) locations and oft-chip memory addresses cannot be addressed. If you attempt to read one of these locations, an undefined value is returned. Writing to these addresses has no effect. Peripheral-File registers Po-P11 re­ ference the I/O ports and other on-chip functions. Table 3-8, Table 3-9, and Table 3-10 list the Peripheral-File registers that are available in Single-Chip mode. >0000 >007F >0080 >OOFF >0100 >0108 >010C > FOOO >F800 >FFFF Register File Reserved On-chip I/O Not Available 4K ROM 2K ROM A. TMS70xO. TMS70CxO and TMS70CTxO Devices '70x2 '70Cx2 Register File >0100 >0117 >0118 >FOOO On-chip I/O Not Available 4KROM >OOFF >0100 >0123 >0124 > FOOO >FFFF >FFFF B. TMS70x2 and TMS70Cx2 Devices Figure 3-6. Single-Chip Mode Memory Map 3-15

TMS7000 Family Architecture - Memory Modes 3-16 Port A is accessed via PF register P4 (APORT). When P4 is read, such as with a MOVP (Move from PF) instruction, the value on the Port A input pins is re­ turned. The input data is read approximately two machine cycles before the completion of the instruction.

• On the TMS70xO and TMS70CxO devices, bit 7 (A7) is the MSb and bit 0 (AO) is the LSb. When the on-chip timer/event counter is placed in the External Event-Counter mode, bit A7/EC1 serves as the external clock input, triggering the event counter on every positive-going transi- tion. .
• On the TMS70CTxO devices, bit 3 (A3) is the MSb and bit 0 (AO) is the LSb.
• On TMS70x2 parts, pins AQ-A4 and pin A7/EC1 are bidirectional I/O pins. Each of these pins can become either an output or an input pin depending upon the value in the Port A Data-Direction Register (ADDR) P5: P5 bit = 1 Corresponding Port A pin becomes an output. P5 bit = 0 Corresponding Port A pin becomes a high-impedance in- put. Figure 3-4 (page 3-7) shows a diagram of the bidirectional I/O logic. Pins A5 and A6/SCLK/EC2 have multiple functions. Normally they are both input-only pins (as on TMS70xO parts), but A5 can also be the serial data receiver (RXD). Pin A6/SCLK/EC2 can also be the serial clock I/O pin (SCLK) for the serial port. A6 can be either the serial clock output or it can drive the on-chip serial clock when connected to an external clock. (See the serial port section for more information, Section 3.8). Pin A6 can also be the external clock input for Timer 2.
• On TMS70Cx2 devices, all pins are bidirectional I/O pins. Each of these pins can become an output or an input pin, depending upon the value in the Port A Data-Direction Register (ADDR) P5. Pins A4/SCLK, A5/RXD, A6/EC2, and A7/EC1 have multiple functions. Pins A4/SCLK and A5/RXD are the serial clock I/O pin and the serial data receiver pin, respectively, when the serial port is used. Pins A6/EC2 and A7/EC1 may be used to clock the on-chip timer/event counter, Timer 2 and Timer 1, respectively. Port B output pins always assert the value of the Port B Data Register, PF register P6 (BPORT). Writing to P6 loads the Port B register, modifying the Port B output pins. Reading from P6 provides the current value of the Port B pins. When RESET goes active, Port B register contents are set to 1s by the on-chip circuitry. (Only pins B4-B7 are available on the TMS70CTxO devices.) Port C, Port 0 (CPORT and DPORT) are bidirectional I/O pins. Data Registers are P8 and P10 of the Peripheral File. Each of these pins can become either an output or an input pin depending upon the value in the port C and 0 Data-Direction Register, locations P9 and P11 (CDDR and DOOR). A 1 causes an output and a 0 causes a high-impedance input. Writing to the Data-Direction Reg­ isters does not affect the Data Registers. Writing to the Data Registers modi-

TMS7000 Family Architecture - Memory Modes IOCNTO APORT BPORT CPORT CDDR DPORT DDDR * RESET * * L1 * L2 fies the programmed output pins. Reading the Data Register returns either the current value at the pin (when the pin is an input) or the current value of the Data Register (for pins configured as outputs). Refer to Figure 3-4 (page 3-7) for a diagram of the bidirectional I/O logic. (Port pins CO-C7 and D4- D7 _ are available on the TMS70CTxO devices.) Peripheral-File instructions ANDP, ORP, and XORP perform a read/modify/­ write cycle on PF registers. When applied to a port's Data Register, these in­ structions can clear, set. or complement the output pins on the port. The following program segment illustrates a use of the I/O lines in the Sin­ gle-Chip mode for most family members. (The TMS70CTxO devices do not contain a" 32 I/O pins initialized below.) EQU EQU EQU EQU EQU EQU EQU MOVP MOVP MOVP MOVP MOVP ORP ANDP BTJZP MOVP XORP BTJOP PO P10 Pll %>3F,IOCNTO %>02,DPORT %>OO,CPORT %>FO,CDDR %>OF,DDDR %>04,DPORT %>7F,CPORT %>08,CPORT,L1 %>55,BPORT %l,BPORT %>41,APORT,L2 Note: I/O control register 1 Port A data register Port B data register Port C data register Port C data-direction register Port D data register Port D data-direction register Set Single-Chip mode, enable all interrupts, clear all pulse flip-flops Load Port D with 0000 0010 (D7-DO) Load Port C with 0000 0000 (C7-C1 ) Config C7-C4 outputs, C3-CO inputs Config D7-D4 inputs, D3-DO outputs Set pin D2 to 1 Clear pin C7 Jump if C3 is 0 Set Port B to 0101 0101 (B7-BO) Toggle bit BO Jump if either A6 or A1 is a 1 The percent sign (%) indicates the Immediate Addressing mode. The in­ struction set is described in Section 6. 3-17

TMS7000 Family Architecture-Memory Modes

3.3.2 Peripheral-Expansion Mode

Peripheral-Expansion mode is selected when: 3-18 Me = VSS and PF Register IOCNTO = 01XX XXXX Peripheral-Expansion mode incorporates features of both the I/O-intensive Single-Chip mode and the memory-intensive Full-Expansion mode. Refer­ ences to Peripheral-File addresses (locations >0100 to >01 FF) not corre­ sponding to on-chip PF registers produce off-chip memory cycles. During Peripheral-File instructions, a PF port is read, even if the value is not needed, such as in a MOVP A, P6. If a hardware configuration makes this read unde­ sirable, use a STA (Store A) instruction with the memory-mapped address of . the PF register. The ability to reference off-chip addresses allows the TMS7000 to be directly connected to most of the popular peripheral devices developed for 8-bit microprocessors. The TMS7000 PF instructions reference these off-chip peripherals just as easily as they access on-chip PF registers. M-A7 B4-B3 TM870xx B5 Be CCl-C7 00-07 BIDlRECllONAL. UNES OlJTPUT UNE8 ALATCH R/W ewu CU<OUT AOORES8/DATA (.ADRO/DATO-ADR7/DAT7l BIDIREC1l0NAI.. UNES Figure 3-7. I/O Ports - Peripheral-Expansion Mode >0000 >007F >0080 >OOFF >0100 >010B >010C >01 FF >0200 > FOOO >F800 >FFFF Register File Reserved On-chip I/O Peripheral Expansion Not Available 4K ROM I I 2K ROM A. TMS70xO and TMS70CxO Devices '70x2 '70Cx2 >0000 >0000 Register File >OOFF >OOFF >0100 >0100 >0117 On-chip I/O >0123 >0118 >0124 >01 FF Peripheral Expansion >01 FF >0200 >0200 Not Available > FOOO > FOOO 4K ROM >FFFF >FFFF B. TMS70x2 and TMS70Cx2 Devices Figure 3-8. Peripheral-Expansion Mode Memory Map

TMS7000 Family Architecture - Memory Modes Port A functions the same as in Single-Chip mode. Port B is divided into two sections: pins B0-B3 function as individual output pins, the same as in Single-Chip mode; pins B4-B7, however, function as external _ memory bus controls:

• Pin B4/ALATCH is strobed to logic 1 while Port C asserts the memory address.
• Pin B5/R/iiii is driven to logic 1 for a read cycle and to logic zero for a write cycle.
• Pin B6/ENABLE is asserted at logic 0 whenever an external memory cycle is in progress.
• Pin B7/CLKOUT is an output clock intended for general memory control timing. Exact signal timing is described in Section 4. References to the Port B Data Register, P6, are handled in a special manner. When a value is written to P6, pins BO-B3 output the new value. Pins B4-87 ignore the new value and continue to output memory bus signals. An external memory write cycle will also write the entire 8 bits of the new value to the external address >0106. When P6 is read, the least significant nibble (BO-B3) is taken from the current value on pins B0-B3. The most significant nibble is obtained by reading the external address >0106. Port C functions as a multiplexed address/data port for the memory-expansion bus. In normal configurations, Port C is attached to the input of an 8-bit latch such as an SN74LS373. The B4/ALATCH signal drives the G input of the latch, so that the latch's Q outputs fOllow the D inputs while B4/ALATCH is high, and ouputs become latched when it falls. After B4/ALATCH falls and data (such as a memory address) is latched, Port C either becomes a high-impe­ dance input for read cycles or it asserts the output data for write cycles. Port D functions identically to a bit-programmable, bidirectional I/O port, as in the Single-Chip mode. Notes: 1. The Port C Data-Direction Register is mapped into external memory. The Port C input or output function can be recreated externally by mapping a latch at location >0108. 2. Because B4/ALATCH, 85/R/W, and Port C are active for both external and internal (ROM and RAM) memory cycles, it is recommended that B6/ENABLE be gated with the chip-select input of all external memory devices to prevent external bus conflicts. 3-19

TMS7000 Family Architecture - Memory Modes

3.3.3 Full-Expansion Mode

Full-Expansion mode ~s selected when: Me = Vss and PF Register IOCNTO = 10XX XXXX Full-Expansion mode uses a 16-bit address to extend the memory addressing capability of the TMS7000 to its full 64K-byte limit. External memory may be accessed with instructions using the Direct. Register File .Indirect, and Indexed Addressing modes of the instruction set. This meets a variety of application requirements by expanding the external program or data storage. Full-Expansion mode I/O is identical to the Peripheral-Expansion mode except that Port D is used to output the most significant byte (MSB) of the 16-bit address. Thus, Port 0 is not available as an I/O port. The four ports are configured as shown in Figure 3-9. Figure 3-10 shows the I/O memory as­ signments for the Full-Expansion mode. M-A7 BIDIRECTIONAl... LIJIES Bo-EI3 OUTPUT LINES B4 ALATCH TM870XX B5 Be ~ B7 CLKOlIT CCl-C7 00-07 Figure 3-9. I/O Ports - Full-Expansion Mode As in the Peripheral-Expansion mode, accesses to Peripheral-File registers (locations >0100 to >01 FF) which are not directly implemented as on-chip registers produce off-chip memory cycles. The on-chip Peripheral-File regis­ ters are listed in Table 3-8, Table 3-9, and Table 3-10. Note that the Port 0 Data Register (OPORT) and the Port 0 Data-Direction Register (DOOR) are implemented as off-chip addresses in the Full-Expansion mode. The port 0 input or output function can be recreated externally by mapping a latch at lo­ cation >010A.

TMS7000 Family Architecture - Memory Modes >0000 >007F >0080 >OOFF >0100 >010B >010e >01FF >0200 >FOOO >F800 >FFFF Register File Reserved On-chip I/O Peripheral Expansion Not Available 4K ROM 2K ROM '70x2 >0000 Register File >OOFF >0100 On-chip I/O >0117 >0118 >01 FF Peripheral Expansion >0200 Memory Expansion >FOOO 4K ROM >FFFF '70Cx2 >0000 >OOFF >0100 >0123 >0124 >01 FF >0200 > FOOO >FFFF A. TMS70xO and TMS70CxO Devices B. TMS70x2 and TMS70Cx2 Devices Figure 3-10. Full-Expansion Mode Memory Map

3.3.4 Microprocessor Mode

Microprocessor mode is selected when: Me = Vee and PF Register IDCNTO = XXXX XXXX Microprocessor mode is intended for applications that do not justify the use of on-chip ROM. The port pins are configured exactly as in Full-Expansion mode (see Figure 3-9). Unlike Full-Expansion mode, no on-chip ROM is re­ ferenced in Microprocessor mode. All memory accesses except for internal RAM and on-chip Peripheral-File locations are now addressed externally. The Me pin must be held at logic 1 (Vee) to place the device in this mode. There are no restrictions on when the value of the Me pin may change, but it is recommended that the value be changed only when the device is in reset. Indeterminant results can occur if the Me pin is changed while the device is accessing memory locations whose internal/external status may change. '70x2 '70Cx2 >0000 >0000 >0000 >007F Register File >0080 Register File Reserved >OOFF >OOFF >OOFF >0100 >0100 >0100 On-chip I/O >010B >0117 On-chip I/O >0123 >010C >0118 >0124 Memory Expansion Memory Expansion >FFFF >FFFF >FFFF A. TMS70xO and TMS70CxO B. TMS70x2 and TMS70Cx2 Devices Devices Figure 3-11. Microprocessor Mode Memory Map 3-21

TMS7000 Family Architecture - System Clock Options

3.4 System Clock Options

The internal state cycle period, called tete), is derived from either a crystal or an external clock source. Both NMOS and CMOS devices can use a crystal, ceramic resonator, or another approximately 50% duty cycle clock as an ex­ ternal clock source. The CMOS devices can also use an R-C circuit with the OSC-OFF low-power mask option (see Section 3.4.2). The internal clock then divides the external clock source frequency by two to produce the inter­ nal state frequency. For example, a 5 M Hz crystal produces an internal fre­ quency of 2.5 MHz, which drives a 400-ns machine cycle.

3.4.1 System Clock Connections

The TMS7000 devices use the following methods to implement the system clock options: Crystals: Parallel resonant crystals are connected between pins XT AL 1 and XTAL2/CLKIN. To optimize the crystal waveform, 15-pF capacitors should be connected between XTAL 1 and ground, and XTAL2/CLKIN and ground. This connection is illustrated in Figure 3-12 8. Ceramic Resonators: Ceramic resonators are connected between pins XTAL 1 and XTAL2/CLKIN. A resistor and two capacitors, with values de­ termined by the selected ceramic resonator, must be connected as shown in Figure 3-12 b.. Values vary by manufacturer and type. External Clock Source: As shown in Figure 3-12 C, external clock sources are con­ nected to XTAL2/CLKIN and XTAL1 is not connected. R-C Circuits: R-C circuits provide a simple, low-cost oscillator for applica­ tions in which frequency toleration is not a concern. R-C cir­ cuits also provide immediate start-up oscillation for the CMOS device upon exiting the Halt OSC-OFF mode of operation (see Section 3.4.2). R-C circuits are connected as shown in Figure 3-12 d. The re­ commended value for the capacitor C is 47 pf. The value of the resistor R required for the desired frequency must be selected with respect to Vee, ambient temperature, and the tolerance of the R-C components. Recommended values for the resistor in the R-C network fall in the range of 1 KO-1 OOKO.

TMS7000 Family Architecture - System Clock Options XTAL1 XTAL2/CLKIN 1"' 1"' CAPACITORS ! - o PARALLEL 15 pF l' RESONANT T 15 pFt t30 pF for TMS7742 only a. Crystal 18----- NC XTAL1 c. Extamal clock source R C b. Ceramic resonator (1al XTAL1 1171 XTAL2 d. R-C circuit Figure 3-12. System Clock Connections 3-23

TMS7000 Family Architecture :...System Clock Options

3.4.2 Low-Power Mask Options for CMOS Devices

The TMS7000 CMOS devices may use oscillator mask options which provide different levels of functionality and power consumption during the Halt low­ power mode. These oscillator options are called OSC-ON and OSC-OFF. The OSC-On option will keep the _on-chip oscillator active during the Halt low-power mode. When the device is brought out of Halt mode, there will be no delay in restoring the full operation since the oscillator is already run­ ning. The OSC-ON option is useful in applications where no delay in restor­ ing full operation after Halt mode is more important than the lower power consumption of the OSC-OFF mode. The OSC-OFF option is useful in applications where very low power con­ sumption is requred in Halt mode. The OSC-OFF option causes the oscillator to cease oscillation when Halt mode is entered. This offers the lowest power consumption, typically 1 !lA. The OSC-OFF mask-programmable option supports an R-C circuit as well as a crystal, ceramic resonator, or other ap­ proximately 50% duty cycle ClKIN signal. If an R-C network is used with this option, it will restart full oscillation immediately upon exiting Halt mode. If a ceramic resonator or crystal is used, there will be a period before the oscil­ lations stabilize, causing a delay in the response to RESET of approximately 10 milliseconds. Because of this stabilization time requirement, an external time constant of at least 10 milliseconds is recommended for RESET when using a crystal or ceramic resonator with the OSC-OFF low-power mask option. (Only RESET may be used to exit the HALT OSC-OFF mode when either a crystal or ceramic resonator is the clock source. See Table 3-12.) Table 3-11. low-Power Mask Options for CMOS Devices MASK HALT POWER CLOCK SOURCE OSCILLATOR OPTION CONSUMPTION START UP Ceramic resonator, crystal 10 millisecond OSC-OFF Lowest delay R-C circuit, external clock No delay source OSC-ON Low Ceramic resonator, crystal, or No delay external clock source Note: OSC-ON and OSC-OFF are mask options, which means the option is placed on a manufacturing template, or mask, that copies the actual circuit onto the silicon device. This means the oscillator option is finalized at the start of manufacture and cannot be changed by software or hardware.

TMS7000 Family Architecture - CMOS Low-Power Modes

3.5 CMOS Low-Power Modes

The TMS7000 CMOS microcomputers can be programmed to enter low­ power modes of operation (Wake-up and Halt) when the IDLE instruction is executed. For information concerning mask options associated with the Halt low-power mode, see Section 3.4.2.

3.5.1 TMS70CxO and TMS70CTxO Low-Power Modes

The TMS70CxO and TMS70CTxO devices support the Wake-Up and Halt low-power modes. These modes are entered when: 1) Bit 5 of the Timer 1 control register (T1 CTL) is set (0 for Wake- Up mode, 1 for Halt mode). and 2) The IDLE instruction is executed. Activating RESET or acknowledging an enabled interrupt releases the device from either mode except for the HALT OSC-OFF mode where the use of either a crystal or ceramic resonator requires activating RESET. Both low-power modes freeze the I/O ports, retaining their conditions before the IDLE in­ struction was executed. Complete RAM data retention is also maintained through both low-power modes as long as power is applied. Table 3-12 de­ scribes the low-power options. Table 3-12. low-Power Options for TMS70CxO and TMS70CTxO Devices MODE Wake-Up Halt (OSC-ON) Halt (OSC-OFF Halt (OSC-OFF CPU ENTER EXIT CLOCK STATUS TIMER 1 STATUS OSC MODE MODE SOURCE VIA VIA Halted Active Active IDLE RES EI...lJ'lT1 , Crystal. R-C Circuit, INT2,INT3 Ceramic Resonator, (if enabled) External Clock Halted Halted Active IDLE ..Bf.S ET, I N11, INT3 (if enabled) Crystal, Ceramic Resonator, External Clock Halted Halted Halted IDLE ..Bf.SET, INT1, R-C Circuit, INT3 (if enabled) External Clock Halted Halted Halted IDLE RESET Crystal, Ceramic Resonator In Wake-Up mode, the oscillator and timer logic remain active. The on-chip timer may be used to release the device from the low-power state. The Icc current requirements in Wake- Up mode are frequency dependent for both the OSC-ON and the OSC-OFF options.

3.5.2 TMS70Cx2 Devices

The TMS70Cx2 devices support the Wake-Up and Halt low-power modes. These modes are entered when the IDLE instruction is executed. An enabled interrupt must be executed to allow the device to return to normal operation. The TMS70Cx2 devices have the ability to disable the individual onboard timers and UART during the low-power modes. To disable Timer 1, set the T1 HALT bit (bit 5 of T1 CL TO) to 1. To disable Timer 2, set the T2HAL T bit (bit 5 of T2Cl. TO) to 1. To disable the UART /Timer 3, set the SPH bit (bit 7 of SCTLO) to 1. By definition, whenever the Timer 1, Timer 2, or the UART/Timer 3 are active when the IDLE instruction is executed, the device is in a Wake-up mode. When all three circuits are disabled when the IDLE in­ struction is executed, the device is in the Halt mode. 3-25

TMS7000 Family Architecture - Interrupts and System Reset

3.6 Interrupts and System Reset

All TMS7000 family devices have a non-maskable system reset pin. RESET. This signal has the highest priority in the interrupt heirarchy. RESET imme­ diately initializes the device. The TMS70xO. TMS70CxO and TMS70CTxO devices have three separate. maskable interrupts that are triggered from three sources. The TMS70x2 and TMS70Cx2 devices have five separate maskable interrupts that can be trig­ gered from as many as seven sources. Each interrupt has a specific priority level; if two or more interrupts occur simultaneously. they are serviced ac­ cording to priority - highest first. lowest last. Table 3-13 summarizes the in­ terrupts. Table 3-13. Interrupt Summary EXTERNAL/ SOURCE PRIORITY VECTOR ADDRESS INTERNAL MSB LSB E RESET pin low Immediate >FFFE >FFFF (highest priority) E INT1 pin activet Priority 1 >FFFC >FFFD E/I Timer/Event counter 1 1: Priority 2 >FFFA >FFFB countdown past 0 E 003 pin activet Priority 3 >FFF8 >FFF9 I RX Buffer Loaded. or TX Priority 4 >FFF6 >FFF7 Buffer Empty. or Timer 3 countdown past 0 E/I Timer/Event counter 2 Priority 5 >FFF4 >FFF5 countdown thru 0 t The external interrupts on the TMS70Cx2 devices can be programmed for level and sense detection. Note: INT4 and INT5 apply to TMS70x2 and TMS70Cx2 devices only. 1: The TMS70CTxO devices do not contain the external event counter pin.

3.6.1 Device Initialization

RESET. interrupt level O. cannot be masked. The processor recognizes a RESET immediately. even in the middle of an instruction execution. To execute the reset function. the RESET pin must be held low for a minimum of 1.25 x tc(C) internal state clock periods. While the RESET pin is asserted (0): 1 ) The Data-Direction Registers for the I/O ports are cleared. On NMOS devices. the output data flip-flops of Ports A. C. and Dare set to all 1 s (see Figure 3-4. page 3-7). On CMOS devices. only Port A's output data flip-flop is set to all 1 s; Ports C and D output data flip­ flops are not altered during a. RESET. This places Ports C and D (and Port A on TMS70x2 and TMS70Cx2 devices) in high-irnpedance input mode. and Port B outputs all 1 s (>FF). regardless of the internal machine clock state.

TMS7000 Family Architecture - Interrupts and System Reset The reset function does not change the INTn flag bits in the IOCNTO register (since all zeros are written). If any of the bits in a Peripheral File Data-Direc­ tion Register (DDR) are set to a 1, the corresponding port pin would become an output, producing a 1 level. (Remember, Data-Direction Registers are set _ to all Os on RESET.) It is generally a good practice to initialize the output data flip-flop with the desired output value (by writing to the port data value register) before writing to the DDR flip-flop to make the corresponding pin an output. Figure 3-13 and Figure 3-14 show examples of possible initialization routines after the assertion of RESET. Device initialization requires 17 state cycles after RESET goes inactive. When RESET returns to its inactive condition (1), the following operations are performed before the first instruction acquisition: 1) All Os are written to the Status Register. This clears the global interrupt enable bit (I), disabling all interrupts. 2) All Os are written to the IOCNTO register. This disables INT1, INT2, and INT3 and leaves the INTn flag bits unchanged. 3) All Os are written to the IOCNT1 register in the TMS70x2 and TMS70Cx2 devices. This disables INT4 and INT5. 4) The PC's MSB and LSB values before RESET was asserted are stored in RO and R1 (Registers A and B), respectively. 5) The Stack Pointer is initialized to >01. 6) The MSB and LSB of the RESET interrupt vector are fetched from lo­ cations >FFFE and >FFFF, respectively (see Table 3-13, page 3-26), and loaded into the Program Counter. 7) Program execution begins from the address placed in the Program Counter. 3-27

TMS7000 Family Architecture - Interrupts and System Reset The Stack Pointer can also be re-initialized following reset by executing a program similar to the one below. STACK MOV %VALUE,B * * LDSP Load Register B with the stack starting point in the Register _ File Put this value into the Stack Pointer register A simple R-C circuit can provide a power-up reset, automatically resetting the TMS7000 when power is applied. The capacitor and resistor values are se­ lected according to the clock frequency used, the minimum voltage at which the RESET signal is at logic 1, and the ramp-up time of the power to the device. The following formula calculates the minimum time required for an adequate device reset: trst = 2 v cc - (1.25t etC)~ + tpwr = RC VIL where: trst Total time RESET pin is held at logical level 0 Vcc Supply voltage VIL Low-level input voltage te(C) Internal machine clock period tpwr Ramp-up time for VCC R Resistor value in ohms (no more than 1 megohm) C Capacitor value in farads 3-29

TMS7000 Family Architecture - Interrupts and System Reset

3.6.2 Interrupt Operation

The TMS7000 family's interrupts can be falling-edge sensitive, falling-edge and level sensitive, rising-edge sensitive, or rising-edge and level sensitive. Table 3-14 illustrates the interrupt configurations supported by each TMS7000 family device. Table 3-14. External Interrupt Operation TMS7000 DEVICE FALLING EDGE FALLING EDGE RISING EDGE RISING EDGE AND INTERRUPTS AND LEVEL AND LEVEL TMS70xO INT1 X 003 X TMS70x2 :~i~ X X TMS7742 001 X 003 X SE70P162 INT1 X INT2 X TMS70CxO, INT1 X TMS70CTxO INT3 X SE70CP160 INT1 X 003 X TMS70Cx2t INT1 X X X X

003 X X X X

t The TMS70Cx2, SE77C42, and SE70CP162 devices' external Interrupts edge/level-sensitive polarity are software programmable. This is accomplished via the I/O control 1 register (P1). 1) When an interrupt is first asserted, its level is gated into the Sync flip­ flop by the internal state clock, tc(C)' which has a cycle period of 2/Fosc. To detect an interrupt, the INTn signal must be active for a mi­ nimum of 1.25 x tc(C) clock periods. 2) The negative output edge of the Sync flip-flop clocks a 1 into the Pulse flip-flop. This is the "edge" detection of the interrupt signal and is the only time a 1 is loaded into the Pulse flip-flop. The Pulse flip-flop will be set within 1.25 state clock cycles of the interrupt assertion. If the signal is removed before the CPU recognizes the interrupt, its occurrence is latched on the Pulse flip-flop output, Q1. 3) Edge-sensitive interrupts detect only the Pulse flip-flop Q1 output, not the INTn level. Once an interrupt has been asserted (INTn goes low), it becomes active if the INTn enable bit and the global interrupt enable bit (I) register are set to one. The "level path" logic shown in Figure 3-15 applies only to external in­ terrupts that are both edge- and level-sensitive; it is not implemented for interrupts that are only edge-sensitive. For more information, refer to Table 3-14.

TMS7000 Family Architecture - Interrupts and System Reset o 8VNC FF +flV CLEAR W PULSE FF INTn FLAG R t Available only for level-sensitive interrupts INTn ENABlE W R 0 02 ENABlE LATCH GLOBAL /NT ENABlE (STATUS REGISTER) Figure 3-15. CPU Interface to Interrupt Logic INTn ACK TO PRIORITY LOGIC INTn ACTIVE 4) As shown in Figure 3-15. when the TMS7000's on-chip logic detects an active interrupt, it sends an INTn ACTIVE signal to the CPU. When the currently executing instruction is completed, the CPU acknowledges the active interrupt and routes INTA back to that interrupt's INTn ACK (interrupt acknowledge) line. If simultaneous interrupts occur, that is, more than one interrupt is active within the same instruction boundary, the interrupts are acknowledged by the CPU according to the priority levels. For example. if both INT2 and INT3 occur within the same in­ struction boundary, INT2 is serviced first. 5) After the CPU acknowledges the interrupt, the INTn ACK line, as shown in Figure 3-15, clears the corresponding Pulse flip-flop. The CPU then pushes the Status Register contents and the Program Counter onto the stack, and clears the Status Register, including the global interrupt ena­ ble (I) bit. The CPU reads an interrupt code from the interrupt priority logic to determine which interrupt requires servicing. The 16-bit vector value is read from the two vector addresses associated with the interrupt being serviced. and is loaded into the Program Counter. The interrupt vector value is the address of the first instruction in the interrupt service routine. The interrupt vector addresses are shown in Table 3-13 on page 3-26. Instruction execution then proceeds at the new address value in the Program Counter. Nineteen internal state clock cycles [tc(c)]are required between the end of an instruction in the interrupted program and the start of the first instruction of the interrupt service routine. Interrupting out of the Idle state requires 17 state clock cycles. 3-31

TMS7000 Family Architecture - Interrupts and System Reset

3.6.3 Interrupt Control

The I/O control registers, 10CNTO, 10CNT1, and IOCNT2, contain the inter­ rupt control bits. All TMS7000 family members have an 10CNTO register. Only TMS70x2 and TMS70Cx2 devices have an 10CNT1 register, because they have two more interrupts, INT4 and INT5; only TMS70Cx2 devices have an IOCNT2 register because only they can change the polarity of their external interrupts. The I/O control registers are mapped into PF locations as follows: Table 3-15. I/O Control Registers PERIPHERAL FILE TMS70xO TMS70x2 TMS70Cx2 TMS70CxO TMS70CTxO IOCNTO PO PO PO IOCNT1 " P16 P16 P2 IOCNT2 N/A N/A P1 o -TIilT3 inactive 1 - TIilT3 pending r 0 - INT2 inactive 1 - INT2 pending o -11iIT1 inactive 11 - TIilT1 pending 7 6 5 4 3 2 1 0 Memory Memory TIilT3 TfilT3 INT2 INT2 001 TNT1 Mode 1 Mode 0 Flag Enable Flag Enable Flag Enable Read Memory Memory TIilT3 mT3 INT2 INT2 TNT1 TIilT1 Mode 1 Mode 0 Clear Enable Clear Enable Clear Enable Write OO':'~ChiP Lo - 001 disabled - M1 enabled 01 - Peripheral _0 - Noe ffect Expansion 1 - Clejl r INT1 flag 10 - Full '--0 - INT2 disable d Expansion 1 - INT2 enabled 11 - Undefined _ 0 - No effect 1 - Clear INT2 flag '--0 - TIilT3 disabled 1 - TNT3 enabled '--0 - No effect 1 - Clear INT3 flag Figure 3-16. 10CNTO - I/O Control Register 0 (PO for All Devices)

TMS7000 Family Architecture - Interrupts and System Reset 7 6 5 4 0 0 0 0 X X X X o -INT5 inactive I' -INT5 pending r 0 - INT4 inactive I ' - INT4 pending 3 2 , 0 INT5 INT5 INT4 INT4 Flag Enable Flag Enable Read INT5 INT5 INT4 INT4 Clear Enable Clear Enable Write L Lo - INT4 disabled 0- NO: - INT4 enabled ffect , - Clea r INT4 flag '--0 - INT5 disable d 1 - INT5 enabled '--0 - No effect , - Clear INT5 flag Figure 3-17. IOCNT1 - I/O Control Register 1 In the I/O control registers, each interrupt is associated with a flag bit (INTn flag) and enable bit (INTn enable). The global interrupt enable (I) bit in the Status Register allows all interrupts to be enabled or disabled at the same time. Three conditions must be met before the CPU will recognize an interrupt: 1) A 1 must be written to the INTn enable bit in the IOCNTO or IOCNT1 register. 2) The global interrupt enable (I) bit in the Status Register must be set to 1 by the EINT instruction. 3) The interrupt must be the highest priority interrupt asserted within an instruction boundary. Through software, the INTn enable bits can be read and written to:

• Writing a 0 individually masks the corresponding interrupt.
• Writing a 1 allows the interrupt to be recognized. The reading of the INTn flag is handled differently (see Figure 3-15 on page 3-31 ):
• An active signal applied to INTn is read as a 1 from one side of an OR gate.
• INTn going active latches a 1 to the other side of the OR gate which stays latched when the signal goes inactive. 3-33

TMS7000 Family Architecture - Interrupts and System Reset 3-34 Read or Write falling edge 1 - Active high/ rising edge o -Edge & level sensitive 1 - Edge sensitive only o -Active low/falling edge 1 - Active high/rising edge o - Edge & level sensitive 1 - Edge sensitive only Figure 3-18. IOCNT2 - I/O Control Register 2 (P1 for TMS70Cx2 Only) Thus, INTn going active is returned both as a latched and an edge-sensitive signal for the TMS70xO and INT3 of the TMS70CxO devices, while the TMS70Cx2 devices can choose sensitivity via IOCNT2. When a 1 is written to the INTn clear bit, the Pulse flip-flop is cleared. Writing a 0 to the INTn clear bit has no effect. The INTn flag bit may be tested in software, regardless of whether the interrupt is enabled or disabled. For example, the following program statement waits for the active edge of the interrupt input on the INT1 pin by testing INT1 flag: WAIT BTJZP %>02,PO,WAIT Wait for INT1- (INT1 flag = 1) This allows external interrupt pins to be polled as inputs. Interrupt input pins have an advantage over the other general-purpose inputs if the input signal is a short pulse. The Pulse flip-flop of the interrupt input will always capture a pulse with a width of at least 1.25 x tc{C} cycles, allowing software to detect that the condition occurred, even after the pulse is gone. Caution: Due to the read/modify/write nature of the bit manipulation instructions (ANDP, ORP, and XORP), it is possible that the INTn flag bits in the 10CNTO and IOCNT1 registers could be unintentionally cleared. To avoid these occurrences, use the MOVP and the STA instructions when writing data to fOCNTO and fOCNT1. Because the INTn flag and INTn clear bits are in the same bit positions, use caution when accessing these bits. For example, you may be able to use XORP to set INT1 enable without altering the state of the INT1 flag (XORP %>03,PO), as long as the INT1 flag does not change state during the in­ struction execution. However, if a short INT1 pulse sets the Pulse flip-flop between the read and write portions of the instruction execution, a 0 would be read from INT1 flag and a 1 would be written to INT1 clear to reclear INT1 flag. In this case, the INT1 pulse would be undetected by the processor. This

TMS7000 Family Architecture - Interrupts and System Reset same instruction would also affect the INT2 flag and INT3 flag in a similar manner as they are also located in the 10CNTO register. Immediately following RESET, all interrupts are globally disabled because the _ I bit (interrupt enable) in the Status Register is reset to O. Also, the 10CNTO register is cleared. This clears the INTri enable bits, disabling INT1, INT2, and INT3 individually and putting the TMS7000 in Single-Chip mode. This does not affect the I NTn flag bits from their previous condition before RESET. On the TMS70x2 device, a 0 must be written by software to the INTn enable bits in the 10CNT1 register to ensure that INT4 and INT5 are also individually disabled following a RESET.

3.6.4 Multiple Interrupt Servicing

When an interrupt is recognized, the global interrupt enable (I) Status Register bit is automatically cleared while the interrupt is serviced. This prevents all other interrupts from being recognized during the execution of the interrupt service routine. Once the service routine is completed by executing the RETI (Return from Interrupt) instruction, the old Status Register contents are popped from the stack. This returns the I bit back to 1, allowing any pending interrupts to be recognized. An interrupt service routine can explicitly allow nested interrupts by executing the EINT instruction to directly set the I bit in the Status Register to a 1, thus permitting other interrupts to be recognized during service routine execution. When a nested interrupt service routine completes, it returns to the previous interrupt service routine when the RET! instruction is executed.

3.6.5 External Interrupt Servicing

The external interrupt interface consists of three discrete input lines that re­ quire no external synchronization: RESET, INT1, and INT3. TMS70xO External interrupts on the TMS70xO devices are high-impedance inputs that are both falling-edge and level sensitive, allowing multiple interrupts to be wire ORed onto one external interrupt pin. TMS70x2, SE70P162, TMS7742 External interrupts on the TMS70x2 devices, the SE70P162 piggyback device, and the TMS7742 EPROM device are high­ impedance inputs that are falling-edge sensitive only. TMS70CxO, TMS70CTxO SE70CP160 The external interrupt INT1 on the TM570CxO, TM570CTxO and SE70CP160 devices is a high-impedance falling-edge sensitive only interrupt, while INT3 is a high-impedance falling-edge and level-sensitive interrupt. TMS70Cx2, SE77C42, SE70CP162 The external interrupts on the TMS70Cx2, SE77C42, and SE70CP162 devices can be individually programmed as fail­ ing-edge sensitive only,falling-edge and level sensitive, rising­ edge sensitive only, or rising-edge and level sensitive. 3-35

TMS7000 Family Architecture - Interrupts and System Reset Certain safeguards should be observed for external interrupts that are both edge- and level-sensitive. The logical-OR of both the Pulse flip-flop output (Q1) and INTn (inverted INTn) affect the state of INTn flag, and can therefore activate the interrupt (see Figure 3-15 on page 3-31). The Pulse flip-flop is automatically cleared when the CPU acknowledges the interrupt. However, as long as the INTn pin is low, the interrupt will remain active even when the Pulse flip-flop output is O. This is how an external interrupt source is detected as a level signal. If INTn is active longer than the shortest path through the interrupt service routine, this same interrupt will be serviced again upon return from the service routine if no higher priority interrupts are active. In many applications this interrupt re-servicing is acceptable; however, in applications where this is a potential problem, the associated I NTn enable bit must be dis­ abled before exiting the interrupt service routine. Upon return from the service routine, INTn flag must be periodically software-polled to determine when INTn has gone inactive, and then INTn enable may be re-enabled. Note that devices with edge-sensitive only interrupts do not require the previously mentioned safeguards. To prevent an interrupt signal from being detected as a level signal, the maxi­ mum pulse (time low) of the signal cannot exceed the following: where: N tc(C) (16 + N) x tc(C) the total number of state clock cycles in the interrupt service routine, up to and including the EINT or RETI instruction the internal state clock cycle period This ensures that the INTn flag is cleared before the first possible instruction boundary in which the interrupt could be re-serviced. Note that this is not of any concern for INT1 on the TMS70CxO and TMS70CTxO devices and inter­ rupts on the TMS70x2 devices, since they are edge-sensitive only, not level­ sensitive.

3.6.6 External Interrupt Signals

Some applications may cause an incorrect interrupt vector to be accessed when using edge- and level-sensitive interrupts on the TMS70xO, TMS70CxO, and TMS70CTxO devices only. This may happen when an INTn pulse goes inactive on the boundary condition when interrupts are being enabled. Two events are necessary for this to occur: 1) First, the Pulse flip-flop is cleared upon entry to the interrupt service routine; since the INTn pin is still active, INTn flag and INT active remain active. 2) Second, the INTn pin goes inactive on the boundary condition when interrupts' are being enabled (RETI and EINT instructions or a write to IOCNTO to enable interrupts). When the INTn pin goes inactive, INTn flag becomes inactive and some time later INT active becomes inactive. This results in INT active being acknowl­ edged by the CPU, but INTn flag becomes inactive before interrupt decode logic can determine which interrupt was pending. Note that INTn has already been serviced, so that re-servicing of the interrupt is not required. If this

TMS7000 Family Architecture - Interrupts and System Reset condition occurs, interrupt vector fetches from locations >FFF8 and >FFF9 (for INT3) will occur for TMS70xO, TMS70CxO and TMS70CTxO devices. This situtation does not exist for edge-sensitive only interrupts (such as INT1 on the TMS70CxO and TMS70CTxO devices and the interrupts on the _ TMS70x2 and TMS70Cx2 devices). In applications where the system design cannot guarantee that the duration of the pulsed interrupt is outside this critical window, three system solutions should be considered.

• A system hardware solution uses an external D-type flip-flop or a one­ shot in the interrupt path, providing a level interrupt which the TMS7000 would externally clear as part of the service routine.
• Prevent the re-servicing of the interrupt as described earlier by setting the associated I NTn enable bit to 0 in the interrupt service routine.
• If only one external interrupt has the potential to cause this boundary condition, for TMS70xO devices, this interrupt should be connected to INT3 since the INT3 vector is fetched when this problem occurs. This would result in INT3 being re-serviced. For TMS70Cx2 devices with edge and level sensitivity enabled, a trap vector should be placed in lo­ cation >FFFO and >FFF1 which points to a RETI instruction. This will return the program to normal program flow if this condition occurs. For TMS70CxO devices, use INT1 since this interrupt is only edge sensitive and will not exhibit the condition. 3-37

TMS7000 Family Architecture - Programmable Timer/Event Counters

3.7 Programmable Timer/Event Counters

The programmable timer/event counters are 8-bit or 16-bit counters with a programmable, prescaled clock source. TMS70xO, TMS70CxO and TMS70CTxO devices contain one timer/event counter, TMS70x2 and TMS70Cx2 devices contain two timer/event counters and one timer. The data and control registers for these two timer/event counters are shown in Figure 3-19 through Figure 3-25 (pages 3-39-3-42).

• Timer 1 is available on all TMS7000 devices. TMS70xO, TMS70CxO, TMS70CTxO and TMS70x2 Timer 1 is an 8-bit timer/event counter with a 5-bit programmable prescaler. It contains an 8-bit capture latch and is accessed through PF registers P2 and P3. Note that the TMS70CTxO devices do not contain the A7/EC1 pin necessary for external event counting. TMS70Cx2 Timer 1 is a 16-bit timer/event counter that contains a 5-bit program­ mable prescaler and a 16-bit capture latch. It is accessed through PF registers P12, P13, P14, and P15.
• Timer 2 is available on the TMS70x2 and TMS70Cx2 devices. TMS70x2 Timer 2 is an 8-bit timer/event counter with a 5-bit programmable prescaler. It is accessed through P18 and P19 of the Peripheral File. TMS70Cx2 Timer 2 is a 16-bit timer/event counter that contains a 5-bit program­ mable prescaler and a 16-bit capture latch. It is accessed at PF registers P16, P17, P18, and P19.
• Timer 3 is available on the TMS70x2 and TMS70Cx2 devices and can be used as an independent timer or as the clock source for the on-chip serial port. Because of this function, Timer 3 is described in more detail in Section 3.8, The Serial Port. Note: The contents of all registers associated with the timers are not affected by a hardware RESET. These registers must be initialized by software.

TMS7000 Family Architecture - Programmable Timer/Event Counters 3-42 Timer 2 Data Register - T2DATA (P18)

7 I 6 I 5 I 4 I 3 121 I 0

MSb Decrementer Value LSb Read MSb T2 Reload Register LSb Write Timer 2 Control Register - T2CTL (P19)

7 I 6 I 5 I 4 I 3 I 2 I 1 I 0

START ISOURCEI Cascade I Prescale Reload Register Read Write Lo- Source bit determines clock source 1 - Clock source is Timer 1 reload signal; overrides Source bit _ 0 - Internal clock source = fosc/16 . 1 - External clock source from pin A6/EC2 '--0 - Stop timer and hold current count value bit to 0 1 - Reload prescaler & decrementer & begin decrementing Figure 3-25. Timer 2 Data and Control Registers (TMS70x2) T2MSDATA (P16) T2LSDATA (P17) 7 6 o Read Cascade START T2CTL1 (P18) o -Timer 2 output disabled o x Read Write 1 - Timer 2 out; toggles BO when T1 decrements through 0 o -Clock determined by Source bit 1 - Clock source is Timer 1 reload signal. overrides Source bit T2CTLO (P19) o Prescaler Reload Register o -. Timer 2 remains active during Idle 1 - Timer 2 will halt during Idle Internal clock source = fosc/4 External clock source from A6/EC2 Read Write o -Stop timer; hold current count value. and clear INT5 flag bit to 0 1 - Reload prescaler & decrementer & begin decrementing Figure 3-26. Timer 2 Data and Control Registers (TMS70Cx2)

TMS7000 Family Architecture - Programmable Timer/Event Counters

3.7.1 Control Registers for Timer/Event Counters 1 and 2

(TMS70xO. TMS70CxO. TMS70CTxO. and TMS70x2 Devices) The control bits and prescaling value of Timers 1 and 2 are determined by the timer control registers T1 CTL (P3) and T2CTL (P19). These bits can only be written to the control registers and cannot be read by a program. When T1 CTL is read, the capture-latch value associated with Timer 1 is returned. T2CTL is a write-only register and will return an irrelevant value when read. Since the control and prescale bits are write only, the read/modify/write instructions such as ANDP, ORP, and XORP should not be used. The following in­ structions should be used for timer control-bit manipulations. MOVP MOVP MOVP where: %>XX >01xx A B Pn Rn %>XX,Pn A,Pn B,Pn STA %>Olxx STA *Rn STA >Olxx(B) Immediate 8-bit hexadecimal data value 16-bit Peripheral-File hexadecimal address Register A Register B Peripheral-File register number General-purpose register pair number The same instructions are required for writing to the timer data registers, T1 DATA and T2DATA, and other write-only registers.

3.7.2 Control Registers for Timer/Event Counters 1 and 2

(TM S70Cx2 Devices) The control bits and prescaling value of Timers 1 and 2 of the TMS70Cx2 devices are determined by the timer control registers T1 CTLO (P15), T1 CTL 1 (P14), T2CTLO (P19), and T2CTL 1 (P18). Data can only be written to these control registers, and cannot be read back by a program. When Timer 1 con­ trol register T1 CTLO is read, the least significant (LS) byte of the capture latch value associated with Timer 1 is returned. When T1 CTL 1 is read, the most significant (MS) byte of the Timer 1 readout latch is returned. When T2CTLO is read, the least significant (LS) byte of the Timer 2 capture latch is returned. When T2CTL 1 is read, the most significant (MS) byte of the Timer 2 readout latch is returned. Since the control and prescale bits are write only, the read/modify/write instructions such as ANDP, ORP, and XORP should not be used. The following instructions should be used for timer control-bit ma­ nipulations. MOVP MOVP MOVP where: %XX' >01xx A B Pn Rn %>XX,Pn A,Pn B,Pn STA STA STA %>Olxx *Rn >Olxx(B) Immediate 8-bit hexadecimal data value 16-bit Peripheral-File hexadecimal address Register A Register B Peripheral-File register number General-purpose register pair number The same instructions are required for writing to the timer data registers, T1 LSDATA, T1 MSDATA, T2LSDATA, T2MSDATA, and other write-only re­ gisters. 3-43

TMS7000 Family Architecture ~ Programmable Timer/Event Counters

3.7.3 Timer Start/Stop (Bit 7) and Capture Latch

Bit 7 of the timer control registers contain a start/stop bit for the timer/event counters. Bit 7 = 0 A start bit of 0 disables or freezes the timer chain at the current count value. Bit 7 = 1 A start bit of 1, regardless of whether the bit was a 0 or a 1 before, loads the prescaler and counter decrementers with the corre­ spondingreload register values, and the timer/event counter op­ eration begins.

3.7.3.1 Timer 1 Capture Latch (TMS70xO, TMS70CxO, TMS70CTxO, and TMS70x2

Devices) The Timer 1 8-bit capture latch can be accessed by reading the Timer 1 control register T1 CTL (P3). T1 CTL will contain the "captured" current Timer 1 value whenever INT3 is triggered even if INT3 is disabled. Please note that when INT3 is used to exit a low-power mode on the TMS70CxO or TMS70CTxO CMOS parts, the capture latch may store an indeterminate value. This is due to the logic design of the CMOS devices. Since the value in the capture latch may not be valid when leaving either of the low-power modes via INT3, it is recommended that the capture latch not be used in this situation.

3.7.3.2 Timer 1 and Timer 2 Capture Latches (TMS70Cx2 Devices)

The TMS70Cx2 contains two 16-bit capture latches, one each for Timer 1 and Timer 2. The Timer 1 16-bit capture latch can be accessed by reading the Timer 1 control registers T1CTLO (P15) and T1CTL1 (P14). The Timer 2 16-bit capture latch can be accessed by reading the Timer 2 control registers T2CTLO (P19) and T2CTL 1 (P18). The §Qture latch values for Timer 1 and Timer 2 are loaded on the active edges of INT3 and INT1, respectively, whether the interrupts are enabled or not. Both capture latches are disabled during the IOLE instruction when their corresponding HALT bits are 1. Reading the Timer 1 control register T1 CTL 1 or the Timer 2 control register T2CTL will return the value of the MSB readout latch of the respective timer. This latch is shared between MSB .of the timer latch and the MSB of the capture latch. It allows the complete 16-bit value of the timer latch or the capture latch to be sampled at one moment. The LSB must be read first, which causes the MSB to' be simultaneously loaded into the readout latch. This latch physically exists in only one location for each timer; however, each latch can be read from two different locations. Timer 1 MSB readout latch can be read from T1 MSDATA (P12) or T1 CTL 1 (P14). Timer 2 MSB readout latch can be read from T2MSOATA (P16) or T2CTL 1 (P18). Reading the LSB of the decrementer or capture latch will update the contents of the readout latch. In order to correctly read the entire 16-bit value of the decrementer or capture latch, the LSB must be read first which will load the MSB readout latch. The MSB readout latch must be read and stored before reading the LSB of either the decrementer or capture latch. The order of 16-bit read operations should be: Timer 1: Decrementer: Read P13 then P12 or read P13 then P14 Capture Latch: Read P1 5 then P1 2 or read P15 then P14 Timer 2: Decrementer: Read P17 then P16 or read P17 then P18 Capture Latch: Read P19 then P16 or read P1 9 then P18 ....

TMS7000 Family Architecture - Programmable Timer/Event Counters 3.7.4 Clock Source Control (Bit 6) (See note below.) For the TMS70xO, TMS70CxO, TMS70CTxO, and TMS70x2 devices, bit 6 (SOURCE) of T1 CTl and T2CTl selects the Timer 1 and Timer 2 clock _ sources, respectively. For the TMS70Cx2 devices, bit 6 (SOURCE) of T1 CTlO and T2CTlO selects the Timer 1 and Timer 2 clock sources, respectively. Bit 6 = 0 A source bit of 0 selects the internally generated clock and places the timer/event counter ill the Realtime Clock mode using the in­ ternal clock source. Each positive transition of the timer clock signal decrements the count chain. Realtime Clock mode allows a program to periodically interrupt and call a service routine, such as a display refresh, by simply setting the prescale reload register and the timer reload register so the routine is called at the desired frequency. Bit 6 = 1 A source bit of 1 selects the external clock source and places the timer/event counter in the Event-Counter mode. In this mode, each positive transition at the Port A event counter pins decre­ ment!; the count chain (when the prescaler is decremented to zero, it is reloaded with the prescaler reload register value and the counter is decremented by one). Summary for all TMS7000 devices (see note below): Tim.er 1 Timer 2 Event Counter Input Pin Pin A7/EC1 Pin A6/EC2 Interrupt level INT2 INT5 The Event-Counter mode allows INT2 and INT5 to function as positive edge­ triggered external interrupts by loading a start value of 0 into both the pres­ caler and timer reload register. A positive transition on A7/EC1 or A6/EC2 decrements the corresponding timer through zero and generates an INT2 or INT5. Event-Counter mode can also be used as an externally provided real­ time clock if an external clock is input on the I/O pin. The minimum clock period on pins A7/EC1 or A6/EC2 must not be less than fosc/16 for TMS70xO, TMS70x2, and TMS70CxO devices, or fosc/4 for TMS70Cx2 de­ vices. The minimum pulse width of the external signal must not be less than 1.25 state clock cycles [1.25 x tc(C)J to be properly detected by the device. Note: The TMS70CTxO devices do not contain an external event counter input pin. Therefore, the clock source must be selected as internal. 3-45

TMS7000 Family Architecture - Programmable Timer/Event Counters

3.7.5 Idle/Timer Halt Bit (Bit 5)

3-46 . The function of the Idle bit (bit 5) in the timer control registers varies de­ pending on the device type.

• TMS70xO and TMS70x2 Bit 5 is not used on any of the TMS7000 NMOS devices.
• TMS70CxO and TMS70CTxO Bit 5 of T1 CTL (P3) register is the IDLE bit. This bit selects either of two low-power modes on these devices when the IDLE instruction is exe­ cuted. (See Section 3.4.2 about CMOS low-power modes.) Bit 5 = 0 Wake-Up low-power mode Bit 5 = 1 Halt low-power mode
• TMS70Cx2 Bit 5 of the T1 CTLO (P15) and T2CTLO (P19) registers acts as a tim­ er-halt bit. This bit selects either of two timer operational modes when the IDLE instruction is executed. Bit 5 = 0 Timer active mode Bit 5 = 1 Halt timer mode

TMS7000 Family Architecture - Programmable Timer/Event Counters

3.7.6 Cascading Timers

The TMS70x2 and TMS70Cx2 devices can have their timers cascaded to- gether to form one large timer. The external clock input for Timer 2 is the Port _ A pin A6/EC2. This pin can also function as the serial clock I/O line (SCLK) for the serial port on the TMS70x2 devices (see Section 3.8, The Serial Port). Several arrangements are possible with Timer 2 in relation to Timer 3 and the serial port because of this:

• Both SCLK and Timer 2 clock internal: the Timer 3 output divided by 2 is driven out of the A6/EC2 pin and Timer 2 is internally clocked by 8 x tc(C).
• SCLK internal and Timer 2 clock external: the Timer 3 output divided by 2 is driven out of the A6/EC2 pin and this pin drives the Timer 2 clock. In this mode, Timer 3 and Timer 2 are cascaded together, with Timer 3 driving Timer 2. This is done by setting the Cascade bit to 0 and the Timer 2 source bit to 1. Timer 2 can then be cascaded under software control to either Timer 1 or Timer 3.
• SCLK external and Timer 2 clock internal: the input signal drives the se­ rial port clock and Timer 2 is internally clocked by 8 x tc(C).
• Both SCLK and Timer 2 clock external: the input signal drives both the serial port clock and Timer 2. The differences between the TMS70x2 and TMS70Cx2 Cascade bits are ex­ plained below.
• TMS70x2 Bit 5 of the T2CTL (P19) register in the TMS70x2 devices is the Cas­ cade bit. This bit is used in conjunction with T2CTL (P19) Source (bit 6) to determine the Timer 2 clock source. Bit 5 = 0 A Cascade bit of 0 allows bit 6 (source) to determine the clock source. Bit 5 = 1 A Cascade bit of 1 selects the output generated by the Timer 1 reload pulse as the clock input to the prescaler of Timer 2. The Cascade bit overrides the Source bit; that is, if the Cas­ cade bit is 1, the Source bit of Timer 2 has no effect.
• TMS70Cx2 Bit 7 of the T2CTL 1 (P18) register is the Cascade bit. This bit is used in conjunction with the T:lCTLO (P19) Source (bit 6) to determine the Timer 2 clock source. Bit 7 = 0 A Cascade bit of 0 allows bit 6 of T2CTLO to determine the clock source. Bit 7 = 1 A Cascade bit of 1 selects the output generated by the Timer 1 reload pulse as the clock input to the prescaler of Timer 2. The Cascade bit overrides the Source bit; that is, if the Cas­ cade bit is 1, the Source bit of Timer 2 has no effect. Note that on the TMS70Cx2 devices, the Timer 2 output (T20UT) can­ not be used if Timer 1 and Timer 2 are cascaded together. 3-47

TMS7000 Family Architecture - Programmable Timer/Event Counters

3.7.7 Timer and Prescaler Operation

The timer clock, whether internal or external, is prescaled by a 5-bit modulo-N counter. The prescaling value is determined by the least significant five bits of the timer control register. The timers decrement and an underflow occurs on the transition from 0 to > FF. Thus, a prescale value of > 7 will produce an fosc/128 clock input into the timer for a TMS70xO device with a timer clock source of fosc/16.

• TMS70xO, TMS70CxO, TMS70CTxO and TMS70x2 Timer 1 Bits 0-4 of Timer 1 control register T1 CTl comprise the Timer 1 prescale reload register value. Timer 2 Bits 0-4 of Timer 2 control register T2CTl comprise the Timer 2 prescale reload register value. (Available on TMS70x2 only)
• TMS70Cx2 Timer 1 Bits 0-4 of Timer 1 control register T1 CTlO comprise the Timer 1 prescale reload register value. Timer 2 Bits 0-4 of Timer 2 control register T2CTlO comprise the Timer 2 prescale reload register value. These steps occur during timer operation: 1 ) Upon starting the timer, the prescaler and timer are loaded from the prescaler reload register and timer reload register, respectively. 2) Each pulse decrements the prescaler by one. 3) When the prescaler countdown decrements through zero, the timer is decremented by one. After the prescaler is decremented, If timer '¢ 0 Reload prescaler and go back to step 2. If timer:;:;; 0 When both the timer and the prescaler decrement through zero together, an interrupt occurs. An INT2 for Timer 1 (INT5 for Timer 2) is momentarily pulsed when both the prescaler and counter decrement past the zero value to­ gether. This sets the I NT2 or I NT5 Pulse flip-flop, as de­ scribed in Section 3.6.2, Interrupt Operation. 4) The 5-bit prescaler and decrementer are then immediately reloaded with the contents of the prescale reload register and the timer reload register, and the timer will start decrementing with the new reload register values.
• TMS70xO, TMS70CxO, TMS70CTxO and TMS70x2 The 8-bit timer reload register is loaded through the Timer 1 data register T1 DATA (P2) for Timer 1 and the Timer 2 data register T2DATA (P18) for Timer 2. This value is write only. When read, T1 DATA and T2DATA contain the current value of the 8-bit decrementer for Timer 1 and Timer 2, respectively, and not the timer reload register value. For this reason, the read/modify/write I/O instructions should not be used to alter the data value in the timer reload register. When read, the T1 CTl contains the capture latch value for Timer 1. (Timer 2 is available on the TMS70x2 only.)

TMS7000 Family Architecture - Programmable Timer/Event Counters

• TMS70Cx2 The 16-bit timer reload registers are loaded through the Timer 1 data registers T1 LSDATA (P13) and T1 MSDATA (P12), and the Timer 2 data _ registers T2LSDATA (P17) and T2MSDATA (P16). This value is write only. When read, T1 LSDATA and T2LSDATA return the current value of the LSB of the Timer 1 and Timer 2 decrementers, respectively, and not the LSB timer reload register value. For this reason, the read/modify/write I/O instructions should not be used to alter the data value in the timer reload registers. T1 MSDATA and T2MSDATA will return the value of the MSB readout latch for Timers 1 and 2, respec- tively. To read the Timer 1 capture latch, first read T1 CTLO (P15) to obtain the LSB, then read T1 CTL1 (P14) to obtain the MSB. To read the Timer 2 capture latch, first read T2CTLO (P19) to obtain.the LSB, then read T2CTL 1 (P18) to obtain the MSB.

3.7.8 Timer Interrupts

When the prescaler and decrementers pass through zero together, an interrupt flag (INTn flag) is set and the prescaler and counter decrementers are imme­ diately and automatically reloaded with the corresponding reload register val­ ues. The interrupt levels generated by the timers are INT2 for Timer 1 and INT5 for Timer 2. The period between successive timer interrupts may be calculated by the following formula:

• TMS70xO, TMS70CxO, TMS70CTxO and TMS70x2 tiNT = tCLK x (PR+1) x (TR+1) where: tiNT = Period between timer interrupts tCLK = Period of the timer input clock which is 16/fosc for Realtime Clock mode or the period of the external input pin for Event­ Counter mode PR 5-bit prescaler reload register value TR 8-bit timer reload register value At the falling edge of the INT3 input, the Timer 1 counter value is loaded into the capture latch. This feature provides the capability to determine when an external event occurred relative to the current Timer 1 decre­ menter value.
• TMS70Cx2 tiNT = tCLK x (PR+1) x (TR+1) where: tiNT = Period between timer interrupts tCLK = Period of the timer input clock which is 4/fosc for Realtime Clock mode or the period of the external input pin for Event­ Counter mode PR 5-bit prescaler reload register value TR 16-bit timer reload register (value written to the MSB and LSB timer reload registers) 3-49

TMS7000 Family Architecture - Programmable Timer/Event Counters On the TMS70Cx2 devices, the falling edge of the INT3 input will cause the 16-bit decrementer value of Timer 1 to be loaded into the Timer 1 capture latch. Likewise, the falling edge of the INT1 input will cause the 16-bit de­ crementer value of Timer 2 to be loaded into the Timer 2 capture latch. This feature provides the capability to determine when an external event occurred relative to the current timer/counter value.

3.7.9 Timer Output Function (TMS70Cx2 Devices)

Timer 1 and Timer 2 have a timer output function which allows the B1 and BO outputs, respectively, to be toggled every time the timer decrements· through zero. This function is enabled by the T1 OUT and T20UT bits (bit 6) in the timer control registers T1 CTL 1 and T2CTL 1. When operating in the timer output mode, the BO and/or B1 output cannot be changed by writing to the Port B Data Register. Writing to the appropriate timer's Start bit will reload and start the timer, and will not toggle the output. The output will toggle only when the timer decrements through zero. The timer output feature is independent of INT2 and INT5; therefore, it will operate with INT2 and INT5 enabled or disabled. Also, if the timer is active during the IDLE instruction, the timer output feature will continue to operate. Whenever the T20UT or T1 OUT bit is returned to 0, 80 or 81 will become an output-only pin, like B2. The value in the BO or B1 data register will be the last value output by the timer output function, to that BO or B1 will not change as the T1 OUT or T20UT bit is returned to O. Whenever Port 8 is read, the value on the BO pin will always be returned, so the current timer output value can be read by reading Port B. The T1 OUT and T20UT bits are set to 0 by a reset, so the timer output func­ tion will not be enabled unless the user sets T1 OUT or T20UT to 1. The Timer 2 output (T20UT) cannot be used if Timer 1 and Timer 2 are cas­ caded together (Cascade bit of T2CTL1 set to 1).

TMS7000 F~mily Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8 Serial Port (TMS70x2 and TMS70Cx2 Devices Only)

The TMS70x2 and TMS70Cx2 devices contain a serial port, greatly enhancing their I/O and communications capabilities. Including a hardware serial port _ on chip saves ROM code and allows much higher transmission rates than could be achieved through software. The full-duplex serial port consists of a receiver (RX). transmitter (TX), and a third timer called Timer 3 (T3). The functional operation of the serial port is configured through software initialization. A set of control words are first sent out to the serial port to initialize the desired communications format. These control words will determine the baud rate, character length, even/odd/off parity, number of stop bits, and so forth. Figure 3-27 (page 3-52) illustrates the serial port functional blocks. The serial port provides Universal Synchronous Asynchronous Receiver/­ Transmitter (USART) communications:

• Asynchronous mode, discussed in Section 3.8.2.1 (page 3-65) inter­ faces with many standard devices such as terminals and printers using RS-232-C formats.
• Isosynchronous mode, discussed in Section 3.8.2.2 (page 3-66) permits very high transmission rates and requires a synchronizing clock signal between the receiver and transmitter.
• Serial I/O mode, discussed in Section 3.8.2.3 (page 3-66) can be used to expand I/O lines and to communicate with peripheral devices requir­ ing a non-UART serial input such as A-to-O converters, display drivers, and shift registers. The serial port also has two multiprocessor protocols, compatible with the Motorola 6801 and Intel 8051. These protocols allow efficient data transfer between multiple processors. They are implemented using isosynchronous or standard asynchronous formats. 3-51

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) 3-52 SMODE SCNTLO 88TAT SERIAL. PORT I I I , "----' , , ...-.--r-' -SCLl( RXBUF ..----;-RXD It-----''--SCLI( , INT" , Figure 3-27. Serial Port Functional Blocks

TMS7000 Family Arch.itecture - Serial Port (TMS70x2 and TMS70Cx2) 3.S.1 Serial Port Registers The serial port is controlled and accessed through registers in the Peripheral File. These registers are listed in Table 3-16. Figure 3-27 contains a block _ diagram of the serial port registers and functional blocks. Table 3-16. Serial Port Control Registers REGISTER NAME TYPE FUNCTION TMS70Cx2 TMS70x2 P20 P17 SMODE FIRST WRITE Serial Port Mode P21 P17 SCTlO READ/WRITEt Serial Port Control 0 P22 P17 SSTAT READ Serial Port Status P23 P20 T3DATA READ/WRITE Timer 3 Data P24 P21 SCTl1 READ/WRITE Serial Port Control 1 P25 P22 RXBUF READ Receiver Buffer P26 P23 TXBUF WRITE Transmission Buffer t Write only for TMS70x2 devices The serial mode register, SMODE, is the RX/TX control register that describes the character format and type of communication mode (Asynchronous, Iso­ synchronous, or Serial I/O). The serial port control 0 register, SCTLO, is the RX/TX control register used to control the serial port functions, TX and RX enable, clearing of error flags, and S/W enable. The serial port Status Register, SSTAT, is the read-only serial Status Register used to report the serial port status. The T3DATA register is the read/write Timer 3 data register. RXBUF is a read-only register containing data from RX. RX8UF is double­ buffered with the internal shift register (RXSHF) so that the the CPU has at least a full frame to read the received data before RX can overwrite it with new data. TXBUF is a write-only register from which TX takes the data it transmits. It is double-buffered with the TX shift register (TXSHF), so that the CPU has a full frame to write new data before TX8UF becomes empty. The TXD and RXD lines use I/O pins 83/TXD and A5/RXD, respectively. This configuration allows the TXD and RXD pins to be used as I/O pins if desired. If serial port transmission is disabled, then TXD follows 83. If reception is disabled, then no receiver interrupts occur and A5 functions as an input pin on TMS70x2 devices and as a general-purpose I/O pin on TMS70Cx2 de­ vices. The 83 I/O pin must be set to a 1 in order to enable the TXD pin. 3-53

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

• 3.B.1.1 Serial Mode Register (SMODE) The SMODE register is the RX/TX control register that describes the character format and type of communication mode (Asynchronous, Isosynchronous, or Serial I/O). STOP STOP CMOOE iCMOOE PEVEN PEVEN PEN PEN 3 2 CHAR1 CHARO CHAR1 CHARO ASYNC ASYNC MULTI MULTI Read Write LJ Lo - 1 - Motorola protocol I ntel protocol o -Isosy nchronous munications chronous munications L- com 1 - Asyn com L- Bits/Character: 00 - 5 bits/char 01 - 6 bits/char 10 - 7 bits/char 11 - 8 bits/char I-0 - Parity disabled 1 - Parity enabled _ 0 - Odd parity 1 - Even parity _ 0 - Serial I/O mode 1 - Communication mode '-0 - One STOP bit 1 - Two STOP bits Figure 3-28. Serial Mode Register - SMODE
• TMS70x2 (Write-only register) SMODE is accessed at Peripheral-File location P17 on the first write after a hardware or serial port reset. SMODE must be the first register written to in the serial port immediately following a reset. After the SMODE register is written to, it cannot be accessed again without first performing another reset operation. The first write operation to location P17 immediately following a reset accesses SMODE. All subsequent writes to P17 access the control register (SCTLO).
• TMS70Cx2 SMODE is accessed anytime at Peripheral-File register P20. Multiprocessor Mode (MULTI) Bit 0 3-54 There are two possible multiprocessor protocols, Motorola (Section 3.8.3.1) and Intel (Section 3.8.3.2). o -Selects the Motorola protocol. , -Selects the Intel protocol.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) The Motorola mode is typically used for normal communications since the In- tel mode adds an extra bit to the frame. The Motorola mode does not add this extra bit and is compatible with RS-232-type communications. Multi­ processor communication is different from the other communication modes • because it uses Wake-Up and Sleep functions. . Communications Mode (ASYNC) Bit 1 This bit determines the serial port communication mode. 0-Selects Isosynchronous mode (Section 3.8.2.2). In this mode, the bit pe­ riod is equal to the SCLK period; bits are read on a single value basis. 1 -Selects Asynchronous mode (Section 3.8.2.1). In this mode the bit period is 8 times the SCLK period and bits are read on a two out of three majority basis. Number of Bits per Character (CHAR1, CHAR2) Bits 2,3 Character length is programmable to 5, 6, 7 or 8 bits. Characters less than 8 bits are right-justified in buffers RXBUF and TXBUF and padded with leading zeros. The unused leading bits in TXBUF may be written as don't cares. The RXBUF and TXBUF register formats are illustrated in Figure 3-33 and Figure 3-34. Parity Enable (PEN) Bit 4 If parity is disabled (PEN set to 0), then no parity bit is generated during transmission or expected during reception. A received parity bit is not trans­ ferred to RXBUF with the received data because it is not considered one of the data bits when programming the character field. On the TMS70Cx2 devices, the parity error flag may be set even though parity is disabled. Parity Even (PEVEN) Bit 5 If PEN is set, then this bit defines odd or even parity according to an odd or even number of 1 bits in both transmitted and received characters. o -Sets odd parity. 1 -Sets even parity. Serial I/O or Communication Mode (CMODE) Bit 6 This bit determines whether the serial port operates in Serial I/O mode or one of the communication modes. o -Puts the serial port in Serial I/O mode which allows easy I/O expansion by using external shift registers. 1 -Selects communication mode. The ASYNC bit (bit 1) determines whether the serial port is in Asynchronous or Isosynchronous mode. The MULTI bit (bit 0) determines if the communication uses the Motorola or Intel protocol. Number of Stop Bits (STOP) Bit 7 This bit determines the number of stop bits sent when the serial port is in Isosynchronous or Asynchronous mode. o -Selects one stop bit. 1 -Selects two stop bits. The receiver checks for one stop bit only. 3-55

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.1.2 Serial Control Register 0 (SCTLO)

The SeTlO register is the RX/TX control register used to control the serial port functions, TX and RX enable, clearing of error flags, and S/W reset. SeTlO is cleared by a hardware or software reset. Read o -Transmitter disabled 1 - Transmitter enabled SCLK enable (TMS70Cx2): o -A4 is general-purpose I/O 1 - A4 is SCLK o - Receiver disabled; A5 is general-purpose I/O 1 - Receiver enabled; A5 is RX input o -Do not reset flags 1 - Reset error flags o -Serial port enable 1 - Reset serial port Serial port halt (TMS70Cx2): o -Serial port & Timer 3 fuliV active during IDLE 1 - Serial port & Timer 3 fuliV halted during IDLE Figure 3-29. Serial Control 0 Register - SCTLO

• TMS70x2 (Write-only register) SeTlO is a write-only register, accessed at Peripheral-File location P17 on the second and subsequent write operations after a hardware or serial port reset. After a hardware or serial port reset, SMODE must be written to before the SeTlO register can be accessed, since the SMODE and SCTlO registers are accessed through the same location. Use the following procedure if you do not know if P17 is SeTlO or SMODE. Writing a 0 to P17 puts this register at SeTlO, but the first write operation might have changed the SMODE value so it needs to be re-initialized. SMODE SCTLO EQU P17 EQU P17 * UARTRS MOVP %0,P17 MOVP %>40,SCTLO MOVP %>XX,SMODE P17 in an unknown state, ensure being at SCTLO Reset the serial port Set SMODE to proper values MOVP %?XOXXXXXX,SCTLO Clear the reset bit * * ( ?=binary) P17 is now SCTLO
• TMS70Cx2 SeTLO is a read/write register, and can be accessed anytime at Peri­ pheral-File location P21.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) Transmit Enable (TXEN) Bit 0 Data transmission through TXD (pin B3) cannot take place unless TXEN is set to 1. When TXEN is reset to 0, transmission does not halt until all the data previ-_ ously written to TXBUF is sent. Thereafter, B3/TXD can be used as general- purpose output. TXEN is set to 0 by a hardware or software reset. In Isosynchronous mode, if an internally generated SCLK is used, the SCLK output at pin A6 (TMS70x2) or A4 (TMS70Cx2) is enabled. When the entire frame is transmitted, TX disables SCLK and sets TXRDY and INT4 flag to a1, and TXEN to O. TXEN has no direct effect on TXRDY or INT4 flag in this mode. Serial Clock Enable (SCLKEN) Bit 1 -TMS70Cx2 devices only This bit determines if the A4/SCLK pin will be used as general-purpose I/O (bit 1 = 0), or as the serial clock SCLK pin (bit 1 = 1). Receive Enable (RXEN) Bit 2 In the communication modes (Asynchronous and Isosynchronous): 0-Prevents received characters from being transferred into RXBUF, and no RXRDY interrupt is generated. However, the receiver shift register (RXSHF) continues to assemble characters. Thus, if RXEN is set during character reception, the complete character will be transferred into RXBUF. 1 -Enables RX (receiver) to set INT4 flag and enable RXRDY. In Serial I/O mode: 0-The UR bit sets RXEN to O. 1 -Enables RX operation. In Isosynchronous mode, if an internally generated SCLK is used, the SCLK output at pin A6 (TMS70x2) or A4 (TMS70Cx2) is enabled. When the entire frame is received, RX disables SCLK and sets RXRDY and INT4 flag to a 1, and RXEN to O. RXEN has no direct effect on RXRDY or INT4 flag in this mode. Error Reset (ER) Bit 4 The error reset bit is used to reset any error flags during serial port operation. 0-No error flags are affected. Software UART Reset (UR) Bit 6 Writing a 1 to this bit puts the serial port in the reset condition, enabling the SMODE register for initialization. SCLK (pin A6 on TMS70x2 devices, pin A4 on TMS70Cx2 devices) is put in the high-impedance input state. The Txe signal is held at 1 so the B3 pin may be used as a general-purpose output line. On TMS70Cx2 devices, the A5/RXe signal becomes a general-purpose I/O line; on TMS70x2 devices, it becomes an input. Until a 0 is written to UR, all affected logic is held in the reset state. UR must be set to 0 before the CPU can write a 1 to CLK and output SCLK on Port A. UR is set to 1 by hardware RESET. The UART reset affects only the items above; it is not a general device reset like the Fi"ESET pin. 3-57

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) Serial Port Halt Enable (SPH) Bit 7 -TMS70Cx2 devices only This bit determines if the serial port and Timer 3 will be active or not during an IDLE instruction. 0-Serial port and Timer 3 will be fully active during an IDLE instruction. 1 -Serial port and Timer 3 will be halted during an IDLE instruction.

3.8.1.3 Serial Port Status Register (SSTAT)

SSTAT is the read-only serial port Status Register. Bits 0, 1, and 6 of this re­ gister are cleared by a hardware or software reset. 0-TXBUF full 1 - TXBUF ready for character o -RXBUF empty 1 - RXBUF ready with new character o -Transmitter written to 1 - Transmitter empty o -If PEN = 1, no parity error 1 - If PEN = 1, parity error o -No overrun error 1 . - Overrun error o -No framing error 1 - Framing error o -N a break detect 1 - Break detect Intel address bit (TMS70Cx2 devices): o -Last address bit received was 0, or I ntel mode not selected 1 - Last address bit received was 1 X - Don't care on TMS70x2 devices Figure 3-30. Serial Port Status Register - SSTAT

• TMS70x2 The SSTAT register is accessed anytime by reading Peripheral-File lo­ cation P17.
• TMS70Cx2 The SSTAT register is accessed anytime by reading Peripheral-File lo- cation P22. . Transmitter Ready (TXRDY) Bit 0 3-58 The TXRDY bit is set by the transmitter to indicate that TXBUF is ready to re­ ceive another character. It is automatically reset when a character is loaded. If the serial port interrupt (INT4) is enabled, it is issued at the same time the TXRDY bit is set .. Resetting the UART sets TXRDY to 1.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) Receiver Ready (RXRDY) Bit 1 This bit is set by the receiver to indicate that RXBUF is ready with a new character. It is automatically reset when the character is read out. If the serial port interrupt (INT4) is enabled, it is set at the same time that the RXRDY bit is set. Resetting the UART sets RXRDY to 1. Transmitter Empty (TXE) Bit 2 The TXE bit is set to 1 when the transmitter shift register (TXSHF) and TXBUF (shown in Figure 3-34, page 3-62) are empty. It is reset to 0 when the TXBUF is written to. Resetting the UART sets TXE to 1. Parity Error (PE) Bit 3 PE is set when a character is received with a mismatch between the number of 1 s and its parity bit. This bit is reset by the ER bit in SeTlO. Disabling the parity does not disable this flag, so this flag may be set even when the parity is disabled. Overrun Error (OE) Bit 4 OE is set when a character is transferred into RXBUF (shown in Figure 3-34) before the previous character has been read out. The previous character is overwritten and lost. OE is reset by the ER bit in SeTlO. Framing Error (FE) Bit 5 FE is set when a character is received with a 0 stop bit, meaning that syn­ chronization with the start bit has been lost and the character is incorrectly framed. The ER bit in SeTlO resets FE. Break Detect (BRKDT) Bit 6 The BRKDT bit shows that a break condition has occurred. BRKDT is set if the RXD line remains continuously low for 10 bits or more, starting from the end of a frame (stop bit). When the break ends, BRKDT is set to a 0 imme­ diately. In the Serial I/O mode, BRKDT remains a O. UR (SeTlO bit 6) sets BRKDT to O. A break is generated by setting Port B bit 3 low. Setting B3 high again resumes TXD operation. The TXD and RXD lines are multiplexed on I/O lines B3 and A5, respectively. This configuration allows the TXD and RXD pins to be used as I/O pins if desired. If transmission is disabled, then TXD follows B3. If reception is dis­ abled, then no receiver interrupts occur and A5 is an input bit. Intel Address Bit (lADD) Bit 7 -TMS70Cx2 devices only This bit shows the last data bit received when using the Intel protocol. o -last address bit received was 0, or Intel mode was not selected. 1 - last address bit received was 1. X - Don't care on TMS70x2 devices. 3-59

TMS7000 Family A.rchitecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.1.4 Serial Control Register 1 (SCTL1)

The SCTl1 register is the read/write serial control register 1. It is' used to control the Timer 3 start/stop function, the source of SClK, multiprocessor communication, Timer 3 interrupt, and the Timer 3 prescaler value. 2-bit prescaler reload reg. for timer o -Disables T3 interrupt to set INT4 flag 1 - Enables T3 interrupt to set INT4 flag Write: 0 - Clear T3FLG 1 - Set T3FLG Read: 0 - T3FLG was software cleared 1 - Timer 3 decremented through 0 or T3FLG was software set Controls TX multiprocessor communication Controls RX multiprocessor communication o -External clock from SCLK pin 1 - Internal SCLK from Timer 3 o -Stop Timer 3 1 - Start Timer 3 ' Figure 3-31. Serial Port Control 1 Register - SCTL 1 eTMS70x2 The SCTL1 register is accessed at Peripheral-File location P21. e TMS70Cx2 The SCTl1 register is accessed at Peripheral-File location P24. Timer 3 Prescale Reload Register (PRE3(1), PRE3(0» Bits 0,1 These are the prescale bits for Timer 3. The internal clock input to Timer 3 is either fosc/4, /8, /16, or /32, depending on how the prescale bits are set. The Timer 3 output divided by 2 is the actual baud rate for the Isosynchronous mode; divided by 8, it is the baud rate for for the Asynchronous mode. Timer 3 Interrupt Enable (T3ENB) Bit 2 3-60 When T3ENB is set to 1, Timer 3 sets INT4FlG to 1 when it sets T3FlG to 1. T3ENB is reset to 0 by a hardware reset, but not by UR (SCTlO bit 6). This allows Timer 3 to operate independently of the serial port.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) Timer 3 Interrupt Flag (T3FlG) Bit 3 The T3FLG bit is set to 1 when both the Timer 3 prescaler and Timer 3 dec­ rement through zero together. T3FLG indicates that Timer 3 caused the serial port interrupt. T3FLG must be cleared by software in the T3 interrupt service _ routine, since it is not cleared when the INT4 vector is fetched by the CPU .. T3FLG is reset to 0 by a hardware reset, but not by UR (SCTLO bit 6). This allows Timer 3 to operate independently of the serial port. Wake-Up (WU) Bit 4 The WU bit controls the TX features of the multiprocessor communication WU to 0; it cannot be set again until UR is cleared. Sleep (SLEEP) Bit 5 The SLEEP bit controls the RX features of the multiprocessor modes (See Serial Clock Source (ClK) Bit 6 The CLK bit determines the SCLK source. Resetting the UART sets CLK to 0; it cannot be set again until UR is cleared. 0-Selects an external SCLK, which is input on the high-impedance A6/SCLK line on the TMS70x2 devices, and pin A4/SCLK on the TMS70Cx2 de­ vices. 1 - Selects an internal SCLK, derived from Timer 3. This signal is output on the low impedance SCLK line. Timer 3 Start (START) Bit 7 This bit controls the starting and stopping of Timer 3. o -Stops Timer 3. 1 - Loads Timer 3 with the Timer 3 data value and then starts the timer. Writing a 1 wi" have no effect if Timer 3 is already active.

3.8.1.5 Timer 3 Data Register

The Timer 3 data register, T3DATA, is a read/write register used to store the countdown value of Timer 3. Figure 3-32. Timer 3 Data Register - T3DATA

• TMS70x2 The T3DATA register is accessed at Peripheral-File location P20.
• TMS70Cx2 The T3DATA register is accessed at Peripheral-File location P23. 3-61

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.7.6 Receiver Buffer

The receiver buffer, RXBUF, is a read-only register used to store the current RX data. Writing has no direct effect on this register. Data in the RXBUF is right justified, padded with leading Os.

7 I 6 I 5 I 4 J 3 I 2 J 1 I 0

0 0 I 0 I+- 5 Data Bits -+ 0 0 I+- 6 Data Bits -+ 0 +- 7 Data Bits -+ +- 8 Data Bits -+ Figure 3-33. Receive Buffer - RXBUF

• TMS70x2 The read-only RXBUF register is accessed at PF location P22.
• TMS70Cx2 The read-only RXBUF register is accessed at PF location P25.

3.8.7.7 Transmitter Buffer

The transmitter buffer, TXBUF, is a write-only register used to store data bits to be transmitted by TX. Data written to TXBUF must be right justified be­ cause the left-most bits will be ignored for characters less than eight bits long. X X I X I+- 5 Data Bits -+ X X I+- 6 Data Bits -+ X +- 7 Data Bits -+ +- 8 Data Bits -+ Figure 3-34. Transmitter Buffer - TXBUF

• TMS70x2 The write-only TXBUF register is accessed at PF location P23.
• TMS70Cx2 The write-only TXBUF register is accessed at PF location P26.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.1.8 RX Signals in Communication Modes

Notes: 1) Format shown is start bit + seven data bits + stop bit. 2) SCLK is continuous, external or internal. 3) If RXEN = 0, RXSHF still receives data from RXD. However, the data is not transferred to RXBUF and RXRDY and INT4FLG are not set. Sequence of Events: 1) RXSHF data is transferred to RXBUF. Error status bits are set if an error is detected. 2) Software writes to INT4CLR to clear INT4FLG. If not, CPU clears. 3) INT4FLG on entry to level 4 interrupt routine. 4) Software reads RXBUF.

3.8.1.9 TX Signals in Communication Modes

Notes: 1 Format shown is start bit + eight data bits + parity bit + two stop bits. 2) SCLK is continuous whether internal or external. Sequence of Events: 1) Software writes to TXBUF. 2) TXBUF and WU data are transferred to TXSHF and WUT. INT4FLG and TXRDY are set. 3) Software writes to INT4CLR to clear INT4FLG or CPU clears INT4FLG on entry to level 4 interrupt routine. 4) Software writes to TXBUF. 5) Software writes to INT4CLR to clear INT4FLG or CPU clears INT4FLG on entry to level 4 interrupt routine. 6) Software resets TXEN; current frame will finish and transmission will stop whether TXBUF is full or empty. 7) TXE is set if TXBUF and TXSFT are empty. 3-63

TMS7000 Family Architecture - Serial Port (TMS70x2 and'TMS70Cx2) 3.B.1.10 RX Signals in Serial If 0 Modes 1NT4 FLG -i I RXEN ----'l-o RXD SCLl< Notes: 1 RXEN has no effect on INT4FLG or RXRDY in Serial I/O mode. 2) RXD is sampled on SCLK rise; external shift registers should be clocked on SCLK fall. 3) The SCLK source should be internal as it is gated by internal circuitry. Sequence of Events: 1) Software starts receiving by setting RXEN. 2) Gated SCLK starts and data is received. 3) RXEN is automatically cleared in last data bit. 4) RXSHF data is transferred to RXBUF, and RXRDY and INT4 are set. 5) Software writes to INT4CLR to clear INT4FLG; if not. CPU clears INT4FLG on entry to level 4 interrupt routine. 6) Software reads RXBUF. 3.B.1.11 TX Signals in Serial If 0 Modes 1NT4 I FLG ----I 3-64 l Notes: 1 Format shown is eight data bits. 2) The SCLK source should be internal as it is gated by internal circuitry. Sequence of Events: 1) Software writes to TXBUF. 2) TXBUF data is transferred to TXSFT; INT4FLG and TXRDY are set, and SCLK starts. 3) Software resets TXEN, current frame will finish and transmission will halt whether rxBUF is full or empty. 4) Frame ends and SCLK stops because TXEN = O.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.2 Clock Sources and Serial Port Modes

The serial port can be driven by an internal (Timer 3) or external baud rate generator. The serial clock source, SCLK, is determined by the SCTL 1 clock _ bit (CLK) as either an input or an output. If an external clock source is se- lected, then the A6/SCLK pin (TMS70x2 devices) or A4/SCLK pin (TMS70Cx2 devices) is a high-impedance input. If an internal clock source is selected, then a 50% duty cycle clock signal is output on the low-impedance SCLK pin. The clock output frequency depends on the crystal frequency. The current logic level of SCLK (internal or external) can be determined by reading SCLK. RX receives data on the rising SCLK edges and TX transmits data on the falling SCLK edges. RX/TX (receiver/transmitter) has three modes: two communication modes - Asynchronous and Isosynchronous - and Serial I/O. Serial I/O Mode links the serial port to shift registers for simple I/O expansion. The Isosynchronous and Asynchronous communication modes link to other synchronous and asyn­ chronous devices. These two modes also have extra features for two forms of multiprocessor communication, Motorola and Intel. In all modes, I/O is NRZ (non-return to zero) format; that is, data value 1 = high level, and data value 0 = low level.

3.8.2.7 Asynchronous Communication Mode

In Asynchronous communication mode, the frame format consists of a start bit, five to eight data bits, an even/odd/no parity bit, and one or two stop bits. The bit period is eight times the SCLK period. Receiving a valid start bit initiates RX operation. A valid start bit consists of a negative edge followed by three samples, two of which must be zero. If two of the three samples are not zero, then the receiver continues to search for a Start bit. These samples occur three, four, and five SCLK periods after the negative edge. This sequence provides false start bit rejection and also locates the center of bits in the frame where the bits will be read on a majority (two out of three) basis. Figure 3-35 illustrates the asynchronous communication format. with a start bit showing how edges are found and majority vote taken. SCLl< TXD RXD FAlLINB EDGE DETECTED "MAJORI1Y VOTE" TAICEN 12laL1se 7 8 1 2 8 Figure 3-35. Asynchronous Communication Format Since RX synchronizes itself to frames, the external transmitting and receiving devices do not have to use the same SCLK; it may be fjenerated locally. If the internal SCLK is used it is output continuously on pm A6/SCLK (TMS70x2 devices) or A4/SCLK (TMS70Cx2 devices). 3-65

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.2.2 Isosynchronous Communication Mode

Isosynchronous communication mode is a hybrid protocol, combining features of the Asynchronous mode and the Serial I/O mode. The Isosynchronous frame format is the same as the Asynchronous mode frame format, consisting of a start bit, five to eight data bits, an even/odd/no parity bit, and one or two stop bits. However,it uses only one serial clock (SCLK) cycle per data bit as compared to 8 SCLKs per data bit for Asynchronous mode. This allows much faster transmission rates than Asynchronous mode. The bit period equals the SCLK period, as it does in Serial I/O mode. Bits are read on a single value basis. Since the RX does not synchronize itself to the data bits, the transmitter and receiver must be supplied with a common SCLK. The benefit of the Iso­ synchronous mode is that the frame format can be configured like the Asyn­ chronous mode, yet the baud rate is that of the Serial I/O mode. Receiving a valid start bit, which consists of a negative edge, initiates RX op­ eration. Since RX does not synchronize itself to data bits, the transmitter and receiver must be supplied with a common SCLK. If the internal SCLK is used it is output continuously on pin A6/SCLK/EC2 (TMS70x2 devices) or A4/SCLK (TMS70Cx2 devices). Figure 3-36 illustrates the Isosynchronous communication format, with a complete frame consisting of a start bit, six data bits, even parity, and two stop bits. seu< TXD RXD FAI..l.INQ EDGE INDICATES START BIT Figure 3-36. Isosynchronous Communication Format In both the Asynchronous and Isosynchronous Communication modes, when a frame is fully received, RXBUF is loaded from RXSHF, RXRDY. and INT4 flag are set to 1, and the error status bits are set accordingly. RXRDY is reset to 0 when the CPU reads RXBUF. Transmission is initiated after the CPU writes to TXBUF. This sets TXE to O. TXSHF is loaded from TXBUF, setting TXRDY and INT4 flag to 1. After completing the transmission, TXSHF reloads if TXBUF is full; if not, TX idles and TXE is 1 until TXBUF is written to. Bit 3 of Port 3 must be set to a 1 to enable data transmission through the B3/TXD pin.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.2.3 Serial I/O Mode

In Serial I/O mode, the frame format is five to eight data bits and one stop bit, _ with no corresponding clock cycle for the stop bit. An external or internal synchronizing clock signal must be supplied from either the internal Timer 3 or an external clock. An external clock must be supplied if the external SCLK option is used. The bit period is equal to the SCLK period. TX operation is initiated by writing to TXBUF when TXRDY equals 1. RX operation is initiated by writing a 1 to the RXEN bit. When the receiver has received a full frame, the RXEN bit is automatically cleared, disabling the receiver. The transmitter starts operating when the TX enable bit (TXEN) is set to 1. Data is written to TXBUF when TXRDY equals 1. Unlike the receiver, the TXEN bit is not au­ tomatically cleared when the transmitter finishes a full frame. To start the receiver and transmitter at the same time, first write the transmitter data to TXBUF and then set both RXEN and TXEN in one instruction. Be careful that the enable bits are not set when Timer 3 rolls over past O. This can be done by adjusting the timer rate before the bits are enabled and then setting the timer to the correct rate after enabling. Figure 3-37 illustrates the serial I/O format for two back-to-back frames, each containing five data bits. INTERNALlY GENERATED SCLK TXD RXD SCLK ACTIVE AND DATA BEING TRANSMITTED OR RECEIVED 1 1 111 1 1 111 i T T T T SCLl< a: TXD INACTIVE AND HIGH Figure 3-37. Serial I/O Communication Format An internal SCLK source will be output on pin A6/SCLK (TMS70x2 devices) or A4/SCLK (TMS70Cx2 devices). In Serial I/O mode, SCLK is only active when data is being transmitted or received; otherwise, SCLK has a value of one. 3-67

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) 3.B.3 Multiprocessor Communication 3-68 When the serial port is in either the Asynchronous or Isosynchronous com­ munications mode, the multiprocessor communication formats are available. These formats efficiently transfer information between many microcomputers on the same serial link. Information is transferred as a block of frames from a particular source to some destination(s). The serial port has features to iden­ tify the start of a block of data, and suppress interrupts and status information from RX until a block start is identified. In both multiprocessor modes the sequence is: 1 ) The serial port wakes up at the start of a block and reads the first frame (containing the destination address). 2) A software routine is entered through either an interrupt or polling rou­ tine and checks the incoming data byte against its address byte stored in memory. 3) If the block is addressed to the microcomputer the CPU reads the rest of the block; if not, the software routine puts the serial port to sleep again and therefore will not receive serial port interrupts until the next block start. On the serial link, all processors set their SLEEP bit to 1 so that they will only be interrupted when the address bit in the data stream is a 1. When the pro­ cessors receive the address of the current block, they compare it to their own addresses and those processors which are addressed set their SLEEP bit to a 0, so that they will read the rest of the block. . Although RX still operates when the SLEEP bit is 1, it will not set RXRDY, INT4 flag, or the error status bits to 1 unless the address bit in the received frame is a 1. The RX does not alter the SLEEP bit; this must be done in soft­ ware. To provide more flexibility, the serial port implements two multiprocessor protocols, one supported by Motorola and the other by Intel. The Motorola protocol is compatible with the Motorola MC6801 processor modes and the Intel protocol is compatible with the Intel protocol for the 8051. The multi­ processor mode is software selectable via the MULTI bit in the SMODE reg­ ister (Figure 3-28). Both formats use the WU and SLEEP flags to control the TX and RX features of these modes. Because the Intel multiprocessor mode contains an extra address/data bit, it is not as efficient as the Motorola mode in handling blocks containing more than 10 bytes of data. The Intel mode is more efficient in handling many small blocks. of data because it does not have to wait between blocks of data as does the Motorola mode.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.3.7 Motorola (MC6807) Protocol

In this protocol, blocks are separated by having a longer idle time between the _ blocks than between frames in the blocks. An idle time of 10 or more bits after a frame indicates the start of a new block. The processor wakes up (serial port resets the SLEEP bit to 0) after the block start signal. The processor now recognizes the next serial port interrupt. The service routine then receives the address sent out by the transmitter and com­ pares this address to its own. If the CPU is addressed, the service routine does not set the SLEEP bit, and receives the rest of the block. If the CPU is not addressed, the service routine sets the SLEEP bit (in software) to a 1. This lets the CPU continue to execute its main program without being interrupted by the serial port. The serial port sets the SLEEP bit to 0 whenever it detects a block start signal. There are two ways to send a block start signal. 1) The first is to deliberately leave an idle time of 10 bits or more by delay­ ing the time between the transmission of the last frame of data in the previous block and the address frame of the new block. 2) In the second method, the serial port implements a more efficient method of sending a block start signal. Using the Wake-Up (WU) bit, an idle time of exactly one frame (timed by the serial port) can be sent. The serial communications line is therefore not idle any longer than ne­ cessary. Associated with the WU bit is the wake-up temporary (WUT) flag. WUT is an internal flag, double buffered with WU. When TXSHF is loaded from TXBUF, WUT is loaded from WU, and WU is reset to O. This arrangement is shown in Figure 3-38. Figure 3-38. Double-Buffered WUT and TXSHF 3-69

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) 3-70 Sending out a block start signal of exactly one frame time is accomplished as follows: 1 ) Write a 1 to the WU bit. 2) Write a data word (don't care) to TXBUF. 3) When TXSHF is free again, TXBUF's contents are shifted to TXSHF, and the WU value is shifted to WUT. 4) If WU was set to a 1, the start, data, and parity bits are suppressed and an idle period of one frame, timed by the serial port, is transmitted. 5) The next data word, shifted out of the serial port after the block start signal, is the second data word written to the TXBUF after writing a 1 to the WU bit. 6) The first data word written is suppressed while the block start signal is sent out, and ignored after that. Writing the first don't care data word to the TXBUF is necessary so the WU bit value can be shifted to WUT. After the don't-care data word is shifted to the TXSHF, the TXBUF (and WU if necessary) may be written to again, since WUT and TXSHF are both double-buffered. Although RX still operates when the SLEEP bit is 1, it will not set RXRDY, INT4 flag, or the error status bits to 1. The RX will set the SLEEP bit to 0 if it times an appropriate 10-bit idle time on RXD. The Motorola multiprocessor communication format is shown in Figure 3-39. RXD/TXD b Ll LJ LltL....l LJ LltLl Llj IJLE PEROOEI OF 10 BITS OR MORE RXD/TXD -.m EXPANDED FIRST FRAME wmtIN BLOCK IS ADDRESS. IT FOLLOWS IDLE PERIOD OF 10 BITS OR MORE FRAME WITHIN BLOCK 1st' MfA lIP IDLE PERIOD LESS THAN 10 BITS Figure 3-39. Motorola Multiprocessor Communication Format

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.3.2 Intel (18051) Protocol

In the Intel protocol, the frame has an extra bit called an address bit just before _ the parity bit. Blocks are distinguished by the first frame(s) in the block with the address bit set to 1, and all other frames with the address bit set to O. The idle period timing is irrelevant. The WU bit sets the address bit. In TX, when the TXBUF and WU are loaded into TXSHF and WUT, WU is reset to 0 and WUT is the value of the address bit of the current frame. Thus, to send an address, set the WU bit to a 1, and write the appropriate address value to the TXBUF. When this address value is transferred to TXSHF and shifted out, its address bit is sent as a 1, which flags the other processors on the serial link to read the address. Since TXSHF and WUT are both double-buffered, TXBUF and WU may be written to im­ mediately after TXSHF and WUT are loaded. To transmit non-address frames in the block, the WU bit must be left at O. On the TMS70Cx2 devices, the received address bit is also placed in the SSTAT IADD bit. RRST ~ WIllftN ~TA BIT T BLOCK 18 ADDRESS. 18 0 FOR FRAME THE ADDR/DATA BIT WITHIN BLOCK. I8t IDLE TIME 18 OF NO SIGNIFICANCE Figure 3-40. Intel Multiprocessor Communication Format 3-71

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.4 Serial Port Initialization

The serial port must be initialized before it can be used; then it may be oper­ ated by simply reading and writing to Peripheral-File registers. A good pro­ gramming practice is not to assume that any registers have particular values at power-up or reset. A program should write to every value or register that might affect the serial port. Initialize the serial port as follows:

• TMS70X2 1) Set 83 data value to 1. This allows the TXD line to transmit. 2) Write to the SMODE register (P17). This sets the character format and the type of communication mode. 3) Write to the SCTlO register (second write to P17) to set the UR bit to O. This same write can also enable the transmitter, receiver, or both. 4) Load the Timer 3 reload register value (P20). 5) Write to SCTl1 (P21) to initialize Timer 3, the clock source, and multiprocessor mode. Once the serial port is initialized it can be operated continuously in the selected operational mode. To send data, simply write to the transmit buffers (P23), making sure that the transmitter is enabled (P17). Take input data from the receive buffer (P22) with the receiver enabled (P17). If the mode must be changed, the serial port must be reset and then re­ initialized for the desired mode. The serial port can be reset in two ways: hardware reset (via the RESET pin) or software reset (via the UR bit in SCTLO).
• TMS70Cx2 1) Set B3 data value to 1. This allows the TXD line to transmit. 2) Write to the SMODE register (P20). This sets the character format and the type of communication mode. 3) Write to the SCTLO register (P21). Enable the receiver or the transmitter or both. The UR bit must be set to O. 4) Load the Timer 3 reload register value (P23). 5) Write to SCTl1 register (P24) to initialize Timer 3, the clock source, and multiprocessor mode, if desired. Once the serial port is initialized it can be operated continuously in the selected operational mode. To send data, simply write to the transmit buffers (P26), making sure that the transmitter is enabled (P21). Take input data from the receive buffer (P25) with the receiver enabled (P21). If the mode must be changed, the serial port must be reset and then re­ initialized for the desired mode. The serial port can be reset in three ways: hardware reset (via the RESET pin) or software reset (via the UR bit in SCTlO), or by writing to the SMODE register.

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.5 Timer 3

Timer 3, illustrated in Figure 3-41 and Figure 3-42, can be used as a stand­ alone timer or as the internal baud-rate generator on TMS70x2 and TMS70Cx2 devices. r----~ .. t__EJ_ f08C ~--~~--~ I SCTLU (T3RUN) SeTL1.B (ClK) I I RELOAD PULSE I r+-+ AS l°:-J . ,11>----+-SERIAL PORT SET T3FlG, SCTL 1.3 .1--SET INTERRUPT 4 FLAG (iOCNT1.1) SCTL1.2_J oo (T3ENB) Figure 3-41. 8-Bit Timer 3 (TMS70x2) ~--~~--~ I SCTLU (T3RUN) UNDERFLOW SCTLO.1_, (SClKEN) 100 (ClK) I SCTL1.Br-1 A4 10 0 ,10 • SERIAL PORT SET T3FLG, SCTL 1.3 .1-SET INTERRUPT 4 FLAG (lOCNT1.1) SCTl1.2_J oO (T3ENB) Figure 3-42. 16-Bit Timer 3 (TMS70Cx2) 3-73

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) Timer 3 is accessed through T3DATA (similar to T1 DATA and T2DATA on the TMS70x2 devices) and SCTl1 (shared with RX/TX functions). The clock source for Timer 3 is internal only, and has a period of 2 )( tc(C). Timer 3 is a free running clock and is updated with new timer reload values when the prescaler and decrementer pass through zero together. Timer 3 is stopped and started by bit 7 in SCTL 1. Timer 3 consists of a 2-bit prescaler (SCTl1 bits 1 and 0) and an 8-bit de­ crementer (register T3DATA). When they decrement through zero, both the prescaler and the decrementer are reloaded from the 2-bit and 8-bit reload registers, respectively. The Timer 3 output goes to the serial port via a +2 circuit, producing an in­ ternal equal mark-space ratio SClK. The baud rate generated by Timer 3 is user-programmable and is determined by the value of the 2-bit prescaler and the 8-bit timer reload register. The equations for determining the baud rates for both the Asynchronous and Isosynchronous modes are: Asynchronous baud rate, TMS70x2 and TMS70Cx2 only: Isosynchronous and Serial I/O baud rate, TMS70x2 and TMS70Cx2 only: where: ' tc(C) = 2/fosc PR = Timer 3 prescale reload register value TR Timer 3 reload register value For example, to program the serial port to operate at 300 baud in Asynchro­ nous mode (with fosc= 8 MHz), the prescaler value is set to 3 and the reload register value is set to 103 decimal, or >67. Other prescaler and timer values for common baud rates are shown in Table 3-17. Table 3-17. Timer Values for Common Baud Rates - TMS70x2 and TMS70Cx2 BAUD 3.579454 MHz 4.9152 MHz 7.158908 MHz 8MHz RATE PS,T ERROR PS,T ERROR PS,T ERROR PS,T ERROR Note: PS = prescaler; T' = timer 3-74

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2) The Timer 3 output always sets T3FLG to 1. and sets INT4 flag to 1 if T3ENB is a 1 when the timer and prescaler decrement through O. This allows Timer 3 to be used as a utility timer if it is not used by the serial port. Timer 3 and its flags are not affected by the serial port software reset. UR. allowing Timer _ 3 to be used independently of the serial port.

3.8.6 Initialization Examples

This section contains four examples that initialize the serial port. In each case the data is moved to and from the buffers in the interrupt routines.

• The first example shows a typical RS-232 application that connects to a terminal.
• The second demonstrates a system using the Serial I/O mode to connect to a shift register.
• The third example uses the baud-rate timer as an additional third timer when the serial port is not used.
• The last example illustrates use of the Intel mode in a multiprocessor application. In all examples. assume the register mnemonics have been equated (EQU) with the corresponding Peripheral-File location.

3.8.6.7 RS-232-C Example

• * * * This example transmits and receives data from a standard RS-232-C-type terminal at 9600 baud with a data format of 7 data bits. 2 stop bits and no parity. DINT ORP MOVP MOVP MOVP MOVP MOVP MOVP MOVP EINT %?OOOOlOOO,PORTB %?00001011,IOCNT1 %0,P17 %?00010000,SCTLO %?11001010,SMODE %?00010101,SCTLO %7,T3DATA %?OlOOOOOO,SCTLl Precaution Enable TX pin Enable INT4 Point to SCTLO Reset the UART Two stop, 7 data bits, no parity, no extra Intel mode bit, communications mode Clear RESET, clear error flags, enable TX and RX Set baud rate to 9600 (4.9152 MHz crystal) Internal clock, prescale=O, no multiprocessing, disable Timer 3 interrupt, start Timer 3 3-75

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.6.2 Serial I/O Example

This routine sends and receives data from a shift register device at 1200 baud with 8 data bits and no parity. SERIAL DINT ORP MOVP MOVP MOVP MOVP * * * MOVP MOVP MOVP EINT %?00001000,PORTB %?00001011,IOCNT1 %O,P17 %?00010000,SCTLO %?OOOOl100,SMODE %?00010101,SCTLO %64,T3DATA %?11000000,SCTL1

3.8.6.3 Extra Timer with No Serial Port

One stop, 8 data bits, no parity, no extra Intel mode bit, Serial I/O mode Clear RESET, clear error flags, enable TX and RX Set baud rate to 1200 (SMHz crystal) Internal clock, prescale=O, no multiprocessing, disable Timer 3 interrupt, start Timer 3 Timer 3 can be used as an additional timer when the serial port is not needed. INT4 occurs whenever the timer passes O. The timer period is determined by the value TIME and the prescale bit in SCTL1. Disable the transmitter and receiver to assure no interrupts come from that source. This timer works best as a periodic interrupt, allowing a task to be performed at a fixed interval. TIMER3 * * * 3-76 DINT MOVP MOVP MOVP MOVP MOVP MOVP MOVP EINT %?OOOOlOll,IOCNTI %O,P17 %?00010000,SCTLO %?01000010,SMODE %?00010000,SCTLO %TIME,T3DATA %?110001XX,SCTL1 Precaution Enable INT4 Point to SCTLO Reset the UART Asynchronous communication mode Clear RESET, clear error flags, disable TX and RX Set timer to selected rate Internal clock, no multiprocessing selected prescale, enable Timer 3 interrupts, start Timer 3

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.6.4 Intel Multiprocessor Example

This example illustrates basic concepts of sending and receiving data in a _ multiprocessor system. The processors are usually close to each other so they can send at maximum speed without problems. The data is sent and received MULTI * * * during the interrupt routines. DINT ORP MOVP MOVP MOVP MOVP MOVP MOVP MOVP EINT %?OOOOlOOO,PORTB %?OOOOlOll,IOCNTl %O,P17 %?OOOlOOOO,SCTLO %?Ol111111, SMODE %?OOOlOlOl,SCTLO %O,T3DATA %?11100000,SCTLl Precaution Enable TX pin (?=binary) Enable INT4 Point to SCTLO Reset the UART One stop, 8 data bits, odd parity, Intel mode bit, communications mode Clear RESET, clear error flags, enable TX and RX Set baud rate to full speed (5MHz crystal) Internal clock, prescale=O, no multiprocessing, disable Timer 3 interrupts, put receiver to sleep, start Timer 3 * Meanwhile, back at the interrupt routines * SENDIT ORP %BIT4,SCTLl * * * * GETIT * * MOVP %ADDRS,TXBUF ANDP %#BIT4,SCTLl MOVP %DATA,TXBUF MOVP RXBUF,A CMP %ADDRS , A JNE NOTIT ANDP %#BIT5,SCTLl Send Wake-Up bit (Bit4=OOOlOOOO) Send address byte wait for the transmit complete interrupt Clear Wake-Up bit (# = logical NOT) start sending data bytes Get address byte (it only interrupts on an address byte when sleeping) Is it this processor's address? If this is not the correct address ignore the rest of the following data bytes Clear Sleep bit and wait for additional data bytes Some method should determine End of Data so that the pro­ cessor can go back to sleep Byte count in first data byte or special end of data byte are two methods 3-77

TMS7000 Family Architecture - Serial Port (TMS70x2 and TMS70Cx2)

3.8.7 Serial Port Interrupts

INT4 is dedicated to the serial port. Three sources can generate an interrupt through INT4: 1) The transmitter (TX), 2) The receiver (RX), and 3) Timer 3 (T3). Setting TXEN to 1 allows data loaded into the TXBUF to be shifted into TXSHF. The TX sets TXRDY and INT4 flag to 1 when TXSHF is loaded from TXBUF. In the communication modes, if RXEN is set to 1, RX sets RXRDY and INT4 flag to a 1 when RXBUF is loaded from RXSHF. If RXEN is 0, RXSHF still receives frames and shifts them into RXBUF, but RXRDY and INT4 flag are held to O. If a character is in RXBUF, and RXEN is then set to a 1, RXRDY and INT4 flag will be set to 1. ' In Serial 110 mode, RXEN is set to initiate the reception of a frame. When the last bit of the frame is received RXEN is reset to 0; however, RXRDY and INT4 flag are still set to 1 when the character is shifted from RXSHF to RXBUF. RXRDY and INT4 flag bits are not masked by RXEN. Timer 3 sets T3FLG and INT4 flag (if T3ENB is 1) when its prescaler and timer decrement through 0 together. When the CPU acknowledges INT4, RXRDY, TXRDY, and T3FLG are the flags that indicate its source. The INT4 service routine must determine which of these sources caused INT4 in the specific application. For example, if all three are likely sources, the INT4 service routine must check for the following pos­ sible situations: 1) RXRDYonly 2) TXRDY only 3) T3 only 4) RXRDY,TXRDY,T3 5} RXRDY, TXRDY 6} RXRDY, T3 7} TXRDY, T3 8} None The last che,ck is necessary because RXRDY, TXRDY, or T3FLG can set INT4 flag. It is possible that one or more interrupts may occur between CPU ac­ knowledgement of INT4 and INT4 service routine testing o~ RXRDY, TXRDY, and T3FLG. The CPU clears the INT4 flag bit when it acknowledges INT4. If a second INT4 source is set in the time between this clearing and the soft­ ware testing, the second or third interrupts will be serviced by the current INT4 service routine. Thus, when INT4 is again acknowledged (INT4 flag was set again by the second interrupt) RXRDY, TXRDY, and T3FLG will all be set to

, ,1 Electrical Specifications

This section contains electrical and timing information for each category of TMS7000 family devices. The NMOS devices are presented first, followed by the CMOS devices. All TMS7000 CMOS devices with the exception of the TMS70CTxO devices can operate at wide voltage and frequency ranges; therefore, the CMOS specifications are presented using two separate test vol­ tage ranges. NMOS Devices: Section Page CMOS Devices: Section Page

4.5 TMS70COOA, TMS70C20A, and TMS70C40A Specifications

4.6 TMS70COOA, TMS70C20A, and TMS70C40A Specifications

4.1 TMS7000, TMS7020, and TMS7040 Specifications

Table 4-1. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted, all voltages are with respect to VSS' Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Rec.ommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 4-2. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 4.5 5 5.5 V ClKIN 2.6 V High-level input voltage All others 2.0 V ClKIN 0.6 V low-level input voltage All others 0.8 V Operating free-air temperature 0 70 ·C

Table 4-3. Electrical Characteristics over Full Range of Operating Conditions PARAMETER TEST CONDITIONS MIN Typt MAX UNIT II I I Port A, input-only pins V I = VSS toV ee ±2 ±10 IJA nput current I VI = 0.4 V to Vee ±10 ±100 IJA 110 pins CI Input capacitance 2 pF VOH High-level output voltage IOH = -400 IJA 2.4 2.8 V VOL Low-level output voltage IOL = 3.2 mA 0.2 0.4 V trW) Output rise time+ See Figure 4-1 9 50 ns tHOl Output fall time+ See Figure 4-1 10 60 ns lee Supply current All outputs open 80 150 mA poeav) Average power dissipation All outputs open 400 825 mW t All tYPical values are at Vee = 5 V, TA = 25"C. + Rise and fall times are measured between the maximum low level and the minimum high level using the 10% and 90% points (see Figure 4-2). Measured outputs have 100-pF loads to VSS' LOAD VOLTAGE 6800 Vo 100pF Figure 4-1. Output Loading Circuit for Test 0UTPIJT8 UV ~

004 V ----VOLCMAlO

Figure 4-2. Measurement Points for Switching Characteristics 4-3

Table 4-4. Recommended Crystal Operating Conditions over Full Operating Range PARAMETER MIN TYP MAX fose Crystal frequency 1.0 5.0 ClKI N duty cycle 50 terPI Crystal cycle time:!: 200 1000 tercI Internal state cycle time 400 2000 tw(PHl elKIN pulse duration high 90 tw{PLl ClKIN pulse duration low 90 tr ClKIN rise timet 30 tf ClKIN fall timet 30 td(PH-CHl ClKIN rise to ClKOUT rise delay 125 200 t Rise and fall times are measured between the maximum low level and the minimum high level. :I: See Section 3.4 for Recommended Clock Connections. XTAL2ICLJ<IN CLKOUT Figure 4-3. Clock Timing 4-4 UNIT MHz ns ns ns ns ns ns ns

Table 4-5. Memory Interface Timing at 5 MHz over Full Operating Free-Air Temperature Range PARAMETER MIN TYP MAX te(C) CLKOUT cycle timet 400 twCCH) CLKOUT high pulse duration 130 170 200 twCCl) CLKOUT low pulse duration 150 190 240 tdCCH-Jl) Delay time. CLKOUT rising to ALATCH fall 260 300 340 tw(JH) ALATCH high pulse duration 150 190 230 tsu(HA-Jl) Setup time. high address valid before ALATCH fall 50 170 220 tsuClA-JLl Setup time. low address valid before ALATCH fall 50 150 220 thlJl-LAI Hold time. low address valid after ALATCH fall 30 45 80 tsu(RW-Jl) Setup time. R/W valid before ALATCH fall 50 140 200 thCEH-RW) Hold time. R/W valid after mAm rise 40 100 thCEH-HA) Hold time. high address valid after ENABLE rise 30 40 tsu(O-EH) Setup time. data output valid before ENABLE rise 230 290 th(EH-O) Hold time. data output valid after ENABLE rise 65 80 tdIEH-A) Delay time. 'Ei'ilABI'E rise to next address drive 60 85 taCEl-O) Access time. data input valid after 'Ei'ilABI'E fall 155 190 ta(A-O) Access time. address valid to data input valid 400 470 tdIA-EH) Delay time. address valid to ENABLE rise 580 730 thCEH-O) Hold time. data input valid after ENABLE rise 0 tdICH-ELl Delay time. CLKOUT rise to ENABLE fall -10 15 50 t te(C) IS defined to be 2/fosc and may be referred to as a machine state or Simply a state. :j: See Section 3.4 for Recommended Clock Connections. UNIT ns ns ns lis ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4-5

exTERNAL READ EXTERNAL WRITE rtcIC)~ N-.I-tw(CH~ I I IL-----lL t I I I ~fw(CL) rlO)tl t: ~tf(qj RAM READ: INTERNAL READ . I I I CLKOUT: I I I I -JLl I : -tI !f-tW(JH)1 ! : ~ r-t 8U(~-JLI It+--* thIEH-HAl HIGH AOORESS 100-07) LOW ADORESSI DATA ICO-C7) I I YtsUIQ-EH) I I I I I I I Figure 4-4. Read and Write Cycle Timing

4.1.1 Application of Ceramic Resonator

The circuit shown in Figure 4-5 provides an economical alternative to quartz crystals where frequency tolerance is not a major concern. Frequency toler­ ance over temperature is about 1 %. TM870x0 XTAl1 XTAl2 Figure 4-5. Ceramic Resonator Circuit The following manufacturers supply ceramic resonators. Murata Corporation of America 2200 Lake Park Dr. Smyrna, GA 30080 (404) 436-1300 Telex - 4363030 Kyocera International 8611 Balboa Ave. San Diego, CA 92123 (714) 279-8319 Telex - 697929 For 5 M Hz operation Resonator ceralock CSA5.00MT Resistor 1 MO 10% Capacitors (both) 30 pF 4-7

4.2 TMS7002 and TMS7042 Specifications

Table 4-6. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted. all voltages are with respect to VSS' Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 4-7. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 4.5 5 5.5 V High-level input voltage ClKIN 2.6 V All other inputs 2.0 V low-level input voltage ClKIN 0.6 V All other inputs 0.8 V Operating free-air temperature 0 70 ·C

Table 4-9. Recommended Crystal Operating Conditions over Full Operating Range PARAMETER MIN TYP MAX fosc Crystal frequency 1.0 8.0 ClKIN duty cycle 50 tC(PI Crystal cycle time:!: 125 1000 tc(C) Internal state cycle time 250 2000 tw(PH) ClKIN pulse duration high 50 tw(PLI ClKIN pulse duration low 50 tr ClKIN rise timet 30 tf ClKIN fall timet 30 td(PH-CH) ClKIN rise to ClKOUT rise delay 70 200 .. t Rise and fall times are measured between the maximum low level and the minimum high level. :I: See Section 3.4 for Recommended Clock Connections. XTAI..2/CLKIN CLKOUT Figure 4-8. Clock Timing 4-10 UNIT MHz ns ns ns ns ns ns ns

Table 4-10. Memory Interface Timing PARAMETER MIN MAX UNIT te(C) CLKOUT cycle timet 250 2000 ns twlCH\\ CLKOUT high pulse duration 0.5teIC\\-40 0.5t elC\\ +10 ns tw(CL) CLKOUT low pulse duration 0.5te(C)-40 0.5t etC) +15 ns td(CH-JL) Delay time. CLKOUT rise to ALATCH fall 0.5t e(C)-1 0 0.5te(C) +30 ns -twlJH) ALATCH high pulse duration 0.25teIC)-15 0.25t eCC)+30 ns I tsu(HA-JL) Setup time. high address valid before 0.25t e(C)-40 0.25tc(C) +45 ns ALATCH fall tsu(LA-JL) Setup time. low address valid before 0.25t c(C)-40 0.25tc(C) +15 ns ALATCH fall th(JL-LA) Hold time. low address valid after 0.25t e(C) 0.25te(C) +45 ns ALATCH fall tsu(RW-JL) Setup time. R/W valid before ALATCH 0.25t e(C)-35 0.25tc(C) +30 ns fall thCEH-RW\\ Hold time. R/W valid after ENABLE rise 0.5t eCC\\-40 ns th(EH-HA) Hold time. high address valid after 0.5t c(C)-50 ns mAmrise tsu(O-EH) S~lUK tire. data output valid before 0.5t c(C)-45 ns E A L rise th(EH-O) Hold time. data output valid after 0.5t c(C)-45 ns ENABLE rise td(LA-EL) Delay tiSC low address high impedance 0.25t e(C)-45 0.25tc(C) ns to ENA E fall td(EH-A) Delay time. 'ENABIT rise to next address 0.5t e(C)-25 ns drive ta(EL-O) Access time. data input valid after 0.75te(C)-105 ns 'Elii'A'EiIT fall ta(A-O) Access time. address valid to data input 1.5t e(CV115 ns valid tdCA-EH) Delay time. address valid to mAm rise 1.5t cIC)-SO 1.5tcCC\\ +30 ns th(EH-O) Hold time. data input valid after 'ENABIT 0 ns rise tdCEH-JH) Delay time. ENABLE rise to ALATCH rise 0.5t eCC)-25 0.5tcCC)+10 ns tdICH-EL\\ Delay time. CLKOUT rise to mAm fall -10 35 ns t te(C) IS defined to be 2/fosc and may be referred to as a machine state or simply a state. 4-11

Table 4-11. Memory Interface Timing at 8 MHz TEST PARAMETER CONDITIONS MIN TYP MAX UNIT te(C) CLKOUT cycle timet 250 ns tw(CH) CLKOUT high pulse duration 85 110 135 ns tw(CL) CLKOUT low pulse duration 85 115 140 ns td(CH.JL) Delay time. CLKOUT rise to ALATCH 115 135 155 ns fall tw(JH) ALATCH high pulse duration 47 70 92 ns tsu(HA-JL) Setup time. high address valid before 22 65 108 ns ALATCH fall tsu(LA-JL) Setup time. low address valid before 22 50 78 ns ALATCH fall th(JL-LA) Hold time. low address valid after 62 90 108 ns ALATCH fall tsu(RW-JL) Setup time. R/W valid before ALATCH 27 60 93 ns fall th(EH-RW) Hold time. R/W valid after ENABLE rise 85 120 ns th(EH-HA) Hold time. high address valid after 75 120 ns ENAB'IT rise tsu(Q-EH) SNtuP time. data output valid before 80 120 ns E ABLE rise f = 8 MHz. th(EH-Q) Hold time. data output valid after 50% duty cycle 80 115 ns ENAB'IT rise td(LA-EL) Delay time. low address high impedancE to ENABLE fall 17 40 62 ns td(EH-A) Delay time. ENABLE rise to next address 100 150 ns drive ta(EL-D) Access time. data input valid after 82 120 ns ENAB'IT fall ta(A-D) Access time. address valid to data input 260 300 ns valid td(A-EH) Delay time. address valid to "E"filA"If[E 295 350 405 ns rise th(EH-D) Hold time. data input valid after 0 ns "E"filA"If[E rise td(EH-JH) Delay time. ENABLE rise to ALATCH 100 105 135 ns rise td(CH-EL) Delay time. CLKOUT rise to ENABIE -10 25 35 ns fall t te(C) IS defined to be 2/fosc and may be referred to as a machine state or simply a state. 4-12

(00-07) EXTERNAL WRITE I RAM READ I I Figure 4-9. Read and Write Cycle Timing INTERNAl.. READ 4-13

4.2.1 Application of Ceramic Resonator

The circuit shown in Figure 4-10 provides an economical alternative to quartz crystals where frequency tolerance is not a major concern. Frequency toler­ ance over temperature is about 1 %. TM870X2 XTAl..1 XTAL2 Figure 4-10. Ceramic Resonator Circuit The following manufacturers supply ceramic resonators. Murata Corporation of America 2200 Lake Park Dr. Smyrna, GA 30080 (404) 436-1300 Telex - 4363030 Kyocera International 8611 Balboa Ave. San Diego, CA 92123 (714) 279-8319 Telex - 697929 For 5 M Hz operation Resonator cera lock CSA5.00MT Resistor 1 Mn 10% Capacitors (both) 30 pF

4.2.2 Serial Port Timing

4.2.2. 7 Internal Serial Clock ___ -.t--l~1+- td(CL-SU I SCLK II II --t! !-td(CL-TO) I RXD RXD SAMPLE SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = tc(C)' PARAMETER TYP tdtCL_SLl CLKOUT low to SCLK low 1/4 t"tCI tdICL-TDI CLKOUT low to new TXD data 1/4 tctC) tdtRD_Cl\\ RXD data valid before CLKOUT low 1/4 t "tCI tdtRDl RXD data valid time 1/2 tetCI

4.2.2.2 External Serial Clock

~d(CL-S) . ~.~td(CL-S) SCLK 1\\\\\\\\\\1--td(SE-TO) --' ,f//}" TXD RXD I 14 td(88-TO)--tI I td(RD-CU -.t I+- RXD 8AMPI..E SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = tclC)' 3) SCLK sampled; If SCLK = 1 then 0, fali transition found. 4) SCLK sampled; if SCLK = 0 then 1, rise transition found. PARAMETER TYP tdtRD-CLl RXD data valid before CLKOUT low 1/4 t "tCI tdlRDI RXD data valid time 1/2 tctC) tdt!':R_Tnl Start of SCLK sample to new TXD data 3 1/4 t dCI tdISE-TD) End of SCLK sample to new TXD data 21/4 t ctCI trltCI_!':1 Clockout low to SCLK transition t~IC) UNIT ns ns ns ns UNIT ns ns ns ns ns 4-15

4.3 TMS7742 Specifications

Table 4-12. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted, all voltages are with respect to VSS' Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 4-13. Recommended Operating Conditionst MIN NOM MAX UNIT Supply voltage 4.5 5 5.5 V Program supply voltage:!: 20.5 21 21.5 V ClKIN 2.6 V High-level input voltage All other inputs 2.0 V low-level. input voltage ClKIN 0.6 V All other inputs 0.8 V Operating free-air temperature 0 70 ·C t Ambient light may affect operational functionality and electrical characteristics. It is recommended to use an opaque label over the window when the EPROM is not being erased. :!: Vpp is applied to the MC pin in EPROM mode only. 4-16

Table 4"15. Recommended Crystal Operating Conditions over Full Operating Range PARAMETER MIN TYP MAX fosc Crystal frequency 1 5 ClKI N duty cycle 50 tc(Pl Crystal cycle time+ 200 1000 tc(C) Internal state cycle time 400 2000 tw(PHl ClKIN pulse duration high 90 tw(PLl ClKIN pulse duration low 90 tr ClKIN rise timet , 30 tf ClKIN fall timet 30 td(PH-CHl ClKI N rise to ClKOUT rise delay 120 200 t Rise and fall times are measured between the maximum low level and the minimum high level. + See Section 3.4 for Recommended Clock Connections. XTAI.2/CU<JN CLKOUT Figure 4-13. Clock Timing 4-18 UNIT MHz ns ns ns ns ns ns ns

Table 4-16. Memory Interface Timing PARAMETER MIN MAX UNIT tc(C) CLKOUT cycle timet 400 2000 ns tw(CH) CLKOUT high pulse duration 0.5tc(C)-40 0.5t c(C) + 10 ns tw(Cl) CLKOUT low pulse duration 0.5tc(C)-40 0.5t c(C) +15 ns td(CH-JLl Delay time, CLKOUT rise to ALATCH fall 0.5t e(C)-10 0.5teIC) +30 ns -tw(JH) ALATCH high pulse duration 0.25te(C)-15 0.25t c(C)+30 ns tsu(HA-JL) Setup time, high address valid before 0.25t c(C)-40 0.25tc(C) +45 ns ALATCH fall tsu(LA-JL) Setup time, low address valid before 0.25t c(C)-45 0.25tc(C) +15 ns ALATCH fall th(JL-LA) Hold time, low address valid after 0.25t e(C) 0.25tc(C) +45 ns ALATCH fall tsu(RW-JL) Setup time, R/W valid before ALATCH 0.25t c(C)-35 0.25tc(C) +30 ns fall th(EH-RW) Hold time, R/W valid after ENABLE rise 0.5t c(C)-40 ns th(EH-HA) Hold time, high address valid after 0.5t c(C)-50 ns ENABLE rise tsu(O-EH) Setup time, data output valid before 0.5t e(C)-45 ns ENABLE rise th(EH-O) Hold time, data output valid after 0.5t c(C)-45 ns ENABLE rise td(LA-EL) Delay time, low address high impedance to ENABLE fall 0.25t c(C)-45 0.25tc(C)+15 ns td(EH-A) Delay time, ENABLE rise to next address 0.5t c(C)-25 ns drive ta(EL-D) Access time, data input valid after 0.75t c(C)-135 ns ENABLE fall talA-D) Access time, address valid to data input 1.5tc(C)-160 ns valid td(A-EH) Delay time, address valid to ENABLE 1.5t e(C) -80 1.5tc(C)+30 ns rise th(EH-D) Hold time, data input valid after ENABLE 0 ns rise tdIEH-JH) Delay time, ENABLE rise to ALATCH rise 0.5t c(C) -70 0.5tc(C)+10 ns td(CH-ELl Delay time, CLKOUT rise to ENABLE fall -10 35 ns t te(C) IS defined to be 2/fosc and may may be referred to as a machine state or simply a state. 4-19

Table 4-17. Memory Interface Timing at 5 MHz TEST PARAMETER CONDITIONS MIN TYP MAX UNIT tc(Cl CLKOUT cycle timet 400 ns tw(CH) CLKOUT high pulse duration 160 185 210 ns tw(CL) CLKOUT low pulse duration 160 190 215 ns td(CH-JL) Delay time. CLKOUT rise to ALATCH 190 210 230 ns fall tw(JH) ALATCH high pulse duration 85 110 130 ns tsu(HA-JL) Setup time. high address valid before 60 100 145 ns ALATCH fall tsu(LA-JL) Setup time. low address valid before 55 90 125 ns ALATCH fall th(JL-LA) Hold time. low address valid after 100 125 145 ns ALATCH fall tsu(RW-JL) Setup time. R/W valid before ALATCH 65 95 130 ns fall th(EH-RW) Hold time. R/W valid after mAB'i:E rise 160 195 ns th(EH-HA) Hold time. high address valid after 150 195 ns mAB'i:E rise tsu(O-EH) Slilup time. data output valid before 155 185 ns E ABLE rise f = 5 MHz. th(EH-O) Hold time. data output valid after 50% duty cycle 155 180 ns EI'JA~[E rise td(LA-EL) De~~ tiBL~ low address high impedancE 55 85 115 ns to A fall td(EH-A) Delay time. mAB'i:E rise to next 175 205 ns address drive ta(EL-D) Access time. data input valid after 165 205 ns mAB'i:Efall ta(A-o) Access time. address valid to data input 440 485 ns valid td(A-EH) Delay time. address valid to mAB'i:E 520 575 630 ns rise th(EH.D) Hold time. data input valid after 0 ns EI'JA~[E rise td(EH-JH) Delay time. mA'IrrE rise to ALATCH 130 160 210 ns rise td(CH.EL) Delay time. CLKOUT rise to mAB'i:E ·10 25 35 ns fall t tc(C) IS defined to be 2/fosc and may be referred to as a machine state or Simply a state. 4·20

(00..07) RAM READ INTERNAL READ Figure 4-14. Read and Write Cycle Timing

4.3.1 Erasure

The TMS7742 is erased by exposing the chip to shortwave ultraviolet light that has a wavelength of 253.7 nanometers (2537 angstroms). The recom­ mended minimum exposure dose (UV intensity )( exposure time) is fifteen watt-seconds per square centimeter. The lamp should be located about 2.5 centimeters (1 inch) above the chip during erasure. After erasure, all bits are at a high level. Note that normal ambient light contains the correct wave­ length for erasure. Therefore, when using the TMS7742, the window should be covered with an opaque label. 4-21

Table 4-18. Switching Characteristics over Recommended Supply Voltage Range and Operating Free-Air Temperature Range TEST PARAMETER CONDITIONSt MIN talA) Access time from address CL = 100 pF. tenlG) Output enable time from G 1 Series 74 TTL load. tdisLGJ:1: Output disable time from G t r :S 20 ns tv(A) Output data valid time after change of addresl'. ~ or G. whichever occurs first t f :S 20 ns t Timing measurement reference levels for inputs and outputs are 0.8 V and 2 V. :I: Value calculated from 0.5 V delta to measured output level. MAX UNITS

1 IJs

Table 4-19. Recommended Conditions for Programming, TA = 25°C MIN NOM MAX UNITS twlE) ~ pulse duration 9 10 11 ms tsulA) Address setup time 2 IJS tsu(Ql Data setup time 2 IJS tsulVppl Vpp setup time 2 IJS theA) Address hold time 0 IJs thlDl Data hold time 2 IJS th(Vp!,) Vpp hold time 2 IJS trec(PG) Vpp recoliery time 2 IJS t,lpGIG G rise time during programming 50 ns tEHD Delay time, data valid after ~ flow 1 IJS Table 4-20. Programming Characteristics, TA = 25°C TEST PARAMETER CONDITIONSt MIN MAX UNITS tdis(pR) Output disable time 0 100 ns t Timing measurement reference levels for Inputs and outputs are 0.8 and 2.0 V. 4-22

4.3.2 Serial Port Timing

4.3.2.1 Internal Serial Clock

CLKOUT "LJL.rLI1. JlJl-Il- -tI t.-td(CL-8U I SCLl( ---+1'"""1 II -! ~ t(l(CL-TD) I RXD RXD 8AMPLE SAVBl Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = tc(C). PARAMETER TYP ttilel _!::L\\ CLKOUT low to SCLK low 1/4 tr.lel tdICL_TDl CLKOUT low to new TXD data 1/4 tr.{CI tdtRD-CL\\ RXD data valid before CLKOUT low 1/4 t c(C) t .. URDI RXD data valid time 1/2 tdCI 4.3.2.2 External Serial Clock. 4-24 Notes: SCLl( ~~ 1\\\\ \\\\~ td(8E-TD) -..I !..!!fII Ei<f(88-TD)---.l I CLKOUT RXD RXD SAMPLE SAVBl 2 CLKOUT = te{C}. 11 The CLKOUT signal is not available in Single-Chip mode. 3 SCLK sampled; If SCLK = 1 then 0, fall transition found. 4 SCLK sampled; if SCLK = 0 then 1, rise transition found. PARAMETER TYP ttiIRD_eL\\ RXD data valid before CLKOUT low 1/4 t dCI tdlRDl RXD data valid time 1/2 !eIC) ttil!::R,T~ Start of SCLK sample to new TXD data 31/4 t "Iel tdISE_TDl End of SCLK sample to new TXD data 21/4 t dC) tdICL.S) Clockout low to SCLK transition ' t "Iel UNIT ns ns ns ns UNIT ns ns ns ns ns

4.4 SE70P162 Specifications

Table 4-21. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted, all voltages are with respect to VSS. Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions indicated in the "Recommended Operating Conditions" section of this specification is not im­ plied. Exposure to absolute maximum rated conditions for ex­ tended periods may affect device reliability. Table 4-22. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 4.5 5 5.5 V High-level input voltage ClKIN 2.6 V All others 2.3 V low-level input voltage ClKIN 0.6 V All others 0.8 V Operating free-air temperature 0 55 'C 4-25

Table 4-24. Recommended Crystal/Clockin Operating Conditions over Full Operating Range PARAMETER MIN TYP MAX fosc Crystal frequency 1.0 8.0 ClKI N duty cycle 50 tcCPI Crystal cycle time:!: 125 1000 tcCCI Internal state cycle time 250 2000 twlPH) ClKIN pulse duration high 50 twCPL) ClKIN pulse duration low 50 tr ClKIN rise timet 30 tf ClKIN fall timet 30 tdlPH-CH) ClKIN rise to ClKOUT rise delay 125 200 .. t Rise and fall times are measured betwen the maximum low level and the minimum high level. * See Section 3.4 for Recommended Clock Connections. CLKOUT Figure 4-19. Clock Timing UNIT MHz ns ns ns ns ns ns ns 4-27

Table 4-25. Memory Interface Timing PARAMETER MIN MAX telC) CLKOUT cycle timet 250 2000 twlCHI CLKOUT high pulse duration 0.5teICI-40 0.5t elCI +1 0 tw(CL) CLKOUT low pulse duration 0.5tcIC)-40 0.5tcIC)+15 tdICH-JL) Delay time, CLKOUT rise to ALATCH fall 0.5t clC) -10 0.5tcIC) +30 twlJH) ALATCH high pulse duration 0.25tcICI-15 0.25t cIC)+30 tsu(HA-JL) Setup time, high address valid before 0.25t c(C)-40 0.25tc(C) +45 ALATCH fall tsu(LA-JL) Setup time, low address valid before 0.25t c(C)-40 0.25tc(C)+15 ALATCH fall th(JL-LA) Hold time, low address valid after 0.25t c(C) 0.25tc(C) +45 ALATCH fall tsu(RW-JL) Setup time, R/W valid before ALATCH 0.25t c(C)-35 0.25tc(C) +30 fall thIEH-RWI Hold time, R/W valid after ENABLE rise 0.5t c1CI-40 th(EH-HA) Hold time, high address valid after ENABLE rise 0.5t e(C)-50 tsu(Q-EH) Serx~lime, data output valid before EN E rise 0.5t e(C)-45 th(EH-Q) Hold time, data output valid after ENABLE rise 0.5t e(C)-45 td(LA-EL) Dela'Uime, low address high impedance to E ABLE fall 0.25t e(C)-45 0.25te(C) td(EH-A) Delay time, ENABLE rise to next address 0.5t c(C)-25 drive ta(EL-O) Access time, data input valid after "ENAIIT"E fall 0.75t e(C) -105 ta(A-O) Access time, address valid to data input 1.5tc(C)-115 valid tdIA-EH) Delay time, address valid to ENABLE rise 1.5t elC) -80 1.5tcIC) +30 th(EH-O) Hold time, data input valid after ENABLE 0 rise tdIEH-JH) Delay time, ENABLE rise to ALATCH rise 0.5t cIC)-25 0.5teIC) +10 tdICH-ELl Delay time, CLKOUT rise to fi\\J"Am fall -10 35 t te(C) is defined to be 2/fosc and may be referred to as a machine state or simply a state. Note: For memory interface timings at 8 MHz, see Table 4-11 on page 4-12. 4-28 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Figure 4-20. Read and Write Cycle Timings 4-29

4.4.1 Serial Port Timing

4.4.7.7 Internal Serial Clock

-.I M- td(CL-8U I 8CLK ---+1-;1 . Ii- -I !-lcI(CL-TD) I 14- RXD RXD SAMPLE SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = tc(C). PARAMETER TYP triICI_l::1 \\ CLKOUT low to SCLK low 1/4 tclC) td/CL_TDl CLKOUT low to new TXD data 1/4 tdC\\ tdlRD-CLl RXD data valid before CLKOUT low 1/4 t elC) trilRDl RXD data valid time 1/2 tdC\\

4.4.7.2 External Serial Clock

SCLK ~~ 1\\ \\\\\\~ td(SE-TDI-; !li!II nD RXD j..:=:: td(SB-TD) ---t! I RXD SAMPLE SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = tc{e). 3) SCLK sampled; If SCLK = 1 then O. fall transition found. 4) SCLK sampled; if SCLK = 0 then 1. rise transition found. PARAMETER TYP tdIRD_CLl RXD data valid before CLKOUT low 1/4 t elCl tdLRD) RXD data valid time 1/2 tclC) t,i/SB_TDI Start of SCLK sample to new TXD data 31/4 t dCl td/SE-TDl End of SCLK sample to new TXD data 2 1/4 t "IC) trlICL_l::l Clockout low to SCLK transition t dCl UNIT ns ns ns ns UNIT ns ns ns ns ns

(Wide Voltage) Vee VIH VIL TA Table 4-26. Absolute Maximum Rating over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted. all voltages are with respect to VSS. Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 4-27. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 2.5 6.0 V XTAL2 pin. 0.8V ee V Vee = 2.5 to 6 V High-level input voltage All other pins. 0.70Vee V Vee = 3 to 6 V All other pins. 0.75V ee V Vee = 2.5 to 3 V XTAL2 pin. 0.2V ee V Vee = 2.5 to 6 V Low-level input voltage All other pins. Vee = 2.5 to 6 V 0.3V ec V Commercial 0 70 'C Operating temperature (TMS70CxONL) range Industrial (TMS70CxONA) -40 85 'C 4-31

Table 4-28. Electrical Characteristics over Full Range of Operating Conditions PARAMETER TEST CONDITIONS MIN TYpt MAX UNIT II Input leakage current VIN = VSS to V ee ±0.10 ±5 IJA CI Input capacitance 5 pF Vee = 2.5 V, IOH = -50 IJA 2.25 2.4 V VOH High~level Vee = 4.0 V, IOH = -0.4 rnA 3.2 3.6 V output voltage:!: Vee = 5.0 V, IOH = -0.7 rnA 3.9 4.5 V Vee = 6.0 V, IOH = -1.0 rnA 4.6 5.4 V t Vee = 5 V. TA = 25°C :!: Output levels ensure 400 rnV of noise margin over specified input levels. 4-32

Table 4-29. Supply Current Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fosc = 6.0 MHz. Vee = 5 V 9.0 14.4 mA fosc = 3.0 MHz, Vee = 5 V 4.5 7.2 mA lee Operating mode fosc = 0.5 MHz. Vee = 5 V 0.8 1.2 mA fosc = Z MHz, Vee = 5 V 1.5 2.4 mA/MHz fosc = 0.5 MHz, Vee = 2.5 V 370 800 IJA fosc = 6.0 MHz. Vee = 5 V 960 1920 IJA fosc = 3.0 MHz. Vee = 5V 480 960 IJA lee Wake-Up mode fosc = 0.5 MHz. Vee = 5 V 80 160 IJA (timer active) f osc = Z MHz. Vee = 5 V 160 320 IJA/MHz fosc = 0.5 MHz. Vee = 2.5 V 40 80 IJA fosc = 6.0 MHz. Vee = 5 V 480 980 IJA lee Halt osc-on fosc = 3.0 MHz. Vee = 5 V 240 500 IJA fosc = 0.5 MHz. Vee.= 5 V 45 100 IJA fosc = Z MHz Vee = 5 V See Note 2 IJA fosc = 0.5 MHz. Vee = 2.5 V 25 60 IJA lee Halt osc-off Vee = 2.5 to 6 V 1 10 IJA Notes: 1. All inputs = Vcc or VSS (except XTAL2). All output pins are open. 2. Maximum current = 160(Z) + 20 IJA XTAL2ICL~ CLKOUT Figure 4-21. Clock Timing 4-33

Table 4-30. Recommended Crystal/Clockin Operating Conditions over Full Operating Range TEST PARAMETER CONDITIONS MIN TYpt MAX UNIT Vee = 2.5 V 0.5 0.8 MHz Vee = 4.0 V 0.5 4.0 MHz fose Crystal frequency Vee = 5.0 V 0.5 6.0 MHz Vee = 6.0 V 0.5 6.5 MHz ClKI N duty cycle 45 55 % Vee = 2.5 V 1250 2000 ns Crystal cycle timet Vee = 4.0 V 250 2000 ns tc(P) Vee = 5.0 V 166 2000 ns Vee = 6.0 V 153 2000 ns Vee = .2.5 V 2500 4000 ns Vee = 4.0 V 500 4000 ns tc(e) Internal state cycle time Vee = 5.0 V 333 4000 ns Vee = 6.0 V 306 4000 ns twlPHl ClKIN pulse duration high 70 ns tw(Pl.l ClKIN pulse duration low 70 ns tr ClKINrise time 30 ns tf elKIN fall time 30 ns tdlPL-eHl ClKIN fall to ClKOUTrise delay 110 250 ns t Vee = 5 V, TA = 25°C t See Section 3.4 for Recommended Clock Connections. 4-34

N :z: :::i1 6 > U 5 II CT I 13 ., 3 0 iii E ~ 2 w u ., ~ 7 i a 5 j 4 UI I 3 (.) JJ 2 o o Vee - Supply Voltage - V Figure 4-22. Operating Frequency Range TA = 25°e

5 MHz

~ -'" V L---

3 MHz

--- I-- ---

0.5 MHz

Figure 4-23. Typical Operating Current vs. Supply Voltage 4-35

(5V ±10%) Vee VIH VIL TA 4-38 Table 4-31. Absolute Maximum Rating over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted, all voltages are with respect to VSS' Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability. Table 4-32. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 4.5 5.5 V XTAL2 pin O.aVee V High-level input voltage All other pins 0.7V ee V XTAL2 pin 0.2Vee V Low-level input voltage All other pins 0.3V ce V Commercial 0 70 'C Operating temperature (TMS70CxONL) range Industrial (TMS70CxONA) -40 85 'C

Table 4-34. AC Characteristics for I/O Ports PARAMETER :rEST CONDITIONS MIN TYP MAX UNITS tr I/O port output Cload= 15 pF,V ec = 5 V 35 60 ns rise time tf I/O port output Cload= 15 pF,V cc = 5 V ,20 .50 ns fall time Note: Rise and fall times are measured between the maximum low leliel and the minimum high level using the 10% and 90% points. Table 4-35. Supply Current Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fosc = 5.0 MHz 7.5 13.5 mA fosc = 3.0 MHz 4.5 8.1 mA Icc Operating mode f osc = 1.0 MHz 1.5 2.7 mA fosc = Z MHz 1.5 2.7 mA/MHz fosc = 5.0 MHz 800 1750 ~A Ice Wake- Up mode fosc = 3.0 MHz 480 1050 ~A (timer active) f osc = 1.0 MHz 160 350 ~A fosc = Z MHz 160 350 ~A/MHz fosc = 5.0 MHz 480 920 ~A lec Halt osc-on f osc = 3.0 MHz 240 560 ~A fosc = 1.0 MHz 80 200 ~A fosc = Z MHz See Note 2 ~A Icc Halt osc-off 1 10 ~A Notes: 1. All inputs = Vec or VSS (except XTAL2). All output pins are open. 2. Maximum current = 180(Z) + 20 ~A. 4-40

Table 4-36. Recommended Crystal/Clockin Operating Conditions over Full Operating Range PARAMETER fose Crystal frequency CLKI N duty cycle tc(P) Crystal cycle time:!: te(C) Internal state cycle time tw(PH) CLKIN pulse duration high tw(PL) CLKIN pulse duration low tr CLKIN rise time tf CLKIN fall time td(PL-CH) CLKIN fall to CLKOUT rise delay t VCC=5V,TA=25·C :!: See Section 3.4 for Recommended Clock Connections. XTAL2/CU<JN CLKOUT Figure 4-30. Clock Timing MIN Typt MAX 0.5 5.0 45 55 200 2000 400 4000 140 250 UNIT MHz ns' ns ns ns ns ns ns 4-41 I

Table 4-37. Memory Interface Timingst PARAMETER tcCC) CLKOUT cycle time twCCH) CLKOUT high pulse duration tw(CL) CLKOUT low pulse duration td(CH-JL) Delay time. CLKOUT rise to ALATCH fall twCJH) ALATCH active duration tsu(HA-JL) Setup time. high address valid before ALATCH fall tsu(LA-JL) Setup time. low address valid before ALATCH fall th(JL-LA) Hold time. low address hold after ALATCH fall tsu(RW-JL) Setup time. R/W valid before ALATCH fall th(EH-RW) Hold time. R/W after ENABLE rise th(EH-HA) Hold time. high address valid after El'.lAIITE rise td(O-EH) DN'a'fi~me. data out valid before E A E rise th(EH-O) Hold time. data out valid after ENABLE rise td(EH-A) Delay time. EiiiABIE rise to next address drive ta(EL-O) Access time. data in after ENABLE fall ta(A-O) Access time. data in from valid address td(A-EH) Delay time. ENABLE high after valid address th(EH-O) Hold time. data input valid after ENABLE rise td(CH-EL) Delay tme. CLKOUT rise to ENAB E fall td(LA-EL) Low address High Z before El'.lAIITE fa II t VCC = 4.5 to 5.5 V CLKIN duty cycle = 50% MIN TYP tcCC) 0.5tcCC)-90 0.5tc(C)-90 0.75t c(C)-50 0.5tc(C)-15 0.5t c(C)-1 00 0.5t c(C)-1 00 0.5t c(C)-60 0.5t c(C) -100 0.25t c(C)-60 0.25t c(C)-60 0.75t c(C)-70 0.25t c(C)-30 0.25t c(C)-60 p.75t c(C)-120 1.5t c(C)-300 ~ .75t c(C)-1 00 -10 35 0.25t c(C)-45 MAX 0.5t cCC)+90 0.5t c(C)+90 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns r\\,: I.j>o,

Table 4-38. Memory Interface Timings at 6 M Hzt PARAMETER te{C) CLKOUT cycle time twCCHl CLKOUT high pulse duration twCCLl CLKOUT low pulse duration tdCCH-JLl Delay time, CLKOUT rise to ALATCH fall tw(JHl ALATCH active duration tsuCHA-Jll Setup time, high address valid before ALATCH fall tsuClA-JLl Setup time, low address valid before ALATCH fall tdLJl-lAl Delay time, low address hold after ALATCH fall tdCRW-Jll Delay time, R/W valid before ALATCH fall thCEH-RWl Hold time, R/W valid after ENABLE rise thCEH-HAI Hold time, high address valid after ENABLE rise tsuCO-EHl Setup time, data out valid before ENABLE rise thCEH-Ol Hold time, data out valid after ENABLE rise tdCEH-Al Delay time, ENABLE rise to next address drive taCEl-D) Access time, data in after ENAB't'E fall taCA-Dl Access time, data in from valid address tdCA-EHl Delay time, ENABLE high after address valid thCEH-D) Hold time, data input valid after ENABLE rise tdCCH-ELl Delay time, CLKOUT rise to ENABLE fall tdClA-Ell Delay time, low address High Z to ENABLE fall t VCC = 4.5 to 5.5 V CLKIN duty cycle = 50% MIN TYP 400 110 200 110 200 250 300 185 200 100 200 100 200 140 200 100 200 40 100 40 100 230 300 70 100 40 100 180 300 300 600 600 700 -10 35 55 100 MAX 290 290 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4-43

I I I I I I I I I I I I Figure 4-31. Read and Write Cycle Timing INTERNAL READ

4.7 TMS70CT20 and TMS70CT40 Specifications (5 V ± 10%)

Table 4-39. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) Vee VIH VIL TA t Unless otherwise noted, all voltages are with respect to Vss. Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 4-40. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 4.5 5.5 V XTAL2 pin 0.8V ee V High-level input voltage All other pins 0.7V ec V Low-level input voltage XTAL2 pin 0.2V CC All other pins 0.3Vcc V Operating temperature range 0 70 ·C 4-45 !

Note: Icc Icc ICC ICC Notes: Table 4-42. AC Characteristics for 1/0 Port PARAMETER TEST CONDITIONS MIN I/O port output rise time Cload = 15 pF, V cc = 5 V I/O port output fall time C10ad = 15 pF, V cc = 5 V 1. Rise and fall times are measured between the maximum low level and the minimum high level using the 10% and 90% points. Table 4-43. Supply Current Requirements PARAMETER TEST CONDITIONS MIN fosc = 5.0 MHz fosc = 3.0 MHz Operating mode f osc = 1.0 MHz fosc = Z MHz Wake- Up mode fosc = 5.0 MHz, (ti mer active) f osc = 3.0 MHz f osc = 1.0 MHz fosc = Z MHz Halt osc-on fosc = 5.0 MHz, f osc = 3.0 MHz f osc = 1.0 MHz TYP TYP 7.5 4.5 1.5 1.5 800 480 160 160 480 240 fosc = Z MHz (See Note 3) Halt osc-off 1 2. All inputs = V cc or VSS (except XTAL2). All output pins are open. 3. Maximum current = 180(Z) + 201JA. MAX UNIT 60 ns 50 ns MAX UNIT 13.5 mA 8.1 mA 2.7 mA 2.7 mA/MHz

1750 IJA

1050 IJA

350 IJA

350 IJA/MHz

920 IJA

560 IJA

200 IJA

10 IJA

Table 4-44. Recommended Crystal/Clockin Operating Conditions over Full Operating Range PARAMETER fosc Crysta I freq u en cy CLKIN duty cycle tC(Pl Crystal cycle time+ tC(Cl Internal state cycle time tw(PH) CLKIN pulse duration high tw(PLl CLKIN pulse duration low tr CLKIN rise time tf CLKIN fall time t V CC = 5 V, T A = 25"C :I: See Section 3.4 for Recommended Clock Connections. 4-48 XTAL2/CLKIN I I I ---t ~tf I t--I I I I I I I I I Figure 4-34. Clock Timing MIN TYPt MAX UNIT 0.5 5.0 MHz 45 55 % 200 2000 ns 400 4000 ns 90 ns 90 ns 30 ns 30 ns

4.8 TMS70C02 and TMS70C42 Specifications (Wide Voltage)

Table 4-45. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted. all voltages are with respect to Vss. Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 4-46. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 2.5 6.0 V MC and XTAL2 pins, 0.8V ee V Vee = 2.5 to 6 V High-level input voltage All other input pins; 0.70Vee V Vee = 3 to 6 V All other input pins, 0.75V ee V Vee = 2.5 to 3 V MC and XTAL2 pins, 0.2V ee V Low-level input voltage Vee = 2.5 to 6 V All other input pins, 0.3V ee V Vee = 2.5 to 6 V Commercial 0 70 ·C Operating free-air (TMS70C42NL) temperature Industrial (TMS70C42NA) -40 85 ·C 4-49

Table 4-47. Electrical Characteristics overFull Range of Operating Conditions PARAMETER TEST CONDITIONS MIN Typt MAX UNIT II Input current Me pin, V IN = VSS or Vee ±0.1 ±5 IJA All others, VIN = VSS to Vee CI Input capacitance 5 pF Vee = 2.5 V, IOH = -50 IJA 2.25 2.4 V VOH High-level Vee = 4.0 V, IOH = -0.4 rnA 3.2 3.6 V output voltage:!: Vee = 5.0 V, IOH = -0.7 rnA 3.9 4.5 V Vee = 6.0 V, IOH = -1.0 rnA 4.6 5.4 V Vee = 2.5 V, IOl = 0.4 rnA 0.2 0.35 V Val Low-level Vee = 4.0 V, IOl = 1.6 rnA 0.4 0.8 output voltage:!: V Vee = 5.0 V, IOl = 2.5 rnA 0.6 1.1 V Vee = 6.0 V, IOl = 3.4 rnA 0.8 1.4 V Vee = 2.5 V, VOH = 2.25 V -50 -200 IJA IOH Output source Vee = 4.0 V, VOH = 3.2 V -0.4 -1.4 rnA current Vee = 5.0 V, VOH = 3.9 V -0.7 -2.2 rnA Vee = 6.0 V, VOH = 4.6 V -1.0 -3.3 rnA Vee = 2.5 V, Val = 0.35 V 0.4 0.9 rnA IOl Output sink Vee = 4.0 V, Val = 0.8 V 1.6 3.5 rnA current Vee = 6.0 V, Val = 1.4 V 3.4 8.0 rnA t Vee = 5 V, TA = 25°C :I: Output levels ensure 400rnV of noise rnargin over specified input levels. 4-50

Table 4-48. Supply Current Requirements PARAMETER TEST CONDITIONS' MIN TYP MAX UNIT fosc = 7.0 MHz. Vee = 5.0 V 17 24.5 rnA fosc = 3.0 MHz, Vee = 5.0 V 7.2 10.5 rnA lee Operating mode f osc = 0.5 MHz, Vee = 5.0 V 1.2 1.8 rnA fosc = Z MHz, Vee = 5.0 V 2.4 3.5 rnA/MHz fosc = 0.5 MHz, Vee = 2.5 V 0.4 1.2 rnA lee Wake-Up mode 1 fosc = 7.0 MHz, Vee = 5.0 V 2400 5600 lolA Lone timer and f osc = 3.0 MHz, Vee = 5.0 V 1200 3300 lolA ART active) f osc = 0.5 MHz, Vee = 5.0 V 250 800 lolA lee Wake-Up mode 2 fosc = 7.0 MHz, Vee = 5.0 V 960 3400 lolA Lone timer active, f osc = 3.0 MHz, Vee = 5.0 V 480 2000 lolA ART inactive) f osc = 0.5 MHz, Vee = 5.0 V 140 550 lolA lee Wake- Up mode 3 f osc = 7.0 MHz, Vee = 5.0 V 1500 2400 lolA (UART active only) , f osc = 3.0 MHz, Vee = 5.0 V 800 1500 lolA fosc = 0.5 MHz, Vee = 5.0 V 180 600 lolA lee Halt osc-on fosc = 7.0 MHz, Vee= 5.0 V 560 1280 lolA f osc = 3.0 MHz, Vee = 5.0 V 240 560 lolA f osc = 1.0 MHz, Vee = 5.0 V 80 200 lolA fosc = Z MHz (See Note 2.) lolA lee Halt osc-off 5 10 lolA Notes: 1. All inputs = Vee or VSS (except XTAL2). All output pins are open. 2. Maximum current = 180(Z) + 20 lolA. 4-51

Table 4-49. Recommended Crystal/Clockin Operating Conditions over Full Operating Range TEST PARAMETER CONDITIONS MIN TVPt MAX UNIT Vee = 2.5 V 0.5 0.8 MHz Vee = 4.0 V 0.5 5.0 MHz fosc Crystal frequency Vee = 5.0 V 0.5 7.0 MHz Vee = 6.0 V 0.5 7.5 MHz ClKIN duty cycle 45 55 % Vee = 2.5 V 1250 2000 ns Crystal cycle timei Vee = 4.0V 200 2000 ns tc(P) Vee = 5.0 V 143 2000 ns Vee = 6.0 V 133 2000 ns Vee = 2.5 V 2500 4000 ns Vee = 4.0V 400 4000 ns tc(e) I nternal state cycle time Vee = 5.0 V 286 4000 ns Vee = 6.0 V 267 4000 ns twlPHI ClKIN pulse duration high 50 ns twlPL) ClKIN pulse duration low 50 ns tr ClKIN rise time 30 ns tf ClKI N fall time 30 ns tdlPL-eHI ClKIN fall to ClKOUT rise delay 110 250 ns t Vee = 5 V, TA = 25'C i See Section 3.4 for Recommended Clock Connections. CLKOUT Figure 4-35. Clock Timing 4-52

18 I I

OIl( 16 E ' .. 14 c ~ 12 :I (.) ~ 10 :I 8 CI) I 6 (.) 9 4 ./ TA = 25°C - ALL OUTPUTS OPEN /VCC = 5V /'" <=4V ./ /.---~ y t"'" 0 2 3 4 5 6 7 8 fosc - Frequency - MHz Figure 4-38. Typical Operating ICC vs. Oscillator Frequency 1.1 TA = 25°e / ALL OUTPUTS OPEN fosc = 0.5 MHz 0.9 ct E ./ / / / , E 0.8 " 0.7 (,) :?: c. c. " II) 0.6 I (,) 0.5 0.4 0.3 Vee - Supplv Voltage - V Figure 4-39. Typical Operating Current vs. Supply Voltage 4-54

4.8.1 Serial Port Timing

4.8.1.1 Internal Serial Clock

8CLl< TXD RXD LQ-[k!JJLrVL tl···· :, -1 1-td(CL-Ttl) I I+- RXD SAMPLE SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = te(C). PARAMETER TYP ttitCI _l::1 I CLKOUT low to SCLK low 1/4 t"tCI tdICL_TDI CLKOUT low to new TXD data 1/4 tdCI tdtRD-CLl RXD data valid before CLKOUT low 1/4 t clC) ttllRDI RXD data valid time 1/2 t"rCI.

4.8.1.2 External Serial Clock

SCLl< ~~ j.== td(88-Ttl)--tj I CLl<OlIT RXD td(RD-CU --.I I+- RXD SAMPLE SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = tetC}. 3) SCLK sampled; (f SCLK = 1 then 0, fall transition found. 4) SCLK sampled; if SCLK = 0 then 1, rise transition found. PARAMETER TYP ttlIRD_CL\\ RXD data valid before CLKOUT low 1/4 t "rCI tdIRDI. RXD data valid time 1/2 tc(C) t.d!SB-TDl Start of SCLK sample to new TXD data 31/4 t dCI tdISI'_TDI End of SCLK sample to new TXD data 2 1/4 t dCI tdlCL-S) Clockout low to SCLK transition t ctC) UNIT ns ns ns ns UNIT ns ns ns ns ns

4.9 TMS70C02 and TMS70C42 Specifications (5V ±10%)

V,H VIL TA Table 4-50. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted, all voltages are with respect to VSS' Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 4-51. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 4.5 5.5 V MC and XTAL2 pins 0.8V ee V High-level input voltage All other input pins 0.7V ee V MC and XTAL2 pins 0.3V ec V Low-level input voltage All other input pins 0.2V cc V Commercial 0 70 ·C Operating temperature (TMS70C42NL) Industrial -40 85 ·C (TMS70C42NA) 4-57

Table 4-52. Electrical Characteristics over Full Range of Operating Conditions PARAMETER TEST CONDITIONS MIN TYpt MAX UNIT II Input leakage current MC pin. V IN = VSS or Vee ±0.1 ±5 IJA All others. VIN = Vss to Vee CI Input capacitance 5 pF VOH High-level I OH = -0.3 rnA Vee-0.05 4.1 V output voltage VOL Low-level I Ol = 1.4 mA 0.2 0.4 V output voltage IOH High-level output VOH = Vee - 0.5 V -0.3 -1.2 mA source current V OH = 2.5 V min -1.0 -3.0 rnA IOl Output sink VOL = 0.4 V 1.4 2.0 mA current Table 4-53. AC Characteristics for Input/Output Portst PARAMETER TEST CONDITIONS MIN TYP MAX UNit trClOl I/O port output rise time Cload = 15 pF. V ee = 5 V 35 60 ns tfliOl I/O port output fall time Cload= 15 pF. Vec = 5 V 20 50 ns t Rise and fall times are measured between the maximum low level and the miniumum high level using the 10% and 90% points. LOAD VOLTAGE 1OOOQ Vo 100pF Figure 4-42. Output Loading Circuit for Test 4-58

-Figure 4-43. Measurement Points for Switching Characteristics Table 4-54. Supply Current Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fasc = 6.0 MHz 15 24 mA fasc = 3.0 MHz 7.2 12 mA Icc Supply current f asc = 1.0 MHz 2.4 4.0 mA fasc = Z MHz 2.4 4.0 mA/MHz ICC Wake- Up mode 1 fasc = 6.0 MHz 2400 5400 IJA Lone timer and f aBC = 3.0 MHz 1200 2900 IJA ART active) f asc = 1.0 MHz 650 1500 IJA Icc Wake-Up mode 2 fasc = 6.0 MHz 960 3200 IJA Lone timer active. f asc = 3.0 MHz 480 1800 IJA ART inactive) f asc = 1.0 MHz 350 1000 IJA Icc Wake- Up mode 3 f asc = 6.0 MHz 1500 2200 IJA (UART active only) f asc = 3.0 MHz 800 1300 IJA fasc = 1.0 MHz 400 1100 IJA Icc Halt osc-on fasc = 6.0 MHz 480 1120 IJA f asc = 3.0 MHz 240 560 IJA f asc = 1.0 MHz 80 200 IJA fasc = Z MHz (See Note 2.) IJA ICC Halt osc-off 5 10 IJA Notes: 1. All inputs = Vee or VSS (except XTAL2). All output pins are open. 2. Maximum current = 180(Z) + 20 IJA. 4-59

Table .,-55. Recommended Crystal/Clockin Operating Conditions over Full Operating Range PARAMETER MIN Typt MAX UNIT fosc Crystal frequency 0.5 6.0 MHz ClKI N duty cycle 45 55 % tc(P) Crystal cycle timet 167 2000 ns tc(C) Internal state cycle time 333 4000 ns twlPH) ClKIN pulse duration high 70 ns tw(PL) ClKIN pulse duration low 70 ns tr ClKI N rise time 30 ns tf ClKI N fall time 30 ns tqLPL·Cft\\ ClKI N fall to ClKOUT rise delay 110 250 ns t Vec = 5 V, TA = 25'C :j: See Section 3.4 for Recommended Clock Connections. XTAL2/CLKIN CU<OUT Figure 4-44. Clock Timing 4-60

Table 4-56. Memory Interface Timingst PARAMETER telC) CLKOUT cycle time tw(CH) CLKOUT high pulse duration twlCL) CLKOUT low pulse duration td(CH-JL) Delay time. CLKOUT rise to ALATCH fall twlJH) ALATCH high pulse duration tsu(HA-JL) Setup time. high address valid before ALATCH fall tsu(LA-JL) Setup time. low address valid before ALATCH fall td(JL-LA) Delay time. low address valid after ALATCH fall tsu(RW-JL) Setup time. R/W valid before ALATCH fall th(EH-RW) Hold time. R/W valid after ENABLE rise th(EH-AH) Hold time. high address valid after ENABLE rise tsu(Q-EH) Setup time. data out valid before ENABLE rise th(EH-Q) Hold time. data out valid after ENABLE rise td(LA-EL) Delay time. low address HI-Z to ENABLE fall td(EH-A) Delay time. ENABLE rise to next address drive td(EL-D) DN~y time. data in after E BLE fall tarA-D) Access time. data in from valid address td(A-EH) Delay time. ENABLE high after address valid th(EH-D) Hold time. Data input valid after ENABLE rise td(EH-JH) Delay time. ENABLE rise to ALATCH rise td(CH-EL) DNn time. CLKOUT rise to E LE fall t fosc = 0.5 to 6.0 MHz Vce = 4.5 to 5.5 V CLKIN duty cycle = 50% MIN TYP MAX 333 4000 0.5te(C)-90 0.5t e(C) 0.5te(C) +90 0.5tcIC)-90 0.5t clC) 0.5teIC) +90 0.5t c(C)-50 0.5te(C) 0.25tcIC)-50 0.25t clC) 0.25t e(C)-45 0.25te(C) 0.25t c(C)-45 0.25te(C) 0.5t c(C)-35 0.5te(C) 0.25t c(C)-40 0.25tc(C) 0.5t c(C)-60 0.5te(C) 0.5t c(C)-60 0.5te(C) 0.5t c(C)-70 0.5te(C) 0.5t e(C)-60 0.5te(C) 0.25t e(C)-45 0.25tc(C) 0.5t c(C)-60 0.5te(C) 0.75t c(C)-160 0.75te(C) 1.5t e(C)-50 1.5te(C) 0.5t e(C)-60 0.5te(C) UNIT ns ns ns ns -ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4-61

Table 4-57. Memory Interface Timings at 6 MHzt PARAMETER MIN TYP MAX UNIT telC) CLKOUT cycle time 333 ns twJCHt CLKOUT high pulse duration 76 166 252 ns twlCL) CLKOUT low pulse duration 76 162 252 ns tdICH-JL) Delay time. CLKOUT rise to ALATCH fall 116 166 ns twlJH) ALATCH active duration 33 83 ns tSI){AH-JL) Setup time, high address valid before ALATCH fall 38 83 ns tsuILA-JL) Setup time, low address valid before ALATCH fall 38 83 ns tdIJL-LA) Delay time, low address hold after ALATCH fall 131 166 ns tdIRW-JLl Delay time, R/W valid before ALATCH fall 43 83 ns th(EH-RW) Hold time, R/W valid after'E'N'A'EiIT rise 106 166 ns th(EH-HA) Hold time, high address valid after'E'N'A'EiIT rise 106 166 ns tsuIQ-EH) Setup time, data out valid before 'E'N'A'EiIT rise 96 166 ns tflCEH-Ql Hold time, data out valid after ENABLE rise 106 166 ns td(LA-EL) Delay time, low address HI-Z to El\\JAl:iIE fall 38 83 ns td(EH-A) Delay time, ENABLE rise to next address drive 106 166 ns tdIEL-O) Delay time, data in after ENABLE fall 90 250 ns ta(A-O) Access time, data in from valid address 300 400 ns td(A-EH) Delay time, El\\JAl:iIE high after address valid 450 500 ns th(EH-O) Hold time, data input valid after ENABLE rise 0 ns tdIEH-JH) Delay time, El\\JAl:iIE rise to ALATCH rise 106 166 ns td(CH-EL) Delay time, CLKOUT rise to ENABLE fall 30 ns t VCC = 4.5 to 5.5 V CLKI N duty cycle = 50% 4-62

(00-07) EXTERNAL WRITE I RAM READ I I Figure 4-45. Read and Write Cycle Timing INTERNAL READ 4-63

4.9.1 Serial Port Timing

4.9.1.1 Internal Serial Clock

CLI<OUT ~JUl-fl- --+I M- tcl(CL-8U ... . I SCLI< -·--+I-il If -! !-~CL-TD) I RXD RXD SAMPLE SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = te(C)' PARAMETER TYP trHCL_SL\\ CLKOUT low to SCLK low 1/4 tdCI tritCI _TnI CLKOUT low to new TXD data 1/4 tclCI tdIRD-CL\\ RXD data valid before CLKOUT low 1/4 t elCI trilRDI RXD data valid time 1/2 t"ICI

4.9.1.2 External Serial Clock

Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = te(C)' 3) SCLK sampled; rf SCLK = 1 then 0, fall transition found. 4) SCLK sampled; if SCLK = 0 then 1, rise transition found. PARAMETER TYP tritRn_CI I RXD data valid before CLKOUT low 1/4 t "tCI tdlRDI RXD data valid time 1/2 telC\\ triISR_TDI Start of SCLK sample to new TXD data 3 1/4 t dCI tdISE-TD\\ End of SCLK sample to new TXD data 21/4 t eIG) tdICL-S\\ Clockout low to SCLK transition t elC\\ UNIT ns ns ns ns UNIT ns ns ns ns ns

4.10 SE77C42 Specifications

Table 4-58. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted, all voltages are with respect to VSS. Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 4-59. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 2.5 6.0 V MC and XTAL2 Pins O.BVee V Vee = 2.5 to 6.0 V High-level input voltage All other input pins 0.70V ce V Vee = 3.0 to 6.0 V All other inputs 0,75V ee V Vee = 2.5 to 3.0 V MC and XTAL pins 0.2V ee V Vee = 2.5 to 6.0 V Low-level input voltage All other inputs Vee = 2.5 to 6.0 V 0.3V ee V Operating temperature Commercial 0 55 'C Oscillator frequency 0.5 7.5 MHz 4-65

Table 4-60. Electrical Characteristics over Full Range of Operating Conditions PARAMETER TEST CONDITIONS MIN Typt MAX UNIT II Input leakage current MC pin, V IN = VSS or Vee ±0.1 ±5 ~A All others, VIN = VSS to Vee CI Input capacitance 5 pF VOH High-level I OH = -0.3 rnA Vee- 0.05 4.7 V output voltage VOL Low-level I OL = 1.4 rnA 0.2 0.4 V output voltage IOH High-level output VOH = Vee - 0.5 V -0.3 -1.2 rnA source current V OH = 2.5 V min -1.0 -3.0 rnA IOl Output sink VOL = 0.4 V 1.4 2.0 rnA current Table 4-61. AC Characteristics for Input/Output Portst PARAMETER TEST CONDITIONS MIN TYP MAX UNIT trllO) I/O port output rise time Cload = 15 pF, V ee = 5 V 35 60 ns tWO) I/O port output fall time Cload = 15 pF, V ee = 5 V 20 50 ns t Rise and fall times are measured between the maximum low level and the mlnlumum high level uSing the 10% and 90% points. LOAD VOLTAGE 1OOOQ Vo 100pF Figure 4-46, Output Loading Circuit for Test 4-66

=====-aQi---vOH(MN) -Figure 4-47. Measurement Points for Switching Characteristics Table 4-62. Supply Current Requirements· PARAMETER TEST CONDITIONS' MIN TYP MAX UNIT fosc = 6.0 MHz 15 24 mA fosc = 3.0 MHz 7.2 12 mA Icc Su pply current f osc = 1.0 MHz 2.4 4.0 mA fosc = Z MHz 2.4 4.0 mA/MHz ICC Wake-Up mode 1 fosc = 6.0 MHz 2400 5400 IJA Lone timer and f osc = 3.0 MHz 1200 2900 IJA ART active) f osc = 1.0 MHz 650 1500 IJA Icc Wake-Up mode 2 fosc = 6.0 MHz 960 3200 IJA Lone timer active, f osc = 3.0 MHz 480 1800 IJA ART inactive) f osc = 1.0 MHz 350 1000 IJA ICC Wake-Up mode 3 f osc = 6.0 MHz 1500 2200 IJA (UART active only) f osc = 3.0 MHz 800 1300 IJA fosc = 1.0 MHz 400 1100 IJA ICC Halt ~sc-on fosc = 6.0 MHz 480 1120 IJA f osc = 3.0 MHz 240 560 IJA f osc = 1.0 MHz 80 200 IJA fosc = Z MHz (See Note 2.) IJA ICC Halt osc-off 5 15 IJA Notes: 1. All inputs = VCC or VSS (except XTAL2).AII output pins are open. 2. Maximum current = 180(Z) + 20 IJA. 4-67

Table 4-63. Recommended .Crystal/Clockin Operating Conditions over Full Operating Range PARAMETER fosc Crystal frequency ClKIN duty cycle tc(P) Crystal cycle timet tc(C) Internal state cycle time tw(PH) ClKIN pulse duration high tw(Pl) ClKIN pulse duration low tr ClKIN rise time tf ClKIN fall time td(PL-CH} ClKIN fall to ClKOUT rise delay t VCC = 5V, TA = 25°C + See Section 3.4 for Recommended Clock Connections. XTAL2/CLKlN CLKOUT MIN Typt 0.5 167 333 110 '-td{PL-CH) I . ~ I tw(PH) I I I Figure 4-48. Clock Timing 4-68 MAX UNIT

6.0 MHz

55 % 2000 ns 4000 ns ns ns 30 ns 30 ns 250 ns

Table 4-64. Memory Interface Timingst PARAMETER te(C) CLKOUT cycle time twlCH) CLKOUT high pulse duration tw(CLI CLKOUT low pulse duration td(CH-JL) Delay time, CLKOUT rise to ALATCH fall twlJH) ALATCH high pulse duration tsu(HA-JL) Setup time, high address valid before ALATCH fall tsu(LA-JL) Setup time, low address valid before ALATCH fall td(JL-LA) Delay time, low address valid after ALATCH fall tsu(RW-JL) Setup time, R/W valid before ALATCH fall th(EH-RW) .!:!2!21i!!!e, R/W valid after ENABLE rise th(EH-AH) Hold time, high address valid after ENABLE rise tsu(Q-EH) Setup time, data out valid before ENABLE rise th(EH-Q) Hold time, data out valid after ENABLE rise td(LA-EL) Delay time, low address HI-Z to ENABLE fall td(EH-A) Delay time, ENABLE rise to next address drive td(EL-D) De~y rme, data in after EN BEfall talA-D) Access time, data in from valid address td(A-EH) Delay time, ENABLE high after address valid th(EH-D) Hold time, Data input valid after ENABLE rise td(EH-JH) Delay time, E1iiABtE rise to ALATCH rise td(CH-EL) Delay time, CLKOUT rise to ENABLE fall t fase = 0.5 to 6.0 MHz VCC = 4.5 to 5.5 V CLKI N duty eycle = 50% MIN TYP 333 0.5teIC)-90 0.5t elC) 0.5te(C)-90 0.5t e(C) 0.5t e(C)-50 0.5te(C) 0.25te(C)-50 0.25t e(C) 0.25t e(C)-45 0.25te(C) 0.25t e(C)-45 0.25te(C) 0.5t e(C)-35 0.5te(C) 0.25t e(C)-40 0.25te(C) 0.5t e(C)-60 0.5te(C) 0.5t c(C)-60 0.5te(C) 0.5t e(C)-70 0.5te(C) 0.5t e(C)-60 0.5te(C) 0.25t e(C)-45 0.25te(C) 0.5t e(C)-60 0.5te(C) 0.75t e(C)-160 0.75te(C) 1.5t e(C) -50 1.5te(C) 0.5t e(C)-60 0.5te(C) MAX 4000 0.5teIC) +90 0.5te(C) +90 UNIT ns ns ns ns ns ns I ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4-69

Table 4-65. Memory Interface Timings at 6 MHzt PARAMETER tele) CLKOUT cycle time tw(CH) CLKOUT high pulse duration twtCL) CLKOUT low pulse duration tdICH·JU Delay time, CLKOUT rise to ALATCH fall twlJH) ALATCH active duration tsu(AH-JLI Setup time, high address valid before ALATCH fall tsu(LA-JL) Setup time, low address valid before ALATCH fall tdIJL-LA) Delay time, low address hold after ALATCH fall tdIRW-JIJ Delay time, R/W valid before ALATCH fall th(EH-RWI Hold time, R/W valid after ENABLE rise th(EH-HA) Hold time, high address valid after ENABLE rise tsuIQ-EH) Setup time, data out valid before ENABLE rise th(EH-Q) Hold time, data out valid after E'NAB'['E rise td(LA-EL) Delay time, low address HI-Z to E'NAB'['E fall tdIEH-A) Delay time, ENABLE rise to next address drive tdIEL-O) Delay time, data in after ENABLE fall ta(A-O) Access time, data in from valid address td(A-EH) Delay time, E'NAB'['E high after address valid thtEH-O) Hold time, data input valid after E'NAB'['E rise tdIEH-JI-Il Delay time, ENABLE rise to ALATCH rise td(CH-EL) Delay time, CLKOUT rise to ENABLE fall t VCC = 4.5 to 5.5 V CLKIN duty cycle = 50% 4-70 MIN TYP 333 76 166 76 162 116 166 33 83 38 83 38 83 131 166 43 83 106 166 106 166 96 166 106 166 38 83 106 166 90 250 300 400 450 500 106 166 MAX 252 252 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

EXTERNAL WRITE RAM READ INTERNAL READ HIGH ADDRESS (00-07) Figure 4-49. Read and Write Cycle Timing 4-71

4.11 SE70CP160A Specifications

These specifications are for wide-voltage operation. For operation at 5 V ±10%, see Section 4.6. Be sure to use an EPROM that uses similar supply voltage specifications. Table 4-66. Absolute Maximum Rating over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted. all voltages are with respect to Vss. Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability. Table 4-67. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 2.5 6.0 V XTAL2 pin, Vee = 2.5 to 6 V O.BVee V High-level input voltage All other pins, Vee = 3 to 6 V 0.70Vee V All other pins, Vee = 2.5 to 3 V 0.75V ee V XTAL2 pin, 0.2V ee V Vee = 2.5 to 6 V Low-level input voltage All other pins, 0.3V ee V Vee = 2.5 to 6 V Operating temperature range 0 55 ·C

Table 4-68. Electrical Characteristics over Full Range of Operating Conditions PARAMETER TEST CONDITIONS MIN Typt MAX UNIT II Input leakage current VIN = VSS to V ee to.1 t5 IJA CI Input capacitance 5 pF Vee = 2.5 V, IOH = -50 IJA 2.25 2.4 V VOH High-level Vee = 4.0 V, IOH = -0.4 mA 3.2 3.6 V output voltage:!: Vee = 5.0 V, IOH = -0.7 mA 3.9 4.5 V Vee = 6.0 V, IOH = -1.0 mA 4.6 5.4 V Vee = 2.5 V, IOL = 0.4 mA 0.2 0.35 V VOL Low-level Vee = 4.0 V, IOL = 1.6 mA 0.4 0.8 V output voltage:!: Vee = 6.0 V, IOL = 3.4 mA 0.8 1.4 V Vee = 2.5 V, VOH = 2.25 V -0.05 -0.2 mA IOH Output source Vee = 4.0 V, VOH = 3.2 V -0.4 -1.4 mA current Vee = 5.0 V, VOH = 3.9 V -0.7 -2.2 mA Vee = 6.0 V, VOH = 4.6 V -1.0 -3.3 mA Vee = 2.5 V, VOL = 0.35 V 0.4 0.9 mA Vee = 5.0 V, VOL=1.1V 2.5 5.5 mA Vee = 6.0 V; VOL = 1.4 V 3.4 8.0 mA t Vee = 5 V, T A = 25"C :!: Output levels ensure 400 mV of noise margin over specified input levels. 4-73

Notes: Table 4-69. Supply Current Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fose = 6.0 MHz, Vee = 5 V 9.0 14.4 mA fose = 3.0 MHz, Vee = 5 V 4.5 7.2 mA Operating mode fose = 0.5 MHz, Vee = 5 V 0.8 1.2 mA fose = Z MHz, Vee = 5 V 1.5 2.4 mA/MHz fose = 0.5 MHz, Vee = 2.5 V 370 800 ~A fose = 6.0 MHz, Vee = 5 V 960 1920 ~A fose = 3.0 MHz, Vee = 5V 480 960 ~A Wake-Up mode fose = 0.5 MHz, Vee = 5 V 80 160 ~A (timer active) f ose = Z MHz, Vee = 5 V 160 320 ~A/MHz fose = 0.5 MHz, Vee = 2.5 V 40 80 ~A fose = 6.0 MHz, Vee = 5 V 480 980 ~A Halt ose-on fose = 3.0 MHz, Vee = 5 V 240 500 ~A fose = 0.5 MHz, Vee = 5 V 45 100 ~A fose = Z MHz Vee = 5 V See Note 2 ~A fose = 0.5 MHz, Vee=2.5V 25 60 ~A Halt osc-off Vee=2.5t06V 1 10 ~A 1. All inputs = Vee or VSS (except XTAL2). All output pins are open. 2. Maximum current = 160 (Z) + 20 ~A 3. ICC applies to the supply current of the SE70CP160A without an EPROM device in­ stalled.

Table 4-70. Recommended Crystal/Clockin Operating Conditions over Full Operating Range TEST PARAMETER CONDITIONS MIN TYPt MAX UNIT Vee = 2.5 V 0.5 0.8 MHz Vee = 4.0 V 0.5 4.0 MHz fose Crystal frequency Vee = 5.0 V 0.5 6.0 MHz Vee = 6.0 V 0.5 6.5 MHz ClKIN duty cycle 45 55 % Vee = 2.5V 1250 2000 ns Crystal cycle timet Vee = 4.0V 250 2000 ns te(P) Vee = 5.0 V 166 2000 ns Vee = 6.0 V 153 2000 ns Vee = 2.5 V 2500 4000 ns Vee = 4.0 V 500 4000 ns te(e) Internal state cycle time V CC = 5.0 V 333 4000 ns VCC = 6.0 V 306 4000 ns tw(PH) ClKIN pulse duration high 50 ns tw(PL) ClKIN pulse duration low 50 ns tr ClKIN rise time 30 ns tf ClKIN fall time 30 ns tdlPL-CHI ClKIN fall to ClKOUT rise delay 140 250 ns t Vec = 5 V. TA = 25°C t See Section 3.4 for Recommended Clock Connections. XTAL2ICU<JN CLKOUT Figure 4-50. Clock Timing 4-75

4.12 SE70CP162 Specifications

These specifications are for wide-voltage operation. For operation at 5 V ± 1 0%, see Section 4.9. Be sure to use an EPROM that uses similar supply voltage specifications. Table 4-71. Absolute Maximum Ratings over Operating Free-Air Temperature Range (unless otherwise noted) t Unless otherwise noted, all voltages are with respect to VSS' Caution: Stresses beyond those listed under "Absolute Maximum Rat­ ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specifi­ cation is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 4-72. Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage 2.5 6.0 V MC and XTAL2 pins, O.BVee V Vee = 2.5 to 6 V High-level input voltage All other input pins, 0.70Vee V Vee=3t06V All other input pins, 0.75V ce V Vee = 2.5 to 3 V MC and XTAL2 pins, 0.2V ee V Vee = 2.5 to 6 V Low-level input voltage All other input pins, Vee = 2.5 to 6 V 0.3V ee V Operating free-air temperature 0 55 'C

Table 4-73. Electrical Characteristics over Full Range of Operating Conditions PARAMETER TEST CONDITIONS MIN Typt MAX UNIT II Input current MC pin, V IN = VSS or Vee ±0.1 ±5 J.IA All others, VIN = Vss to Vee CI Input capacitance 5 pF Vee = 2.5 V, IOH = -50 J.IA 2.25 2.4 V VOH High-level Vee = 4.0 V, IOH = -0.4 mA 3.2 3.6 V output voltage:!: Vee = 5.0 V, IOH = -0.7 mA 3.9 4.5 V Vee = 6.0 V, IOH = -1.0 mA 4.6 5.4 V Vee = 2.5 V, IOl = 0.4 mA 0.2 0.35 V VOL Low-level output voltagei Vee = 4.0 V, IOl = 1.6 mA 0.4 0.8 V Vee = 5.0 V, IOl = 2.5 mA 0.6 1.1 V Vee = 6.0 V, IOl = 3.4 mA 0.8 1.4 V Vee = 2.5 V, VOH = 2.25 V -50 -200 J.IA IOH Output source Vee = 4.0 V, VOH = 3.2 V -0.4 -1.4 mA current Vee = 5.0 V, VOH = 3.9 V -0.7 -2.2 mA Vee = 6.0 V, VOH = 4.6 V -1.0 -3.3 mA Vee = 2.5 V, VOL = 0.35 V 0.4 0.9 mA IOl Output sink Vee = 4.0 V, VOL = 0.8 V 1.6 3.5 mA current Vee = 5.0 V, VOL = 1.1 V 2.5 5.5 mA Vee = 6.0 V, VOL = 1.4 V 3.4 8.0 mA t Vee = 5 V, TA = 25'C i Output levels ensure 400 mV of noise margin over specified input levels. 4-77

Table 4-74. Supply Current Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fose = 6.0 MHz. Vee = 5.0 V 14.6 21 mA fose = Z MHz. Vee = 5.0V 2.4 3.5 mA/MHz lee Wake-Up mode 1 fose = 6.0 MHz. V ee = 5.0 V 2400 5600 IlA Lone timer and f ose = 3.0 MHz, Vee = 5.0 V 1200 3300 IlA ART active) f ose = 0.5 MHz, Vee = 5.0 V 250 800 IlA f ose = 0.5 MHz. Vee = 5.0 V 140 550 IlA lee Wake-Up mode 3 f ose = 6.0 MHz. Vee = 5.0 V 1500 2400 IlA (UART active only) f ose = 3.0 MHz. Vee = 5.0 V 800 1500 IlA fose = 0.5 MHz. Vee = 5.0 V 180 600 IlA lee Halt osc-on fose = 6.0 MHz 480 1120 IlA f ose = 3.0 MHz 240 560 IlA f ose = 1.0 MHz 80 200 IlA fose = Z MHz (See Note 3.) IlA Icc Halt osc-off 5 10 IlA Notes: 1. All inputs = Vee or VSS (except XTAL2). All output pins are open. 2. Icc applies to the supply current of the SE70CP162 without an EPROM device installed. 3. Maximum current = 180(Z) + 20 1lA. 4-78

Table 4-75. Recommended Crystal/Clockin Operating Conditions over Full Operating Range TEST PARAMETER CONDITIONS MIN Typt MAX UNIT Vee = 2.5 V 0.5 0.8 MHz Vee = 4.0 V 0.5 5.0 MHz fosc Crystal frequency Vee = 5.0 V 0.5 7.0 MHz Vee = 6.0 V 0.5 7.5 MHz ClKIN duty cycle 45 55 % Vee = 2.5 V 1250 2000 ns Crystal cycle timet Vee = 4.0 V 200 2000 ns tc(P) Vee = 5.0 V 143 2000 ns Vee = 6.0 V 133 2000 ns Vec=2.5V 2500 4000 ns Vcc = 4.0V 400 4000 ns tc(C) I nternal state cycle time V ce = 5.0 V 286 4000 ns VCC=6.0V 267 4000 ns twlPHl ClKI N pulse duration high 50 ns twlPll ClKIN pulse duration low 50 ns tr ClKIN rise time 30 ns tf ClKIN fall time 30 ns tdIPL-CHl ClKIN fall to ClKOUT rise delay 110 250 ns t VCC = 5 V, TA = 25'C :I: See Section 3.4 for Recommended Clock Connections. XTAL2/CU<IN CU<Ol1T Figure 4-51. Clock Timing 4-79

4.12.1 Serial Port Timing

4.12.1.1 Internal Serial Clock

LQ-l1£}JLJ}ll- II II -I !+-td(CL-TD) I RXD SAMPLE SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = te(C). PARAMETER TYP tdICL-SL\\ CLKOUT low to SCLK low 1/4 telC) tt!Ir.1 _ TI1\\ CLKOUT low to new TXD data 1/4 t"Ir.\\ tdIRD-CL\\ RXD data valid before CLKOUT low 1/4 t elC) tdlRDl RXD data valid time 1/2 t"Ir.\\

4.12.1.2 External Serial Clock

~~ SCLK 1\\\\ \\\\~ td(SE-TD)-\\ UIIII TXD RXD !+== td(8B-TD)--tl1 td(RD-CU ---.\\ I+- RXD SAMPLE SAVED Notes: 1) The CLKOUT signal is not available in Single-Chip mode. 2) CLKOUT = te(C}. 3) SCLK sampled; rf SCLK = 1 then 0, fall transition found. 4) SCLK sampled; if SCLK = 0 then 1, rise transition found. PARAMETER TYP tt!IRn_r.L\\ RXD data valid before CLKOUT low 1/4 t "IC\\ tdlRDl RXD data valid time 1/2 telC) tdISB-TD) Start of SCLK sample to new TXD data 31/4 t elC) tt!ISF_TDl End of SCLK sample to new TXD data 21/4 t "Ir.\\ tdICL-S) Clockout low to SCLK transition t elC) UNIT ns ns ns ns UNIT ns ns ns ns ns

TMS7000 Assembly Language instructions are mnemonic operation codes (or mnemonics) that correspond directly to binary machine instructions. An as­ sembly language program (source program) must be converted to a machine language program (object program) by a process called assembling before a computer can execute it. Assembling converts the mnemonics to binary values and associates those values with binary addresses, creating machine language instructions. Assembler directives, discussed in Section 5.5, control this pro­ cess, place data in the object program, and assign values to the symbols used in the object program. TMS7000 assembly language is processed by a two-pass Macro Assembler that executes on a host computer. During the first pass the assembler: 1) Maintains the Location Counter, 2) Builds a symbol table, and 3) Produces a copy of the source code. During the second pass the assembler: 1) Reads the copy of the source code and 2) Assembles the object code using the opcodes and symbol table pro­ duced during the first pass. This section discusses the following topics: Section Page 5-1

The TMS7000 Assembler - Source Statement Format

5.1 Source Statement Format

An ~ssembly language source program consists of source statements that may contain assembler directives, machine instructions, pseudo-instructions, or comments. Source statements may contain four ordered fields - label, com­ mand, operand, and comment. Source statements that have an asterisk (*) in the first character position are comments and do not affect the assembly. The syntax for source statements other than comment lines is: [<label>] <mnemonic> [<operand>] [<comment>] where:

• The label and comments fields are optional.
• One or more blank spaces must separate each field.
• A statement must start with either a label or a blank space. Note that square brackets ([ and]) indicate an optional entry. Figure 5-1 illustrates one method of entering source statements. labels begin in column 1, opcodes in column 8, operands in column 14, and comments in column 26. The assembler produces the three left hand numbers. The first is the statement number, the second shows the .program address, and the third shows the data value. lOT CLR LABELl MOVP BTJZ END 'EXAMPLE' B P4,A %Ol,A,LABELl Figure 5-1. Source Statement Format

The TMS7000 Assembler - Source Statement Format

5.1.1 Label Field

The label field is optional for machine instructions and for many assembler directives. If it is not used, the first character position must contain a blank. The label begins in the first character position of the source statement and extends to the first blank. It contains a symbol of up to 6 alphanumeric char­ acters; the first character must be a letter. A source statement that contains only a label field is a valid statement. It as- signs the current value of the location counter to the label, which is equivalent _ to the following directive statement: <label> EQU $

5.1.2 Command Field

The command field begins after the blank that terminates the label field. It is terminated by one or more blanks and may not extend past the right margin. If the label is omitted, the command can start in the second character position. The command field can contain one of the following opcodes:

• Machine-instruction mnemonic
• User-defined instruction
• Assembler directive

5.1.3 Operand Field

The operand field begins following the blank that ends the command field. It may not extend past the right margin of the source record. The operand field may contain one or more constants or expressions (described in Section 5.2 and Section 5.4) separated by commas. It is terminated by one or more blanks. 5.1 .4 Comment Field The comment field begins after the blank that terminates the operand field (or the blank that terminates the command field, if there are no operands). The comment field can extend to the end of the source record, if required, and can contain any ASCII character including blanks. The comment field contents (up to the end of the input record) are listed in the assembly source listing but do not affect the assembly. 5-3

The TMS7000 Assembler - Constants

5.2 Constants

The assembler recognizes five types of constants, each internally maintained as a 16-bit quantity:

• Decimal integer constants
• Binary integer constants Hexadecimal integer constants Character constants
• Assembly-time constants

5.2.1 Decimal Integer Constants

Decimal integer constants are written as strings of decimal digits, ranging from -32,768 to +65,535. Positive decimal integer constants in the range 32,768 to 65,535 are considered negative when interpreted by functions needing 2's complement values. These are valid decimal constants: 1000 -32768 65535 Constant equal to 1000 or > 3E8 Constant equal to -32768 or >8000 Constant equal to 25 or >19 Constant equal to 65535 to >FFFF

5.2.2 Binary Integer Constants

Binary integer constants are written as strings of up to 16 binary digits (0/1) preceded by a question mark (7). If less than 16 digits are specified, the as­ sembler right justifies the bits. These are valid binary constants:

700010011 Constant equal to 19 or >13

70111111111111111 Constant equal to 32767 or > 7FFF

711110 Constant equal to 30 or >001 E

The TMS7000 Assembler - Constants

5.2.3 Hexadecimal Integer Constants

Hexadecimal integer constants are written as strings of up to four hexadecimal digits preceded by a greater than sign (». Hexadecimal digits include the decimal values '0' through '9' and the letters 'A' through T. These are valid hexadecimal constants: >78 >37AC

5.2.4 Character Constants

Character constants are written as strings of one or two alphabetic characters enclosed in single quotes. Two consecutive single quotes are required to re­ present a single quote in a character constant. The characters are represented internally as 8-bit ASCII characters. A character constant consisting of only two single quotes (no letter) is valid and is assigned the value >0000. These are valid character constants: 'AS' 'c' 'N' '''0' Represented internally as > 4142 Represented internally as >43 or >0043 Represented internally as >4E or >004E Represented internally as >2744

5.2.5 Assembly-Time Constants

Assembly-time constants are symbols assigned values by an EQU directive (see the EQU directive). The symbol value is determined at assembly time. It is considered to be absolute or relocatable according to the relocatability of the expression, not according to the relocatability of the Location Counter value. Absolute value symbols may be assigned values with expressions using any of the above constant types. 5-5

The TMS7000 Assembler - Symbols 5,3 Symbols Symbols are used in the label field and the operand field. A symbol is a string of alphanumeric characters (A-Z, 0-9, and $). The first character in a symbol must be A-Z or $. No character may be blank. When more than six characters are used in a symbol, the assembler prints all the characters, but only recog­ nizes the first six characters during processing (the assembler also prints a symbol truncation warning). Therefore, the first six characters of a symbol should be unique. User-defined symbols are valid only during the assembly in which they are defined. Symbols used in the label field become symbolic addresses. They are associ­ ated with locations in the program and must not be used in the label field of other statements. Mnemonic opcodes and assembler directive names may be used as valid user-defined symbols in the label field. Symbols used in the operand field must be defined in the assembly, usually by appearing in the label field of a statement or in the operand field of a REF or SREF directive. These are examples of valid symbols: START ADD OPERATION Each of these symbols will be assigned the value of the location where it ap­ pears -in the label field. Note that the symbol OPERATION will be truncated to OPERAT. 5,3,1 Predefined Symbols 5-6 The dollar sign ($), register (Rn), and port (Pn) symbols are predefined. The dollar sign represents the current value of the location counter. Register and port symbols are in the form Rn and Pn, respectively, where n is a constant in the range 0-255. All registers and peripheral file addresses should be defined before they are used in instructions. These are examples of valid predefined symbols: RO P22 The current location Register 0 Peripheral Register 22 The symbol ST (Status Register) is reserved and may not be re-defined.

The TMS7000 Assembler - Symbols

5.3.2 Terms

Terms are used in the operand field of machine instructions and assembler directives. A term may be a binary, character, decimal or hexadecimal con­ stant, an absolute assembly-time constant or a label having an absolute value.

5.3.3 Character Strings

Several assembler directives require character strings as operands. A character string is a string of characters enclosed in single quotes. Single quotes within _ a character string are represented by two consecutive single quotes. The maximum length of a string is defined for each directive that requires a char- acter string; The characters are represented internally as 8-bit ASCII charac- ters. These are valid character strings: 'SAMPLE PROGRAM' Defines a 14-character string, SAMPLE PRO­ GRAM 'PLAN "C'" Defines an 8-character string, PLAN 'C' 'OPERATOR MESSAGE: PRESS START SWITCH' Defines a 37-character string, OPERATOR MES­ SAGE: PRESS START SWITCH 5-7

The TMS7000 Assembler - Expressions

5.4 Expressions

Expressions are used in the operand fields of assembler directives and machine instructions. An expression is a constant or symbol, a series of constants or symbols, or a series of constants and symbols separated by arithmetic opera­ tors. Each constant or symbol may be preceded by a unary minus sign (-), a unary plus sign (+), or the unary invert symbol (#). The # symbol causes the value of the logical complement of the following constant or symbol to be used. An expression may not contain embedded blanks. Symbols defined as external references may be operands of arithmetic instructions within certain limits, as described in Section 5.4.1.

5.4.1 Arithmetic Operators in Expressions

The arithmetic operators used in expressions are: Addition Subtraction Multiplication Signed division Logical not (inversion) When the assembler evaluates an expression, it first negates symbols or con­ stants preceded by a minus (-) sign and then performs arithmetic operations from left to right. The assembler does not assign precedence to any operation other than unary plus or unary minus. All operations are integer operations; any fractions produced by division are truncated. For example, the expression 4+5*2 is evaluated as 18, not 14. The expression 7+1/2 is evaluated as 4; the expression 1/2+7 is evaluated as 7 (note trun­ cation). The assembler checks for overflow conditions when arithmetic operations are performed. It issues a warning message when an overflow occurs or when the sign of the result is not as expected in respect to the operands and the operation performed. Examples where a "VALUE TRUNCATED" message is given are: -2*>4000 >8000*2 >FFFE+2 ->8000-1 -1*>8001 -2*>8000 When the immediate value is greater than >7F and you precede the value with %#, signifying immediate and unary negation operations, the assembler cor­ rectly calculates the value but issues an error message. Ignore the EX­ PRESSION OUT OF BOUNDS error message. (Note that this problem has been fixed in version 2.3 of the assembler.) The following example illustrates this condition.

The TMS7000 Assembler - Expressions 5.4.2 TEST TMS7000 MACRO ASSEMBER PAGE 0001 0001 * 0002 * DX-10 X-SUPPORT TEST SOFTWARE 0003 *

0004 IDT 'TEST'

0005 FOOO AORG >FOOO

0006 FOOO 52 MOV %> 10, B

0007 F002 OD LDSP

0008 F003 01 IDLE

0009 F004 28 ADD %#>40,A

0010 F006 28 ADD %#>7F,A

0011 F008 28 ADD %#>80,A

0012 END

0001 ERROR, 0000 WARNINGS, LAST ERROR AT 001l

Logical Operands in Expressions If a pound sign (#) precedes a number or an expression it is complemented. All other arithmetic operations have precedence over the logical not (#) op­ eration, except where modified by parentheses.

5.4.3 Parentheses in Expressions

Use parentheses to alter the order of expression evaluation. Parenthetical ex­ pressions can be nested up to eight levels. The portion of an expression within the innermost parentheses is evaluated first. then the next innermost pair is evaluated, etc. When all parenthetical phrases have been evaluated, the expression is evaluated from left to right. Evaluation of parenthetical phrases at the same nesting level may be considered to be simultaneous. This expression is evaluated as follows: LAB1 +«4+3)*7) 1) Add 4 to 3 2) Multiply 7 by 7 3) Add the value of LAB1 to 49 5-9

The TMS7000 Assembler - Expressions

5.4.4 Well-Defined Expressions

Some assembler directives require well-defined expressions in operand fields. Well-defined expressions contain only symbols or assembly-time constants that are defined before they are encountered in the expression. The evaluation of a well-defined expression must be absolute. A well-defined expression must not contain a character constant.

5.4.5 Relocatable Symbols in Expressions

An expression that contains a relocatable symbol or relocatable constant im­ mediately following a multiplication or division operator is illegal. When the result of evaluating an expression up to a multiplication or division operator is relocatable, the expression is illegal. If the current value of an expression is relocatable with respect to one relo­ eatable section, a symbol of another section may not be included until the value of the expression becomes absolute. Some examples of relocatable symbols used in expressions are: BLUE+1 GREEN-4 2*16+RED 440/2-RED The sum of the value of symbol BLUE plus one. The result of subtracting four from the value of symbol GREEN. The sum of the value of symbol RED plus the product of two and 16. The result of dividing 440 by two and subtracting the value of symbol RED from the quotient. RED must be absolute. Table 5-1 defines the relocatability of the result for each type of operator. Table 5-1. Results of Operations on Absolute and Relocatable Items in Expressions A B A+B A-B AxB AlB ABS ABS ABS ABS ABS ABS(B<>O) ABS RELOC RELOC illegal t illegal RELOC ABS RELOC RELOC :j: § RELOC RELOC illegal ". illegal illegal t Illegal unless A equals zero or one. If A is one, the result is relocatable. If A is zero, the result is an absolute zero. :1: Illegal unless B equals zero or one. If B is one, the result is relocatable. If B is zero, the result is an absolute zero. § Illegal unless B eq!,lals one. If B equals one, the result is relocatable. ". Illegal unless A and B are in the same relocatable segment. If A and B are in the same section, the result is absolute. 5-10

The TM S7000 Assembler - Expressions

5.4.6 Externally Defined Symbols in Expressions

Externally defined symbols (defined in REF and SREF directives) are allowed in expressions under the following conditions: 1) Only one externally referenced symbol may be used in an expression. The character preceding the referenced symbol must be a plus sign, a blank, or a comma (the @ sign is not considered). The portion of the expression preceding the symbol, if any, must be added to the symbol. The portion of the expression following the referenced symbol must not include multiplication, division, or logical operations on the symbol (as for a relocatable symbol described in Section 5.4.5). 4) The remainder of the expression following the referenced symbol must be absolute. The assembler limits the total number of external referenced symbols to 255 per module. Modules using more than 255 external symbols must be broken into smaller modules for assembly and linked using the link editor. 5-11

The TMS7000 Assembler - Assembler Directives

5.5 Assembler Directives

Assembler directives control the assembly process. This section discusses the various categories of directives supported by the TMS7000 Assembler and defines the directives in alphabetical order. Directives that Affect the Location Counter As the assembler reads program source statements it increments its Location Counter. The Location Counter contents correspond to the memory locations assigned to the resulting object code. Twelve directives, listed in Table 5-2 on page 5-13, affect the Location Counter. BES and BSS advance the Lo­ cation Counter to provide a block of program memory for the object code. The EVEN directive ensures an even address word boundary. The remaining nine directives initialize the Location Counter and define its value as relocata­ ble, absolute, or dummy. Directives in this category include: - AORG BES BSS CEND CSEG DEND DORG DSEG EVEN Directives that Affect Assembler Output PEND PSEG RORG Directives that affect assembler output are mainly used to improve program useability. The IDT directive supplies a program identifier; the five other di­ rectives affect the source listing. IDT LIST - OPTION PAGE - TlTL UNL .' Directives that Initialize Constants These directives assign values to successive bytes or words of the object code (BYTE, DATA), place text characters in object code for display purposes (TEXT), or initialize constants to be used during the assembly (EQU). BYTE DATA EQU - TEXT Directives for Linking Programs The Link Editor resolves externally referenced symbols and definitions. These directives help the Link Editor by identifying symbols and definitions that may be used or defined by another program module. This allows separate program modules to be assembled separately and integrated into an executable pro­ gram. DEF - LOAD REF - SREF Miscellaneous Directives This category includes those assembler directives not applicable to the other categories: - COpy - END MLIB

The TMS7000 Assembler - Assembler Directives Table 5-2. Summary of Assembler Directives DIRECTIVES THAT AFFECT THE LOCATION COUNTER MNEMONIC DIRECTIVE SYNTAX BES Block ending with symbol [<label>] BES <wd-exp> [<comment> ] BSS Block starting with symbol [<label>] BSS <wd-exp> [<comment>] CEND Common segment end [<label>] CEND [<comment>] CSEG Common segment [<label>] CSEG ['<string>' [<comment>]] DEND Data segment end [<label>] DEND [<comment>] -DORG Dummy origin [<!abel>] DORG [<exp> [<comment>]] DSEG Data segment [<label>] DSEG [<comment> ] EVEN Even boundary [<label> ] EVEN [<comment>] PEND Program segment end [<label>] PEND [<comment> ] PSEG Program segment [<label>] PSEG [<comment>] RORG Relocatable origin [<label>] RORG [<exp> [<comment>]] DIRECTIVES THAT AFFECT ASSEMBLER OUTPUT MNEMONIC DIRECTIVE SYNTAX lOT Program identifier [<label> ] IDT '<string>' [<comment>] LIST Restart source listing [<label>] LIST [<comment>] OPTION Output options [<label>] OPTION <option list> [<comment>] PAGE Page eject [<label>] PAGE [<comment> ] TITL Page title [<label>] TITL '<string>' [<comment> ] UNL Stop source listing [<label>] UNL [<comment>] DIRECTIVES THAT INITIALIZE CONSTANTS MNEMONIC DIRECTIVE SYNTAX BYTE Initialize byte [<label> ] BYTE <exp>[,<exp>] [<comment>] DATA Initialize word [<label>] DATA <exp>[,<exp>] [<comment>] EQU Define assembly-time [<label>] EQU <exp> [<comment>] constant TEXT Initialize text [<label>] TEXT [-)' <string>' [<comment>] DIRECTIVES FOR LINKING PROGRAMS MNEMONIC DIRECTIVE SYNTAX DEF External definition [<label> ] DEF <symbol>[, <symbol>] [<comment>] LOAD Force load [<label> ] LOAD <symbol> [, <symbol> ] [<comment> ] REF External reference [<label>] REF <symbol> [,<symbol>] [<comment>] SREF Secondary external [<label>] SREF <symbol> [,<symbol>] [<comment>] reference MISCELLANEOUS DIRECTIVES MNEMONIC DIRECTIVE SYNTAX COPY Copy source file [<label> ] COpy <filename> [<comment> ] END Program end [<label>] END [<symbol> [<comment>]] MUB Define macro library [<label>] MUB ' <pathname>'. [<comment>] 5-13

_ Description Example 7 Example 2 5-14 Absolute Origin Directive [<Iabelt>] AORG [<wd-exp> [<comment>]] Label Optional; if used, the label is assigned the same value that AORG places in the Location Counter. Operand Optional; if used, the operand field must contain a well-de­ fined expression «wd-exp». Comment Optional; may only be used with the operand field. AORG loads the Location Counter with the first address of a segment of absolute code. This address is usually specified by the operand. If no op­ erand is used, the value in the Location Counter equals the length of all preceding absolute code. When no AORG directive is entered, the object program does not include absolute addresses. AORG >lOOO+X Symbol X must be absolute and previously defined. If X has a value of 6, the Location Counter is set to >1006. If a label had been included, it would have been assigned the value >1006. Avoid using AORG in object modules which will be linked. Linking a mo­ dule that contains an AORG directive may produce an II/ega/ immediate tag . encountered error at link time. Use the PSEG, CSEG, and DSEG directives instead to identify the locations in the source code. Use the PROGRAM, COMMON, and DATA commands in the link control file to define the lo­ cations. The link control file will look similar to this example: TASK PROGRAM DATA COMMON INCLUDE INCLUDE END MYPROG >F006 >FFDO FILEl FILE2 Program starting point (PSEG) Trap and vector table stg pt (DSEG) Additional starting location (CSEG)

Block Ending with Symbol Directive BES Syntax Fields [<label>] BES <wd-exp> [<comment>] Label Optional; if used, the label is assigned the value of the lo­ cation following the block. Operand Contains a well-defined expression that represents the num ber of bytes to be added to the Location Counter. Comment Optional Description BES increments the Location Counter by the operand value. Example 1 BUFF2 BES >10 A 16-byte buffer is reserved. If the Location Counter had contained >100 when the directive was processed, BUFF2 would have been assigned the value >110. 5-15

_ Description Example 5-16 Block. Starting with Symbol Directive [<label>] BSS <wd-exp> [<comment>] Label Optional; if used, a label is assigned the value of the location of the first byte in the block. Operand Contains a well-defined expression that represents the num- berof bytes to be added to the Location Counter. Comment Optional BSS increments the Location Counter by the operand value. Avoid using the BSS directive for defining register names. Using BSS in this manner may produce a Pass 1 /Pass2 operand conflict error at assembly time. Use the EOU directive for defining register names. BUFFl BSS 80 Card input buffer, An 80-byte buffer is reserved starting at location BUFF1.

Initialize Byte Directive BYTE Syntax Fields

Description

[<label>] BYTE <exp> [.<exp>] [<comment>] Label Operand Optional; if used, the label is assigned the location where the assembler places the first byte. Contains one or more expressions separated by commas. These expressions cannot contain external references. The assembler evaluates each expression and places the value in a byte as an 8-bit number. If truncation is required, the as- sembler prints a truncation warning message and puts the 8 _ LSbs of the value in the byte. Comment Optional BYTE places one or more values in one or more successive bytes of mem­ ory. KONS BYTE >F+l,-l,'D'-'=',O,'AB'-'AA' This example initializes five bytes, starting with a byte at location KONS. The contents of the resulting bytes are 00010000, 11111111, 00000111, 00000000, and 00000001. 5-17

Common Segment End Directive [<label>] CEND [<comment>] Label Optional; if used, the label is assigned the value of the Lo­ cation Counter before modification. Operand Not used Comment Optional CEND terminates the definition of a block of common-relocatable code by placing a value in the Location Counter and defining succeeding locations as program-relocatable. The Location Counter is set to one of the following values:

• The maximum value the Location Counter has ever attained by as­ sembling any preceding block of program-relocatable code.
• Zero, if no prograin-relocatable code was previously assembled. If encountered in data-or program-relocatable code, this directive functions as a DEND or PEND. CEND is invalid when used in absolute code.

Copy Source File Directive COpy Syntax Fields [<label>] COpy <filename> [<comment>] Label Operand Optional Names a file that source statements are read from. The file name may be:

• An access name recognized by the operating system
• A synonym form of an access name Comment Optional COpy changes the source input for the assembler. A COpy directive may be placed in a file being copied. Nested copying of files can be performed by placing a COpy directive in a file being copied. The assembler limits such nesting to eight levels; the host operating system may place additional restrictions on nesting capabilities. COpy SFILE This example causes the assembler to take its source statements from a file SFILE. At the end-of-file for SFILE, the assembler resumes processing source statements from the file or device previous to the COpy directive. 5-19

[<label>] CSEG ['<string>'[,<exp>] [<comment>]] Label Optional; if used, the label is assigned the value placed in the Location Counter. Operand Optional (see preceding Description). Comment Optional; may only be used with the operand field. CSEG begins or continues a common-relocatable segment (relocatable with respect to a common segment) at the address in the Location Counter. If the operand is not used, the CSEG directive defines the beginning of (or continuation of) the blank common segment of the program. When used, the operand field contains a character string of up to six char­ acters enclosed in quotes. (The assembler truncates strings that are longer than s.ix characters and prints a truncation error message.) If this string did not previously appear as the operand of a CSEG directive, the assembler: 1 ) Associates a new relocation section number with the operand, 2) Sets the Location Counter to zero, and 3) Defines succeeding locations as relocatable with respect to the new relocatable section. If the operand string was previously used in a CSEG, the succeeding code represents a continuation of the particular common segment associated with the operand. The Location Counter is restored to the maximum value attained during the previous assembly of any portion of that particular common segment. The second operand, <exp>, specifies the memory alignment for the beginning of the Section. Common-relocatable code is normally terminated by a CEND directive, but can also be terminated by the PSEG, DSEG, AORG, and END directives. The CEND and PSEG directives define succeeding locations as program­ relocatable. The DSEG and AORG directives terminate the common seg­ ment by beginning a data or an absolute segment. The END directive terminates the common segment and the program. The CSEG directive permits construction and definition of independently relocatable segments of data that several programs can access or reference at execution time. Information placed in the object code by the assembler permits the link editor to relocate all common segments independently and make appropriate adjustments to all addresses that reference locations within common segments. Locations within a common segment may be referenced by several different programs if each program contains a CSEG directive with the same operand or no operand.

Common Segment Directive CSEG Example COMIA CSEG 'ONE' <Common-relocatable section, type 'ONE'> COM2A CEND CSEG 'TWO' <Common-relocatable section, type 'TWO'> COM2B COMIC CEND CSEG 'ONE' <Common-relocatable section, type 'ONE'> CEND COMIB COMIL COM2L DATA COMIB-COMIA LENGTH OF SEGMENT 'ONE' DATA COM2B-COM2A LENGTH OF SEGMENT 'TWO' The three blocks of code between the CSEG and CEND directives are common -relocatable. The first and third blocks are relocatable with respect to one common relo­ cation type; the second is relocatable with respect to another. The first and third blocks comprise the common segment 'ONE'; the value of the symbol COM1 L is the length in bytes of this segment. The symbol COM2A is the symbolic address of the first word of the first word of common segment TWO'; COM2B is the common-relocatable (type 'TWO') byte address of the location following the segment. (Note that the symbols COM2B and COM1 C are of different relocation types and possibly different values.) The value of the symbol COM2L is the length in bytes of common segment 'TWO'. 5-21

_ Description Example Example TEST 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 0020 0021 0000 0000 0002 0004 0006 0008 OOOA oooe OOOE 0010 0012 0014 0014 0014 0016 0018 001A 001C Initialize Word Directive [<label>] DATA <exp>[,<exp>] [<comment>] Label Optional; if used, the label is assigned the location where the assembler places the first word. . Operand Contains one or more expressions separated by commas. The assembler evaluates each expression and places the value in a word as a 16-bit number. Words are stored most significant byte first, i.e., at the lower address. Comment Optional DATA places one or more values in one or more successive 2-byte words of memory. KONS1 DATA 3200,1+'AB',-'AF',>F4AO,'A' This example initializes five words, starting with a word at location KONS1. The contents of the resulting words are >OC80, >4143, >BEBA. >F4AO,· and >0041. In a DATA directive statement with an operand of multiple fields, the as­ sembled value of the location counter symbol ($) will not be correctly calculated if the $ is not in the first field (i.e., a correct value will be calcu­ lated for $ if it is in the first field of the DATA statement.) lhe following example shows both cases. This example is for assembler revision 2.1 .

7000 FAMILY MACRO ASSEMBLER

DX2.1 . 83.074 15:23:38 0001 0009 0008 0004' 0006' 0008 0009 OOOF' 0008 0008 0015' PAGE IDT DATA DATA DATA DATA DATA DATA DATA 'TEST $' $ $,8,9 $+3,7+1 7+1 $+3 CORRECT VALUE FOR $$ CORRECT VALUE FOR CORRECT VALUE FOR $ CORRECT VALUE FOR $

0009 DATA 9,8,$

INCORRECT VALUE FOR $ 0014'

0008 DATA 7+1,$+3

001D' INCORRECT VALUE FOR $

0022 END

NO ERRORS, NO WARNINGS 5-22

External Definition Directive DEF Syntax Fields [<label>] DEF <symbol> [.<symbol>] [<comment>] Label Optional; if used, the label assumes the current value of the Location Counter. Operand Contains one or more symbols, separated by commas, to be defined in the program being assembled. Comment Optional Description DEF makes one or more symbols available to other programs for reference. _ All symbols used in the DEF statement must be defined in the same module. Example 1 DEF ENTER,ANS This example causes the assembler to include symbols ENTER and ANS in the object code; these symbols are available to other programs. 5-23

Data Segment End Directive [<data>] DEND [<comment>] label Optional; if used, the label is assigned the value of the Lo­ cation Counter before modification. Operand Not used Comment Optional DEND terminates a block of data-relocatable code and defines succeeding locations as program-relocatable. One of two values is placed in the Lo­ cation Counter: 1) The maximum value attained by the Location Counter as a result of assembling the preceding block of program-relocatable code 2) Zero, if no program-relocatable code was previously assembled If encountered in common-relocatable or program-relocatable code, DEND functions as a CEND or PEND, and the assembler issues a warning mes­ sage. Like CEND and PEND, DEND is invalid in absolute code.

Dummy Origin Directive DORG Syntax Fields [<label>] DORG [<exp> [<comment>]] Label Operand Optional; when used, the label is assigned the same value that is placed in the Location Counter. Optional; when used, it contains an expression <exp> that can be either absolute or relocatable. Any symbol in the ex- pression must have been previously defined. When the operand field is absolute, the. Location Counter is assigned the absolute value. When the operand is relocatable, _ the Location Counter is assigned the relocatable value and the same relocation type as the operand. When this occurs, space is reserved in the section that has that relocation type. Comment Optional Description DORG loads the Location Counter with the beginning address of a dummy block or section. This address is specified by the operand. The assembler does not generate code for a dummy section, but operates normally in all other respects. The symbols that describe the dummy section layout are available when the remainder of the program is assembled. Example 1 Example 2 DORG 0 The assembler assigns values relative to the start of the dummy section to the labels within the dummy section. This example is appropriate for de­ fining a data structure. The executable portion of the module (following the RORG directive) should use the labels of the dummy section as relative addresses. In this manner, the data is available to the procedure regardless of the memory area into which the data is loaded. RORG 0 (code as desired) DORG $ (data segment) END This is appropriate for the executable portion (procedure division) of a procedure that is common to more than one task. The coc;je corresponding to the dummy section must be assembled in another program module. In this manner, separate data portions (dummy sections) are available to the procedure portion. The DORG directive may also be used with data-relocatable or common­ relocatable operands to specify dummy data or common segments. 5-25

CSEG 'COM1' DORG $ DATA $ DATA >FOOO CEND n$n has a common-relocatable value In this example, no object code is generated to initialize the common seg­ ment COM1, but space is reserved and all common-relocatable labels de­ scribing the structure of the common block (including LAB1 and MASK) are available for use throughout the program.

Data Segment Directive DSEG Syntax Fields [<label>] DSEG [<comment>] Label Optional; if used, the label is assigned the data-relocatable value placed in the Location Counter. Operand Not used Comment Optional DSEG begins a block of data-relocatable code at the address in the Lo- cation Counter. Data-relocatable blocks comprise the data segment of a _ program. The data segment can be relocated independently of the program segment at link-edit time. This separates modifiable data from executable code. A data-relocatable block is normally terminated by a DEND directive. It can also be terminated by a PSEG, CSEG, AORG, or END directive. The PSEG and DEND directives identify succeeding locations as program-relocatable. The CSEG and AORG directives terminate the data segment by beginning a common or an absolute segment, respectively. The END directive termi­ nates the data segment and the program. The Location Counter is initially set to zero. RAM DSEG Start of data area <Data-relocatable code> ERAM DEND LRAM EQU ERAM-RAM The block of code between the DSEG and DEND directives is data-relo­ eatable. RAM is the symbolic address of the first word of this block; ERAM is the data-relocatable byte address of the location following the code block. The value of the symbol LRAM is the length in bytes of the block. 5-27

[<label>] END [<symbol> [<comment>]] label Operand Optional; if used, the label assumes the current value of the Location Counter. Optional; when used, the operand contains a program-relo­ eatable or absolute symbol that specifies the program entry- point. If the operand is not used, no entry point is placed in the object code. Comment Optional; may only be used with the operand field. Description END terminates the assembly. It should be the last source statement of a program. Any source statements following the END directive are considered part of the next assembly. Example 5-28 END START This example terminates program assembly. The assembler also places the value of START in the object code as an entry point.

Define Assembly-Time Constant Directive EQU Syntax Fields Label A symbol that will be assigned the operand's value. Operand An expression whose value is assigned to the label. Comment Optional Description EOU assigns a value to a symbol. Example Example Note: <exp> may not contain a REF'd symbol or forward references. SUM EQU R5 This example assigns an absolute value to the symbol SUM, making SUM available to use as a register address. A register should always be defined before it is used. TIME EQU HOURS This example assigns the value of the previously defined symbol HOURS to the symbol TIME. When HOURS appears in the label field of a machine instruction in a relocatable block of the program, the value is a relocatable value. The two symbols may be used interchangeably. Symbols in the operand field must be previously defined. 5-29

[<label>] EVEN [<comment>] Label Optional; if used, the label is assigned the value in the Lo­ cation Counter after the directive is processed. Operand Not used Comment Optional EVEN places the Location Counter on the next word boundary (even byte address). When the Location Counter is already on an even boundary, the Location Counter is not altered. WRFl EVEN Assures that the Location Counter contains an even boundary address and assigns the Location Counter address to label WRF1.

Program Identifier Directive lOT Syntax Fields [<label>] lOT '<string>' [<comment>] Label Optional; if used, the label is assigned the current value of the Location Counter. Operand Contains the module name <string>, a character string of up to eight characters enclosed in single quotes. The assembler truncates strings that are longer than eight characters and prints a truncation error message. Comment Optional lOT assigns a name to the object module produced. IDT 'CONVERT' This example assigns the name CONVERT to the module being assembled. The module name is printed in the source listing as the operand of the lOT directive and appears in the page heading of the source listing. The module name is also placed in the object code and is used by the link editor for automatic entry-point resolution. A routine whose entry point is to be au­ tomatically resolved by the link editor must be declared as the 'string' on the lOT statement for that module. The entry point must also be REF'd in this case. Note: Although the Assembler accepts lowercase letters and special charac­ ters within the quotes, ROM loaders (for example) will not. Therefore, only uppercase letters and numerals are recommended. 5-31

Restart Source Listing Directive [<label>] LIST [<comment>] Label Optional; if used. the label assumes the current value of the Location Counter. Operand Not used Comment Optional; if used. the assembler does not print the comment. LIST restores printing of the source listing after it was cancelled by a UNL directive. This directive is not printed in the source listing. but the line counter increments.

[<label>] LOAD <symbol> [. <symbol>] [<comment>] Label Optional Operand Contains one or more symbols, separated by commas, to be used in the operand field of a subsequent source statement. Comment Optional The LOAD directive is like a REF, but the symbol does not need to be used in the module containing the LOAD. The symbol used in the LOAD must be defined in some other module. LOADs are used with SREFs. If one­ to-one matching of LOAD and DEF symbols does not occur, then unre­ solved references will occur during link editing. MODULEA1 LOAD C. 0 MODULE C MODULEA2. LOAD C MODULES SREF C, D. Eo F OATAC OATAD OATAE OATAF MODULE 0 MODULEE MODULEA3 LOAD Eo F MODULEF

• Module A1 uses a branch table in module B to obtain one module C, 0, E, or F.
• Module A1 knows which of module C, 0, E, and F it requires.
• Module B has an SREF for C, 0, E, and F.
• Module C has a OfF for C.
• Module 0 has a DEF for D.
• Module E has a DEF for E.
• Module F has a DEF for F.
• Module A1 has a LOAD for the modules C and 0 it needs.
• Module A2 has a LOAD for the module C it needs.
• Module A3 has a LOAD for the modules E and F it needs. 5-33

The LOAD and SREF directives permit module B to be written to handle a highly involved case and still be linked together without unnecessary mo­ dules since A1 only has LOAD directives for the modules it needs. When a link edit is performed, automatic symbol resolutions will pull in the modules appearing in the LOAD directives. If the link control file included A1 and A2, modules C and D would be pulled in while modules E and F would not be pulled in. If the link control file included A3, modules E and F would be pulled in while modules C and D would not be pulled in. If the link control file included A2, module C would be pulled in while modules D, E, and F would not be pulled in.

Define Macro Library Directive MUS Syntax Fields [<label>] MUB '<pathname>' [<comment>] Label Optional; if used, the label assumes the current value of the Location Counter. Operand Contains the pathname, a character string of up to 48 char­ acters enclosed in single quotes. Longer strings produce truncation error messages. Comment Optional The MUB directive provides the assembler with the name of a library con­ taining macro definitions. The operand is a directory path name (con­ structed according to the host operating system conventions) enclosed in single quotes (see lOT and TITL directives). This directive is defined only for hosts that support libraries on hard disks. Note: Neither the assembler nor its runtime support have access to the oper­ ating system's synonym table, and so cannot expand pathnames. The use of synonyms prevents finding any macros in that library. MLIB 'MYVOLUME.MACDIR.CMPXMACS.NEWMACS' MLIB 'USER32.BIGPROJ.MYTASK.MACROS' This example causes the macro function, when the program finds a macro call SUBMAC (not previously defined), to search first for a file named USER32.BIGPROJ.MYTASK.MACROS.SUBMAC, and then if that file isn't found, to search for a file named MYVOLUME. MACDIR.­ CMPXMACS . NEWMACS . SUBMAC, in that order. On a VAXNMS system, a pathname would be specified as follows: MLIB'DRCO:[MOORE.ASM32]' The following program segment illustrates macro library use for an MS/PC-DOS system. MLIB 'E:' Pathname must be a drive name Typical assembly code XMAC YMAC END First macro call Another macro call The assembler will search the drive specified by the MUB directive for a file with the same name as the macro. The macro name cannot have an ex­ tension. Only one macro is allowed per file. 5-35

OPTION <ciption-list> Label Not used Operand <option-list> (see preceding Description) Comment Not used OPTION selects several options for the assembler listing output. The <op­ tion-list> operand is a list of keywords separated by commas. Each key­ word selects one of the following listing features: BUNLST: DUNLST: TUNLST: FUNLST: XREF: NOLlST: SYMLST: Limit the listing of BYTE directives to one line Limit the listing of DATA directives to one line Limit the listing of TEXT directives to one line Turn off all unlist options Produce a symbol cross-reference listing Inhibit all listing output (this overrides the LIST directive) Produce a symbol listing in the object file, no symbols are put in the listing file

[<p'age>] PAGE [<comment>] Label Optional; if used, the label assumes the current value of the Location Counter. Operand Not used Comment Optional; if used, the assembler does not print the comment. PAGE prints the source program listing on a new page. The PAGE directive is not printed in the source listing, but the line counter increments. _ PAGE The assembler begins a new page of the source listing. The next source statement is the first statement listed on the new page. Using the PAGE directive to separate source listing into logical divisions improves program documentation. 5-37

Program Segment End Directive [<label>] PEND [<comment>] Label Optional; if used, the label is assigned the value of the Lo­ cation Counter before modification. Operand Not used Comment Optional The PEND directive is the program-segment counterpart of the DEND and CEND directives. It begins a section of program-relocatable code at the address in the Location Counter. The value placed in the Location Counter is the maximum value it attained by assembling all preceding program-re­ locatable code. It is invalid when used in absolute code.

Program Segment Directive PSEG Syntax Fields [<label>] PSEG [<comment>] Label Optional; if used, the label is assigned the value placed in the Location Counter. Operand Optional Comment Optional PSEG begins a program-relocatable segment at the address in the Location Counter. The Location Counter is set to one of the following values: _

• The maximum value the Location Counter has attained by assembling any preceding block of program>relocatable code.
• Zero, if no program-relocatable code was previously assembled. The PSEG directive is the program-segment counterpart of the DSEG and CSEG directives. Together, the three directives provide a consistent method of defining the various types of relocatable segments. The following se­ quences of directives are functionally equivalent. SEQUENCE 1 SEQUENCE £ DSEG DSEG <Data-relocatable code> <Data-relocatable code> DEND CSEG CSEG <Common-relocatable code> <Common-relocatable code> CEND PSEG PSEG <Program-relocatable code> <Program-relocatable code> PEND END END 5-39

External Reference· Directive «label>] REF <symbol> (.<symbol>] «comment>] Label Optional; if used, the label assumes the current value of the Location Counter. Operand Contains one or more symbols, separated by commas, to be used in the operand field of a subsequent source statement. Comment Optional REF pro.vides access to one or more symbols defined in other programs. If a symbol is listed in the REF statement, then a corresponding symbol must also be present in a DEF statement in another source module. If the symbol is not defined in another module, then an error occurs at link edit time. The system generates a summary list of all unresolved references. REF ARG1,ARG2 This example causes the assembler to include symbols ARG1 and ARG2 in the object code so that the corresponding addresses may be obtained from other programs.

Relocatable Origin Directive RORG Syntax Fields [<label>] RORG [<exp> [<comment>]] Label Operand Optional; if used, the label is assigned the same value that is placed in the Location Counter. Optional; when used, the operand must be a relocatable' ex­ pression «exp». It can only contain previously defined symbols. Comment Optional; may only be used with the operand field. RORG places a value in the Location Counter. If encountered in absolute code, RORG also defines succeeding locations as program-relocatable. The operand usually specifies the value placed in the Location Counter. If the operand is not used, the Location Counter is replaced by:

• The current maximum length of the program segment of the program, if RORG appears in absolute or program-relocatable code.
• The maximum length of the data segment if RORG appears in data­ relocatable code.
• The maximum length of the common segment if RORG appears in common -relocatable code. The length of the program-, data-, Or common-relocatable segment, at any time during assembly, is determined by either of the following: 1 ) The maximum value the Location Counter has ever attained as a result of the assembly of any preceding block of relocatable code. Zero, if no relocatable code has been previously assembled. Since the Location Counter begins at zero, the length of a segment and the next available address within that segment are identical. If RORG appears in absolute code, a relocatable operand must be pro­ gram-relocatable. In relocatable code, the operand's relocation type (data, common, or program) must match that of the current location counter. In absolute code RORG places the operand value in the Location Counter and changes the Location Counter's relocation type to program-relocatable. In relocatable code RORG places the operand value in the Location Counter but does not change the Location Counter's relocation type. RORG $-10 Overlay ten bytes The $ symbol contains the value of the current location. This example sets the Location Counter to the current location less ten bytes. The instructions and directives following the RORG directive replace the ten previously as­ sembled words of relocatable code, permitting correction of the program without removing source records. If a label had been included, the label would have been assigned the value placed in the Location Counter. 5-41

Relocatable Origin Directive SEG2 RORG The Location Counter contents depend upon preceding source statements. Assume that after'defining data for a program that occupies >44 bytes, an AORG directive initiates an absolute block of code. The absolute block is followed by the RORG directive from the preceding example. This places >0044 in the Location Counter and defines the Location Counter as relo­ eatable. Symbol SEG2 is a relocatable value, >0044. The RORG directive from the above example would have no effect except at the end of an ab­ solute block or a dummy block.

Secondary External Reference Directive SREF Syntax Fields [ <label>] SREF <symbol> [,<symbol>] [<comment>] Label Optional; if used, the label assumes the current value of the Location Counter. Operand Contains one or more symbols, separated by commas, to be used in the operand field of a subsequent source statement. Comment Optional Description SREF provides access to one or more symbols defined in other programs. _ Unlike REF, SREF does not require a symbol to have a corresponding Example 1 symbol listed in a DEF statement of another source module. The SREF'd symbol will be an unresolved reference but no error message will be pro- duced. SREF ARG1,ARG2 This example causes the link editor to include symbols ARG1 and ARG2 in the object code so that the corresponding addresses may be obtained from other programs. 5-43

_ Description Example Example 5-44 Initialize Text Directive [<label>] TEXT [-]' <string>' [<comment>] Label Optional; if used, the label is assigned the location where the assembler places the first character. Operand Contains a character string of up to 52 characters enclosed in single quotes; it may be preceded by a unary minus sign. Comment Optional TEXT places one or more characters in successive bytes of memory. The assembler negates the last character of the string when the string is pre­ ceded by a minus (-) sign (unary minus). MSGl TEXT 'EXAMPLE' Message heading This example places the 8-bit ASCII representations of the characters in successive bytes. When the Location Counter is on an even address, the result is >4558, >4140, >504C, and >45xx. >xx, the contents of the rightmost byte of the fourth word, are determined by the next source state­ ment. The label MSG1 is assigned the value of the first byte address, con­ taining >45. MSG2 TEXT -'NUMBER' When the Location Counter is on an even address, the result is >4E55, >4042, and >45AE. The label MSG2 is assigned the value of the byte address in which >4E is placed.

[<label>] TITl '<string>' [<comment>] Label Operand Optional; if used, the label assumes the current value of the location Counter. Contains the title «string», a character string of up to 50 characters enclosed in single quotes. The assembler truncates a string longer than 50 characters and prints a truncation error message. Comment Optional; the assembler does not print the comment but does _ increment the line counter. Description TITl supplies a title to be printed in the heading of each page of the source listing. The title is printed on the next page after TITl is processed, and on subsequent pages until another TITl directive is processed. The TlTl di­ rective must be the first source statement submitted to the assembler if a title heading is desired on the listing's first page. This directive is not printed in the source listing. Example 1 TITL '**REPORT GENERATOR * * , This example prints the title "REPORT GENERATOR"" in the page head­ ings of the source listing. 5-45

Stop Source Listing Directive [<label>] UNL [<comment>] Label Optional; if used, the label assumes the value of the Location Counter. Operand Not used Comment Optional; if used, the assembler does not print the comment. UNL halts the source listing output until a LIST directive is processed. It is not printed in the source listing, but the source line counter is incre­ mented. This directive is frequently used in MACRO definitions to inhibit the listing of the macro expansion. It is useful for reducing assembly time and the size of the source listing.

The TMS7000 Assembler - Symbolic Addressing Techniques

5.6 Symbolic Addressing Techniques

The assembler processes symbolic memory addresses for addressing registers. The following example illustrates this type of coding: SUM EQU R33 Assign SUM for register 33 QUAN EQU R34 Assign QUAN for register 34 ADD QUAN,SUM Add QUAN to SUM * Store in SUM The two initial EQU directives assign meaningful labels to be used as register addresses in the subroutine. 5-47

The TMS7000 Assembler - Assembler Output

5.7 Assembler Output

This section discusses assembler output, including source listings, error mes­ sages, a cross reference listing, and object code.

5.7.1 Source Listing

A source listing shows source statements and the object code they produce. Each page of the source listing has a title line at the top .. Any title supplied by a TITL directive is printed on this line. A page number is printed to the right of the title. A blank line follows the title line; subsequent lines contain the assembled source statements. Each assembled source statement contains a source statement number, a program counter value, the object code assem­ bled, and the source statement as entered. If a source statement produces more than one byte of object code, the assembler prints the program counter value and object code on a separate line for each additional byte. Each added line is printed following the source statement line .

0018 F1S6 42

F1S8 OS, .2. MOV R10,RS The source statement number, 0018 in the example, is a 4-digit decimal number. Source records are numbered in the order in which they are entered including those source records that are not printed in the listing (TITL, LIST, UNL, and PAGE directives are not listed; source records between a UNL di­ rective and a LIST directive are not listed). The difference between two con~ secutive source record numbers indicates if a source record was entered but not listed. The next field on a line of the listing contains the program counter value (hexadecimal). In the example, F156 is the program counter value. Not all directives affect the program counter; the field is blank for those directives that do not affect it (the lOT, REF, DEF, EQU, SREF, and END directives leave the program counter field blank). The third field normally contains a single blank. However, the assembler places a dash in this field when warning errors are detected. . The fourth field contains the hexadecimal representation of the object code, 420A05 in the preceding example. Note that the assembler produces a line containing the program counter value and the assembled object code for each byte of object code. All machine instructions and the BYTE, DATA, and TEXT directives use this field for object code. The EQU directive places the value corresponding to the label in the object code field. The fifth field contains the characters of the source statement as they were scanned by the assembler. Spacing in this field is determined by the spacing in the source statement. The four source statement fields will be aligned in the listing only when they are aligned in the source statements or when tab char­ acters are used.

The TMS7000 Assembler - Assembler Output

5.7.2 Normal Completion Error Messages

The assembler issues two types of error messages: normal completion mes­ sages and abnormal completion messages (Section 5.7.3). When the assem­ bler completes an assembly, it indicates any errors it encounters in the assembly listing. The assembler indicates errors following the source line in which they occur. At the end of a module (lOT-END pair), the corresponding messages are printed. Table 5-3 lists error, warning, and information messages. Table 5-3. Assembly Listing Errors NONFATAL ERRORS MESSAGE EXPLANATION/RESPONSE WARNING - 'CEND' ASSUMED This is a warning that the following two state- WARNING - 'DEND' ASSUMED ments will produce: WARNING - 'PEND' ASSUMED CSEG 'DATA' WARNING - 'DSEG' ASSUMED DSEG WARNING - SYMBOL TRUNCATED The maximum length for a symbol is six characters. WARNING - STRING TRUNCATED Check the syntax for the directive in question to determine the maximum length for the string. WARNING - TRAILING OPERAND(S) WARNING - BYTE VALUE TRUNCATED A value that is to be used as a byte value was lar- ger than can be loaded into a byte. "LAST WARNING FATAL ERRORS MESSAGE EXPLANATION/RESPONSE ABSOLUTE VALUE REQUIRED DISPLACEMENT TOO BIG An instruction with an operand with a fixed upper limit was encountered that overflowed this limit. INVALID EXPRESSION This may indicate invalid use of a relocatable symbol in arithmetic. EXPRESSION OUT OF BOUNDS There is a range limit for the value being used that was exceeded. DUPLICATE DEFINITION The symbol appears as an operand of a REF state- ment, as well as in the label field of the source, OR. the symbol appears more than once in the la- bel field of the source. INVALID RELOCATION TYPE The type of variable isn't relocatable. INVALID OPCODE The second field of the source record contained an entry that is not a defined instruction, directive, pseudo-op, DXOP, DFOP, or macro name. INVALID OPTION The option given in the OPTION directive are in- valid. INVALID REGISTER VALUE The given register value is too large or too small. 5-49

The TMS7000 Assembler - Assembler Output Table 5-3. Assembly Listing Errors (Concluded) FATAL ERRORS (CONTINUED) MESSAGE EXPLANATION/RESPONSE INVALID SYMBOL The symbol being used has invalid characters in it. VALUE TRUNCATED The value used was too big for the field, so it has been truncated. SYMBOL USED IN BOTH REF AND DEF , Symbol cannot be both referenced and defined in the same module. CQPY FILE OPEN ERROR File does not exist or is already being used. EXPRESSION SYNTAX ERROR Unbalanced parentheses OR invalid operations on relocatable symbols. INVALID ABSOLUTE CODE DIRECTIVE The directive PEND, DEND and CEND have no meaning in absolute code. LABEL REQUIRED BLANK MISSING A blank is needed but one was not found. (Usu- ally the blank is required in column 1.) COMMA MISSING Expected a comma but did not find one. Usually means that more operands were expected. COpy FILENAME MISSING INDIRECT n MISSING The indirect addressing (*) Was needed. SYMBOL REQUIRED OPERAND MISSING There was no operand field. REGISTER REQUIRED A register should be used rather than a label or an absolute number. CLOSE (') MISSING STRING REQUIRED TEXT directive used with no text following. PASS1 /PASS2 OPERAND CONFLICT The symbols in the symbol table did not have the same value in PASS1 and PASS2. Registers and peripheral files should be defined before they are used in an instruction. This error is also produced when the BSS directive is used to define a register name; use EQU instead. SYNTAX ERROR UNDEFINED SYMBOL The symbol being llsed has not been REF'ed or it has been DEF'ed but not used. DIVIDE BY ZERO ILLEGAL SHIFT COUNT The shift count being asked for is not valid. CANNOT INDEX BY REGISTER ZERO INFORMATION MESSAGES MESSAGE EXPLANATION/RESPONSE OPCODES REDEFINED As a result of an MLiB directive, one or more as- sembler opcodes has been redefined by a MACRO within a MACRO directory. You should take action if this is not intended. MACROS REDEFINED As a result of an MLiB directive, one or more cur- rently defined macros has been redefined by a MACRO (of the same name) with a MACRO di- rectory. You should take action if this is not in- tended. 5-50

The TMS7000 Assembler - Assembler Output

5.7.3 Abnormal Completion Error Messages

Most abnormal completion error messages are issued by the operating system under which the assembly runs (messages in this category include those concerned with file I/O errors). Refer to the applicable operating system ref­ erence manual for detailed information. Table 5-4 lists the abnormal error messages. Table 5-4. Abnormal Completion Error Messages UNEXPECTED END OF PARSE ERROR MAPPING PARSE - ASSEMBLER BUG INVALID OPERATION ENCOUNTERED NO OPCODE INVALID LISTING ERROR ENCOUNTERED SYMBOL TABLE ERROR INVALID LIB COMMAND 10 UNKNOWN ERROR PASSED, CODE = XXXX 5-51

The TMS7000 Assembler - Assembler Output

5.7.4 Cross-Reference Listing

The assembler prints an optional cross-reference listing following the source listing, as specified by the assembler OPTION directive. The format of the listing is shown in Figure 5-2. LABEL VALUE DEFN REFERENCES ADDT 01A8 0325 0314 ADSR D OlAO 0316 0342 0343 0348 0349 GT 0006 0997 OBTCHN R 0088 SQUIB U 0127 0233 Figure 5-2. Cross-Reference Listing Format As Figure 5-2 shows,

• The assembler prints each symbol defined or referenced in the assembly in the label column. If a single character follows the symbol, it repres­ ents the symbol attribute. These symbol-attribute characters and their meanings are listed in Table 5-5.
• The second (value) column contains a four-digit hexadecimal number, the value assigned to the symbol. The number of the statement that defines the symbol appears in
• the third (definition) column. This column is left blank for undefined symbols.
• The fourth (reference) column lists the source statement numbers that reference the symbol. A blank in this column indicates that the symbol was never used. Table 5-5. Symbol Attributes CHARACTER MEANING R External reference (REF) D External definition (DEF) U Undefined M Macro name S Secondary reference (SREF) . L Force load (LOAD)

The TMS7000 Assembler - Object Code

5.8 Object Code

The assembler produces object code that may be linked to other code modules or programs, and loaded directly into the computer. Object code consists of records containing up to 71 ASCII characters. You can correct record data manually for simple temporary changes for debugging. This prevents a lengthy re-assembly but it causes problems if you don't update the source. Figure 5-3 shows an example of object code. SAMPLE 1 - ACTUAL CODE OUTPUT KOOOOTESTPROG9F006B327BBBSABB0002BCAFBBS246BODA2BOOOOBA242B02A27F113F ~ B2003BA2FFB09A2BFFOBBA222BOAA2B4408BS208BDS02BA2FOBOBCFBE32EB78047FOF6F I B0292BOA80BOAA2BOOOAB230FBE2EFBD202BBDE7BFB4DB0203BE206B4202B03727F127F B1004B7D02B04E7B03DAB04DOBE20SBD204B7401BOSOAB72FFB030A9F862*OB7F1DSF 9FFF4BF862BF862BF862BF862BF862BF0067F7A4F TESTPROG 11/28/84 1S:59: 3 ASMMLP 2.1 83.074 SAMPLE 2 -EXPANDED CODE WITH KEYS (REFERENCE ONLY) KOOOOTESTPROG9F006B327BBBSABB0002BCAFBBS246BODA2BOOOOBA242B02A27F113F 1 2 3 4 S 6 7 8 9 10 *88BF800B71EFBF788BF822B71EF*88BF848B71EF*88BF871B71EFBF788BF89781111F 11 12 13 BFFACB9C019FFFEBF8C47FAD1F 14 1S TESTPROG 11/28/84 1S:59: 3 ASMMLP 2.1 83.074 1 ) K - Begins each program 2) 0000 - Bytes of relocable code, always 0 for final linked code 3) TESTPROG - Name from the lOT statement of the program 4) 9 -Address follows 5) F006 - Beginning address 6) B - 16-bit word follows 7) 327 B - 16-bit word. MS B first 8) 7 - Checksum follows 9) Fl13 - Checksum (2's complement of the sum of all ASCII characters prior to and including the 7 tag) 10) F -End of line 11) • - 8-bit byte to follow 12) 8 - Ignore checksum - useful when object code patching 13) 1111 - Any 4 numbers can follow an 8 tag 14) 9 - Address follows 15) FFFE - Address of vector area 16) : -Last line of object module Note: Table 5-6 provides an explanation of the tag characters. Figure 5-3. Sample Object Code 5-53

The TMS7000 Assembler - Object Code

5.8.1 Object Code Format

Formatted object code contains records made up of fields sandwiched be­ tween tag characters. The specific tag character, defined by the assembler or linker, specifies the function of the fields with which it is associated. A tag character occupies the first position on each line of object code and identifies the fields it precedes to the loader. Table 5-6 details the various tag characters and their associated fields. Table 5-7 lists field and tag character information. Table 5-6. Tag Characters TAG CHARACTER DESCRIPTION 5-54 K Placed at the beginning of each program; followed by two fields. Fields - Field one contains the number of bytes of program relocatable code. - Field two contains the program identifier assigned to the program by an I DT directive. When no lOT directive is entered, field two is blank. The linker uses the program identifier to identify the program, and the number of bytes of program-relocatable code to determine the load bias for the next module or program. M Used when data or common segments are defined in the program; followed by three fields. Fields - Field one contains the length, in bytes, of data-or common-relocatable code. - Field two contains the data or common segment identifier, and field three contains a "common number." The identifier is a six-character field containing the name $DATA (padded on the right by one blank) for data segments and $BLANK for blank common segments. If a named common segment appears in the program, an M tag will appear in the object code with an identifier field corresponding to the operand in the defining CSEG directive(s). - Field three consists of a four-character hexadecimal number defining a unique com­ mon number to be used by other tags that reference or initialize data of that particular segment. For data segments, this common number is always zero. For common segments (including blank common), the common numbers are assigned in increas­ ing order, beginning at one and ending with the number of different common seg­ ments. The maximum number of common segments that a program may contain is 127. 1,2 Used with entry addresses. Fields - The associated field is used by the linker to determine the entry point in which exe­ cution starts when linking is complete. Tag character 1 is used when the entry address is absolute; tag character 2 when the address is relocatable. The field lists the address in hexadecimal form. 3,4,X Tag characters 3, 4, and X are used for external references. Tag character 3 is used when the last appearance of the externally referenced symbol is in program-relocatable code; tag character 4 when it is in absolute code; and the X tag when it is in data-or com­ mon-relocatable code. Tag characters 3 and 4 are associated with two fields. Tag character X may identify one additional field. Fields - Field one contains the location of the last appearance of the symbol. - Field two contains the symbol itself. - Field three is only used to supply the common number for the X tag.

The TMS7000 Assembler - Object Code TAG CHARACTER E Table 5-6. Tag Characters (Continued) Used for external references. An E tag is used when a nonzero quantity is to be added to a reference. Fields - Field 1 identifies the reference by occurrence in the object code (0, 1, 2, ... ). In other words, the value in field one is an index into references identified by 3, 4, V, X, Y and Z tags in the object code. The list is maintained by order of occurrence (i.e., the first entry in the list is the symbol located in field two of the first 3, 4, V, X, Y, or Z tag). - Field 2 contains the value to be added to the reference after the reference is resolved. Used for external references of an 8-bit value. It serves the same purpose for 8-bit va­ lues that the E-tag serves for 16-bit values. 5, 6, W Used for external definitions. Tag character 5 is used when the location is program­ relocatable. Tag character 6 is used when the location is absolute. Tag character W is used when the location is data-or common-relocatable. The fields are used by the linker to provide the desired linking to the external definition. Fields - Field one contains the location of the last appearance of the symbol. - Field two contains the symbol of the external definition. - Field three of tag character W contains the common number. 7 Precedes the checksum, and is placed at the end of the set of fields in the record. The checksum is an error detection word and is formed as the record is being written. It is the two's complement of the sum of the 8-bit ASCII values of the characters of the re­ cord from the first tag of the record through the checksum tag, 7. 9, A S, P Used with load addresses, required for data words that are to be placed at other than the next immediate memory addresses. Tag character 9 is used when the load address is absolute. Tag character A is used when the load address is program-relocatable. Tag character S is used when the load address is data-relocatable. Tag character P is used when the load address is common-relocatable. Fields - Field one contains the load address. - Field two is only present for tag character P and contains the common number .

• , B, C, T, N Used with data words. Tag characters' and B are used when the data is absolute (i.e., an instruction word or a word that contains text characters or absolute constants). Tag
• is used for absolute byte data (8 bits) and B is used for absolute word data (16 bits). Tag character C is used for a word that contains a program-relocatable address. Tag character T is used for a word that contains a data-relocatable address. Tag character N is used for a word that contains a common-relocatable address. Fields - Field one contains the data word. The linker places the data word in the memory location specified in the preceding load address field or in the memory location that follows the preceding data word. - Field two is only used with N and contains the common number. G, H, J Used when the symbol table option is specified. Tag character G is used when the lo­ cation or value of the symbol is program-relocatable, tag character H is used when the location or value of the symbol is absolute, and tag character J is used when the lo­ cation or value of the symbol is data-or common-relocatable. Fields - Field one contains the location or value of the symbol. - Field two contains the symbol to which the location is assigned. - Field three is used with tag character J only and contains the common number. 5-55

The TMS7000 Assembler - Object Code Table 5-6. Tag Characters (Concluded) TAG CHARACTER DESCRIPTION 5-56 U V. Y,Z Generated by the LOAD directive. The symbol specified is treated as if it were the value specified in an INCLUDE command to the linker. Fields - Field one contains zeros. - Field two contains the symbol for which the loader will search for a definition. Used for secondary external references. Tag character V is used when the last appear­ ance of the externally referenced symbol is in program-relocatable code; tag character Y when it is in absolute code; and the Z tag when it is in data-or common-relocatable code. Tag characters V and Yare associated with two fields. Tag character Z may identify one additional field. Fields - Field one contains the location of the last appearance of the symbol. - Field two contains the symbol itself. - Field three is only used to supply the common number for the Z tag.

8 Also associated with the checksum field, but used when the checksum field is to be

ignored. D Specifies a load bias. Its lone associated field contains the absolute address that will be used by a loader to relocate object code. The Link Editor does not accept the D tag. F Placed at the end of the record. It may be followed by blanks. The end of each record is identified by the tag character 7 followed by the checksum field and the tag character F (this data is described above). The assembler fills the rest~f the record with blanks and a sequence number and begins a new record with the appropriate tag character. The last record of an object module has a colon (:) in the first character posi­ tion of the record, followed by blanks or time and date identifying data. Table 5-7 defines the object record format and tags.

The TMS7000 Assembler - Object Code TAG K M M M A S P B C T N W X G H J U V y Z D F Notes: 1. Table 5-7. Object Record Format and Tags I 1ST FIELD I 2ND FIELD I 3RD FIELD MODULE DEFINITION PSEG Length Pro~am ID (8) DSEG Length $DA A 0000 Blank Common I.ength $BLANK Common # CSEG Length Common Name (6) Common # ENTRY POINT DEFINITION Absolute Address P-R Address LOAD ADDRESS ABSOLUTE ADDRESS P-R Address D-R Address C-R Address Common or CBSEG # DATA Absolute 8-bit Value (2) Absolute 16-bit Value P-R Address D-R Address C-R Address Common or CBSEG # EXTERNAL DEFINITIONS Absolute Value Symbol ml P-R Address Symbol 6 D-R/C-R Address Symbol 6 Common # EXTERNAL REFERENCES P-R Address of Chain Symbol tl Absolute Address of Chain Symbol 6 D-R/C-R Address of Chain Sbmbol 6 Common· Symbol Index Number A solum)Offset Mask (2) Symbol Index Number Offset 2 SYMBOL DEFINITIONS P-R Address Symbol tl Absolute Value Symbol 6 D-R/C-R Address Symbol 6 Common # FORCE EXTERNAL LINK

10000 I Symbol (6) I

SECONDARY EXTERNAL REFERENCE P-R Address of Chain Entry Symbol t~l Absolute Address of Chain Symbol 6 D-R/C-R Address of Chain Symbol 6 Common # CHECK SUM I Value I I IGNORE CHECK SUM I Any Value I I LOAD BIAS I Absolute Address I I END OF RECORD I I I END OF OBJECT MODULE 1 j I .. All field widths are four characters unless otherwise specified by numbers In parenthesIs. If the first tag is 01 (hex), the file is in compressed object format. P-R Program segment relative (address) D-R Data segment relative (address) C-R Common segment relative (address) 5-57

The TM57000 Assembler - Object Code

5.8.1.1 External References in Object Code

The Link Editor allows the use of external references in the object code. (See Section 7.)

5.8.1.2 Changing Object Code

In most cases, changing the object code is not the recommended way to cor­ rect errors in a program. All changes or corrections to a program should be made in the source code, then the program should be re-assembled. Failure to follow this procedure can make subsequent program correction or mainte­ nance impossible. The information in the following paragraphs is intended for those rare instances when re-assembly is not possible. Any changes made directly to the object code should be thoroughly documented so that the pro­ grammers who come later can see what the program actually does, not what the source code says that it does. To correct the object code without re-assembling a program, change the ob­ ject code by changing or adding one or more records. One additional tag character is recognized by the loader to permit specifying an abolute address that will be used to relocate object code. The additional tag character, D, may be used in object records changed or added manually. Tag character D is followed by a load bias (offset) value. The loader uses this value instead of the load bias computed by the loader itself. The loader adds the load bias to all relocatable entry addresses, external references, external definitions, load addresses, and data. The effect of the D tag character is to specify that area of memory into which the loader loads the program. The tag character D and the associated field must be placed ahead of the object code generated by the assembler. Correcting the object code may require only changing a character or a word in an object code record. You may duplicate the record up to the character or word in error, replace the incorrect data with the correct data, and duplicate the remainder of the record up to the seven tag character. The changes will cause a checksum error when the checksum is verified as the record is loaded, so you must:

• Change the 7 tag character to an 8 tag character, in which case the checksum value is ignored, or
• Recalculate the checksum. When more extensive changes are required, you may write an additional object code record or records. Begin each record with a tag character 9, A, S, or P, followed by an absolute load address or a relocatable load address. This may be an address into which an existing object code record places a different va­ lue. The new value on the new record will override the other value when the new record follows the other record in the loading sequence. Follow the load address with a tag character', B, C, T, or N and an absolute data word or a relocatable data word. Additional data words preceded by appropriate tag characters may follow. When additional data is to be placed at a nonsequen­ tial address, write another load address tag character followed by the load address and data words preceded by tag characters. When the record is full, or all changes have been written, write tag character F to end the record.

The TMS7000 Assembler - Object Code When additional relocatable memory locations are loaded as a result of changes, you must change field one of tag character K, which contains the number of bytes of relocatable code. For example, if the object field written by the assembler contained 1000 hex bytes of relocatable code and you have added eight bytes in a new object record, additional memory locations will be loaded. You must find the K tag character in the object code file and change the value following the tag character from 1000 to 1008; you must also change the tag character 7 to 8 in that record, or recalculate the checksum. When added records place corrected data in locations previously loaded, the added records must follow the incorrect records. The loader processes the records as they are read from the object file, and the last record that affects a _ given memory location determines the contents of that location at execution time. The object code records that contain the external definition fields, the external reference fields, the entry address field, and the final program start field must follow all other object records. An additional field or record may be added to include reference to a program identifier. The tag character is 4, and the hex­ adecimal field contains zeros. The second field contains the first six characters of the I DT character string. External definitions may be added using tag character 5 or 6 followed by the relocatable or absolute address, respectively. The second field contains the defined symbol, filled to the right with blanks when the symbol contains less than six characters. Note: Both object code to be linked and object code to be downloaded can be changed without re-assembling the program. The link editor, though, will not accept tag character D in changed or added object records. 5-59

The TMS7000 Assembler - Object Code 5-60

Assembly Language Instruction Set The TMS7000 instruction set contains 61 instructions that control input, out­ put, data manipulation, data comparison, and program flow. The instruction set can be divided into eight functional categories: Arithmetic Instructions Branch and Jump Instructions Compare Instructions Control Instructions Load and Move Instructions Logical Instructions Shift Instructions I/O Instructions Note: TMS70x2 and TMS70Cx2 devices have 256 bytes of on-chip RAM; their register locations range from RQ-R255. TMS70xO and TMS70CxO de­ vices have 128 bytes of on-chip RAM; their register locations range from RQ-R127. Topics in this section include: Section Page 6-1

Assembly Language Instruction Set - Definitions

6.1 Definitions

Table 6-1 lists and defines the symbols used in the instruction set. Table 6-1. TMS7000 Symbol Definitions SYMBOL DEFINITION SYMBOL DEFINITION A Register A or RO in Register File B Register B or R1 in Register File Rn Register n of Register File Pn Port n of Peripheral File (0 S n S 255) s Source operand d Destination operand Rs Source register in Register File Ps Source register in Peripheral File (0 S s < 255) Rd Destination register in Register File Pd Destination in Peripheral File (0 S d S 255) Rp Register pair iop Immediate operand ST Status Register SP Stack Pointer PC Program Counter pcn Location of the next instruction $ Current value of Program Counter b Bit number, as in b7 (0 S b S 7) offset Relative Address (offset = ta - pcn) ta Target Address (ta = offset + pcn) @ I ndicates an address or label % Indicates immediate operand * I.ndicates Indirect Register File XADDR> Indicates an extended address Addressing mode operand ? Binary number > Hexadecimal number MSB Most significant byte LSB Least significant byte MSb Most significant bit LSb Least significant bit cnd Condition ( ) Contents of -+ Is assigned to <- Becomes equal to [ 1 Indicates an optional entry. < > Indicates something that must be typed The brackets themselves are not in. For example, <offset> indicates that entered. an offset must be entered. The brackets themselves are not entered. 6-2

Assembly Language Instruction Set - Addressing Modes

6.2 Addressing Modes

TMS7000 Assembly Language supports eight addressing modes, listed in Ta­ ble 6-2. Addressing modes that use 16-bit operands are sometimes referred to as extended addressing modes. Table 6-2. TMS7000 Addressing Modes ADDRESSING MODE EXAMPLE Single Register LABEL DEC B INC R45 CLR R23 Dual Register LABEL MOV B,A ADD A,R17 CMP R32,R73 Peripheral File LABEL XORP A,P17 MOVP P42,B Immediate LABEL AND %>C5,R55 ANDP %VALUE,P32 BTJO %>D6,R80,LABEL Program Counter Relative LABELl JMP LABEL DJNZ A,LABEL BTJO %>16,R12,LABEL BTJOP B,P7,LABEL Direct Memory LABEL LDA @>F3D4 CMPA @LABEL Register File Indirect LABEL STA *R43 Indexed LABEL2 BR @LABEL(B) 6-3

Assembly Language Instruction Set - Addressing Modes

6.2.1 Single Register Addressing Mode

Single Register Addressing mode instructions use a single register that con­ tains an 8-bit operand. The register can be specified as Rn, where n is the Register File number in the range 0-127 or 0-255, depending upon the amount of on-chip RAM available. . A and B can denote RO and R1, respectively. Single Register Addressing mode instructions that use registers A and B are also called implied operand instructions. Single Register Addressing mode instructions that specify Rn are called single operand instructions. Figure 6-1 illustrates the object code generated by a single operand instruction for the the following cases: Case 1: <inst> A <inst> B Case 2: <inst> Rn CASE 1 CA6E2 (PC) 4 OPCODE (PC)--tj OPCODE (PC +1)4 Rn Figure 6-1. Single Register Addressing Mode Object Code

6.2.2 Dual Register Addressing Mode

Dual Register Addressing l110de instructions use a source and a destination register that contain 8-bit operands. Assembly language syntax specifies the source register before the destination register. Figure 6-2 illustrates the byte requirements for all dual addressing instructions including the unique re­ quirements of the Move instructions using this addressing mode. A B iop Rs DESTINATION A B Rd Bytes Needed for Move Instructions SOURCE A B iop Rs DESTINATION A B Rd 2 3 2 3 2 3 2 3 Bytes Needed for all Other Instructions Figure 6-2. Dual Register Addressing Mode Byte Requirements

Assembly Language Instruction Set - Addressing Modes

6.2.3 Peripheral-File Addressing Mode

Peripheral-File Addressing mode instructions perform I/O tasks. Each PF re­ gister is an 8-bit port that can be referred to as Pn. Four instructions use Peripheral-File Addressing mode:

• MOVP,
• ANDP,
• ORP, and
• XORP. These instructions may use Register A or B as the source register and Pn as the destination register. MOVP may also be executed using Pn as the source register and A or B as the destination register. (BT JOP and BT JZP are also Peripheral-File instructions, but they have a different format.) Figure 6-3 il­ lustrates the byte requirements of the instructions using the Peripheral-File Addressing mode. DESTINATION DESTINATION A B Pd Pd SOURCE i~1 I I I SOURCE A§

2 B 3

Bytes Needed for Bytes Needed for all ANDP. ORP. and MOVP BT JOP and BT JZP Instructions Instructions Figure 6-3. Peripheral-File Addressing Mode Byte Requirements 6-5

Assembly Language Instruction Set - Addressing Modes

6.2.4 Immediate Addressing Mode

Immediate Addressing mode instructions use an immediate 8-bit operand. The immediate operand can be a constant value or a label preceded by a· percent sign (%). The MOVD instruction uses 16-bit immediate operands in two special formats. Figure 6-4 illustrates the simplest case of an instruction using this mode. (PC14 OPCODE

• • • Figure 6-4. Immediate Addressing Mode Object Code

6.2.5 Program Counter Relative Addressing Mode

All Jump instructions use Program Counter Relative Addressing mode. The assembly language source statement for a jump instruction always includes a target address (ta). The microcomputer uses the target address to calculate an offset as follows: offset = ta - pen, where pcn is the location of the next instruction and -128 ~ ra ~ 127. Figure 6-5 illustrates object code generated by a Jump instruction. (PC) -tI OPCOOE

• • lOP N B Y D T E
• • (PC + n) -----..j OFFSET Figure 6-5. Program Counter Relative Addressing Mode Object Code

Assembly Language Instruction Set - Addressing Modes

6.2.6 Direct Memory Addressing Mode

Direct Addressing mode instructions use a 16-bit address that contains the operand. The 16-bit address is preceded by an @ sign and can be written as a constant value or as a label. Figure 6-6 shows how the object code pro­ duced by an instruction using the Direct Memory Addressing mode generiltes a 16-bit effective address. . (PC) ----..f OPCOOE (PC + 1) (PC + 2) 18-BIT EFFECTIVE ADDRESS Figure 6-6. Direct Memory Addressing Mode Object Code

6.2.7 Register File Indirect Addressing Mode

Register File Indirect Addressing mode instructions use the contents of a reg­ ister pair as a 16-bit effective address. The indirect Register File address is written as a register number (Rn) preceded by an asterisk (*), i.e.: *Rn. The LSB of the address is contained in Rn, and the MSB of the address is con­ tained in the previous register (Rn-1). Figure 6-7 shows how the object code produced by an instruction using Register File Indirect Addressing mode generates a 16-bit effective address. (PC) --4 OPCODE Rn-2 Rn-1 18-BIT (PC + 1)--.f EFFECTIVE Rn • Rn ADDRESS Rn+1 Figure 6-7. Register File Indirect Addressing Mode Object Code 6-7

Assembly Language Instruction Set - Addressing Modes

6.2.8 Indexed Addressing Mode

Indexed Addressing mode instructions generate a 16-bit address by adding the contents of the B Register to a 16-bit direct memory address. The as­ sembly language statement for the Indexed Addressing mode contains the di­ rect memory address written as a 16-bit constant value or a label, preceded by an @ sign and followed by a B in parentheses: @LABEL(B). The addition automatically transfers any carries into the MSB. Figure 6-8 illustrates how the object code produced by an instruction using the Indexed Addressing mode generates a 16-bit effective address. Do not confuse this mode with the MOVD (Move Double) instruction's addressing mode. (PC) --1 OPCODE (PC+1) ADOR MaB (PC+2) ADOR LSB Figure 6-8. Indexed Addressing Mode Object Code 18-BIT EFFECTIVE ADDRESS

Assembly Language Instruction Set - Overview

6.3 Instruction Set Overview

Table 6-3 lists all instruction formats, opcodes, byte lengths, cycles/instruc­ tion, operand types, status bits affected, and an operational description. The TMS7000 Assembly Language instructions are presented in alphabetical order following the instruction overview table. All instructions may have op­ tional labels preceding the mnemonic and comments following the operands. Labels, mnemonics, operands, and comments must be separated by at least one space: START MOVP %>OO,PO Initialize to single chip The byte count for each instruction may be determined from its instruction type and its operands. 6-9

Assembly Language Instruction Set - Overview Table 6-3. TMS7000 Family Instruction Overview MNEMONIC DPCOD BYTES CYC.LES STATUS OPERATION DESCRIPTION TdC\\ C N Z I ADC B,A 69 1 5 R R R x (s) + (d) + (C) .... (d) RS,A 19 2 8 Add the source, destination, and carry bit RS,B 39 2 8 together. Store at the destination address. RS,Rd 49 3 10 %iop,A 29 2 7 %iop,B 59 2 7 %iop,Rd 79 3 9 ADD BA 68 1 5 R R R x (s) + (d) .... (d) RS,A 18 2 8 Add the source and destination operands at RS,B 38 2 8 the destination address. RS,Rd 48 3 10 %iop,A 28 2 7 %iop,B 58 2 7 %iop,Rd 78 3 9 RS,A 13 2 8 AND the source and destination operands RS,B 33 2 8 together and store at the destination RS,Rd 43 3 10 address. %iop,A 23 2 7 %iop,B 53 2 7 %iop,Rd 73 3 9 B,Pd 93 2 9 AND the source and destination operands %iop,Pd A3 3 11 together, and store at the destination address. (1) 0 R R x BTJO B,A,Ofst 66 2 7 (9) If (s) .AND. (d) #: 0, Rn,A,Ofst 16 3 10 (12) then (PC) + offset .... (PC) Rn,B,Ofst 36 3 10 (12) If the AN D of the source and destination Rn,Rd,Ofst 46 4 12 (14) operands ¢ 0, the PC will be modified to %iop,A,Ofst 26 3 9 (11) include the offset. %iop,B,Ofst 56 3 9 (11) %iop,Rn,Ofst 76 4 11 (13) (1 ) 0 R R x BTJOP A,Pn,Ofst 86 3 11 (13) If (s) .AND. (Pn) #: 0, B,Pn,Ofst 96 3 10 (12) then (PC) + offset .... (PC) %>iop,Pn,Ofst A6 4 12 (14) If the AN D of the source and destination operands ¢ 0, the PC will be modified to include the offset. (1 ) 0 R R x BTJZ B,A,Ofst 67 2 7 (9) If (s) .AND. NOT(d} ¢ 0, Rn,A,Ofst 17 3 10 (12) then (PC) + offset -+ (PC) Rn,B,Ofst 37 3 10 (12) If the AND of the source and NOT(destina- Rn,Rf,Ofst 47 4 12 (14) tion operands ¢ 0, the PC will be modi- %>iop,A,Ofst 27 3 9 (11) fied to include the offset. %> iop, B,Ofst 57 3 9 (11) %>iop,Rn,Ofs 77 4 11 (13) Note: Add two to cycle count if branch is taken. &egen~: tatus Bit set always to O. 1 Status Bit set always to 1 . R Status Bit set to a 1 or a 0 depending on results of operation. x Status Bit not affected. b Bit ( ) affected. Ofst Offset 6-10

Assembly Language Instruction Set - Overview Table 6-3. TMS7000 Family Instruction Overview (Continued) MNEMONIC OPCODI BYTES CYCLES STATUS T,,{C\\ C N Z (1 ) 0 R R BTJZP A,Pn,Ofst 87 3 11 (13) B,Pn,Ofst 97 3 10 (12) %>iop,Pn,Ofst A7 4 12 (14) BR @Label 8C 3 10 x x x @Label{B) AC 3 12 "Rn 9C 2 .9 CALL @Label 8E 3 14 x x x @Label{B) AE 3 16 "Rn 9E 2 13 CLR A B5 1 5 0 0 1 B C5 1 5 Rd 05 2 7 CLRC BO 1 6 0 R R CMP B,A 60 1 5 R R R Rn,A 10 2 8 Rn,B 3D 2 8 Rn,Rn 40 3 10 %iop,A 20 2 7 %iop,B 50 2 7 %iop,Rn 70 3 9 CMPA @Label 80 3 12 R R R @Label(B) AD 3 14 °Rn 90 2 11 DAC B,A 6E 1 7 R R R RS,A 1E 2 10 RS,B 3E 2 10 RS,Rd 4E 3 12 %>iop,A 2E 2 9 %>iop,B 5E 2 9 %>iop,Rd 7E 3 11 DEC A B2 1 5 R R R B C2 1 5 Rd 02 2 7 DECO A BB 1 9 R R R B CB 1 9 Rp DB 2 11 DINT 06 1 5 o 0 0 Note: Add two to cycle count if branch is taken. Legend: o Status Bit set always to O. 1 Status Bit set always to 1. OPERATION DESCRIPTION I x If (s) .AND. NOT{Pn) ¢ 0, then (PC) + offset -+ (PC) If the AND of the source and NOT{desti- nation) operands ¢ 0, the PC will be mo- dified to include the offset. x (d) -+ (PC) The PC will be replaced with the contents of the destination operand. x (SP) + 1 -+ (SP) (PC MSB) -+ ({SP» (SP) + 1 -+ (SP) (PC LSB) -+ ((SP» Operand Address -+ (PC) x 0-+ (d) Clear the destination operand. x 0-+ (C) Clears the carry bit. x (d) - (s) computed Set flags on the result of the source operand subtracted from the destination operand. x (A) - (s) computed Set flags on result of the source operand subtracted from A. x (s) + (d) + (C) -+ (d) (BCD) The source, destination, and the carry bit are added, and the BCD sum is stored at the destination address. x (d) - 1 -+ (d) Decrement destination operand by 1 . x (rp) - 1 -+ (rp) Decrement register pair by 1. C = 0 on 0 - FFFF transition. 0 o -+ (global interrupt enable bit) Clear the I bit. R Status Bit set to a 1 or a 0 depending on results of operation. x Status Bit not affected. b Bit () affected. Ofst Offset 6-11

Assembly Language Instruction Set - Overview Table 6-3. TMS7000 Family Instruction Overview (Continued) MNEMONIC BYTES CYCLES STATUS ~PCOD Tc(CI C N Z I (1 ) x OJNZ A,Ofst BA 2 7 (9) B,Ofst CA 2 7(9) Rd,Ofst OA 3 9(11) DSB B,A 6F 1 7 R Rs,A 1 F 2 10 RS,B 3F 2 10 Rs,Rd 4F 3 12 %>iop,A 2F 2 9 %>iop,B 5F 2 9 %>iop,Rd 7F 3 11 EINT 05 1 5 1 IDLE 01 1 6 x INC A B3 1 5 R B C3 1 5 Rd 03 2 7 INV A B4 1 5 0 B C4 1 5 Rd 04' 2 7 JMP Ofst EO 2 7 x (1 ) x JC Ofst E3 2 5 (7) JEQ Ofst E2 2 5 (7) JHS Ofst E3 2 5 (7) JL Ofst E7 2 5 (7) IN Of5t E1 2 5 (7) JNC Ofst E7 2 5 (7) JNE Ofst E6 2 5 (7) JNZ Of5t E6 2 5 (7) JP Ofst E4 2 5 (7) JPZ Ofst E5 2 5 (7) JZ Ofst E2· 2 5 (7) LOA @Label 8A 3 11 0 @Label(B) AA 3 13 'Rn 9A 2 10 Note: Add two to cycle count if branch is taken. Legend: o Status Bit set always to O. 1 Status Bit set always to 1. x x x R R x 1 1 1 x x x R R x R R x. x x x x x x R R x OPERATION DESCRIPTION (d) - 1 -+ (d); If (d) '1= 0, (PC) + offset -+ (PC) The source operand is subtracted from the destination; this sum is then reduced by 1 and the carry bit is then added to it. The result is stored as a BCD number. 1 -+ (global interrupt enable bit) Set the I bit. (PC) -+ (PC) until interrupt (PC) + 1 .... (PC) after return from interrupt Stops !-IC execution until an interrupt. (d) + 1 -+ (d) Increase the destination operand by 1. NOT(d) .... (d) 1's complement the destination operand. (PC) + offset -+ (PC) The PC is modified by an offset to create a new PC value. If conditions are met, then (PC) + offset -+ (PC) If the needed conditions are met, the PC is modified by the offset to form a new PC value. (s) .... (A) Move the source operand to A. R Status Bit set to a 1 or a 0 depending on results of operation. x Status Bit not affected. b Bit ( ) affected. Ofst Offset 6-12

Assembly Language Instruction Set - Overview Table 6-3. TMS7000 Family Instruction Overview (Continued) MNEMONIC OPCOD BYTES CYCLES STATUS TcIC} C N Z lOSP 00 1 5 x MOV A,B CO 1 6 0 A,Rd 00 2 8 B,A 62 1 5 B,Rd 01 2 7 RS,A 12 2 8 RS,B 32 2 8 RS,Rd 42 3 10 %>iop,A 22 2 7 %>iop,B 52 2 7 %>iop,Rd 72 3 9 MOVO %>iop,Rp 88 4 15 0 %>iop(B),Rp A8 4 17 Rp,Rp 98 3 14 MOVP A,Pd 82 2 10 0 B,Pd 92 2 9 %>iop,Pd A2 3 11 PS,A 80 2 9 PS,B 91 2 8 MPY B,A 6C 1 44 0 RS,A 1C 2 47 RS,B 3C 2 47 Rn,Rn 4C 3 49 %>iop,A 2C 2 46 %>iop,B 5C 2 46 %>iop,Rn 7C 3 48 NOP 00 1 4 x OR B,A 64 1 5 0 RS,A 14 2 8 RS,B 34 2 8 RS,Rd 44 3 10 %>iop,A 24 2 7 %>iop,B 54 2 7 %>iop,Rd 74 3 9 ORP A,Pd 84 2 10 0 B,Pd 94 2 9 %>iop,Pd A4 3 11 POP A B9 1 6 0 B C9 1 6 Rd 09 2 8 Note: Add two to cycle count if branch is taken. Legend: o Status Bit set always to O. 1 Status B it set always to 1. x x R R R R R R R R x x R R R R R R OPERATION DESCRIPTION I x (B) -+ (SP) load SP with Register B's contents. x (s) .... (d) Replace the destination operand with the. source operand. x (rp) -+ (rp) Copy the source register pair to the destination register pair. x (s) -+ (d) Copy the source operand into the destina- tion operand. x (s) x (d) .... (A,B) Multiply the source and destination oper- ands, store the result in Registers A (MSB) and B (lSB). x (PC) + 1 -+ (PC) Add 1 to the PC. logically OR the source and destination operands, and store the results at the desti- nation address. x (s) .OR. (d) -+ (d) logically OR the source and destination operands, and store the results at the des- tination address. x «SP» .... (d) (SP) -1 .... (SP) Copy the last byte on the stack into the destination address. R Status Bit set to a 1 or a 0 depending on results of operation. x Status Bit not affected. b Bit ( ) affected. 6-13

Assembly Lang'uage Instruction Set - Overview Table 6-3. TMS7000 Family Instruction Overview (Continued) MNEMONIC PPCODI BYTES CYCLES STATUS Te{e} C N Z I POP ST 08 1 6 Loaded from stack PUSH A B8 1 6 x x x x B C8 1 6 Rs 08 2 8 PUSH ST OE 1 6 x x x x RETI OB 1 9 Loaded from the stack RETS OA 1 7 x x x x RL A BE 1 5 b7 R R x B CE 1 5 Rd DE 2 7 RLC A BF 1 5 b7 R R x B CF 1 5 Rd OF 2 7 RR A BC 1 5 bO R R x B CC 1 5 Rd DC 2 7 RRC A BD 1 5 bO R R x B CD 1 5 Rd DO 2 7 SBB B,A 6B 1 5 R R R x RS,A 1B 2 8 RS,B 3B 2 8 RS,Rd 4B 3 10 %>iop,A 2B 2 7 %>iop,B 5B 2 7 %>iop,Rd 7B 3 9 SETC 07 1 5 1 0 1 x Note: Add two to cycle count if branch is taken. Legend: o Status Bit set always to O. 1 Status Bit set always to 1. OPERATION DESCRIPTION «SP» -. (ST) (SP) • 1 -. (SP) Replace the Status Register with the last byte of the stack. (SP) + 1 .... (SP) (s) .... (SP) Copy the operand onto the stack. (SP) + 1 .... (SP) (Status Register) -. «SP» Copy the Status Register onto the stack . (SP) .... (PC) LSByte (SP) • 1 .... (SP) (SP) .... (PC) MSByte (SP) • 1 .... (SP) (SP) .... Status Register (SP) • 1 .... (SP) (SP) .... (PC LSB) (SP) • 1 .... (SP) (SP) .... (PC MSB) (SP) • 1 .... (SP) Bit(n) .... Bit(n + 1) Bit(7) .... Bit(O) and Carry Bit(n) .... Bit(n :+- 1) Carry .... Bit(O) Bit(7) .... Carry Bit(n + 1) .... Bit(n) Bit(O) .... Bit(7) and Carry Bit(n + 1) .... Bit(n) Carry .... Bit(7) Bit(O) .... Carry Destination minus source minus 1 plus carry; stored at the destination address. 1 .... (C) Set the carry bit. R Status Bit set to a 1 or a 0 depending on results of operation. x Status Bit not affected. b Bit ( ) affected. 6·14

Assembly Language Instruction Set - Overview Table 6-3. TMS7000 Family Instruction Overview (Concluded) MNEMONIC DPCOD BYTES CYCLES STATUS OPERATION DESCRIPTION Tc(C) C N Z I STA @Label 8B 3 11 0 R R x (A) .... (d) @Label(B) AB 3 13 Store A at the destination. 'Rd 9B 2 10 STSP 09 1 6 x x x x (SP) .... (B) Copy the SP into Register B. SUB B,A 6A 1 5 R R R x (d) - (s) .... (d) RS,A 1A 2 8 Store the destination operand minus the RS,B 3A 2 8 source operand into the destination. RS,Rd 4A 3 10 %>iop,A ·2A 2 7 %>iop,B 5A 2 7 %>iop,Rd 7A 3 9 SWAP A B7 1 8 R R R x d(Hn,Ln) .... d(Ln,Hn) B C7 1 8 Swap th!;l operand's hi and 10 nibbles. Rn 07 2 10 TRAP 0-23 E8-FF 1 14 x x x x (SP) + 1 .... (SP) (PC MSB) .... (SP) (SP) + 1 .... (SP) (PC LSB) .... (SP) (Entry Vector) .... (PC) TSTA BO 1 6 0 R R x 0 .... (C) Set carry bit; set sign and zero flags on the TSTB C1 1 6 0 XCHB A B6 1 6 0 Rn 06 2 8 XOR B,A 65 ' 1 5 0 RS,A 15 2 8 RS,B 35 2 8 RS,Rd 45 3 10 %>iop,A 25 2 7 %>iop,B 55 2 7 %>iop,Rd 75 3 9 XORP APd 85 2 10 0 B,Pd 95 2 9 %>iop,Pd A5 3 11 Note: Add two to cycle count if branch is taken. Legend: o Status Bit set always to O. 1 Status Bit set always to 1. value of Register A R R x 0 .... (C) Set carry bit; set sign and zero flags on the value in Register B. Swap the contents 'of Register B with (d). Logically exclusive OR the source and destination operands, store at the destination address. Logically exclusive OR the source and destination operands, store at the destination. R Status Bit set to a 1 or a 0 depending on results of operation. x Status Bit not affected. b Bit ( ) affected. 6-15

(s) + (Rd) + (C) -+ (Rd) c Z N Set to 1 on carry-out of (s) + (Rd) + (C) Set on result Set on result ADC adds the contents of the source, the contents of the destination register, and the carry bit. It stores the result in the destination register. Adding a 0 to the destination register is equivalent to a conditional in­ crement (increment on carry). ADC can implement multi-precision addition of signed or unsigned in­ tegers. For example, the 16-bit integer in register pair (R2,R3) may be added to the 16-bit integer in (A.S) as follows: ADD R3,BLow order bytes added ADC R2,A High order bytes added LABELl ADC R66,Rl17 Adds the contents of * register 66, register * 117, and the carry bit, * and stores the sum in * register 117 ADC B,A Adds the contents of * Register B, Register A, * and the carry bit, and * stores the sum in * Register A ADC %>3C,R29 Adds >3C, contents of * register 29, and the * carry bit, and stores * the sum in register 29

(s) + (Rd) -+ (Rd) ADD c Z N Set to 1 on carry-out of (s) + (Rd) Set on result Set on result ADD adds two bytes and stores the result in the destination register. It can be used for signed 2's complement or unsigned addition. LABEL ADD A,B Adds the contents of * Registers A and B, stores * the results in B ADD R7,A Adds the contents of R7 * and A, and stores the * results in A ADD %TOTAL,R13 Adds the contents of * TOTAL to R13 and stores * the result in R13 6-17

(s) .AND. (Rd) -+ (Rd) C N Z "'0 Set on resu It Set on result AND logically ANDs the two 8-bit operands. Each bit in the first oper­ and is AN Oed with the corresponding bit in the second operand. This is useful for clearing and resetting bits. If you need to clear a bit in the destination operand, then put a 0 in the corresponding source bit. A 1 in a source bit will not change the corresponding destination bit. This is the truth table for the AND instruction: Source Destination AND Bit Bit Result 0 0 0 0 1 0 1 0 0 1 1 1 LABEL AND %>1,R12 Clear all bits in R12 except Bit 0, which will remain unchanged AND R7,A AND the contents of R7 to A * and store the contents in A AND B,A AND the contents of B to A * and store the contents in A

C N Z +-0 Set on result Set on result ANDP ANDP clears one or more bits in a Peripheral-File register. It can reset an individual output line to zero when the source is an immediate oper­ and serving as a mask field. Since the peripheral register is read before it is ANDed, it may not work with some peripheral locations which have a different function when reading than when writing. The only valid .' source operands are A, B, and %>iop. • I LABEL ANDP %>DF,P6 Clear bit 5 of Port B (P6) ANDP %>FE,P9 Clear Bit o of Port C Data Direction Register (CDDR - P9) ANDP A,P33 AND the contents of A and P33 and store in P33 6-19

[<label>] BR <XADDR> (XADDR) .... (PC) None BR BR branches to any location in the the 64K memory space, including the on-chip RAM. BR supports three extended addressing modes:

• Direct
• Indirect
• Indexed The powerful concept of computed GOTOs is supported by the BR *Rn instruction. An indexed branch instruction of the form BR @TABLE (B) is an extremely efficient way to execute one of several actions on the basis of a control input. This is similar to the Pascal CASE statement. For example, suppose Register B contains a control value. The program can branch to label ACTIONO if B=O, ACTION1 if B=1, etc, for up to 128 different actions. This technique may also be used to transfer con­ trol on character inputs, error codes, etc. LABELl BR @THERE Direct addressing BR @TABLE(B) Indexed addressing BR *R14 Indirect addressing LABEL2 EQU $ Start execution here MOV R3,B Move control input to B RL B Multiply by 2 to get *. table offset BR @TABLE(B) Branch to correct J<cnd> statement DISPATCH EQU $ Dispatch table JMP ACTIONO JMP ACTIONl JMP ACTIONn ACTIONO EQU $ * <Code for action 0> ACTIONl EQU $ * <Code for action 1> ACTIONn EQU $ * <Code for action n>

Bit Test and Jump If One BTJO If (s [Bit x]) .AND. (Rn [Bit x]) ".0, then (PC) + offset ~ (PC) C N Z .... 0 Set on (s) .AND. (Rn) Set on (s) .AND. (Rn) BT JO tests for at least one bit position that contains a corresponding 1 in each operand. The source operand can be used as a bit mask to test for one or more 1 bits in the specified register. The operands are not I changed by this instruction. If a corresponding 1 bit is found, the pro- .. gram branches to the offset.

• LABEL BTJO %>14,R4,ISSET Jump to ISSET if R4 * (bit 2) or R4 (bit * 4) is a 1 BTJO %>l,A,LOOP Jump to LOOP if bit * o of Register A is * a 1 BTJO R37,Rl13,START Jump to START if any * 1 bit of R113 corre- * sponds to a 1 bit * in R37 6-21

Bit Test and Jump If One -' Peripheral BTJOP . If (s [Bit x]) .AND. (Pn [Bit x]) ~ 0, then (PC) + offset ~ (PC) C N z .... 0 Set on (s) .AND. (Pn) Set on (s) .AND. (Pn) BT JOP tests for at least one bit position that contains a corresponding 1 in each operand. The source operand can be used as a bit mask to test for at least one 1 bit in the Peripheral-File register. LABEL BTJOP %>81,P4,THERE Jump to THERE if * bit 0 or bit 7 of * Port A contain * a 1 BTJOP %>FF,P10,STORE Test all bits of * Port D Data (P10) ; * jump to STORE if * any of the bits * are 1s BTJOP B,PSO,AGAIN Jump to AGAIN if * any 1 bit of ·PSO * corresponds to any * 1 bit of the B * Register

Bit Test and Jump If Zero BTJZ C N Z +-:0 Set on (s) .AND. (NOT Rn) Set on (s) .AND. (NOT Rn) BT JZ tests for at least one bit position which has a 1 in the source and a 0 in the destination. The source operand can be used as a bit mask to test for zero bits in the specified register. The operands are un- changed by this instruction. The jump is calculated starting from the .' opcode of the instruction just after the BT JZ. • , LABEL BTJZ A,R23,ZERO If any 1 bits in A * correspond to a bits * in R23 then jump to * ZERO to 0 bits in R23 * then jump to ZERO BTJZ %>FF,A,NEXT If A contains any 0 * bits, jump to NEXT BTJZ R7,R15,OUT If any 0 bits in R15 * correspond to 1 bits * in R7, jump to OUT 6-23

-ExamPles 6-24 Bit Testalid Jump if Zero - Peripheral BTJZP C N Z <-0 Set on (s) .AND. (NOT Pn) Set on (s) .AND. (NOT Pn) BT JZP tests for at least one bit position which has a 1 in the source and an 0 in the Peripheral-File register. The source operand can be used as a bit mask to test for zero bits in the Peripheral-File register. The oper­ ands are unchanged by this instruction. The jump is calculated starting from the opcode of the instruction just after the BT JZP. LABEL BTJZP %>21,P4,THERE Jump to THERE if P4 * (bit 0) or P4 (bit * 5) is 0 BTJZP %>FF,P28,STORE Jump to STORE if P28 * contains any Os BTJZP B,P37,NEXT Jump to NEXT if P37 * contains any 0 bits * corresponding to 1 * bits in Register B

[<label>] CALL <XADDR> (SP) + 1 .... (SP) (PC MSB) .... «SP» (SP) + 1 .... (SP) (PC LSB) .... «SP» (XADDR) .... (PC) None CALL invokes a subroutine and pushes the PC contents on the stack. I The operand indicates the starting address of the subroutine. Use the ~ PUSH and POP instructions to save, pass, or restore Status or register values. The extended addressing modes of the CALL instruction allow • , powerful transfer of control functions. LABEL CALL @LABEL4 Direct addressing CALL @LABEL5(B) Indexed addressing CALL *R12 Indirect addressing 6-25

[<label>] CLR <Rd> 0-+ (Rd) C N Z --0 --0 --1 CLR CLR clears or initializes any file register including Registers A and B. LABEL CLR B CLR A CLR R105 Clear Register B Clear Register A Clear register 105

[<label>] CLRC Set status bits C N Z '-0 Set on value of Register A Set on value of Register A CLRC CLRC clears the carry flag. This may be required before an arithmetic or rotate instruction. The logical and move instructions typically clear the carry bit. The CLRC opcode is equivalent to the TST A opcode. LABEL CLRC Clear the carry bit 6-27

(Rn) - (s) computed but not stored C N Z 1 if (Rn) .:::. (s) Sign of result 1 if (Rn) = (s) CMP compares the destination operand to the source operand and sets the status bits. The CMP instruction is usually used in conjunction with a Jump instruction; Table 6-4 shows which Jump instructions can be used on status conditions set by CMP execution. Table 6-4. Compare Instruction Examples - Status Bit Values (S) (Rn) (Rn)-(S) C N Z INSTRUCTIONS THAT WILL JUMP FF 00 01 0 0 0 JL JNC JNE JNZ JP JPZ

00 FF FF 1 1 0 JHS JC JNE JNZ IN

00 7F 7F 1 0 0 JHS JC JNE JNZ JP JPZ 81 00 7F 0 0 0 JL JNC JNE JNZ JP JPZ 00 81 81 1 1 0 JHS JC JNE JNZ IN 80 00 80 0 1 0 JL JNC JNE JNZ IN 00 80 80 1 1 0 JHS JC JNE JNZ IN 7F 80 01 1 0 0 JHS JC JNE JNZ JP JPZ 80 7F FF 0 1 0 JL JNC JNE JNZ IN 7F 7F 00 1 0 1 JHC JC JEQ JZ JPZ 7F 00 81 0 1 0 JL JNC JNE JNZ IN LABEL CMP R13,R89 Set status bits on * result of RS9 minus R13 CMP B,R39 Set status bits on result * of R39 minus (B) CMP %>03,A Set status bits on result * of (A) minus >03

Compare Accumulator Extended [<label>] CMPA <XADDR> (A) - (XADDR) computed but not stored C N Z 1 if (A) logically ~ (XADDR) 1 if (A) arithmetically < (XADDR) 1 if (A) = (XADDR) CMPA CMPA compares a long-addressed operand to the A register via direct, indirect, -or indexed addressing modes. It is especially useful in table lookup programs that store the table either in extended memory or in program ROM. The status bits are set exactly as if Register A were the destination and the addressed byte the source. LABEL CMPA @TABLE2 Direct addressing CMPA @TABLE(B) Indexed addressing CMPA *R123 Indirect addressing 6-29

Decimal Add with Carry DAC (s) + (Rd) + (C) .... (Rd), Produces a decimal result C N Z 1 if value of (s)" + (Rd) + C.?:. 1 00 Set on result Set on result DAC adds bytes in binary-coded decimal (BCD) form. Each byte is as­ sumed to contain two BCD digits. DAC is not defined for non-BCD operands. DAC with an immediate operand of zero value is equivalent to a conditional increment of the destination operand (increment desti­ nation on carry). The DAC instruction automatically performs a decimal adjust on the binary sum of (s) + (Rd) + C. The carry bit is added to facilitate adding multi-byte BCD strings, and so the carry bit must be cleared before execution of the first DAC instruction. LABEL DAC %>24,A" Add the packed BCD value 24, * and the carry bit to the * Register A carry bit to * Register A DAC R55,R7 Add the BCD value of R55, * and the carry bit to the * BCD value of R7 DAC B,A Add the carry bit to the * BCD value in Register B * to Register A

[<label>] DEC <Rd> (d) - 1 --+ (Rd) C N Z o if (Rd) decrements from >00 to >FF; 1 otherwise Set on result Set on result DEC DEC subtracts 1 from any addressable operand. It is useful in counting and addressing byte arrays. LABEL DEC RI02 Decrement RI02 by 1 DEC A DEC B Decrement Register A by 1 Subtract 1 from the contents of Register B 6-31

[<label>] DECO <Rp> (Rp) - 1 -+ (Rp) DECO C N Z o if most significant byte decrements from >00 to >FF; other­ wise, C = 1 Set on most significant byte of result Set on most significant byte of result DECO decrements 16-bit indirect addresses stored in the Register File. Tables longer than 256 bytes may be scanned using this instruction. The JZ (Jump on Zero) command is often used in conjunction with the DECO command. Note that JZ jumps when the MSB equals zero - not just when both bytes equal zero. LABEL DEeD RSl Decrement (RSO,RS1) register pair, RS1=LSB

[<label>] DINT o .... (Global interrupt enable status bit) I .... 0 C ""0 N ""0 Z ""0 DINT DINT simultaneously disables all interrupts. Since the interrupt enable flag is stored in the Status Register, the POP ST or RETI instructions may re-enable interrupts even though a DINT instruction has been exe- cuted. During the interrupt service, the interrupt enable bit is automat- _ ically cleared after the old Status Register value has been pushed onto • the stack. LABEL DINT Disable global interrupt enable bit 6-33

Decrement Register and Jump If Not Zero (Rd) - 1 -+ (d) If (Rd) ¢ 0, then (PC) + offset -+ (PC) None DJNZ DJNZ is used for looping control. It combines the DEC and the JNZ instructions, providing a faster and more compact instruction. DJNZ does not change the status bits. LABEL DJNZ R15,THERE Decrement R15. If R15 ¢ * 0, jump to THERE. DJNZ A,AGAIN Decrement Ai if A ¢ 0, * jump to AGAIN DJNZ B,BACK Decrement Bi if B ¢ 0, * jump to BACK

Decimal Subtract with Borrow DSB (Rd) - (s) - 1 + (C) .... (Rd) (decimal result) C N Z 1 no borrow required, 0 if borrow required Set on result Set on result DSB performs multiprecision decimal BCD subtraction. A DSB in- struction with an immediate operand of zero value is equivalent to a conditional decrement of the destination operand. The carry bit func- ~ tions as a borrow bit, so if no borrow in is required, the carry bit should be set to 1. This can be accomplished by executing the SETC instruc- tion. • . LABEL DSB R15,R76 R76 minus R15 minus 1 plus * the carry bit is stored * in R76 DSB A,B Register B minus Register * A minus 1 plus the carry * bit is stored in * Register B DSB B,R7 R7 minus Register B minus * 1 plus the carry bit * stored in R7 6-35

. Enable Interrupts [<label>] EINT -+ (Global interrupt enable bit) I <-- 1 C <-- 1 N +- 1 Z <-- 1 EINT EINT simultaneously enables all interrupts. Since the interrupt enable flag is stored in the Status Register, the POP ST or RETI instructions may disable interrupts even though an EINT instruction has been exe­ cuted. During the interrupt service, the interrupt enable bit is automat­ ically cleared after the old Status Register value has been pushed onto the stack. Thus, the EINT instruction must be included inside the inter­ rupt service routine to permit nested or multilevel interrupts. LABEL EINT All interrupts are enabled.

[<label>] IDLE (PC) .... (PC) until interrupt (PC) + 1 .... (PC) after return from interrupt None For NMOS devices, IDLE suspends program operation until either an interrupt or reset occurs. It is the programmer's responsibility to assure that the interrupt enable status bit (and individual interrupt enable bits in the i/O control register) are set before executing the IDLE instruction. Upon return from an interrupt, control passes to the instruction follow­ ing the IDLE instruction. For CMOS devices, the IDLE instruction causes the device to enter one of two low-power modes, which use a fraction of the normal operating power. In Wake-Up mode, the on-chip oscillator remains active, and activating the timer interrupt or the external interrupts (RESET, INT1, or INT3) releases the device from the low-power mode. In Halt mode, using the osc-off clock option, the oscillator and timers are disabled; the device can only be released from Halt mode by an external interrupt or RESET. Using the osc-on clock option in Halt mode, the oscillator con­ tinues to operate and only the timers are disabled; the device can only be released from Halt mode by an external interrupt or RESET. For more information about low-power modes, see Section 3.5. LABEL IDLE 6-37 I

[<label>] INC <Rd> (Rd) + 1 -+ (Rd) C N Z 1 if (Rd) incremented from >FF to >00; 0 otherwise Set on resu It Set on result INC increments the value of any register. It is useful for incrementing counters into tables. LABEL INC A INC B INC R43 Increment Register A by 1 Register B is increased by 1 Register 43 is increased by 1

[<label>] INV <Rd> C N Z <-0 Set on result Set on result INV INV performs a logical or 1s complement of the operand. A 2's com­ plement of the operand can be made by following the INV instruction with an increment (INC). A 1s complement reverses the value of every bit in the destination. LABEL INV A INV B INV R82 Invert Register A (Os become _ 1s, 1s become Os) Invert Register B Invert register 82 6-39

[<label>] JMP <offset> (PC) + offset -+ (PC) JMP (The PC contains the address of the instruction immediately following the jump.) None JMP jumps unconditionally to the address specified in the operand. The second byte of the J MP instruction contains the 8-bit relative address of the operand. The operand address must therefore be within -128 to + 127 bytes of the location of the instruction following the J M P in­ struction. The assembler will indicate an error if the target address is beyond -128 to +127 bytes from the next instruction. For a longer jump the BR (branch) instruction can be used. LABEL JMP THERE Load the PC with the address of THERE

J<cnd> Syntax Execution Status Bits Affected Jump on Condition J<cnd> If tested condition is true, (PC) + offset -+ (PC) (The PC contains the address of the instruCtion immediately following the jump.) None Conditional Jump Instructions INSTRUCTION MNEMONIC C N Z Jump if Carry JC 1 X X Jump if Equal JEQ X X 1 Jump if Higher or Same JHS 1 X X Jump if Lower JL 0 X X Jump if Negative JN X 1 X Jump if No Carry JNC 0 X X Jump if Not Equal JNE X X 0 Jump if Non-zero JNZ X X 0 Jump if Positive JP X 0 0 Jump if Positive or Zero JPZ X 0 1 Jump if Zero JZ X X 1 Use the J<cnd> instructions after a CMP instruction to branch ac­ cording to the relative values of the operands tested. After MOV, MOVP, LOA, or STA operations, a JZ or JNZ may be used to test if the value moved was equal to zero. IN and JPZ may be used in this case to test the sign bit of the value moved. LABEL JNC TABLE If the carry bit is clear, * jump to TABLE JP HERE If the negative and zero flags * are clear, jump to HERE JZ NEXT If the zero flag is set, jump * to NEXT 6-41

[<label>] LDA <XADDR> (XADDR) -+ (A) C N Z +-0 Set on value loaded Set on value loaded LDA reads values stored anywhere in the full 64K-byte memory space. LDA uses three extended addressing modes: Direct Addressing mode provides an efficient means of directly accessing a variable in memory. Indexed addressing gives an efficient table look-up capability for most applications.

• Indirect addressing allows the use of very large look-up tables and the use of multiple memory pointers since any pair of registers can be used as the pointer. LABEL LDA @LABEL4 Direct addresing LDA @LABEL5(B) Indexed addressing LDA *R13 Indirect addressing

[<label>] LDSP (8) -+ (SP) None LDSP LDSP copies the contents of Register 8 to the Stack Pointer register. Use LDSP to initialize the Stack Pointer. LABEL LDSP Copy Register B to the Stack Pointer 6-43

_ExamPles 6-44 Move (s) -+ (Rd) C N Z +-0 Set on value loaded Set on value loaded MOV MOV transfers values within the register space. Immediate values may be loaded directly into the registers. A MOV that uses Register A or B as an operand produces shorter and quicker moves. LABEL MOV A,B Move the contents of Register * A to Register B MOV R32,R105 Move the contents of register * 32 to register 105 MOV %>10,R3 Move >10 to register 3

(s) --+ (Rp) C N Z .... 0 Set on MSb moved Set on MSb moved MOVD MOVD moves a two-byte value to the register pair indicated by the destination register number. (Note that Rp should be greater than 0 or the MSb may be lost.) The destination points to the LSB of the desti­ nation register pair. The source may be a 16-bit constant, another reg- ister pair, or an indexed address. For the latter case, the source must _ be of the form "%ADDR(B)" where ADDR is a 16-bit constant or ad- • dress. This 16-bit value is added (via 16-bit addition) to the contents of the B register, and the result placed in th.e destination register pair. This stores an indexed address into a register pair, for use later in indirect addressing mode. This is not to be confused with the extended ad­ dressing instruction @LABEL(B). LABEL MOVD %>1234,R3 Load register pair R2,R3 * with >1234 MOVD RS,R3 Copy R4,RS to R2,R3; * RS,R3 = LSB MOVD %TAB(B) ,R3 Load register pair R2,R3 * with the effective * address of TAB + B 6-45

MOVp· Syntax Execution Status Bits Affected _ Description Examples 6-46 Move to/from Peripheral Register MOVP or (s) -+ (Pd) or (Ps) -+ (d) C N Z .... 0 Set on value moved Set on value moved MOVP transfers values to and from the Peripheral File. This may be used to input or output 8-bit quantities on the I/O ports. The Peripheral File also contains control registers for the interrupt lines, the I/O ports, and the timer controls. The operands supported by this instruction are A, Band %> iop. During Peripheral-File instructions, a Peripheral-File port is always read before a write. The read can include output operations such as MOVP A,P6. If this read is undesirable because of hardware configuration, use a ST A (Store A) instruction with the memory-mapped address of the peripheral register. LABEL MOVP A,P6 Move the contents of * Register A to Port B RDPORT MOVP P4,B Move Port A data into * Register B LOADD MOVP %>12,P27 Move the hex value 12 into Register 27

(s) x (Rn) .... (AB) Result always stored in AB C N Z "'0 Set on MSb of results (Register A) Set on MSb of results (Register A) MPY MPY performs an 8-bit multiply for a general source and destination operand. The 16-bit result is placed in the A B register pair with the most significant byte in A. Multiplying by a power of two is a conven­ ient means of performing double-byte shifts. If a double byte shift is three places or less, then it may be faster to use RLC or RRC instead of _ mUltiply. If a single byte needs shifting then it is almost always faster • to use RLC or RRC. LABEL MPY R3,A Multiply (R3) with (A), store * result in A, B register pair MPY %>32,B Multiply >32 with (B), store * in register pair A, B MPY R12,R7 Multiply (R12) with (R7) and * store in A, B register pair 6-47

[<label>] NOP (PC) + 1 --> (PC) None NOP NOP is useful as a pad instruction during program development, to "patch out" unwanted or erroneous instructions or to leave room for code changes during development. It is also useful in software timing loOps. LABEL NOP

(s) .OR. (Rd) -+ (Rd) C N Z +-0 Set on result Set on result OR logically DRs the two operands. Each bit of the 8-bit result follows the truth table below. The OR operation is used to set bits in a register. If a register needs a 1 in the destination then a 1 is placed in the corre­ sponding bit location in the source operand. This is the truth table for the OR instruction: Source Destination OR Bit Bit Result 0 0 0 0 1 1 1 0 1 1 1 1 LABEL OR A,R12 OR the A Register with R12, * store in R12 OR %)OF,A Set lower nibble of A to 1s, * leave upper nibble unchanged OR R8,B OR (R8) with (B) , store in B 6-49

• Examples 6-50 OR Peripheral Register C N Z +-0 Set on result Set on result ORP ORPlogically ORs the source operand with a Peripheral-File location, and write the result back to the Peripheral File. This may be used to set an individual I/O bit of a peripheral register. Since the peripheral register is read before it is ORed, it may not work with some peripheral locations which have a different function when reading than when writing. LABEL ORP A,P39 ORP B,P90 OR (A) with (P39), store in P39 OR (B) with (P90), store in P90

[<label>] POP <Rd> (Stack top) -+ (Rd) (SP) - 1 -+ (SP) (Move value then decrement SP) C N Z Set on value POPed Set on value POPed POP POP pulls a value from the top of the stack. The data stack can be used to save or pass values, especially during subroutines and interrupt ser­ vice routines. The Status Register may be replaced with the contents on the stack by the statement POP ST. This one-byte instruction is usually executed in conjunction with a previously performed PUSH ST instruction. LABEL POP R32 Load R32 with top of stack POP ST Load Status Register with top of stack 6-51

[<label>] PUSH < Rs> (SP) + 1 --+ (SP) (Rs) --+ (top of stack) (Increment SP then move value) C N Z +- 0, Or not affected by a PUSH ST instruction. Set on value PUSHed Set on value PUSHed PUSH PUSH places a value on the top of the stack. The data stack is used to save or pass values, especially during subroutines and interrupt service routines. The Status Register may be pushed on the stack with the statement LABEL PUSH ST. This one-byte instruction is usually executed in conjunction with a subsequently performed POP ST instruction. The Status Register is unaffected. LABEL PUSH A Move (A) to top of stack PUSH ST Move status to top of stack

Return from Interrupt RETI [<label>] RETI «SP» -+ (PC LSB) (SP) - 1 -+ (SP) «SP» -+ (PC MSB) (SP) - 1 -+ (SP) «SP» -+ (ST) (SP) - 1 -+ (SP) Status Register is loaded from the stack RETI is typically the last instruction in an interrupt service routine. RETI restores the Status Register to its state immediately before the interrupt _ occurred and branches back to the program at the instruction boundary i • where the interrupt occurred. Registers A and B, if used, must be re­ stored to original values before the RETI instruction. LABEL RETI Restore to program control 6-53

[<label>] RETS «SP» -+ (PC LSB) (SP) - 1 -+ (SP) «SP)) -+ (PC MSB) (SP) - 1 -+ (SP) None RETS RETS is typically the last instruction in a subroutine.RETS branches to the location immediately following the subroutine call' instruction. In the called subroutine there must be an equal number of POPs and PUSHes so that the stack is pointing to the return address and not some other data. LABEL RETS Return to program control

[<label>] RL <Rd> Bit(n) .... Bit(n+1) Bit(7) .... Bit(O) and carry C N Z Set to bit 7 of the original operand Set on result Set on resu It RL RL circularly shifts the destination contents one bit to the left. The MSb is shifted into the LSb; the carry bit is also set to the original MSb value. For example, if Register B contains the value >93, then RL changes the contents of B to >27 and sets the carry bit. LABEL RL R102 RL A RL B 6-55

[<label>] RLC <Rd> Carry -+ Bit(O) C N Z Set to bit 7 of the original operand Set on result Set on result RLC RLC circularly shifts the destination contents one bit to the left and through the carry. The original carry bit contents shift into the LSb, and the original MSb shifts into the carry bit. USb LSb For example, if Register B contains the value >93 and the carry bit is a zero, then the RLC instruction changes the operand value to >26 and the carry to one. Rotating left effectively multiplies the value by 2. Using multiple rotates, any power of 2 (2, 4, 8, 16, ... ) can be achieved. This type of multiply is usually faster than the MPY (multiply) instruction. This instruction is also useful in rotates where a value is contained in more than one byte such as an address or in multiplying a large multibyte number by 2. Care must be taken to assure that the carry is at the proper value. The SETC or CLRC instructions may be uS,e to setup the correct value. LABEL RLC R72 RLC A RLC B

Synt"x Execution Status Bits Affected [<label>] RR <Rd> Bit(n+1) .... Bit(n) Bit(O) .... Bit (7) and carry C N Z Set to bit 0 of the original value Set on result Set on result RR RR circularly shifts the destination contents one bit to the right. The LSb is shifted into the MSb, and the carry bit is also set to the original LSb value. For example, if Register B contains the value >93, then the "RR B" in­ struction changes the contents of B to > C9 and sets the carry status bit. LABEL RR A 6-57

RRC· Syntax Execution Status Bits Affected Rotate Right Through Carry [<label>] RRC <Rd> Bit(n+1) .... Bit(n) Carry .... Bit(7) Bit(O) .... Carry C N Z Set to bit 0 of the original value Set on result Set on result RRC RRC circularly shifts the destination contents one bit to the right through the carry. The carry bit contents shift into the MSb, and the LSb is shifted into the carry bit. MSb LSb For example, if Register B contains the value >93 and the carry bit is zero, then RRC changes the operand value to >49 and sets the carry bit. When the carry is 0 this instruction effectively divides the value by two. A value of >80 becomes >40. By using this instruction once more, the value can be divided by any power of two. Care must be taken to assure the correct value in the carry bit. LABEL RRC R32

C N Z Set to 1 if no borrow; 0 otherwise Set on result Set on result SBB SBB performs multiprecision 2's complement subtraction. An SBB in­ struction with an immediate operand of zero value is equivalent to a conditional decrement of the destination operand. If (s) =0 and (C) =0 then (Rd) is decremented, otherwise it is unchanged. A borrow occurs if the result is negative. In this case, the carry bit is set to O. The carry _ bit can be thought of as the "no-borrow" bit. • LABEL SBB %>23,B Subtract (B) from >23, sub- * tract 1, add the carry bit; * store in Register B SBB B,A (B) minus (A) minus 1 plus * the carry bit is stored * in Register A SBB %>33,R6 Subtract (R6) from >33, sub- * tract the inverse of the * carry bit 6-59

[<label>] SETe 1 -+ (e) C N Z +-1 +-0 +-1 Set Carry SETC SHe sets the carry flag (if required) before an arithmetic or rotate in­ struction. LABEL SETC

[<label>] STA <XADDR> (A) -+ (XADDR) C N Z "'0 Set on value loaded Set on value loaded STA stores values anywhere in the 64K-byte memory address space. STA uses three extended addressing modes:

• • Direct Addressing provides an efficient means of directly accessing a variable in memory. Indexed Addressing provides efficient table look-up. Indirect Addressing allows the use of very large look-up tables and the use of multiple memory pointers since any pair of registers can be used as the pointer. LABEL STA @VALUE Direct addressing STA @TABLE(B) Indexed addressing STA *R13 Indirect addressing 6-61

[<label>] STSP (SP) -+ (B) None STSP STSP copies the SP to Register B. This instruction can be used to test the stack size. The indexed addressing mode may be used to reference operands on the stack. For example. STSP; then LDA @>OOOO(B) will put the present value on top of the stack into Register A. LABEL STSP Copy the SP to Register B

(Rd) - (s) --+ (Rd) C N Z Set to 1 if result> 0, otherwise set to ° Set on result - Set on result SUB SUB performs 2's complement subtraction. The carry bit is set to ° if a borrow is required. The carry bit could be renamed a "no-borrow" bit in this case. LABEL SUB R19,B (B) minus (R19) is * stored in R19 SUB %>76,A (A) minus >76 is stored * in A SUB R4,R9 (R9) minus (R4) stored * in R9 6-63

_ Examples 6-64 Swap Nibbles [<label>] SWAP <Rn> C N Z Set to bit ° of the result or bit 4 of the original Set on results Set on results SWAP SWAP exchanges the first four bits with the second four bits. This in­ struction is equivalent to four consecutive RL (rotate left) instructions. It manipulates four bit operands, especially useful for packed BCD op­ erations. LABEL SWAP R45 Switch Lo and Hi nibbles of R45 SWAP A Switch Lo and Hi nibbles of A SWAP B Switch Lo and Hi nibbles of B

[<label>] TRAP <n> where n = 0-23 (SP) + 1 (PC MSB) (SP) + 1 (PC LSB) (Entry vector) TRAP Affected None Trap is a one-byte subroutine call. The operand <n> is a trap number which identifies a location in the trap vector table, addresses >FFDO to >FFFF in memory. The contents of the two-byte vector location form _ a 16-bit trap vector to which a subroutine call is performed. TRAP is • an efficient way to invoke a subroutine. The highest block of memory is the trap vector table, and can contain up to 23 subroutine addresses. The subroutine addresses are stored like all other addresses in memory, with the least significant byte in the higher-addressed location, as shown below. >FFDO >FFD1 >FFEO >FFE1 >FFFA >FFFB >FFFC >FFFD >FFFE >FFFF TRAP VECTOR TABLE Trap 23 address Trap 23 address Trap 1 5 address Trap 15 address Trap 2 address Trap 2 address Trap 1 address Trap 1 address Trap 0 address Trap 0 address MSB LSB MSB LSB MSB LSB Note that TRAPs 0, 1, 2, and 3 correspond to the hardware-invoked interrupts 0, 1, 2, and 3, respectively. The hardware-invoked interrupts, however, push the Program Counter and the Status Register before branching to the interrupt routine, while the TRAP instruction pushes only the Program Counter. TRAP 0 will branch to the same code exe­ cuted for a system reset but will not set or clear all the registers like the hardware RESET. LABEL TRAP 15 6-65

I I Example 6-66 Test Register A [<label>] TSTA C,N,Z bits set C N Z +-0 Set on value in Register A Set on value in Register A TSTA TSTA sets the status bits according to the value in Register A. This in­ struction is equivalent to the CLRC (Clear Carry) instruction. LABEL TSTA Test Register A

[ < label>] TSTB C,N,Z bits set C N Z .... 0 Set on value in Register B Set on value in Register B TSTB TSTB sets the status bits according to the value in Register B. It may be used to clear the carry bit. This instruction is equivalent to the XCHB B (exchange B with B) instruction. LABEL TSTB Test Register B 6-67

[<label>] XCHB <Rn> C N Z +-0 Set on original contents of B Set on original contents of B XCHB XCHB exchanges a register with Register B without going through an intermediate location. The XCHB instruction with the B Register as the operand is equivalent to the TSTB instruction. LABEL XCHB A XCHB R3 Exchange Register B with Register A Exchange Register B with R3

C N Z +-0 Set on result Set on result XOR performs a bit-wise exclusive OR operation on the operands. The XOR instruction can be used to complement bits in the destination op­ erand. Each bit of the 8-bit result follows the truth table below. This operation can also toggle a bit in a register. If the bit value in the des­ tination needs to be the opposite from what it currently is, then the source should contain a 1 in that bit location. This is the truth table for the XOR instruction: LABEL Source Bit XOR R9B,R125 XOR %>1,R20 XOR B,A Destination XOR Bit Result 0 0 1 1 0 1 1 0 XOR (R9B) with (R125), store in R125 Toggle bit 0 in R20 XOR (B) with (A), store in A 6-69

• Examples 6-70 Exclusive OR Peripheral Register XORP (s) .XOR. (Pd) -> (Pd) C N Z <-0 Set on result Set on result XORP performs a bit-wise exclusive OR operation on the operands. The XORP instruction can be used to complement bits in the destination PF register. Since the peripheral register is read before it is XORed, it may not work with some peripheral locations which have a different function when reading than when writing. LABEL XORP %>Ol,P9 Invert bit 0 of P9 (Port C * DDR) ; this inverts the * direction of the pin XORP %>AA,P29 Toggle odd bits of P29 XORP B,P99 XOR (B) with (P99) , store * in P99

The TMS7000 Assembler creates both absolute and relocatable object code that can be linked to form executable programs from separately assembled modules. An entire program need not be assembled at one time. A long program can be divided into separately assembled modules, avoiding a long assembly and reducing the symbol table size. Caution must be observed when assembling a long program with excessive labels; this may cause an assembler error from symbol table overflow. Modules that are common to several pro­ grams can be assembled once and accessed when needed. These separate­ ly-generated modules can be linked together by the Link Editor, forming a single linked object module that is stored in a library and/or loaded as re­ quired. The Link Editor User's Guide (literature number SPNU037) contains a complete description of the Link Editor, related files, linker commands, linking examples, and error messages. This section provides all the information that most TMS7000 users need to link program modules. Section Page 7-1

Linking Program Modules - Relocation Capability

7.1 Relocation Capability

Absolute code is appropriate for code that must be placed in dedicated areas of memory. It must always be loaded into the same memory area. Relocatable code includes information that allows a loader to place the code in any available memory area, allowing the most efficient use of available me­ mory. Object code generated by an assembler contains machine language in­ structions, addresses, and data. The code may include absolute segments, program-relocatable segments, data-relocatable segments, and numer­ ous common-relocatable segments. In assembly language source pro­ grams, symbolic references to locations within a relocatable segment are called reloeatable addresses. These addresses are represented in the object code as displacements from the beginning of a specified segment. A program-relo­ eatable address, for example, is a displacement into the program segment. At load time, all program-relocatable addresses are adjusted by a value equal to the load address. Data-reloeatable addresses are represented by a displace­ ment into the data segment. There may be several types of eommon-relocat­ able addresses in the same program, since distinct common segments may be relocated independently of each other. Expressions may contain more than one symbol that is not previously defined. Expressions on either side of a multiplication or division symbol must be ab­ solute; if they are relocatable, the expression is illegal. An expression in which the number of relocatable symbols or constants added to the expression ex­ ceeds the number of relocatable symbols or constants subtracted from the expression by more than one is illegal. That is, if: NA = Number of relocatable values added, and NS = Number of relocatable values subtracted Then, if NA - NS = o Neither The expression is absolute The expression is relocatable The expression is illegal An expression containing relocatable symbols or constants of several different relocation types is absolute if it is absolute with respect to all relocation types. If it is relocatable with respect to one relocation type and absolute with respect to all other relocation types, it is relocatable. Examples of valid expressions include: BLUE+1 GREEN.-4 2*16+RED 440/2-RED The value of symbol BLUE + 1 The value of symbol GREEN - 4 2 times 16 plus the value of symbol RED 440 divided by two less the value of symbol RED. Red must be absolute.

Linking Program Modules - Link Editor Operation Decimal, hexadecimal. and character constants are absolute. Assembly-time constants defined by absolute expressions are absolute, and assembly-time constants defined by relocatable expressions are relocatable. Any symbol that appears in the label field of a source statement (other than an EQU directive) is absolute when the statement is in an absolute block of the program. Any symbol that appears in the label field of a source statement (other than an EQU directive) is relocatable when the statement is in a re­ locatable block of the program. The type of the label or an EQU directive is the type of an expression in an operand field.

7.2 Link Editor Operation

The Link Editor combines separate modules to produce a single linked output module. It resolves externally referenced symbols and definitions created by the REF and DEF directives. Without this function, all modules would have to be compiled or assembled at once. The Link Editor builds a list of symbols from the REF tags in the object modules that are to be included in the linking process. The Link Editor then resolves the references by matching DEF tag symbols with the REF tags and inserting the correct values for these symbols in the linked object code. A link control file, which must be created before the assembly, controls the Link Editor operation. The link control file contains a set of link control com­ mands (control stream) that direct the Link Editor in combining various object modules. Figure 7-1 shows a sample link control file. Table 7-1 summarizes the linker commands most often used to link TMS7000 program modules. The link control commands define which modules are to be linked and how they are to be linked. The Link Editor automatically resolves the REF and DEF tag symbols between object modules specified in the INCLUDE commands. The Link Editor links the object modules in the order specified by the link control commands. Thus, the structure of the control stream determines the structure of the linked object module. TASK PROGNAME Defines name (8 letters maximum) INCLUDE MYPRGRAM.MPO Pathnames of object files, compatible INCLUDE OTHERPGM.MPO with user's computer system END Last statement of link module Figure 7-1. Sample Link Control File 7-3

Linking Program Modules - Link Editor Operation Table 7-1. Linker Commands Used to Link TMS7000 Program Modules COMMAND SYNTAX AND DESCRIPTION COMMON Syntax: COMMON {<base> [ , <name>] [ , <name>] .. } Defines the starting address for the specified common segment (CSEG). Commons that are loaded at the specified address must be specifically identified within this command. COMMON is only valid when used with PROGRAM. <base> is the starting location of the common segment. It can be a decimal or a hexa- decimal number. <name> is the name of the common segment. DATA Syntax DATA <base> Defines the absolute starting address for the data segment (DSEG) in the linked output. DATA is only valid when used with PROGRAM. <base> is the starting location of the data segment. END Syntax: END Indicates the end of the link control stream. This command is required in every link control file. INCLUDE Syntax: Defines one or more modules to be included in the linking process. This is a required command. More than one INCLUDE statement may be used. <acnm> is the access name of a file containing the object module(s) to be inluded in the linking process, and «name» is a member in a library. PROGRAM Syntax: PROGRAM <base> Defines the absolute starting address for the program segment (PSEG) in the linked output. <base> is the starting location of the program segment. TASK Syntax: TASK [<name>] Defines the name of the task; this becomes the lOT name, placed on the last record of the object module. <name> is the task module identifier, and can have up to eight characters. If omitted, the lOT name of the first included module is used as the task name. 7-4

Linking Program Modules - Link Editor Operation Avoid using AORG in object modules which will be linked. Linking a module that contains an AORG directive may produce an //legal immediate tag en­ countered error at link time. Use the PSEG, CSEG, and DSEG directives in­ stead to identify the locations in the source code. Use the PROGRAM, COMMON, and DATA commands in the link control file to define the lo­ cations. The link control file will look similar to this example: TASK PROGRAM DATA COMMON INCLUDE INCLUDE END MYPROG >F006 >FFDO FILEl FILE2 Program starting point (PSEG) Trap and vector table stg pt (DSEG) Additional starting location (CSEG) 7-5

Linking Program Modules - Directives Used for Linking

7.3 Directives Used for linking

The assembler includes four directives used for linking program modules: lOT Names the program module. REF Names symbols used in the current module but defined in another module. SREF Names symbols used in the current module that may not be defined in another module. OEF Names symbols defined in the current module that can also be used by other modules. For more information about directives, see Section 6, Assembler Directives. 7.3.1 lOT - Program Identifier Directive _ The lOT directive assigns a name to the program module. Its syntax is: [label] IDT <string> where [label] is optional, and <string> contains the module name. If a module will be linked, it must include an lOT directive. Each module name is limited to eight characters and must be unique.

7.3.2 DEF - External Definition Directive

Symbols defined in a program module and required by other program modules must be defined by the DEF directive. The following example shows a pro­ gram named ROUTINES that DEFs a routine named SUBR1. The label SUBR1 must be defined in the program. Example 7-1. File A 7-6 IDT 'ROUTINES' DEF SUBR1,SUBR2 Subroutines #1 and #2 entry points SUBR1 EQU $ RETS SUBR2 EQU $ RETS END Subroutine #1 starts here Subroutine #2 starts here When the program in Example 7-1 is linked with the program in Example 7-2, the references are automatically resolved.

Linking Program Modules - Directives Used for Linking

7.3.3 REF and SREF - External Reference Directives

If a module uses a symbol that is defined in a different module, it must be ex­ ternally referenced by the REF or the SREF directive. The following example shows a program, MAIN, which REFs a subroutine named SUBR1. (SUBR1 is not defined in File B.) Example 7-2. File B lOT REF CALL END 'MAIN' SUBR1 @SUBR1 Subroutine #1 entry point Execute subroutine #1 now 7-7

Linking Program Modules - Directives Used for Linking 7-8

The TMS7000 Macro Assembler supports a macro definition language. Macro definitions allow you to create your own "commands." This is especially useful when a program executes a particular task several times. A macro de­ finition contains source statements that are associated with a unique macro name. When the macro name is used as an opcode in a program source statement (referred to as a macro call), the macro definition's predefined source statements are substituted for the macro call statement. This section discusses the following topics: Section Page 8-1

Macro Language - Defining Macros

8.1 Defining Macros

A macro definition begins with a source statement like this: <MACNAME> $MACRO [<parml>,<parm2> ... ] [<comment>] where: <MACNAME> Names the macro; it may contain a maximum of six alpha­ numeric characters. It is placed in the source statement's label field. $MACRO . Identifies this source statement as the first line of a macro definition; it appears in the opcode field. <parms> Parameters passed to the macro when called (not all macros will have parameters); they appear in the operand field. <comment> Optional. . There are three methods for defining macros: 1) Macros can be defined in the sour~e file where they are used. Macros must be defined before they are called; it is good practice to place all the definitions at the top of the file. This provides easy reference to all the definitions because they are in one location. 2) Macros can also be defined in external files. These files are simply text files, like the assembler source file. Only one macro may be defined per external file. These external macro definition files are collected to form a macro library. 3) All macros can be placed in one file without the source program, and then the COpy directive can be used to include the macro file in the source program. When a macro is called, the assembler searches several places for its definition. Let's assume that the directory file 'VOLUME.DIRECTORY.MACUS' contains a library of macro definitions. The MUS directive tells the assembler that a macro library exists. The MUS directive syntax is: HLIB 'VOLUME.DIRECTORY.MACLIB' The quoted string names the macro library. (This string represents a directory name in the host operating system format.) This library contains a definition for a macro named CPXADD. Assume that an assembly language source program contains the following macro call: LABEL CPXADD CX1,CX2 The assembler uses the following .search order to find the macro definition: 1) The in-memory macro table is the first place searched. CPXADD will be in the macro table if: a) It was previously defined in the assembler source file or b) It has already been read from a macro file.

Macro Language - Defining Macros 2) IfCPXADD is not found in the macro table, the assembler searches the normal assembler opcode/directive table. If found there, the op­ code will be assembled as a normal machine instruction. 3) If the definition is not in the opcode/directive table, the macro name is appended to the macro library name. If more than one MUB directive was encountered, the assembler searches the most recently defined library first, then the library defined before that, and so on. If the file is found, the macro definition is copied into the assembler's macro file (in a compressed format), and an entry is made in the macro table for later use. The search order prevents a macro defined in a library from automatically re­ defining a machine instruction because the assembler searches the opcode table before the libraries. This can be circumvented in two ways: 1) Define the macro in the source program or 2) Include another file in the macro library called an MUST (macro list). An MUST file is a text file that contains the names of the opcodes and cur­ rently defined macros that are redefined by macros in the library. A typical MUST file might be constructed as follows; note that there is only one definition per line and each statement begins in column one. file named <MUS directory name>.MUST record 1 ADD (opcode) record 2 LACK (opcode) record 3 MOV (opcode) record 4 FSUB (macro) eof (MUST) The MUST is read (if provided) when the MUB directive is processed. If a name found there matches a currently defined opcode or a name in the macro table, the matching entry is removed from its table. This forces a search of the libraries, since the name will not be found elsewhere. The following message is printed when a name is found that matches an opcode: , ** OPCODES REDEFINED' The message appears after the printing of the MUB statement. A similar mes­ sage: , ** MACROS REDEFINED' appears when currently defined macros are redefined. If you do not want an opcode or macro to be redefined, you must delete the appropriate records from the MUST file. The name of a macro in a file should be the same as the file name, or the macros are not used efficiently. If the file named CPXADD contains a defi­ nition line such as CPXMUL $MACRO MR, MD the macro CPXMUL is entered into the macro table, and the next call to CPXADD will be undefined and re-entered into the macro table as CPXMUL. 8-3

Macro Language - Defining Macros

8.1.1.1 Using Macro Libraries on MS/PC-DOS Systems

The following program segment suggests a method for using macro libraries on an MS/PC-DOS system. MLIB ADD MOV * XMAC * NOP * YMAC * NOP END 'E: I R3,R4 R6,R9 The pathname must be a drive name Typical assembly code First macro call Another macro call The assembler searches the drive specified by the MLiB directive for a file with the same name as the macro. The macro name cannot have an extension. Only one macro is allowed per file. The assembler searches the current MS/PC- DOS directory structure for the drive specified in the MUB directive. A possible example of macro library use is:

• Store all macros on the A drive in a directory named MACROS.
• Store the TMS7000 assembler on the E drive (or any drive other than A) in a directory named PROGRAMS. The assembler program name is XASM7.EXE.
• Store the source program on the E drive in a directory named ASSEM­ BLY. The source program name IS CODE.ASM. It includes this directive statement: .MLIB 'A: I
• Issue a path statement that includes the program directory: PATH E:\\;E:\\MSDOS;E:\\PROGRAMS
• The following batch file will assemble the program: CD A:\\MACROS CD E:\\ASSEMBLY XASM7 CODE.ASM; Insure execution from drive E: Change A: drive's directory Change E: drive's directory Assemble the file CODE.ASM

8.1.2 Sample Macros

Assume that a symbol representing a memory address, ADR, is set in a source file:

Macro Language - Defining Macros ADR EQU )FOOO This is a simple example of a macro definition that increments ADR: INCADR $MACRO LDA INC STA $END where: @ADR A @ADR Names a macro, INCADR. Identifies the beginning of the macro definition. INCADR $MACRO LDA @ADR INC A STA @ADR $END Are model statements that are substituted into the source pro­ gram when the macro is called. A model statement "models" an assembler language statement. Such a statement is (or will form after macro substitution) a legal language statement. Identifies the end of the macro definition. The macro INCADR can now be used in the source program as often as nec­ essary. Call the macro by entering the following line into the source file: INCADR The macro assembler replaces this line with the macro definition: LDA @ADR INC A STA @ADR INCADR is limited because the macro can only be used with a single memory location, ADR. The following macro uses parameters and is more flexible. It can be used with any memory location. INC $MACRO M where: M M.S LDA @:M.S: INC A STA @:M.S: $END Is a macro parameter. It is replaced by the actual parameter when the macro is called. Is the strinQ component of this variable (the symbol representation of the variable). For example, the fine: INC Y will be replaced by: LDA @Y INC A STA @Y but INC DATA4 will be replaced by: LDA @DATA4 INC A STA @DATA4 8-5

Macro Language - Strings, Constants, and Operators Macro language literal strings are identical to the character strings used by TMS7000 assembly language. The strings contain one or more characters enclosed in single quotes. Examples of valid strings are: 'ONE' , , (a blank) Macro language constants are defined in the same manner as assembly lan­ guage constants. Examples of valid constants are: >9F3C $ (current PC value) Arithmetic operators can be used in operands. Functions of +, -, * (mul­ tiply), and / (divide) can be used to generate operand values. Examples using arithmetic operators are: LABEL EQU $+4 (current ,PC value + 4) Relational operators can also be used. Relational operators compare the values of two variables or constants and return the answer of TRUE or FALSE. The relational operators are: ::: Equal > Greater than < Less than #= Not equal Examples using relational operators are: $IF $IF A.V>3 B.L#=A.L Process succeeding block if value component of variable A is >3. Process succeeding block if length component of variable B is not equal to length component of variable A. The macro assembler also allows the use of Boolean operators, which per­ form the desired operation and return either TRUE or FALSE. The Boolean operators are: & AND ++ OR NOT An example using the Boolean operators is: $IF --((A.V>3)&(B.L#=A.L» Macro symbol components can be concatenated with literal strings, model statement characters, and other macro variables. Conc.atenation is indicated by writing character strings side by side with string mode references.

Macro Language - Variables

8.3 Variables

Macro definitions can include variables which are represented in the same manner as symbols in the assembler symbol table (AST). Macro variables can have a maximum length of two characters. Examples of valid variables are: VA SC A Note: Macro variables are strictly local, available only to the macro which defines them. Symbols in the assembler symbol table can only be accessed through symbol components. Macro variables can be defined in two ways: 1) As parameters defined by the $MACRO statement, and 2) In $ASG statements (see the $ASG verb). The macro translator maintains a macro symbol table (MST) similar to the AST. Each MST entry contains the. variable/parameter and its string, value, length, and attribute components. The macro expander module places pa­ rameters in the MST when macro calls are processed aAd places variables in the MST when it processes $ASG statements.

8.3.1 Parameters

Parameters are variables that are declared in the $MACRO definition state­ ment. The parameter declaration sequence corresponds to the sequence of the operands in the macro call statement. During macro expansion, the parame­ ters receive the values of the macro call operands. Examples of $MACRO statements with parameters are: LABEL NAME $MACRO A,B3 $MACRO O,RC,AM 8-7

Macro Language - Variables There are four types of variable/parameter components: 1 ) The string component of an MST entry contains a character string assigned to the macro variable/parameter by the macro expander. The value component of an MST entry contains: a) The binary equivalent of the string component, if the string com­ ponent is an integer. b) The value of the symbol, if the string component is a symbol in the AST. c) The length of the list, if the parameter is an operand list. The length component contains the number of characters in the string component. The attribute component of the MST is a bit vector. The bits corre­ spond to the attributes of the variable or parameter. The following statement defines a macro with parameters X and NUM: ADDK $MACRO X,NUM The following statement calls the ADDK macro: ADDK VARl,3 The MST now contains entries for parameters X and NUM and their associated components: Parameter X: String Component Attrit>ute Component Is the character string VAR1. Indicates that the parameter is supplied in a ma­ cro call (keyword $PCALL). length Component Parameter NUM: Is 4. String Component Value Component lenQth Component Attribute Component Is the character 3. Is 3 also, expressed as a 16-bit binary number. Is 1. Indicates that the parameter is supplied in the macro call (keyword $PCALL). Each component of a macro variable can be accessed individually in either binary or string mode: In binary mode, the referenced macro variable component is treated as a signed 16-bit integer. Binary mode is accessed by writing the variable name and component. A reference to the string component of a macro variable in binary mode is the 16-bit integer value of the ASCII repre­ sentation of the first two characters of the string. For example, the bi­ nary mode value of the string component of X, in the preceding example, is >5641, which is the ASCII representation for VA. String mode access of macro variable components is signified by en­ closing the variable in a pair of colon characters (:). For example, :X: Note: Colons are always used in pairs to enclose a variable name. If a variable component qualifier is used, the pair of colons enclose the entire qualified name.

Macro Language - Variables

8.3.3 Variable Qualifiers

Table 8-1 lists the names used to indicate variable/parameter components. The variable name is followed by a period (.) and the single letter qualifier. Table 8-1. Variable Qualifiers QUALIFIER MEANING S The string component of the variable A The attribute component of the variable V The value component of the variable L The length component of the variable The following examples show qualified variables for the macro call: ADDK VAR1,3 which was defined by the following statement: ADDK $MACRO X,NUM X.S Is the string component (binary mode) of variable VAR1. X.S equals the binary equivalent for VA, or >5641. If string mode is indicated, as in :X.S:, the string component is the character string VAR1. X.A Is the attribute component of variable VAR1. This component is ac­ cessed by using logical operators and keywords as described in Table 8-2, Table 8-3, and Table 8-4. X.V Is the value component of variable VAR1. X.l Is the length component of variable VAR1; in this case, it is equal to the character string 4. Unqualified variables (except those in $ASG statements) refer to the variable's string component. These two strings are equivalent: :CT.S: WAY Variable CT qualified; string component = WAY. :CT: WAY Variable CT unqualified; string component = WAY. Note: Binary references to macro variables in model statements must be quali­ fied. 8-9

Macro Language - Variables Entries in the assembler symbol table have symbol components. To access symbol components in a macro, the symbol must be assigned to the string component of a macro variable by an $ASG statement. The additional qual­ ifiers shown in Table 8-2 are used with macro variables to access the AST symbol's components. Table 8-2. Variable Qualifiers for Symbol Components QUALIFIER MEANING SS String component of a symbol that is the string component of a variable. SV Value component of a symbol that is the string component of a variable. SA Attribute component of a symbol that is the string component of a vari- able. SL Length component of a symbol that is the string component of a variable. The following examples show qualified variables that specify symbol compo­ nents of variable string components. Assume that the following statement appears in the source program: MASK EQU >FF This statement appears in a macro definition: $ASG Vl.S TO MASK V1.SS Is the string component of the symbol MASK. This is null unless a macro instruction has caused a string to be associated with it by using a $ASG statement. V1.SV Is the value component of the symbol MASK (>FF). In the string mode, :V1.SV: equals the character string 255. V1.SA Is the attribute component of the symbol MASK. This component may be accessed by using logical operators and keywords. V1.SL Is the length component of the symbol MASK. If a string has been assigned to MASK, then V1.SL is the length of that string. Concatenation is especially useful when a previously defined string is aug­ mented with additional characters. Assume that CT.S represents the string ONE. : CT. S:' WAY' produces the string 'ONE WAY' If CT.S represented the character string TWO, the result of the concatenation in the example would be TWO WAY. Strings and qualified variables can be concatenated as required. Components of variables that are represented by a binary value (e.g., CT.V and CT.L) are converted to their ASCII decimal equivalent before concatenation. For example: : CT. S' WAY ': CT. L: expands into ONE WAY 3 since the length component of the variable CT is three.

8.4 Keywords

Keywords identify assembler symbol and macro parameter attribute compo­ nents. Each keyword represents a bit position in a word that contains all of the symbol or parameter attribute components. Keywords can be used with logical operators and attribute components to test or set a specific attribute of a symbol or parameter. The following paragraphs describe how keywords are used with symbols and parameters. Table 8-3 lists keywords that are used with a logical operator and the symbol attribute component (.SA) to test or set the corresponding attribute compo­ nent in the AST. Table 8-3. Symbol Attribute Keywords KEYWORD MEANING $REL Symbol is relocatable $REF Symbol is an operand of an REF directive $DEF Symbol is an operand of a DEF directive $STR Symbol has been assigned a component string $MAC Symbol is defined as a macro name $UNDF Symbol is not defined Note: Using these attributes in conditional assembly (with the $IF verb) may lead to pass conflict errors if the symbol is not defined before the macro is called. Assume that the next statement is an assembler program source statement and the second statement appears in a macro definition: MASK EQU $ASG >FF Vl.S TO MASK The next line ANDs symbol MASK's attribute component with a flag corre­ sponding to the keyword $STR. Vl.SA&$STR This expression is TRUE when MASK's contents are not null; otherwise, the expression is FALSE. The next example shows ORs symbol MASK's attribute component with the flag corresponding to 'the keyword $REL. Vl.SA++$REL 8-11

Table 8-4 lists keywords that are used with a logical operator and the macro symbol attribute component to test or set the corresponding attribute in the MST attribute component. Use these attribute keywords to test or set attribute components of all variables in the MST. Table 8-4. Parameter Attribute Keywords KEYWORD MEANING $PCALL Parameter appears as a macro-instruction op- erand $POPL Parameter is an operand list; the value compo- nent contains the number of operands in the list $PSYM Parameter is a symbolic memory address t t A symbolic memory address is recognized when the variable is preceded by an @ character. The following expressions use parameter attribute component keywords: P6.A&$PCALL AN 0 variable P6's attribute component with the flag corresponding to keyword $PCALL. The expression is' TRUE when variable P6 is a parameter supplied in a ma­ cro call. otherwise the expression is FALSE. RA.A++$PSYM OR variable RA's attribute component with the flag cor­ responding to keyword $PSYM.

Macro Language - Assigning Values to Parameters Macro definitions expand macro calls (statements that have the macro name as an opcode). Macro definition syntax is: <macro name> $MACRO [<parm>] [,<parm>] [<comment>] Macro call syntax is: <macro name> [<operand/list>],[<operand/list>] [<comment>] When a macro call is processed, the macro expander associates the first pa­ rameter in the $MACRO statement with the first operand or operand list in the macro call, the second parameter with the second operand or operand list, and so on. Each operand may be any assembler expression or address type, or a quote­ enclosed character string. An operand list is a group of operands enclosed in parentheses and separated by commas (when two or more operands are in • list). An operand list is processed as a set after the outer parentheses are re- : moved, during macro expansion. Operands (or operand lists) may be nested in parentheses in the macro call for use within macro definitions. The following $MACRO statement defines two parameters. ONE $MACRO Pl,P2 The corresponding macro call ONE PAR1,PAR2 associates PAR1 with P1 and PAR2 with P2. However, a call such as: ONE PAR1,(PAR21,PAR22) associates PAR1 with P1 and the list PAR21 ,PAR22 with P2. Now :P2: or :P2.S: can be used as a pair of operands in a model statement. The $PCALL attribute is set for each parameter that receives a value. When the $MACRO statement defines more parameters than the number of operands in the macro call, the $PCALL attribute is not set for the excess parameters. The $PCALL attribute is also not set if an operand is "null"; Le., the call line has two commas adjacent or an operand list of zero operands. Expansion of the macro can be controlled by the number of operands by using the $PCALL at­ tribute and $IF statement. For example, the following macro definition and macro call AMAC $MACRO Pl,P2,P3 AMAC AB1,AB2 sets $PCALL for parameters P1 and P2 but not for P3. Similarly, AMAC XY, ,XY3 sets $PCALL for P1 and P3 but not for P2. 8-13

Macro Language - Assigning Values to Parameters 8-14 When the macro instruction has more operands than the number of parameters in the $MACRO statement, the excess operands are combined with the oper­ and or operand list corresponding to the last parameter to form an operand list (or a longer operand list). In the macro statements below, the operands of the two macro calls would be assigned to the parameters in the same ways: ( 1) ONE TWO THREE FIX (2) A B C D E F G H I PARM EQU EQU EQU $MACRO FIX FIX EQU EQU DATA DATA EQU EQU EQU EQU EQU $MACRO PARM Pl,P2 Define Macro FIX ONE,TWO,THREE Call Macro FIX ONE, (TWO, THREE) Call Macro FIX 101 119 P1,P2,P3,P4,P5,P6,P7,P8,P9 @A"B,(),C,(D),E,(G,(H,I)) Parameter assignments: P1.S = A P1.A = $PCALL P1.L = 1 P1.V = 7 P3.S = B P3.A = $PCALL P3.L = 1 P3.V = 15 P5.S = C P5.A = $PCALL P5.L = 1 P5.V = 17 P7.S = E P7.A = $PCALL P7.L = 1 P7.V = 95 P9.S = (no string) P9.A = 0 (all false) P9.L = 0 P9.V = 0 P2.S = (no string) P2.A = (all false) P2.L = 0 P2.V = 0 P4.S = (no string) P4.A = $POPL P4.L = 0 P4.V = 0 P6.S = D P6.A = $PCALl.$POPL P6.L = 1 P6.V = 1 PB.S = G,(H,I) PB.A = $PCALL,$POPL PB.L = 7 PB.V = 2

8.6 Verbs

The macro language supports seven verbs that are used in macro language statements. Table 8-4 lists the seven verbs. Any statement in a macro defi­ nition -that does not contain a macro language verb in the operation field is processed as a model statement. Table 8-5. Macro language Verb Summary VERB DESCRIPTION SMACRO Marks beginning of macro definition SVAR Declares variables for macro definitions SASG Assigns values to variable components SIF Provides conditional processing $ELSE Begins an alternate block in a conditional process $ENDIF Terminates conditional processing $END Marks the end of a macro definition 8-15

$MACRO Syntax _ Example 8-16 Macro Definition Verb $MACRO <macro name> $MACRO [<parm>][,<parm>] [<comment>] The $MACRO verb begins a macro definition. It must be the first state­ ment in the definition. $MACRO assigns a name to the macro and de­ clares the macro parameters. The macro name contains one to six alphanumeric characters; the first must be a letter. Each <parm> is a parameter for the definition as de­ scribed in Section 8.3.1. The operand field may contain as many pa­ rameters as the size of the· field allows and must contain all parameters used in the macro definition. The comment field can only be used if there are parameters. The macro definition is used to expand macro calls (statements that have the macro name as an opcode). The macro name specifies the macro definition to be used. When a macro call is processed, the macro expander associates the first parameter in the $MACRO statement with the first operand or operand list in the macro call, the second parameter with the second operand or operand list. and so on. ONE $MACRO Pl,P2 specifies two parameters. A call such as ONE PAR1,PAR2 associates PAR1 with P1 and PAR2 with P2. Note: A macro definition supercedes previous macro definitions and op­ codes with the same name. Symbolic operands which appear in a macro call are treated as symbolic operands in opcodes; if they are not defined with the program in which they appear, they will be listed as undefined symbols.

$VAR Syntax Declare Variables Verb $VAR The WAR statement declares the variables for a macro definition. $VAR is required only if the macro definition contains one or more variables that are not parameters. More than one $VAR statement may be in­ cluded; each $VAR statement may declare more than one variable. Each <var> in the operand is a variable as previously described (see Section 8.3). The $VAR statement does not assign values to any components of the variables. $VAR statements may appear anywhere in the macro defi­ nition to which they apply, provided each variable is declared before the first statement that uses the variable. Placing $VAR statements imme­ diately following the $MACRO statement is recommended. $VAR A,CT,V3 Three variables for a macro This example declares variables A. CT, and V3; A. CT, and V3 must not have been declared as parameters. 8-17

$ASG Assign Values to Variable Components Verb $ASG Syntax $ASG <expression/string> TO <var> [<comment>] The $ASG statement assigns values to variable components. Variables that are not parameters do not have values for any components until values are assigned using $ASG statements. Variable components with previously assigned values may be assigned new values with $ASG statements. The expression operand may be any expression valid to the assembler and may contain binary mode variable references and the keywords in Table 8-3 and Table 8-4. Note: The binary mode value of a string component or symbol string component used in an expression is the binary value of the first two characters of the string. Thus, if GP.S has the string LAST, the value used for GP.S is an expression in the <string> hexadecimal number >4C41 which is the ASCII representation for LA. A string may be one or more characters enclosed in single quotes, or the concatenation of such a literal string with the string mode value of a qualified variable. The <var> may be either an unqualified variable or a qualified variable. When the operands are both unqualified variables, all components are transferred to target variables. When the destination variable is qualified, only the specified component receives the corresponding component of the expression or string. An exception to this is when a string is as­ signed to the string component of a variable or symbol, the length component of that variable or symbol is set to the number of characters in the assigned string. If the attribute component of the destination variable is to be changed, only those attributes which can be tested us­ ing keywords are changed. Other attributes maintained by the macro assembler mayor may not be changed as appropriate. Note: A qualified variable that specifies the length component is illegal as a destination in a $ASG statement and will not set the length component. Assume that variables P3, V3,and CT were previously declared as pa­ rameters ($MACRO statement) or variables ($VAR statement). * * Assign all the components of variable P3 to variable V3. $ASG P3 TO V3 * Concatenate string 'ES' to the string com- * ponent of variable P3, and set the string

$ASG· Assign Values to Variable Components Verb $ASG * * * * * * * * * * * * * * * * * * * component to the result. Also, add 2 to the value of the new length component. $ASG :P3.S:'ES' TO P3.S Set the flag in the attribute component of variable CT to indicate the symbolic address attribute. $ASG A++PSYM TO CT.A The $ASG statement may be used to modify symbol components as shown in the following examples. Assume that P3.V = 6 and P3.S = SUB. Assign 'TEN' as the string component of variable G .. When 'TEN' is a symbol in the AST, this statement allows the use of in­ direct component qualifiers to modify the components of symbol TEN. $ASG 'TEN' TO G.S Set the value component of the symbol in the string component of variable G to the value component of variable P3. In this case, the value component of TEN is set to 6. $ASG P3.V TO G.SV Concatenate string 'A', the string compo­ nent of variable P3, and string'S' and place the result in the indirect string component of the same symbol. Thus, the string component of TEN is ASUBS and the length component is 5. $ASG 'A' :P3.S: 'S' TO G.SS Note: Keywords in an $ASG statement must be used with a Boolean op­ erator and an attribute component of a variable in the source field. The attribute component must come first. 8-19

$IF Syntax Begin Conditional Block Verb $IF $IF <expression> [<comment>] The $IF statement provides conditional processing in a macro definition. An $IF statement is followed by a block of macro language statements terminated by an $ELSE statement or an $ENDIF statement. When the $ELSE statement is used, it is followed by another block of macro lan­ guage statements terminated by an $ENDIF statement. When the ex­ pression in the $IF statement has a nonzero value (or evaluated as TRUE), the block of statements following the $IF statement is proc­ essed. When the expression in the $1 F statement has a zero value (or evaluated as FALSE), the block of statements following the $IF state­ ment is skipped. When the $ELSE statement is used and the expression in the $IF statement has a nonzero value, the block of statements fol­ lowing the $ELSE statement and terminated by the $ENDIF statement is skipped. Thus, the condition of the $1 F statement may determine whether or not a block of statements is processed, or which of two blocks of statements is processed. A block may consist of zero or more statements. The <expression> may be any expression as defined for the $ASG statement and may include qualified variables and keywords. The expression defines the condition for the $IF statement. Note: The $IF expression is always evaluated in binary mode. Specifically, the relational operations «,> ,= ,#=) operate only on the binary .mode values of macro variables. Boolean operators may be nested. In addition, $IF blocks may be nested, at most, 44 levels deep. These examples show conditional processing in macro definitions: $IF KY.SV BLOCK $ELSE BLOCK $ENDIF A B Process the statements of BLOCK A when the indirect value com­ ponent of the variable KY con­ tains a non-zero value. Process the statements of BLOCK B when the component contains zero after processing either block of statements. Continue processing the statement fol­ lowing the $ENDIF statement . $IF --(T.A&$PCALL) Process the statements of BLOCK A when the attribute component of parameter T indicates that BLOCK A parameter T was not supplied in the macro instruction. If para-

$IF Begin Conditional Block Verb $IF $ENDIF $IF T.L=5 . BLOCK A $ENDIF meter T was supplied, do not process the statements of BLOCK A. Continue processing at the statement following the $ENDIF statements in either case. Process the statements of BLOC~ A when the length component of variable T is equal to 5, do not process the statements of BLOCK A. Continue processing at the statement following the $ENDIF. 8-21

$ELSE Syntax Alternate Conditional Block Verb $ELSE $ELSE [<comment>] The $EL~E statement begins an alternate block to be processed if the preceding $IF expression was false.

$ENDIF Syntax Terminate Conditional Block Verb $ENDIF $ENDIF [<comment>] The $ENDIF statement terminates the conditional processing initiated by an $1 F statement in a macro definition. 8-23

$END Syntax End Macro Definition Verb $END $END [<macro name>] [<comment>] The $END statement ends a macro definition. When executed, the $END statement terminates the processing of the macro definition. The <ma­ cro name> parameter is optional. $END FIX Terminates the definition of macro FIX.

Macro Language - Model Statements Most macro definitions contain model statements. A model statement is, or produces, an assembly language statement. Model statements are com­ posed of the usual assembly language statement elements and can include qualified variable components (string mode only). The source statement produced must be a legal assembly language statement. The following examples show model statements: MOV %6,R12 This model statement is itself an assembly language source statement that contains a machine instruction. :P7.S: MPY : P 2 . S: , R8 : V 4 • S : This model statement begins with the string component of variable P7. Three blanks, M PY, and three more blanks are concatenated to the string. The string component of variable P2 is concatenated to the result, to which R8 and three blanks are concatenated. A final concatenation places the string component of variable V4 in the model statement. This produces an assembly language _ instruction in which the label, comment and part of the operand fields are : supplied as string components. :MS.S: This model statement is the string component of variable MS. Preceding statements in the macro definition must place a valid assembly language source statement in the string component to prevent assembly errors. Note: Conditional assembly directives may not appear as operations in a model statement. Comments supplied in model statements may not contain pe­ riods (.) since the macro assembler scans comments in the same way as model statements and improper use of punctuation may cause syntax er­ rors. 8-25

Macros may simply substitute a machine instruction for a macro instruction, or they may include conditional processing, access the assembler symbol ta­ ble, and employ recursion. Several examples of macro definitions are de­ scribed in the following paragraphs. S.S.1 Macro 10 ID Example macro 10 is a macro with a default value. The macro supplies two DATA directives to the source program. It consists of nine macro language statements, four of which are model statements. $MACRO WS,PC Defines ID with parameters WS and PC Model statement - places a DATA direc­ tive with the string of the first pa­ rameter as the operand in the source program. DATA $IF DATA $ELSE DATA :WS.S: PC.A&$PCALL :PC. s: ,15 START, 15 Tests for presence of p~rameter PC Model statement - places a DATA direc­ tive in the source program. The first operand is the string of the second parameter, and the second operand is 15. This statement is processed if the second parameter is present. Start of alternate portion of defi­ nition. Model statement - places a DATA direc­ tive in the source program. The first operand is label START, and the second operand is 15. This statement is pro­ cessed if the second parameter is omitted. START EQU $ Model statement - places a label START in the source program. This statement 8-26 $ENDIF $END is processed if the second parameter is omitted. End of conditional processing. End of macro. The macro call syntax is: [<LABEL>] ID <address>[,<address>] [<comment>] The addresses may be expressions or symbols. A sample 10 call would be: ID WORK1,BEGIN This would be replaced with the following source code: DATA WORK1 DATA BEGIN,15 If only one operand is supplied, the macro instruction could be coded as fol­ lows: ID WORK2

This would produce the following source code: START DATA DATA EQU WORK2 START, 15 This form of the macro instruction imposes two restrictions on the source program: 1) The source program may not use the label START and 2) May not call macro ID more than once. Problems with labels supplied in macros may be prevented by reserving certain characters for use in macro-generated labels. A macro definition may maintain a count of the number of times it is called and use this count in each label generated by the macro. NO ERRORS, This example shows how to implement both those comments which appear in the macro definition only and those which appear in the macro expansion. _. When this macro is called, the statement in line six generates a comment. IDT 'GENCMT' GENCMT $MACRO $VAR V * This is a macro. definition comment * $ASG '* , TO V.S :V.S: This is a macro expansion comment * $END GENCMT * This is a macro expansion comment * 0000 DATA 0,1 0001 GENCMT * This is a macro expansion comment * GENCMT * This is a macro expansion comment * 0004 DATA 4 END NO WARNINGS This example shows the recursive use of macros. FACT produces the assem­ bly code necessary to calculate the factorial of N, and store that value at data memory address LOC. Macro FACT accomplishes this by calling FACT1, which calls itself recursively. FACT $MACRO $IF MOV STA $ELSE MOV STA $ASG FACTI $ENDIF N,LOC N.V<2 %1,A @:LOC: * 1% = 0% =1 %:N.V:,A * N greater than/equal 2, @:LOC: * so store N at LOC N.V-1 TO N.V * Decrement N :N.V:,:LOC: * Do Factorial of N-l 8-27

• FACTI $END $ MACRO $IF LDA MPY MOV STA $ASG FACTI $ENDIF $END M,AREA M.V>I @:AREA: %:M.V: ,A B,A @:AREA: M.V-I TO M.V :M. V: , :AREA: * Multiply factorial so far * by current position * Save result * Decrement position * Recursively calls itself

8.8.4 Macro PULSE

This is a set of macros in which the name describes an addressing mode ex­ pected by the macro. The example assigns Register A to a port, Register B to a port, and an immediate value to a port. These macros can be useful in pro­ gramming I/O routines. PULSEA $MACRO PX ORP A, :PX.S: $END * PULSEB $MACRO PX ORP B, :PX.S: $END * PULSEI $MACRO I,PX ORP % : I • S : , : PX • S : $END

Macro Language - Error Messages Table 8-6 lists and defines the Macro error messages which may be generated. Table 8-6. Macro Error Messages MACRO ERROR MESSAGE DESCRIPTION MACRO LINE TOO LONG In a macro definition, macro directive lines may only be 58 characters long, and model statements, when fully ex- panded, may only be 60 characters long. LONG MACRO VARIABLE QUALIFIER Macro variable qualifiers may only be one or two characters in length. TOO MANY MANY VARIABLES The total number of macro parameters, variables and labels in one macro definition may not exceed 128. INVALID MACRO QUALIFIER The only valid macro qualifiers are: S,V, L, A. SS, SV, SL and SA VARIABLE ALREADY DEFINED A macro variable cannot be redefined within a macro. IF LEVEL EXCEEDED The maximum nesting level of $IF directives is 44. MACRO ASSEMBLER The Macro Assembler has detected an internal PROGRAM ERROR error. These can be caused by incorrect syntax. 8-29

Macro Language - Error Messages 8-30

This section contains sample TMS7000 applications to aid you in system de­ velopment. Section Page 9-1

Design Aids - Microprocessor Interface Example

9.1 Microprocessor Interface Example

Figure 9-1 illustrates a method for interfacing a TMS70x2 microcomputer to external memory devices such as EPROM and RAM. This interface is de­ signed to operate at the TMS70x2's maximum operating frequency (8 MHz). Any combination of ROM, RAM or other peripheral devices could be added into the circuit and enabled by the other SEL pins, provided that their timing requirements allow them to be interfaced to the TMS70x2. In this circuit, the Mode Control pin (MC) is tied to Vcc, placing the TMS70x2 in Microprocessor mode. All 16 addressing bits on Ports C and D are available in Microprocessor mode. The on-chip ROM is disabled in this mode, and its address space is available externally. For more information on port and mode operation see Section 3. Note the following features in this sample circuit:

• Port A and the lower nibble of Port B operate the same as in the Sin­ gle-Chip mode. The memory control signals are brought out on the upper nibble of Port Port C becomes the multiplexed least significant 8-bit address bus (A7-AO) and full 8-bit data bus.
• Port D becomes the most significant 8-bit address bus (A15-A8).
• The least significant 8 bits of the 16-bit address bus (A7-AO) are latched into the SN74AS373 (U2) by the ALATCH signal during read/write memory cycles.
• A full address decode is accomplished with the SN74AS138 (U3). Eight memory select lines (SEL7-SELO) are generated by U3 and are each in­ dividually activated on an 8K-byte address block. Table 9-1 lists the address range decoded by each select pin. Table 9-1. Memory Address Decode PIN ADDRESS RANGE ill7 > EOOO to >FFFF SEL6 >COOO to >DFFF ill5 >AOOO to >BFFF ill4 >8000 to >9FFF SEL3 >6000 to >7FFF SEL2 >4000 to >5FFF ill1 >2000 to >3FFF SELO >0000 to >1 FFF

Design. Aids - Microprocessor Interface Example U1 TMS70x2 C7 AD7 A06 C6 CS A04 C4 A03 C3 AD2 C2 CO B4/ALATCH B6/ENABLE BS/R!W MC U2 74AS373 so 80 7D 7Q 60 80 50 sa 40 4Q 3D 3Q 2D 2D 10 1Q G oc A12 A11 A10 AS ~~-4~-----+---IE U6 SN74AS32 '-----' A10 AS AB AS AO S G Figure 9-1. TMS70x2 Microprocessor Interface Sample Circuit The devices used in this circuit are: U1 TMS70X2 - 8-bit microcomputer with UART. U2 SN74AS373 - The AS version of the 373 is used in this circuit, allowing use of the less expensive TMS2764-25 EPROM chip (U4) instead of the TMS2764-20 EPROM chip. U3 SN74AS138 - Like U2, the AS version of the 138 allows use of less expensive EPROMs. U4 TMS2764-25 - This EPROM chip is the slowest (least expensive) de­ vice that can be used in this circuit because the timing requirement [T.-p(A-D)] for the TMS70x2 is 260 ns. The propogation delay through U;.: IS 6 ns, so only 254 ns remain for the EPROM Chif to use. Therefore, the TMS2764-25 with its 250 ns access time [T a(A) was selected. U5 TMS4016-15 - This is the slowest RAM chip that can be used in this circuit because the timing requirementJT C\\(EL-D)] for the TMS70x2 is 82 ns. The propogation delay through 6 IS 5.8 ns, so only 76.2 ns re­ main for U5 to use. Therefore, the TMS4016-15 with its 75-ns delay time was selected. U6 SN74AS32 - The AS version of this chip allows use of the less expen­ sive TMS4016-15 RAM instead of the TMS4016-12 RAM. 9-3

Design Aids - Microprocessor Interface Example

9.1.1 Read Cycle Timing

The TMS70x2 requires a minimum address-to-data access time [ta(A-O)] of 260 ns at 8 MHz. ta(A-D) for the TMS2764-25 in this circuit is: Access time (260 ns) ~ tphl[U2] + t a(A)[U4] > 6 + 250 260 ns ~ 256 ns ta(A-D) for the TMS4016-15 in this circuit is: Access time (260 ns) ~ tJ:!hl[U2] + t a(A)[U5] > 6 + 150 260 ns ~ 156 ns The TMS70x2 parameter used to calculate ta(A-DJ will also be used to calcu­ late chip-se/ect-to-data access time. ta(E) for the TMS2764-25 in this circuit is: Access time (260 ns) 260 ns ~ ~hl[U3] + t a(E)[U4] > 6 + 250 ~ 256 ns Since the chip select to the TMS4016-12 is gated with the ENABLE signal, use the access time Ta(EL-D) to calculate the chip-select-to-data time. ta(S) for the TMS4016-15 in this circuit is: Access time (82 ns) ~ !Plh[U6] + t a(S)[U5] > 5.8 + 75 82 ns ~ 80.8 ns The TMS70x2 requires a minimum ENABLE-rise-to-data-disable time of 100 ns at 8 M Hz. The minimum requirement for the TMS2764-25 in this cir­ cuit is: Disable time (100 ns) ~ tdis(G) [U4] 100 ns ~ 85 ns The requirement for the TMS4016-15 in this circuit is: Disable time (100 ns) ~ tdis(S)[U5] + t phl[U6] > 50 + 5.8 100 ns ~ 55.8 ns The TMS70x2 requires a minimum data-output-valid time (T d(EH-A) of 80 ns at 8 MHz. Since S is gated to the ENABLE line, the ENABLE ~ignal can be used to calculate the data-output requirement for the TMS4016- 15. Output valid (80 ns) ~ tl!hl[U6] + t h(D)[U5] > 5.8 + 10 80 ns ~ 15.8 ns

Design Aids - Microprocessor Interface Example Table 9-2. Memory Interface Timing PARAMETER MIN MAX UNIT tc(G) CLKOUT cycle timet 250 2000 ns tw(GH) CLKOUT high pulse duration 0.5tc(G)-40 0.5tc(C)+10 ns tw(GL) CLKOUT low pulse duration 0.5tc(C)-40 0.5tc(C)+15 ns tdICH-JLl Delay time, CLKOUT rise to ALATCH fall 0.5t cIC)-10 0.5tcIC) +30 ns tw(JH) ALATCH high pulse duration 0.25tc(C)-15 0.25t c(C) +30 ns tsu(HA-JL) Setup time, high address valid before 0.25t c(C)-40 0.25tc(G) +45 ns ALATCH fall tsu(LA-JL) Setup time, low address valid before 0.25t c(C)-40 0.25tc(G) +15 ns ALATCH fall th(JL-LA) Hold time, low address valid after 0.25t c(C) 0.25tc(C) +45 ns ALATCH fall tsu(RW-JL) Setup time, R/W valid before ALATCH 0.25t c(C)-35 0.25tc(C) +30 ns fall th(EH-RW) Hold time, R/W valid after ENABLE rise 0.5t c(C)-40 ns th(EH-HA) Hold time, high address valid after 0.5t c(C)-50 ns ENABLE rise tsu(Q-EH) Setup time, data output valid before 0.5t c(C)-45 ns ENABLE rise -th(EH-O) Hold time, data output valid after 0.5t c(C)-45 ns ENABLE rise td(LA-EL) Delay tist low address high impedance 0.25t c(C)-45 0.25tc(C) ns to ENA E fall td(EH-A) Delay time, ENABLE rise to next address 0.5t c(C,-25 ns drive ta(EL-D) Access time, data input valid after 0.75t c(C)-1 05 ns ENABLE rise ta(A-D) Access time, address valid to data input 1.5tc(C)-115 ns valid td(A-EH) Delay time, address valid to ENABLE rise 1.5t c(C)-80 1.5tc(C) +30 ns th(EH-D) Hold time, data input valid after ENABLE 0 ns rise td(EH-JH) Delay time, ENABLE rise to ALATCH rise 0.5t c(C)-25 0.5tc(C)+10 ns td(CH-EL) Delay time, CLKOUT rise to ENABLE fall -10 35 ns t tc(C) IS defined to be 2/fosc and may be referred to as a machine state or simply a state. 9-5

Design Aids - Microprocessor Interface Example Table 9-3. TMS4016-15 Timing Characteristics PARAMETER MIN MAX UNIT talA} Access time from address 150 ns talS) Access time from chip select low 75 ns tdis(S} Output disable time after chip select high 50 ns theA) Address hold time 0 ns tsulO) Data setup time 60 ns th(D) Data hold time 10 ns Table 9-4. TMS2764-25 Timing Characteristics PARAMETER MIN MAX UNIT talA) Access time from address 250 ns talE) Access time from E 250 ns ten(G) Output enable time from G 100 ns tdislG) Output disable from G 0 85 ns Table 9-5. SN74AS373. SN74AS138. and SN74AS32 Propogation Delay Times PARAMETER MIN MAX UNIT tpd Propogation delay, SN74AS373 6 ns tpd Propogation delay, SN74AS138 6 ns tpd Propogation delay, SN74AS32 5.8 ns 9-6

Design Aids - Programming the TMS7742 9,2 Programming the TMS7742 The TMS7742 is an EPROM version of the TMS7042. It can be programmed using these devices:

• Standard PROM programmer (see Section 9.2.1, page 9-8)
• TMS7000 Evaluation Module (see Section 9.2.2, page 9-9)
• TMS7000 XDS Emulator (see Section 9.2.3, page 9-10) The TMS7742 can emulate the TMS7020, TMS7040, and TMS7042:
• TMS7020 and TMS7040 Emulation: The TMS7742 can emulate the TMS7020 and TMS7040 in all operating modes. It does not directly emulate edge- and level-sensitive interrupts, but does emulate level-sensitive only interrupts.
• TMS7042 Emulation: The TMS7742 can directly emulate the TMS7042 in all operating modes at up to 5 MHz operation. Table 9-6 shows the pin conditions required for operating in the various modes. Note that the RESET and XTAL2 pins must be held low to enter EP­ ROM mode. Table 9-6. Mode Select Conditions for the TMS7742 EPROM EPROM MODE SELECT SINGLE- PERIPH.- FULL- MICRO- PROG. VERIFY CHIP EXPANSION EXPANSION PROCESSO~ MODE MODE I/0. Control I Bit 7 0 0 1 X X X regIster I Bit 6 0 1 0 X X X Mode Control pin VSS VSS MC) VSS Vee Vpp VSS RESET pin Vee Vee Vee Vee VSS VSS XTAL2 pin N/A N/A N/A N/A VSS VSS Notes: 1. X = don't care 2. N/A = not applicable 9-7

Design Aids - Programming the TMS7742

9.2.1 Programming the TMS1742 Using a PROM Programmer

A PROM programmer can be used to program the TMS7742 in a manner si­ milar to programming a TMS2732A EPROM. A 40-to-24-pin conversion socket is required and RESET and XTAL2 must be grounded. Some PROM programmers implement current-limiting circuitry to sense correct EPROM placements. The TMS7742 can draw a maximum of 250 rnA during pro­ gramming; if your PROM programmer produces an EPROM placement error, you must supply an external +5 V ± 1 0% power supply to the TMS7742. Figure 9-2 shows the connections for the 40-to-24-pin socket. A 40-to-24 pin adapter socket is available from Texas Instruments (Part Number RTC/PGM2732-06) or from various PROM Programming manufacturers. TMS2732A SOCKET TMS2732A SOCKET PIN FUNCTION FUNCTION PIN B5/R/W VSS GNO 12 B6/ENABLE B4/ALATCH Bl B3/TXO B2 MC G/Vpp 20 A7 AO C7 08 17

2 A6 Al C6 07 16

3 A5 A2 C5 06 15

4 A4 A3 C4 05 14

5 A3 A4 C3 04 13 '

12 GNO RESET DO A8 23

12 GNO - XTAL2/CLKIN 02 All 21

6 A2 07 04 E 18

7 Al 06 05 AO 8

Figure 9-2. PROM Programmer 40-to-24-Pin Conversion Socket Use the following sample procedure to program the TMS7742 on a PROM programmer: 1) Insert the TMS7742 into the conversion socket. 2) Place the conversion socket (with the TMS7742) into the 24-pin socket on the PROM programmer. 3) Program and verify the contents of the TMS7742 in the same manner as any standard EPROM.

Design Aids - Programming the TMS7742 The RTC/EVM7000 (TMS7000 Evaluation Module) can be used to program the TMS7742. A 40-to-28-pin conversion socket is required and RESET and XTAL2 must be grounded. This socket (Part Number RTC/PGM2764-06) is available from Texas Instruments. Figure 9-3 shows the connections for the 40-to-24-pin socket. . TMS2764 TMS2164 IPINI FUNCTION FUNCTION IPIN) B5JR/W 4 Vss GNO 1141 87/CLKOUT 2 3 B6/ENABLE so B4/ALATCH B3/TXO B2 MC JUMPER· 141 AS ._----- A' CS a7 I1BI

151 AS A2 - a6 1171

iNf3 C, . a2 1'21 iN'i'1 CO - a, 1111 1141 GNO _.- RESET DO AB 1261 A6/SCLK/EC2 0' ._-A9 1241 A5/RXD .. - --VCC 12BI 1'41 GNO ----XTAl2 --A11 1231 Figure 9-3. RTC/EVM7000 40-to-28-Pin Conversion Socket Use the following procedure to program the TMS7742 on an RTC/EVM7000: 1) Verify that the TMS7742 is erased (all >FFs). a) Set the switch between pin 36 on the TMS7742 and pin 22 on the conversion socket (read/Verify position). b) Enter: ?VE Q FFF l <CR> 2) Program the TMS7742. Note that the program to be loaded into the TMS7742 must reside in EVM memory beginning at address >F006 or above. a) Set the switch between pin 36 on the TMS7742 and pin 1 on the conversion socket (program position). b) Enter: ?PE Q FFF FOOO l <CR> 3) Compare the TMS7742 EPROM to EVM memory to verify that they are identical. a) Set the switch between pin 36 on the TMS7742 and pin 22 on the conversion socket (read/verify position). b) Enter: ?CE Q FFF FOOO l <CR> 9-9

Design Aids - Programming the TMS7742 The TMS7742 can be programmed using the TMS7000 XDS, the driver pro­ gram, and an interface board. Figure 9-4 shows the schematic for the inter­ face board and Figure 9-5 contains the driver program. PROGRAMt cc VERIFY ! 7000 xes TARGET CABLE 108 Cl : 29 Q2 C2 31 30 03 C4 32 32 05 C6 33 33 08 C7~ 35 08 D2 24 A2 03 23 10 A3 04 22 9 M 06 1 BAli 08 20 7NJ D1 19 e 107 B03 27M Bl 4 M B2 6 23 1010 B3 37 24 All __ Vu 40 E""1/xT~r"t, 223 +5V Figure 9-4. Interface Circuit for Programming the TMS7742 with the TMS7000 XDS 9-10

Design Aids - Programming the TMS7742 IDT 'EPROM' * * * * * * This program checks to see if the TMS7742 is blank, then programs and verifies the EPROM byte by byte. The program can also verify that the contents of XDS memory are identical to the TMS7742. * ADDRES COUNT COUNT2 EQU EQU EQU RS Current address Number of bytes to program * INTROL EQU PO Interrupt control PORTA EQU P4 PORTB EQU P6 PORTC EQU P8 PORTD EQU P10 ADDR EQU PS DDDR EQU P11 CDDR EQU P9 * * AO E- * Al G-/VPP 21V * A2 INT1- light 2 * A3 INT3- light 3 * 32VE- ENOT EQU ?00000001 E- VPP2l EQU ?00000010 21V to VPP/G ERRl EQU ?00001011 Not blank error ERR2 EQU ?00000111 Not programming correctly ERR3 EQU ?00000011 Failed verify test READ 1 EQU ?00001110 Read setup READ2 EQU ?00001111 Release read setup >EOOO START %>FF,ADDR Outputs %>FF,DDDR Outputs error AORG DINT MOVP MOVP MOVP MOVP MOVP BTJZP MOVD MOVD CALL CMP JNZ DECD DECD JC %>OO,CDDR Inputs %O,INTROL Full-Expansion mode, no ints BLANK LOOPBL %178,P2 Timer latch %>40,PORTA,VERIFY Verify or program? %>FFFF,ADDRES Check memory for all blanks %>FFF,COUNT Put in counts and pointers @READ Read memory %>FF,A Is it blank? (>FF blank) ERRORl If no, error ADDRES Next address COUNT LOOPBL End of routine? Figure 9-5. Driver Program for Programming the TMS7742 with the TMS7000 XDS 9-11

Design Aids - Programming the TMS7742 PROGRM MOVD %>FFFF,ADDRES MOVD %>FFF,COUNT LOOPPR LDA *ADDRES MOV A,B CALL @WRITE DECD ADDRES DE CD COUNT JC LOOPPR VERIFY MOVD %>FFFF,ADDRES MOVD %>FFF,COUNT LOOPVE CALL @READ MOV A,B LDA *ADDRES CMP B,A JNZ ERROR3 DECD ADDRES DECD COUNT Program EPROM Put in counters Get data from XDS memory Program one address Next address ' End of routine? Check memory for all blanks Put in counters and pointers Read EPROM Get original data Does EPROM compare to original? If no, error Next address JC LOOPVE End of routine? ERROR 1 MOVP %ERR1,PORTA Fail blank - light 2 JMP STOP2 ERROR2 MOVP %ERR2,PORTA JMP STOP2 ERROR3 MOVP %ERR3,PORTA STOP2 IDLE Fail programming - light 3 Fail verify - lights 2 and 3 JMP STOP2 READ CALL @SETUP Put address on bus READB MOVP %>OO,CDDR Port C = inputs MOVP %READ1,PORTA Turn on enable MOVP PORTC,A Read data MOVP %READ2,PORTA Turn off enable WRITE CALL @SETUP Put address on bus MOVP B,PORTC Put data on bus MOV %3,COUNT2 Initialize counter PULSE MOVP %>FF,CDDR Port C = outputs ANDP %#VPP21,PORTA Turn on VPP ANDP %#ENOT,PORTA Turn on E-* MOVP %>80+3l,P3 Start timer HERE2 BTJZP %8,INTROL,HERE2 Wait for timer countout MOVP %?OOlOlOlO,INTROL Clear timer flag DJNZ COUNT2,HERE2 Wait a total of 55 ms ORP %ENOT,PORTA Turn off E- ORP %VPP21,PORTA Turn off VPP CALL @READB Read EPROM CMP A,B Compare to actual data JNE ERROR2 If not equal lulse again RETS then turn on ight 3 Figure 9-5. Driver Program for Programming the TMS7742 with the TMS7000 XDS (Concluded) 9-12

Design Aids - Programming the TMS7742 Use the following procedure to program the TMS7742 using the TMS7000 XDS Emulator. To avoid the possiblity of leaving +21 V on Vpp, do not stop the program until the I DLE light is on. 1) Enter: INIT(3,0,0,Q) 2) Enter: ROM=EOOO 3) Set the switch on interface board to program. 4) Download object code into XDS memory (>FOOQ->FFFF). 5) Download the driver program into XDS memory (this will not affect the present program at memory locations >FOOQ->FFFF). 6) Use the MR command to set the following values: PC =- >EOOO, ST =- >00, SP =- >60 7) Enter: P 5=FF, P4=FF (This clears the programming voltages on the socket.) 8) Insert the target cable into socket A. 9) Insert the TMS7742 into socket B. 10) Enter: RUN (Light 4 should go on.) 11) The program will take approximately four minutes to complete; light 1 will go on when the program is complete. 12) If an error was encountered, light 2 and/or light 3 will be lit. Examine addresses >04 and >05 for the error location. Register A contains EP­ ROM data, and Register B contains the original data. 13) Remove the TMS7742. If an error condition is found, then the indicator lights on the XDS front panel will show the pattern for the error. Table 9-7 shows the status conditions in­ dicated by the front panel lights. 9-13

Design Aids - Programming the TMS7742 Table 9-7. Error Patterns for XDS XDS LIGHTS STATUS 1 2 0 0 0 0 1 0 1 0 1 1 1 1 Light 1 Light 2 Light 3 Light 4

0 Program is not running

1 Program is running

1 Program is finished. no errors

1 Programming error

1 EPROM was not blank

1 Verify error

~gram is in IDLE state I T1 003 Processor is running To verify the TMS7742 EPROM memory against the XDS memory, set the switch on the interface board to verify and follow the programming procedure. As a precaution, do not connect the +21.7-V power supply. _ 9.2.4 TMS7742 Erasure 9-14 The TMS7742 can be erase by exposing the chip to shortwave ultraviolet light that has a wavelength of 253.7 nanometers (2537 angstroms). The recom­ mended minimum exposure dose (UV intensity x exposure time) is 15 watt­ seconds per square centimeter. The lamp should be located about 2.5 centimeters (1 inch) above the chip during erasure. After erasure, all bits are at a high level. Note that normal ambient light contains the correct wave­ length for erasure; therefore, when using the TMS7742 the window should be covered with an opaque label.

9.3 Programming the SE77C42

The SE77C42 is an EPROM version of the TMS70C42. It can be programmed using these devices:

• Standard PROM programmer (see Section 9.3.1, page 9-15)
• TMS7000 Evaluation Module (see Section 9.3.2, page 9-16) The SE77C42 can emulate the TMS70C42.
• TMS70C42 Emulation: The SE77C42 can directly emulate the TMS70C42 in all operating modes. Table 9-8 shows the pin conditions required for operating in the various modes. Note that the RESET and XTAL2 pins must be held low to enter EP­ ROM mode. Table 9-8. Mode Select Conditions for the SE77C42 EPROM EPROM MODE SELECT SINGLE- PERIPH.- FULL- MICRO- PROG. VERIFY CHIP EXPANSION EXPANSION PROCESSOR MODE MODE I/0. Control I Bit 7 0 0 1 X X X reg Ister I' 6 Bit 0 1 0 X X X Mode Control pin VSS VSS VSS Vee Vpp VSS MC) RESET pin Vee Vee Vee Vee Vss Vss XTAL2 pin N/A N/A N/A N/A VSS VSS Notes: 1 . X = don't care 2. N/ A = not applicable

9.3.1 Programming the SE77C42 Using a PROM Programmer

The SE77C42 can be programmed like any Texas Instruments TMS27C64 on a wide variety of PROM programmers. Programming the SE77C42 requires a 40-to-28 pin adapter socket with the RESET and XTAL2 pins grounded. Contact your PROM manufacturer of local TI field sales office for program­ ming support. Figure 9-6 shows the connections needed to be made for the 40-to-28 pin programming socket. This programming socket is also available through your EPROM programmer manufacturer or through Texas Instruments (Part Number RTC/PGMC82A-06). 9-15

Note: When using the TMS27C64 programming algorithm to program the SE77C42, it is important to remember that the adapter socket maps the 4K EPROM of the SE77C42 into the upper 4K memory map of the TMS27C64. In other words, locations > FOOO to >FFFF of the SE77C42 correspond to locations >1000 to >1 FFF of the TMS27C64. TMS72C&4 SOCKET TMS27C64 SOCKET PIN FUNCTION FUNCTION PIN B5/Rm 40 vss GNO 14 B7/CLKOUT 39 B6/ENABLE BO 38 B4/ALATCH Bl 37 B3/TXO B2 36 MC vpp A7 AO 35 C7 08 19

4 A6 Al 34 C6 07 18

5 A5 A2

, @j~ C5 06 17

6 A4 A3 C4 05 16

22 G A7/ECl 11 30 C2 03 13

14 GNO RESET DO A8 25

27 PGM --A6/SCLK/EC2 01 A9 24

14 GNO --XTAL2/CLKIN 02 All 23

8 A2 07 04 E 20

9 Al 06 05 AO 10

Figure 9-6. PROM Programmer 40-to-28-Pin Conversion Socket Use the following sample procedure to program the SE77C42 on a PROM programmer: 1) Insert the SE77C42 into the conversion socket. 2) Place the conversion socket (with the SE77C42) into the 28-pin socket on the PROM programmer. 3) Program and verify the contents of the SE77C42 in the same manner as any standard TMS27C64 EPROM. Caution: Do not program the SE77C42 on an EPROM programmer which implements a "Signature Row" programming algorithm. The high voltage used for this application may damage the SE77C42.

The RTC/EVM7000C (TMS7000 CMOS Evaluation Module) can be used to prEgram the SE77C42. A 40-to-28 pin conversion socket is required and R SET and XTAL2 must be grounded. Figure 9-6 shows the required con­ nections for the 40-to-28 pin socket. and the socket is also available through Texas Instruments (Part Number RTC/PGMC82A-06). Use the following procedure to program the SE77C42 on an RTC/EVM7000C: 1) Verify that the SE77C42 is erased (all >FFs). a) Enter: ?VE 1000 1FFF £;. <CR> Note: If an error statement appears at this point concerning the "C" character, a software patch may be required in the Debug Monitor EPROM "U43" to program 12.5 Volt Vpp EPROMs. If so, the procedure in Section 9.3.3 will enable the EVM to program 12.5 Volt Vpp EPROMs. 2) Program the SE77C42. Note that the program to be loaded into the •• SE77C42 must reside in EVM memory beginning at address >F006 or above. (If the code is planned to be put into a ROM coded device, it is suggested to start the program at > F006 or above for a 4K device or > F806 or above for a 2K device. See Section 12.1.1.) a) Enter: ?PE 1006 1FFF F006 £;. <CR> 3) Compare the SE77C42 EPROM to the EVM memory to verify that they are identical. a) Enter: ?CE 1006 1FFF F006 £;. <CR> 9.3.3 Modify the RTC/EVM7000C Debug Monitor to Enable 12.5 Volt Vpp Programming This step is required only if the EVM in use contains software revision 1.4 and errors are occuring whenever you are trying to program an EPROM with the"C" (12.5 Volt Vpp EPROM) identifier. (Example: ?PE 1006 1FFF F006 £;.) The following steps will modify the code in the present "U43" TMS2764 EP­ ROM. The new code will then be programmed into a new TMS2764 EPROM which will be used to replace to original "U43" EPROM. 1) Move the present contents of U43 into user RAM. a) ? $MV EOOO FFFF 4000 9-17

2) Modify three bytes using the $MM command. a) ? $MM SEED (Change contents from 40 to 80) 40 80 <CR> b) ?$MM SEFS (Change contents from OF to OC) OF OC <CR> c) ?$MM SF04 (Change contents from FF to 3F) FF 3F <CR> 3) Program a blank TMS2764 to replace the present "U4'3". a) ?$PE 0 IFFF 4000 <CR> b) Power-down the EVM and replace U43 with new EPROM.

9.3.4 SE77C42 Erasure

The SE77C42 can be erased by exposing the chip to shortwave ultraviolet light that has a wavelength of 253.7 nanometers (2537 angstroms). The re­ commended minimum exposure dose (UV intensity x exposure time) is 15 watt-seconds per square centimeter. The lamp should be located about 2.5 centimeters (1 inch) above the chip during erasure. After erasure, all bits are at a high level. Note that normal ambient light contains the correct wave­ length for erasure; therefore, when using the SE77C42 the window should be covered with an opaque label.

Design Aids - Serial Communication with the TMS1000 Family This section discusses using the TMS7000 for serial communication with a UART (Universal Asynchronous Receiver Transmitter). It describes imple­ menting the UART function in software using any TMS7000 device and with the on-chip serial port using the TMS7042.

9.4.1 Communication Formats

The TMS7000 family handles three basic formats of serial communication - Asynchronous, Isosynchronous and Serial I/O. The first two require framing bits to be added to the data, allowing the receiver to properly detect incoming data. The last two require an addition serial clock to synchronize the data. This UART routine uses Asyncronous communications; all the formats are discussed in detail in Section 3. In Asynchronous format, as shown in Figure 9-7, each character to be transmitted is preceded by a Start framing bit and followed by a Parity bit (if parity is enabled), then one or more Stop framing bits. MARKING START DO D1 LaB ---+~ INCREASING l1ME On PARITY STOP MARKING MeB Figure 9-7. Asynchronous Communication Format The Start bit is a logical 0, or space. It notifies the receiver to start assem­ bling a character and allows the receiver to synchronize itself with the trans­ mitter. A Parity bit is an additional bit added to a character for error checking. The Parity bit is set to 0 or 1 in order to make the number of 1 s in the character (including the Parity bit) even or odd depending on whether even or odd parity is selected. The Stop bit is a logical 1 or mark. One or more Stop bits are added to the end of the character to ensure that the Start bit of the next character will cause a transition on the communication line. The connections for both the software and on-chip hardware UARTs are identical. Both use A5/RX for the incomming data and B3/TX for outgoing data. The connections are shown in Figure 9-8. The TMS7000 outputs a TIL-level signal which must be converted to ± 12 volts for RS-232-C com­ patibility. The 75188 and 75189 devices are used for this purpose. 9-19

Design Aids - Serial Communication with the TMS7000 Family

6 VOLTS

:1:12 V TX OUT TTL LEVEL. TM87000 DEVICE TTL LEVEL. RXIN Figure 9-8. I/O Interface This software UART routine will run on any TMS7000 family microcomputer. It requires the use of one timer to produce a consistent baud rate without re­ quiring full use of the program's time. This UART will run mainly in the In­ terrupt-2 routine, allowing the main program to run independently of the UART. The timer is configured so that the interrupts arrive every half bit. This is be­ cause the receiver section must find the start bit as soon as possible, but it must also test the following bits at the middle of the bit. Testing at the edge of a bit time would produce data errors. Figure 9-9 shows the start bit de­ tection. FIND START ooJ-ofNn DATA 1 TEST DATA BIT TEST DATA J, J, err Figure 9-9. Start Bit Detection The software, which consists of a receiver routine and a transmitter routine, runs mainly during the Interrupt-2 routine. Both routines maintain a progres­ sive State Counter, which will have one of the following values to indicate its condition: State 0 The receive portion is in this state until a low Start bit is detected. State 1 This state begins a half bit later and tests for a valid Start bit. State 2 and State 3 The 8 character bits are built in states 2 and 3.

Design Aids - Serial Communication with the TMS7000 Family State 4 and State 5 The Parity bit is received in states 4 and 5. If the parity does not agree with the parity of the input byte then a bit is set to indicate a pa rity error. State 6 and State 7 These states look for the Stop bit. If the stop bit is not found, then another bit is set to indicate a framing error. The complete character is then placed in the RXSTOR register and a bit is set to indicate to the main program that a character is ready to be read. The main program must clear the parity and framing error bits. The transmitter routine operates similarly to the receiver routine, using a sep­ arate State Counter to record its condition. The transmitter routine skips every other interrupt because the routine can be entered every full bit instead of ev­ ery half bit. as in the receiver routine. The transmitter sends out bytes stored in a table. This table can be in either ROM or RAM and the table ends with a > FF to signify the end of string. Parity is calculated for both the receiver and transmitter by exclusive ORing the data bits together to produce even parity for the string.

9.4.2.1 Software UART Enhancements

If it is not necessary for the transmitter and receiver to run simultaneously, then _ several inprovements can be implemented.

• The transmitter's baud rate can easily be doubled by interrupting every full bit instead of every half bit.
• The receiver can be improved by connecting the RX-in line to RX and to an Interrupt pin (INT1 or INT3). When the Start bit is detected, the program enters the external interrupt routine. This interrupt routine must start the timer to count out one-half bit and also disable the interrupt. When the half-bit interrupt occurs, the timer must be reset and restarted to produce a full-bit interrupt; this would occur in the middle of the data bits.
• The parity can be selected by testing an even/odd bit and setting the initial parity register (TXPAR, RXPAR) to the correct value. Currently, the registers are cleared for every new byte, producing even parity.
• An extra stop bit could be added by using a test bit and repeating States 6 and 7 if the bit is set.
• Additional RS-232-C signals could be added to the program to interface to more complex equipment. 9-21

Design Aids - Serial Communication with the TMS7000 Family

9.4.2.2 Software UART Routines

OPTION XREF,SYMLST * * This program simultaneously transmits and * receives RS-232-C format data. * Maximum baud rate 4800 at 8 Mhz. * * Transmitt pin out B3 * Receiver pin in AS * * STATER STATET RXBUF RXCNT RXSTOR RXPAR TXCNT TXTABL TXBUF TXPAR BITS * * * * * IOCNTL TIMERL TIMERC PORTA PORTB AD DR UART REGISTERS EQU R2 EQU R3 EQU R4 EQU RS EQU R6 EQU R7 EQU R8 EQU R9 EQU R10 EQU Rll EQU R12 The state of the current receive data The state of the current transmit data Build the input byte here The number of bits left to receive Pick up the finished input word here Bit O=parity (7 other bits free) The number of bits left to transmit Address offset from String beginning Shift the out word from here. Bit 0 = parity ( 7 other bits free) BitO= Transmit routine now or next INT Bit1= Transmitter active now Bit2= Receiver contains word now Bit3= Framing error ( bad stop bit) Bit4= Finished with the string output BitS= Parity error PERIPHERAL PORTS AND REGISTERS EQU PO Interrupt control EQU P2 Timer latch value EQU P3 Timer control EQU P4 Port A data EQU P6 Port B data EQU PS Port A Data-Direction register ...

Design Aids - Serial Communication with the TMS7000 Family OOCF 0083 0001 0002 0004 0008 0010 0020 0040 0080 F806 F806 F807 F809 F80A F80D F80F F8ll F812 F815 F818 F81B F81E F821 F824 F825 F826 AB CA OD EO FD 0001 FB 2E 00 00 04 00 05 08 06 CF 02 83 03 FD * BAUD RATE * CRYSTAL 300 600 1200 2400 4800 * 5 MHz Latch 129 63 129 64 32 * Prescale 3 3 0 0 0 * 8 MHz Latch 207 207 207 103 51 * Prescale 3 1 0 0 0 * CRYSTAL FREQ * (BAUDRATE * 2) * 16 BAUD1 EQU 207 Value for the timer latch BAUD2 EQU >80+3 Value for the timer control * register BITO EQU 1 Various bit constants to BIT1 EQU 2 make code more readable BIT2 EQU 4 BIT3 EQU 8 BIT4 EQU 16 BITS EQU 32 BIT6 EQU 64 BIT7 EQU 128 * AORG >F806 START DINT Disable all interrupts MOV %>FD,B Set index to clear out CLR A all of RAM CLEAR STA @l(B) Store Os into all of RAM DJNZ B,CLEAR Loop until RAM is alIOs MOV %>60,B Set stack pointer LDSP * MOV %BIT1,BITS Active transmittter and * initialize receiver MOVP %?00101110,IOCNTL Enable Timer INT MOVP %?OOOOOOOO,PORTA Clear Port A MOVP %?OOOOOOOO,ADDR Init. AS for input MOVP %?00001000,PORTB Initialize Port B MOVP %BAUD1,TIMERL Put the baud rate MOVP %BAUD2,TIMERC into the timer * latch and timer * control EINT Start looking for * interrupts LOOP IDLE Wait for timer interrupt JMP LOOP or execute main program * here 9-23

... Design Aids - Serial Communication with the TMS7000 Family * TIMER 1 INTERRUPT

28 INTER2 EQU $ Start of timer interrupt

F828 B8 PUSH A Store registers F829 C8 PUSH B F82A 32 02 MOV STATER,B Get current receiver * state F82C CF RLC B Double in preparation * for jump F82D AE F844 CALL @JUMPR(B) Go perform receiver * tasks F830 77 02 OC OD BTJZ %BIT1,BITS,OUTIs a word being * transmitted? F834 75 01 OC XOR %BITO,BITS Do only every * other interrupt F837 77 01 OC 06 BTJZ %BITO,BITS,OUTTransmit 1/2 the * time F83B 32 03 MOV STATET,B Move transmit state to * index F83D CF RLC B F83E AE F8A5 CALL @JUMPT(B) Go to proper state of * routine F841 C9 OUT POP B F842 B9 POP A Restore the registers F843 OB RETI Exit the routine * RECEIVER JUMP TABLE * . F844 EO OE JUMPR JMP STATEO Check for start bit F846 EO 13 JMP STATE 1 Check for half a start * bit F848 EO 21 JMP STATE2 Bit boundry, wait for * 1/2 bit F84A EO 22 JMP STATE3 Test input for data F84C EO 1D JMP STATE4 Parity bit boundary F84E EO 34 JMP STATE 5 Check parity bit F850 EO 19 JMP STATE6 Stop bit boundary F852 EO 47 JMP STATE7 Check middle of the stop *. bit * Is the receive line low? F854 A6 20 04 02 STATEO BTJOP %BIT5,PORTA,ISPACE F858 D3 02 INC STATER If so, new start bit, F85A OA ISPACE RETS go to next state, * if not, do nothing * Check for false starts F85B A7 20 04 03 STATE 1 BTJZP %BIT5,PORTA,ISTART F85F D5 02 CLR STATER Clear state if false * start F861 OA RETS 9-24

Design Aids - Serial Communication with the TMS7000 Family F862 72 08 05 ISTART MOV %8,RXCNT Number of bits to * receive * Initialize parity F865 73 FE 07 AND %#BITO,RXPAR F868 D3 02 INC STATER Go to State 2 F86A OA RETS * F86B STATE2 EQU $ States 2,4 and 6 are F86B STATE4 EQU $ identical in operation F86B D3 02 STATE6 INC STATER Half bit, go to next * state F86D OA RETS * * Input new bit F86E A7 20 04 01 STATE3 BTJZP %BIT5,PORTA,BITLOW F872 07 SETC A 1 was found F873 DD 04 BITLOW RRC RXBUF Build the input word * here * Build up even parity F875 45 04 07 XOR RXBUF,RXPAR F878 D2 02 DEC STATER Goto half state * Is entire byte in? F87A DA 05 06 DJNZ RXCNT,OUTP3 * Store byte in storage register F87D 42 04 06 MOV RXBUF,RXSTOR F880 72 04 02 MOV %4, STATER Go to State 4 F883 OA OUTP3 RETS Check for even parity (use BTJZ for * odd parity) F884 76 01 07 09 STATE5 BTJO %BITO,RXPAR,IS1 * Out if both parities O? F888 A7 20 04 09 ISO BTJZP %BIT5,PORTA,OUTPAR F88C 74 20 OC BADPAR OR %BIT5,BITS Bit 5= Parity error F88F EO 04 JMP OUTPAR * Continue if parities both =1 F891 A7 20 04 F7 lSI BTJZP %BIT5,PORTA,BADPAR F895 D3 02 OUTPAR INC STATER Reset State Counter F897 74 04 OC OR %BIT2 , BITS Set 'Word ready' bit F89A OA RETS * * Stop bit = I? F89B A6 20 04 03 STATE7 BTJOP %BIT5,PORTA,ISSTOP F89F 74 08 OC OR %BIT3, BITS Bit 3= Framing error F8A2 D5 02 ISSTOP CLR STATER Reset State Counter F8A4 OA RETS * TRANSMITTER SECTION * * TRANSMITTER JUMP TABLE * F8A5 EO 08 JUMPT JMP STATEA Start outputting string F8A7 EO OB JMP STATEB Output start bit F8A9 EO 15 JMP STATEC Output data bits F8AB EO 2A JMP STATED Output parity bit F8AD EO 37 JMP STATEE Output stop bit 9-25

... Design Aids.-Serial Communication with the TMS7000 Family * F8AF D5 09 STATEA CLR TXTABL Initialize table pointer F8Bl 8E F8Fl CALL @FIRST Load the first byte into * buffer * Send out a Start bit F8B4 A3 F7 06 STATEB ANDP %#BIT3,PORTB F8B7 72 08 08 MOV %8,TXCNT 8 bits per character * Initialize parity to 0 F8BA 73 FE OB AND %#BITO,TXPAR F8BD D3 03 INC STATET Go to the next state F8BF OA RETS * F8CO 45 OA OB STATEC XOR TXBUF,TXPAR Build up Parity bit * Send a 1 or a O? F8C3 77 01 OA 05 BTJZ %BITO,TXBUF,TRANSO F8C7 A4 08 06 ORP %BIT3,PORTB Output a 1 bit F8CA EO 03 JMP NXTBIT F8CC A3 F7 06 TRANSO ANDP %#BIT3,PORTB Output a 0 bit F8CF DC OA NXTBIT RR TXBUF Point to the next bit F8Dl DA 08 02 DJNZ TXCNT,OUTC Are all 8 bits done * yet? F8D4 D3 03 INC STATET Output stop bits next F8D6 OA OUTC RETS * * Output even parity (use BTJO for * odd parity) F8D7 77 01 OB 05 STATED BTJZ %BITO,TXPAR,PARTYO F8DB A4 08 06 ORP %BIT3,PORTB Output a 1 bit F8DE EO 03 JMP OUTD F8EO A3 F7 06 PARTYO ANDP %#BIT3,PORTB Output a 0 bit F8E3 D3 03 OUTD INC STATET Output stop bit next F8E5 OA RETS * F8E6 A4 08 06 STATEE ORP %BIT3,PORTB Send out a stop bit F8E9 72 01 03 MOV %l,STATET Send out start bit * next F8EC 74 01 OC OR %BITO,BITS Go to TX routine every * other interrupt * F8EF D3 09 INC TXTABL Point to next byte * from table F8Fl 32 09 FIRST MOV TXTABL,B Setup output table * pointer F8F3 AA F908 LDA @STRING(B) Get value from table F8F6 72 01 03 MOV %l,STATET Output Start bit next F8F9 2D FF CMP %>FF,A FF = end of string F8FB E6 08 JNE NEWTX Jump if not end of * string F8FD 74 10 OC OR %BIT4,BITS End of text string, * set bit F900 73 FD OC AND %#BITl,BITS Turn off transmitter F903 D2 03 DEC STATET Start at beginning * next time F905 DO OA NEWTX MOV A,TXBUF Store new byte F907 OA RETS 9-26

Design Aids - Serial Communication with the TMS7000 Family F908 41 42 43 F90C 45 46 47 F910 49 4A 4B F914 4D 4E 4F F918 51 52 53 F91C 56 55 57 F920 59 SA 31 F924 33 34 35 F928 37 38 39 F92C FF F92D F92D OB FFF8 FFF8 2D F828 FFFC 2D F806 S This text string could be in RAM or ROM TEXT 'ABCDEFGHIJKLMNOPQRSTVUWXYZ1234567890' INTER1 INTER3 BYTE >FF End of string byte EQU RETI AORG DATA END $ External interrupts vectors Not used in this program >FFFE-(3*2) INTER3,INTER2,INTER1,START NO ERRORS, NO WARNINGS

9.4.3 Hardware UART (TMS70x2)

The main portions of the serial port are the receiver (RX), transmitter (TX), and timer (T3). The complete functional definition of the serial port is configured by the user program. A set of control words must first be sent out to configure the serial port. For more information about the serial port, see Section 3. The serial port is controlled and accessed through registers in the Peripheral File. The registers associated with the serial port are shown in Table 9-9. Table 9-9. Serial Port Control Registers REGISTER NAME TYPE FUNCTION TMS70Cx2 TMS70x2 P20 P17 SMODE FIRST WRITE Serial Port Mode P21 P17 SCTLO READ/WRITEt Serial Port Control 0 P22 P17 SSTAT READ Serial Port Status P23 P20 T3DATA READ/WRITE Timer 3 Data P24 P21 SCTL1 READ/WRITE Serial Port Control 1 P25 P22 RXBUF READ Receiver Buffer P26 P23 TXBUF WRITE Transmission Buffer t Write only for TMS70x2 devices The hardware serial port program is divided into three sections: 1) The initialization section 2) The transmitter section 3) The receiver section 9-27

Design Aids - Serial Communication with the TMS7000 Family The transmitter and the receiver sections are in the serial-port interrupt service routine. The main body of the program follows the initialization section and runs between interrupts.

9.4.3.1 Initialization

The program first initializes all registers, starting with the interrupt control re­ gisters IOeNTO and IOeNT1. The stack pointer is set and output ports A and B are initialized. Next, the serial port registers are set up. The first write operation to PF lo­ cation P17 immediately following a reset accesses the SMODE register. All subsequent writes to P17 access the control register SeTlO. If the condition of P17 is unknown, then writing a single 0 to P17 will cause the register to be seTlO. The program can then reset the serial port by writing a 1 to the UR bit in SeTlO. Finally, the serial port timer is started and the interrupts are enabled. The processor then waits for the timer interrupt to service the serial port. Faster baud rates allow less time for the main program to run, since it only runs be­ tween the interrupts. INT4 is dedicated to the serial port. Three sources can generate an interrupt through INT4: the transmitter (TX), the receiver (RX), and Timer 3 (T3). The serial port can be driven by Timer 3 or external baud rate generator. The Timer 3 interrupt function is usually disabled when using the UART because the timer will interrupt 16 times for every bit or about 160 times per byte. In this HWUART program, the T3 interrupt is disabled and the internal Timer 3 is chosen as the serial clock.

9.4.3.2 Transmitter

When the program enters the serial port interrupt routine, it determines if the transmitter or receiver caused the interrupt. If the interrupt occurred because the transmitter is empty, then the program takes the next byte in the transmitter table and places it in the transmitter buffer. The first byte of the transmitter data contains the total number of bytes in the string. If the index is zero, the program places this byte count into the index register instead of transmitting it. This is an alternate method to the software UART's example of ending the string with a unique character.

9.4.3.3 Receiver

If the receiver causes an interrupt and no errors exist, then the program takes the value in the receiver buffer and places it into a receiver table. After the character is placed into the table, the character counter at the beginning of the table is updated. The main program must take this data and reset the character count before the RAM buffer becomes full. This is an alternate method to the software UART's example of putting the value in a register and setting a flag for the main program.

Design Aids - Serial Communication with the TMS7000 Family

9.4.3.4 Error Conditions

If the program detects an error condition in the serial port Status Register, then the program sets a bit in RAM for the main program body to detect. When the main program detects this error bit, it looks at SSTAT to determine the cause of the error and takes action (if necessary). The main program may cause the byte to be retransmitted, if necessary.

9.4.3.5 Baud Rates

The baud rate generated by Timer 3 is user-programmable and is determined by the value of the 2-bit prescaler and the 8-bit timer reload register. The se­ rial port discussion in Section 3 provides a table of common baud-rate values.

9.4.3.6 RS-232-C Interface

The RS-232-C interface consists of SN75188 line drivers and SN75189A line receivers as shown Figure 9-8. This is the same interface circuit used in the software example. Port A5 (input) of the TMS70x2 is used for all data re­ ceptions, and Port 83 (output) is used for all data transmissions.

9.4.3.7 Hardware UART Routines _

• * This program uses the onboard UART to simulta­ * neously transmit and receive characters. * Characters for transmitting are placed starting * at TTABLE with the first byte equal to the * string byte count. The received bytes are * stored in the table RTABLE with the beginning * byte equal to the characters received. PORTA EQU P4 Port A - UART input ADDR EQU P5 Port A direction PORTB EQU P6 Port B - UART output IOCNTl EQU P16 Interrupt 4,5 control SMODE EQU P17 Serial port mode SCTLO EQU P17 Serial port control 0 SSTAT EQU P17 Serial port control status T3DATA EQU P20 Timer 3 data SCTL1 EQU P21 Serial port control 1 RXBUF EQU P22 Receiver buffer TXBUF EQU P23 Transmitter buffer 9-29

Design Aids - Serial Communication with the TMS7000 Family 0005 0006 0007 0008 001E 0001 0002 0004 0008 0010 0020 0040 0080 F006 F006 liliiii F007 A2 2A 00 FOOA A2 03 10 FOOD 52 60 FOOF 00 FOlD A2 FB 05 F013 A2 08 06 F016 A2 00 11 F019 A2 40 11 F01C A2 7E 11 F01F A2 15 11 9-30 POINTT EQU POINTC EQU BITS EQU * RTABLE EQU R5 Pointer into receiver table R6 Number of bytes ready to send R7 Transmitter chars send so far R8 Store random conditional bits here

030 Beginning of receiver table

BITO EQU 1 Bit constants to make code more BIT1 EQU 2 readable BIT2 EQU 4 BIT3 EQU 8 BIT4 EQU 16 BITS EQU 32 BIT6 EQU 64 BIT7 EQU 128 START * * AORG DINT MOVP MOVP MOV LDSP MOVP MOVP MOVP MOVP MOVP MOVP >F006 %>2A,IOCNTO %>03,IOCNT1 %>60,B Disable interrupts (precaution) Single chip, clear INT flags Disable I1, 12, 13 Clear INT4 flag and enable INT4 Initialize stack pointer %#BIT2,ADDR Set A2 = input others are output %BIT3,PORTB Enable TX by setting B3 = 1 %>00,P17 Make sure P17 points to SCTLO %BIT6,SCTLO Reset the UART via the UR bit %?0l1i11l0 ,SMODE One stop bit, communi­ cations mode, even parity, 8 bits, Asynchronous mode, Motorola %>15,SCTLO Clear the serial port reset bit

Design Aids - Serial Communication with the TMS7000 Family F022 A2 00 15 F025 A2 CO 15 F028 A2 67 14 F02B 05 F02C D5 07 F02E D5 06 F030 D5 05 * * * * * Clear all error flags and enable the transmitter and receiver MOVP %)00,SCTL1 Make sure the start bit is off MOVP %)CO,SCTL1 Use internal CLK, reset T3FLAG Disable T3 interrupt and set PS= 0 MOVP %103,T3DATA Set timer at 1200 baud EINT (5 MHz) Enable maskable interrupt SETUP CLR POINTC Clear bytes transmitted count * * CLR CLR POINTT POINTR Clear bytes to transmit Clear bytes received count *** Main body of program goes here * *** Main body finds and corrects serial port * error conditions by checking Bit 0 of * 'BITS' and SSTAT. _ F036 EO 03 F038 74 01 08 the * Was there an error? JMP ERROR OR SAVEIT %BITO,BITS Set an error bit for main program to find and continue F03B B8 SAVEIT PUSH A Save register A F03C C8 F03D A7 02 11 12 F041 D3 05 F043 7D 1E 05 F046 E3 OB F048 32 05 F04A 80 16 F04C AB 001E F04F 62 F050 8B 001E * * RXCV SKIP1 PUSH B BTJZP %BIT1,SSTAT,TXOUT Did receiver cause interrupt? INC CMP JHS MOV MOVP STA MOV STA POINTR %30,POINTR TXOUT POINTR,B RXBUF,A @RTABLE(B) B,A @RTABLE Get receiver table ponter Is receiver table full yet? get out of routine if so Get index value Put received character in Register A Put value into table Store the new character count Put count at location o in table and exit 9-31

Design Aids - Serial Communication with the TMS7000 Family F053 A7 01 11 16TXOUT BTJZP %BITO,SSTAT,OUTI4 * Did XMIT cause interrupt? F057 4D 06 07 XMIT CMP POINTT,POINTC * Is the table finished? F05A E3 11 JHS OUTI4 Jump if finished F05C D3 07 INC POINTC Point to the next index F05E 32 07 MOV POINTC,B Get transmit table * pointer F060 AA F070 SKIPO LDA @TTABLE(B) Load value from TX * table F063 5D 00 CMP %O,B Is this the byte count? :F065 E6 04 JNE OUTPUT If not, output the byte F067 DO 06 MOV A,POINTT If so, put into pointer F069 EO 02 JMP OUTI4 F06B 82 17 OUTPUT MOVP A,TXBUF Put data into * transmitter F06D C9 OUTI4 POP B Restore registers F06E B9 POP A F06F OB RETI Return to main program F070 1A TTABLE BYTE 26 Text can be either in * ROM or RAM registers F071 41 42 43 44 TEXT 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' F075 45 46 47 48 F079 49 4A 4B 4C F07D 4D 4E 4F 50 F081 51 52 53 54 F085 55 56 57 58 F089 59 SA FFF6 AORG -(4+1)*2 Set up 4 vectors * =interrupts FFF6 F032 FOO6 DATA INTER4,START,START,START,START FFFA FOO6 F006 FFFE F006 END NO ERRORS, NO WARNINGS 9-32

Design Aids - The Status Register

9.5 The Status Register

The Status Register contains four status bits that provide conditional exe­ cution for a variety of arithmetic and logical tasks. The carry (C), negative (N), zero (Z), and interrupt enable (I) flags occupy bits 7-4 of the Status Register. The C, N, and Z bits are affected by most instructions. The global interrupt enable (I) bit is affected by the EINT, DINT, and POP ST instructions. MSb78543210LSb IcINlzlll+~EU~EI Figure 9-10. Status Register Section 9.5.1 describes the way in which the compare instructions can be used to create the necessary status conditions for either a logical-type (un­ signed) or arithmetic-type (signed) jump instruction. In Section 9.5.2 de­ scribes the effects of addition and subtraction on the Status Register for both signed and unsigned systems. Finally, Section 9.5.3 describes how SWAP and the rotation instructions (RR, RRC, RL, and RLC) can be used to clear, _ set, shift, or test the various status bits as required. The compare instructions, CMP and CMPA. affect the C, N, and Z bits in the Status Register by subtracting a source operand (S) from a destination oper­ and (d). Destination and source may be misnomers in this case, because the result of (d) - (s) is not stored; however, the status bits are set according to the result of the subtraction. C Serves as a "no-borrow" bit. If (d) is greater than or equal to (s), then there is no borrow and C is set to 1. C is set to 0 if (d) is less than (s). N Is set to the same value as the MSb of the result. For 2's complement (signed) systems, N = 1 indicates a negative number, and N = 0 indi­ cates a positive number. Z Is set to 1 if the source is equal to the destination [(d) = (s)]. The CMP instruction uses the contents of a register (Rn) as the destination operand, and either an immediate operand or the contents of another Rn as the source operand. The CMPA instruction uses the contents of Register A as the destination operand and one of the extended addressing modes (Direct, Register File Indirect. or Indexed) generates the source operand. Table 9-10 illustrates the limits of both signed and unsigned systems by listing the status bits affected for various source and destination operands substituted into the (d) - (s) expression. 9-33

Design Aids - The Status Register Table 9-10. Compare Instruction Examples: Status Bit Values SOURCE DESTINATION D-S C N Z INSTRUCTIONS THAT WILL JUMP FF 00 01 0 0 0 JL JNC JNE JNZ JP JPZ FF FF 1 1 0 JHS JC JNE JNZ IN 7F 7F 1 0 0 JHS JC JNE JNZ JP JPZ 00 7F 0 0 0 JL JNC JNE JNZ JP JPZ 81 81 1 1 0 JHS JC JNE JNZ IN 00 80 0 1 0 JL JNC JNE JNZ IN 80 80 1 1 0 JHS JC JNE JNZ IN 80 01 1 0 0 JHS JC JNE JNZ JP JPZ 7F FF 0 1 0 JL JNC JNE JNZ IN 7F 00 1 0 1 JHS JC JEQ JZ JPZ 00 81 0 1 0 JL JNC JNE JNZ IN Since the compare instructions do not alter the source and destination oper­ ands, these instructions can be executed before a conditional jump instruction to test for a particular relationship between the source and destination oper­ ands. Table 9-11 lists the necessary status bit conditions for each of the conditional jump instructions. Table 9-11. Status Bit Values for Conditional Jump Instructions CONDITION ON STATUS BIT MNEMONIC INSTRUCTION WHICH JUMP VALUES FOR JUMP: IS TAKEN C N Z JC/JHS Jump If Carry/Jump If Higher (d) unsigned >= (s) 1 X X or Same JNC/JL Jump If No Carry/Jump If Lower (d)unsigned«s) 0 X X JZ/JEQ Jump If Zero/Jump If Equal (d) = (s) X X 1 JNZ/JNE Jump If Non-zero/Jump If Not (d)';' (s) X X 0 Equal JP Jump If Positive (d) - (s) = pos # X 0 0 IN Jump If Negative (d) - (s) = neg # X 1 X JPZ Jump If Positive or Zero (d) - (s) = pos # or 0 X 0 X Note: X = Don't Care 9-34

Design Aids - The Status Register The TMS7000 instruction set supports both single and multi-precision addi­ tion and subtraction for either binary or BCD, signed (2's complement) or unsigned data. The f9110wing example illustrates 32-bit addition with the ADD and ADC in­ structions: ADD R30,R120 ADC R29,R1l9 ADC R28,Rl18 ADC R27,Rl17 Since no initial carry-in is desired, the first instruction is ADD. The ADC in­ struction is then executed three times in succession to transfer the carry through all 32 bits. The following example illustiates 24-bit subtraction with the SUB and SBB instructions: SUB R4,R127 SBB R3,R126 SBB R2,R125 Since no initial borrow-in is desired, the first instruction is SUB. The SBB instruction is then executed twice in succession to achieve the 24-bit result. Figure 9-11 illustrates the rotation operations performed by the four rotation instructions Rotate Right (RR), Rotate Ri9ht Through Carry (RRC), Rotate Left (RL), and Rotate Left Through Carry (RLC), and the SwAp instruction. SWAP executes the equivalent of four consecutive RL instructions, setting the C bit in the Status Register equal to bit 4 of the original operand or bit 0 (LSb) of the result. CD--r-j 871 861 851 B4J 831 821 81 180 h r 871 861 851 8414831 821 81 180 b-'0 RL RR cEJ:=-l 87 1 86 1 851 84.1831 82181180 h d 871861 851 84~831 821 81 180 ~ RLC RRC OLD OLD NEW NEW MSN LSN MSN LSN OLD ~ NEW ~ o 1111111~lolololol gJ 10101oloJ111111~1 Figure 9-11. Swap and Rotation Operations 9-35

Design Aids - Stack Operations

9.6 Stack Operations

The stack is located in RAM and can be tailored to your needs. One powerful application of the stack is the establishment of tables. For example, Figure 9-12 illustrates a dispatch table with an interpretive program counter (IPC). An IPC is used in some high level languages, such as Pascal, to ~ive the proper execution sequence. The IPC can be contained in any re~ister; It points to an interpretive pseudo code (pcode) byte that in turn specifies one of 256 dispatch routines. The overall effect of this function is that a program can execute one of a large number of different routines depending on a single va­ lue stored in a register. EOU LDA DECD RL MOV LDA PUSH LDA PUSH RETS R3 *IPC IPC A A,B @DTABLE(B) A @DTABLE+l (B) A Interpretive Program Counter Get the input code range=0-127 Point to next input code Double pointer for word table Move to index register Lookup MSB address of Put MEB on stack Lookup LSB address of Put LEB on stack Jump to address on stack DTABLE DATA ROVO,ROV1,ROV2,ROV3address of routines DATA ROV4,ROV5,ROV6,ROV7address of routines Figure 9-12. A Dispatch Table with an Interpretive Program Counter (lPC) 9-36 Note that the assembler expressions have 16-bit values. Forthose instructions requirinlLan 8-bit operand, the expression is truncated to the least significant 8 bits. This may produce a warning message, but the value will be correct. Thus, the following instructions place byte values >AA, >55, and >55 at memory locations >8000, >8001, and >8002, respectively: AA55 LABEL E8U >AA55 8000 A RG >8000 8000 AA55 DATA LABEL 16-bit word * LSB only 8002 55 BYTE LABEL-(LABEL/256*256) The most significan~byte (MSB) of an expression can be obtained by dividing the value by 256 (2 ) as shown below: AA55 LABEL E8U >AA55 8000 A RG >8000 8000 AA55 DATA LABEL 8002 AA BYTE LABEL/256 MSB only

Design Aids - Subroutine Instructions

9.6 Subroutine Instructions

Two instructions, CALL and TRAP, can invoke subroutines. TRAP is a one byte subroutine call. Both instructions save the current value of the Program Counter (PC) on the stack before transferring control to the subroutine. Since the return address is stored on the stack, subroutines can be easily nested. The two instructions differ only in the way in which the subroutine address is determined and in the amount of program memory required for execution. The CALL instruction uses the Extended Addressing modes (Direct. Register File Indirect, and Indexed) to specify the subroutine address. This permits simple calls with a fully specified address as well as more complex calls with a calculated address. Of the two types of instructions, the CALL instruction requires more program memory than the TRAP instructions. For example: CALL @BITTEST requires three bytes of memory - one byte for the opcode and two bytes for the subroutine address. If the subroutine is called six times, 18 bytes are ne­ cessary to implement the CALLs. The equivalent task for the TRAP instruction requires only 8 bytes for six successive uses of the same TRAP, since only the opcode byte is necessary after the first use. Six of these 8 bytes are the TRAP opcodes and the other two bytes are the trap vector. The first use of the TRAP _ instruction requires one opcode byte plus the two bytes of the subroutine • address which are located in the Trap Table. Each subsequent use requires only one more byte, compared to three bytes for each CALL. All the trap vectors are stored at the end of memory with the most significant byte of the trap subroutine stored in the lower numbered location. The exact address where the trap vector (which is the trap subroutine address) is stored is de- rived from the following formula. LSB of Address which contains the TRAP subroutine address = >FFFF - 2 x N where N is the TRAP number. MSB of address = LSB - 1 The TRAP instructions (TRAPs 4-23) provide the most efficient means of in­ voking subroutines. Figure 9-13 shows a subroutine call generated by a TRAP instruction. 9-37

Design Aids - Subroutine Instructions 9-38 BITTEST TRAP 4 BR MAINPR EQU $ RETS (Main Program) (More Main program) (Subroutine Body) AORG >FFF6 Trap 4 vector DATA BITTEST Figure 9-13. Example of a Subroutine Call by Means of a TRAP Instruction The Return from Subroutine (RETS) instruction should be executed to pop the PC from the stack and restore program control to the instruction imme­ diately following the CALL or TRAP instruction.

Design Aids - Multiplication and Shifting The MPY instruction performs an 8-bit by 8-bit multiply and stores the 16-bit result in Registers A and B. The most significant byte (MSB) of the result is in Register A. and the least significant byte (lSB) is in Register B. The MPY instruction can also be used to perform multi-bit right or left shifts by using an immediate operand as the multiplier. For example: MPY %8,B The preceding example multiplies the value of Register B by 8. After the in­ struction executes, Register B contains the previous value left-shifted three bits (23 = 8) with no fill bits. Register A contains the previous value's most significant three bits which produces a value equivalent to shifting the previ­ ous value right five bits (8 - 3 = 5) with no fill bits. Using this method, it is possible to shift any 8-bit value left or right up to 8 bits. In many cases this is faster than the rotate instructions and .almost always takes less program bytes. If the word only needs to be shifted one or two places then the rotate instructions may take less execution time. Table 9-12 lists the number of bits right-or left-shifted for a range of immediate multipliers. Table 9-12. Multi-Bit Right or Left Shifts by Immediate Multiply IMMEDIATE BITS BITS MULTIPLIER RIGHT LEFT SHIFTED SHIFTED 2 7 1 4 6 2 8 5 3 16 4 4 32 3 5 64 2 6 128 1 7 Multi-precision multiplications can be easily executed by breaking the multi­ plier and the multiplicand into scaled 8-bit quantities, as shown in the exam­ ples at the end of this section. 9-39

Design Aids - The Branch Instruction The branch instruction (BR) unconditionally transfers program control to any desired location in the 64K byte memory space. BR supports direct, indexed, and indirect addressing:

• Direct addressing is used for simple GOTO programming.
• Indexed addressing allows table branches. This indexed branch tech­ nique is similar to the Pascal CASE statement. Program control is trans­ ferred to location CASEO if the input is 0, to CASE1 if it is a 1, etc. This transferring method can implement up to 85 different cases. In the ex­ ample below, indexed addressing is used to access a relative branch ta­ ble: JTABLE MOVP P4,A Get data from A port * (value < 85) ADD A,B Add twice to triple value ADD A,B Multiply it by 3 * (BR is 3 bytes long) BR @CTABLE(B) Branch according to the * A port value * 2 * CTABLE BR @CASEO If P4 0 do this branch BR @CASEl If P4 1 do this branch BR @CASE2 If P4 2 do this branch
• The branch instruction can also be used with indirect addressing in order to branch to a computed address. For example, suppose that a com­ puted branch address has been constructed in R19 and R20. The de­ sired program control transfer is made by: BR *R20

9.9 Interrupts

The number of interrupts and the hardware configuration for a TMS7000 fa­ mily device are specified in Sections 2 and 3. The TMS7020, for example, has three interrupts in addition to RESET. RESET and the interrupts are vectored through predetermined memory lo­ cations. RESET uses the TRAP 0 vector which is stored at memory locations >FFFE and >FFFF. The interrupts also use the TRAP vector table with INT1 using the TRAP 1 vector, etc. Thus, the TRAP 2 instruction involves the same code as the interrupt INT2. The interrupts differ from the TRAPs; they push the Status Register value on the stack, clear the interrupt enable bit in the Status Register, and reset the corresponding interrupt flag bit. Thus the EINT instruction must be used if nested interrupts are desired. The return from interrupt (RETI) instruction re­ stores the Status Register and the Program Counter, re-enabling interrupts. Many interrupt service routines alter the status of key registers such as Regis­ ters A and B. These routines should use the stack to restore the machine state to the desired value. For example, the following interrupt routine performs an I/O driven table look-up. Registers A and B are used, but their values are saved and restored: INT PUSH PUSH MOVP LDA MOVP POP POP * RETI A Store Registers A and B on stack B P4,B Get input from Port A @LOOKUP(B)Do a table lookup to get new value A,P6 Output new value on Port B B Restore Registers A and B in the A reverse order that they were put on Back to main program All interrupts are usually disabled during an interrupt service routine. If it is necessary for an interrupt to occur while the processor is servicing another interrupt, then the global interrupt enable bit should be set to 1 by the inter­ rupt service routine. The number of interrupts that can be serviced at anyone time is determined by the size of the stack, which is also the internal RAM size (the stack resides in the Register File). Since other registers and data will most probably share the same space, the stack size is usually much less. When nesting interrupts, great care must be taken to avoid corrupting the data in the registers used by the most recent routine. If INT1 interrupts an ongoing INT1 service routine, then the registers used by the INT1 routine are used in two different contexts. If provisions are not made for these situations, such as di­ sabling all interrupts at critical times, then data errors will occur. Sometimes a program contains distinct portions that require different re­ sponses to the same interrupt call. Since the interrupt vector is always set in nonchangeable ROM, another method must be used to change the vector for each part. One method for accomplishing this is to store a second vector in a RAM register pair and allow the first instruction in the interrupt routine exe­ cute an indirect branch on that register. 9-41

• Program to demonstrate multiple interrupt service * routine locations. * Main Program MOVD %SERVIC,RI27 EINT IDLE MOVD %SERVI2,R127 * First Interrupt I Service SERVIC PUSH A PUSH B Put INTI service routine address in register Turn on and wait for interrupts Change INTI routine to SERVI2 Routine Beginning of the INTI service routine for this part of the program * Second Interrupt 1 Service Routine SERVI2 PUSH A Start of another interrupt DEC R4 1 service routine INTI BR * Interrupt AORG DATA DATA *R127 vector table at >FFFC INTI >F806 The entire INTI service routine tranfers control to the address which is in R127 and RI26 end of memory Address of Interrupt I service routine Reset vector start of program

Design Aids - Write-Only Registers Certain TMS70xx peripheral registers are write-only registers, which means that the program cannot directly ascertain the contents of the register. Table 9-13 lists write-only registers. Table 9-13. Write-Only Registers REGISTER LOCATION FUNCTION REGISTER LOCATION FUNCTION IOCNTO PO Current mode IOCNT1 P16 Interrupts T1DATA P2 Timer 1 latch T1CTl P3 Timer 1 control T2DATA P18 Timer 2 latch T2CTl P19 Timer 2 control T3DATA P20 Timer 3 latch SCTlO P17 Serial port SMODE P17 Serial port TXBUF P23 Transmit buffer Problems may arise using some instructions with these write-only registers because most have a separate read-only function at the same address. An error may occur when you execute an instruction that reads the register, mo­ difies the value and then writes back to the register. These instructions are ANDP, ORP, XORP. For instance, the program cannot turn on the timer by ORing a 1 to the timer Start bit, because the instruction will read the capture latch, set the MSb to 1, and then write this value to the timer control register. Unfortunately, this will change the prescaler and the timer may wait forever for a nonexistent external clock source. The solution to this problem involves image registers which store the con­ tents of a write-only register. An image register is a RAM register set aside to contain the value ofa particular register. Whenever the write-only PF register must be changed, the program first fetches its image register, changes it, and then writes the image register to the peripheral register. This way, the image register always contains the value of the peripheral register. The following code using an image register could be used to turn on the timer start bit. OR %>80,T1CTLI Turn on start bit of * timer control MOV T1CTLI,A MOVP A,T1CTL Move the image register to the Peripheral File 9-43

Design Aids - Sample Routines The following sections contain sample routines to show the various ways the TMS7000 handles common software tasks. Actual programs usually contain a combination of simple routines such as these along with custom routines tailored to the applications. . This routine clears all the internal RAM registers. It can be used at the be­ ginning of a program to initialize the RAM to a known value. Register Function A Holds the initialization value B Index into the RAM AORG >FOO6 * CLEAR MOV %126,B Number of register to clear - 2 CLR A Load the initialization value of * zero LOOP STA @2(B) Clear the location indexed by * B + 2 DJNZ B,LOOP Loop until all RAM is cleared

Design Aids - Sample Routines This routine performs a simple alternating 0/1 test on the RAM. The RAM is tested by writing a >AA, >55 pattern to the entire RAM and then checking the RAM for this pattern. The inverted pattern is then written to RAM and re­ checked. Finally, the entire RAM is cleared. If an error is found, a bit is set in a flag register. Register Before After After No Error Error A XX 0 ? B XX 0 ? Rn XX 0 ? FLAG XX 0 Bit 0 = 1 Passing data: Registers affected: None All Ending data: All registers = 0 Bit 0 in FLAG = 1 if error was found MOV FILLR MOV FILLl STA RR DJNZ RR MOV COMPAR CMPA JNE RR FILLO * ERROR * EXIT DJNZ TSTA IN JZ CLR JMP OR EQU %>55,A %>FD,B @2{B) A B,FILLl A %>FD,B @2(B) ERROR A B,COMPAR FILLR EXIT A FILLR %l,FLAG Start RAM fill with >55 Set RAM start address - 2 (don't change register A or B) Fill RAM with AA 55 pattern Change from 55 to AA to 55 Fill the entire RAM with this pattern Change to beginning number Refresh index Check for errors Exit if the values don't match Change from 55 to AA to 55 Check the entire RAM Is Reg A now 55, AA or aO? =AA, change to opposite pattern =00, finished now get out =55, clear the RAM now Repeat the fill and check routine Set bit 0 in the flag register Continue program here 9-45

Design Aids - Sample Routines This routine checks the integrity ofthe ROM by performing a checksum on the entire ROM. All ROM bytes from >F008 to >FFFF are added together in a 16-bit word. This sum is checked against the value at the beginning of the ROM (>F006,>F007). If the values don't match, then an error has occured and a bit is set in a register. Register Before After After Error No Error A XX ?? ?? B XX ?? ?? R2 XX CHKSUM MSB CHKSUM MSB R3 XX CHKSUM LSB CHKSUM LSB R4 XX >FO >FO R5 XX >07 >07 R6 XX >FF >FF R7 XX >FF >FF FLAG XX Bit 1 =0 Bit 1 = 1 AORG DATA ROMCHK MOVD MOVD MOVD * ADDLOP ERROR EXIT LDA ADD ADC DECD DECD JC LDA CMP JNE LDA CMP JEQ OR EQU >F006 CHECKSUM Put correct checksum into ROM Other initialization program here %>FFFF,R5Starting address (end of memory) %>FF7,R7 Number of bytes to add + 1 %>O,R3 Reset summing register *R5 A,R3 %O,R2 ADDLOP @>F007 A,R3 ERROR @>F006 A,R2 EXIT %2,FLAG Get ROM byte Add to 16-bit sum Point to next address Decrement byte counter Continue until byte count goes past 0 Compare LSB stored to LSB sum Set error bit if different Compare MSB stored to MSB sum Set error bit if different Set bit 1 in the Flag register Continue program here

Design Aids - Sample Routines This program converts a 16-bit binary word to a packed 6-nibble value. Register Before After A XXXX BCD MSB B XXXX BCD R2 XXXX BCD LSB R3 BINARY MSB ZERO R4 BINARY LSB ZERO R5 XXXX ZERO AORG >F006 * BN2BCD CLR A Prepare answer registers CLR B CLR R2 MOV %16,R5 Move loop count to register LOOP RLC R4 Shift higher binary bit out RLC R3 Carry contains higher bit DAC R2,R2 DAC B,B Double the number then add the * binary bit DAC A,A Binary bit (a 1 in carryon 1st * time is doubled 16 times). DJNZ R5 ,LOOP Do this 16 times, once for each * RETS

9.11.5 BCD-to-Binary Conversion

A B * BCD2BN Before BCD X X AORG >F006 MOV AND SWAP CMP JHS MPY AND CMP JHS ADD A,R2 %>FO,A A %10,A ERROR %10,A %>OF,R2 %lO,A ERROR R2,B bit After Binary MSB Binary LSB X Store word in R2 Isolate MSB Move to LSB position Is it a valid BCD digit? Goto error routine if not Multiply MSB by 10, results at A,B in binary Isolate LSB Is it a valid BCD digit? Add LSB to binary MSB to finish * conversion ERROR RETS END 9-47

Design Aids - Sample Routines The following subroutine uses the addition instructions to add two multi-digit numbers together. Each of the numbers is a packed BCD string of less than 256 bytes (512 digits) stored at memory locations STR1 and STR2. This routine adds the two strings together and places the result in STR2. The strings must be stored with the most significant byte in the lowest numbered register. The TMS7000 family instruction set favors storing all numbers and addresses with the most significant byte in the lower numbered location. Register Before After Function A B STR1 STR2 * * * * * ADDBCD LOOP XXXX ?7n Accumulator XXXX 0 length of string XXXX ?7n Temporary save register XXXX no change BCD string XXXX STR1+STR2 Target string. 6 bytes max Decimal Addition Subroutine Stack must have 3 available bytes. On output: STR2 = STRl + STR2 CLRC PUSH 'LDA MOV LDA POP DAC PUSH STA DJNZ POP RETS ST @STR1-l(B) A,R2 @STR2-1(B) ST R2,A ST @STR2-1(B) B,LOOP ST Clear carry bit Save status of stack Load current byte Save it in R2 Load next byte of STR2 Restore carry from last add Add decimal bytes Save the carry from this add Store result Loop until done Restore stack to starting position Back to calling routine Notice the use of the Indexed Addressing mode to reference the bytes of the decimal strings. Notice also the need to push the status register between de­ cimal additions. to save the decimal carry bit. Register B is used to keep count of the number of bytes that have been added.

Design Aids - Sample Routines

9.11.7 Fast Parity

This routine presents a quick way to determine the parity of a byte. By ex­ clusiving ORing all the bits of the byte together, a single bit will be derived which is the even parity of the word. When exclusive ORing, an even number of 1 s will combine to form a 0, leaving either an odd 1 or 0 bit. This routine keeps splitting the byte in half and exclusive ORing the two halves. Register A B Carry Before Target XXXX XXXX After ???? ???? Parity Function Passing byte from program Length of string Status bit, result to calling routine * STEP 1 * Byte bits 7654 3210 SUBROUTINE TO FIND EVEN PARITY * XOR 7654 [MSN above] * * * STEP 2 * * * STEP 3 * * * xxxx ABCD xx ab ---> a b XOR a x P [MS bit] {answer } * PARITY MOV SWAP XOR * * * MOV RR RR XOR MOV RR XOR RR RETS A,B A B,A A,B A A B,A A,B A B,A A Duplicate the target byte Line up the MS nibble with the LS nibble Exclusive OR the nibbles to get a nibble answer Duplicate the nibble answer Line up bits 0, 1 of the answer to bits 2, 3 of the answer XOR to get a new 2-bit answer Duplicate this 2-bit answer Line up bit 0 with bit 1 XOR to get final even parity answer Rotate answer into the carry bit and bit 7 Carry = 0 = even # of Is Carry = 1 = odd # of Is Use JC, IN or JNC JPZ in next executed instruction 9-49

Design Aids - Sample Routines

9.11.8 Overflow and Underflow

An exclusive OR of the C and N bits ANDed with the exclusive OR of the MSbs of the operands can be used as a check for an overflow or underflow for subtraction in a signed system (if (C XOR N) AND (MSb1 XOR MSb2) '" 1 then out of range). When adding two signed numbers, the test for an out-of-range condition is similar to the subtraction method. When an exclusive OR of the C and N bits ANDed with the inverse of the exclusive OR of the MSbs of the two operands equals one then an overflow or underflow has occurred (if (C XOR N) AND (NOT(MSb1 XOR MSb2)) '" 1 then out of range). Register A OPRND1 OPRND2 Before XXXX XXXX XXXX After nn OPRND1 OPRD2-0PRD1 Function Subtraction results * Routine to check for signed underflow or overflow * If (C XOR N) AND (MSbl XOR MSb2) '" 1 then out of range NOTNEG * ISNEG CXORNI * * * OUTRNG * * NOERR MOV XOR SUB IN JNC JMP JC TSTA JPZ OPRNDl,A OPRND2,A OPRNDl,OPRND2 ISNEG NOERR CXORNI NOERR NOERR Get XOR of the MSbs Subtract 2 signed numbers N '" 0 C XOR N '" 1, First part of equation is true N"'l C XOR N '" 1; set flags for MSbl XOR MSb2 If (N XOR C) AND (MSbl XOR MSB2) '" 1 then out of range. For addition change this instruction to IN NOERR Out of range; underflow or overflow No underflow or overflow

Design Aids - Sample Routines

9.11.9 Bubble Sort

This routine will sort up to 256 bytes using the bubble sort method. Longer tables could be sorted using the Indirect Addressing mode. Register A B * FLAG * SORT LOOPl LOOP2 AORG EQU CLR MOV LDA CMPA JL INC PUSH LDA STA POP STA DJNZ Function Temporary storage register Index into the table Holds flag to indicate a byte swap has been made >F006 FLAG %149,B @TABLE(B) @TABLE-l(B) LOOP2 FLAG A @TABLE-l(B) @TABLE(B) A @TABLE-l(B) B,LOOPl 'Swap has been made' flag Reset swap flag 150 bytes to be sorted Look at entry in table Look at next lower byte If lower skip to next value Entry is not lower, set swap flag Store upper byte Take lower byte Put where upper was Get the old upper byte Put where the lower byte was Loop until all the table is looked at BTJO %>FF,FLAG,SORT * If swap was made, then resweep table * If no swap was maQe, then table is done 9-51

Design Aids - Sample Routines

9.11.10 Table Search

Table searches are efficiently performed by using the CMPA (Compare Reg­ ister A Extended) instruction. In the following example, a 150 byte table is searched for a match with a 6-byte string: Register A B TABLE STRING * SEARCH LOOP1 LOOP2 MATCH * NOFIND Before XXXX XXXX XXXX XXXX XXXX After ?17? 1717 ??n no change no change MOV MOV XCHB DEC JZ LDA XCHB CMPA JNE DJNZ EQU EQU %150+1,R2 %6,B B NOFIND @TABLE-1(B) @STRING-1(B) LOOP 1 B,LOOP2 Function Table length Long string in table Target string, 6 bytes max Table length = 150 bytes String length = 6 bytes Swap pointers, long string in B Table end? If so, no match found Load test character Swap pointers, string pointer in B Match? If not, reset string pointer else test next character Match found No match found The Indexed Addressing mode is used in this example and has the capability to search a 256-byte string, if needed. Register B alternates between a pointer into the 6-byte test string and a pointer into the longer table string.

Design Aids - Sample Routines 9.11.11 16-Bit Address Stack Operations This routine performs 16-bit stack operations using the 1 -byte TRAP instruc­ tion for pushing and popping. It uses macros to make code more readable. All values pass through Register A. Function Register A Passing register for routines Indirect pointer MSB Indirect pointer LSB Define Macro PUSH16 as a trap instruction PUSH16 $MACRO TRAP 6 $END * * * Define Trap 7 to be the POP16 operation POP16 $MACRO TRAP 7 $END * TRAP6 INC R3 PUSH16 ADC STA %O,R2 *R3 Increment the indirect pointer Push Register A * TRAP 7 * * RETS LDA DECD RETS *R3 POP16 Pop into Register A decrement the indirect pointer AORG >FFFO Set up Trap and Interrupt * vectors DATA TRAP7,TRAP6,INT5,INT4,INT3,INT2,INTl,RESET END * Examples of use MOVD %)1234,R3Initialize the 16-bit stack pointer MOV %DATA,A Load Register A PUSH16 Use the macro to push A onto the stack POP16 Return a value from the stack. MOV A, TEMP Move the value to a temporary register 9-53

Design Aids - Sample Routines 9.11.12 16-by-16 (32-Bit) Multiplication XL YH YL RSLT3 _ RSLT2 RSLTl RSLTO * MPY32 9-54 This example multiplies the 16-bit value in register pair R2,R3 by the value in register pair R4,R5. The results are stored in R6, R7, R8, R9, and Registers A and B are altered. l6-BIT MPY: XH YH XL YL X VALUE Y VALUE EQU EQU EQU EQU EQU EQU EQU EQU CLR CLR MPY MOV MOV MPY ADD ADC MPY ADD ADC ADC MPY ADD ADC x XLYLl XHYLm XLYHm XHYHm XHYHl XLYLm XHYLl XLYHl

1 LSB

m = MSB RSLT3 RSLT2 RSLTl RSLTO RSLT2 RSLT3 XL,YL B,RSLTO A,RSLTl XH,YL Rl,RSLTl RO,RSLT2 XL,YH Rl,RSLTl RO,RSLT2 %O,RSLT3 XH,YH Rl,RSLT2 RO,RSLT3 Higher Lower Higher Lower Msb of operand of X operand of X operand of Y operand of Y the final result LSB of the final result Clear the present value Multiply LSBs Store LSB in result register 0 Store MSB in result register 1 Get XHYL Add to existing result XLYL Add carry if present Multiply to get XLYH Add to existing result XLYL+XHYL Add to existing results and carry Add if carry present Multiply MSBs Add once again to the result reg Do the final add to the result reg

Design Aids - Sample Routines This program divides a 16-bit dividend by an 8-bit divisor giving a 8-bit quo­ tient and an 8-bit remainder. All numbers are unsigned positive numbers. The dividend's MSB must be less than the divisor to ensure an 8-bit quotient. Dividend: Q-FFFF Divisor: 1-255 Quotient: 0-255 Register A B Before DIVIDEND MSB DIVIDEND LSB DIVISOR R3 XXXX AORG >F006 * BINDVD MOV DVDLP RLC RLC JNC SUB SETC JMP SKIPl CMP JNC SUBIT SUB * * * DIVEND DJNZ RLC %8,R3 B A SKIPl R2,A DIVEND R2,A DIVEND R2,A R3,DVDLP B After REMAINDER QUOTIENT DIVISOR ZERO Set loop counter to 8 Multiply dividend by 2 * These * steps are not needed * if the divisor is limited _ * to 7 bits * Is MSB of dividend > divisor If so dividend=dividend - divisor C=l gets folded into next rotate Next bit, is the divide done. Finish the last rotate 9-55

Design Aids - Sample Routines This program divides a 16-bit dividend by an 8-bit divisor, producing a 16-bit quotient and an 8-bit remainder. All numbers are unsigned positive numbers. The dividend's MSB can be larger than divisor. Dividend: O-FFFF Divisor: 0-255 Quotient: o-FFFF 18 r8 8"'-- Register Before After A XXXX REMAINDER B DIVISOR DIVISOR R2 DIVIDEND MSB QUOTIENT MSB R3 DIVIDEND LSB QUOTIENT LSB R4 XXXX ZERO AORG >FOO6 * BINDVD MOV %16,R4 Set loop counter to 16 (8+8) CLR A Initialize result register DVDLP RLC R3 Multiply dividend by 2 RLC R2 RLC A JNC SKIP1 * These * steps are not needed SUB B,A * if the divisor is limited SETC * to 7 bits JMP DIVEND * SKIP1 CMP B,A Is MSB of dividend > divisor JNC DIVEND SUB B,A If so dividend=dividend * - divisor * C=l gets folded into next * rotate DIVEND DJNZ R4,DVDLP Next bit, is the divide done? RLC R3 Finish the last rotate RLC R2

Design Aids - Sample Routines This program divides a 16-bit dividend by an 16-bit divisor, producing a 16-bit quotient and a 16-bit remainder. All numbers are unsigned positive numbers. The dividend's MSB can be larger than divisor. Dividend: Q-FFFF Divisor: Q-FFFF Quotient: Q-FFFF 18 r18 18nr- Register A Before XXXX B XXXX DIVIDEND MSB DIVIDEND LSB DIVISOR MSB DIVISOR LSB XXXX After REMAINDER MSB REMAINDER LSB QUOTIENT MSB QUOTIENT LSB DIVISOR MSB DIVISOR LSB ZERO AORG >F006 * BINDVD MOV * CLR CLR DIVLOP RLC RLC RLC RLC JNC SUB SBB * SETC %16,R6 A B B A SKIP1 R5,B R4,A Set loop counter to 16 (8 + 8) Initialize result register Multiply dividend by 2 Check for possible error condition that results when a 1 is shifed past the most significant bit Correct by subtracting out the divisor JMP DIVEND * SKIP1 CMP R4,A Is MSB+LSB of dividend > divisor JNC DIVEND JNE MSBNE Are MSBs equal? CMP R5,B If so, compare LSBs JNC DIVEND * MSBNE SUB R5,B If borrow, dividend=divi­ dend - divisor * * * SBB DIVEND DJNZ RLC RLC R4,A C=l get folded into next rotate Next bit, is the divide done? R6,DIVLOP R3 Finish the last rotate 9-57

Design Aids - Sample Routines

9.11.16 Keyboard Scan

This routine reads a 16-key keyboard, returns the hex digit of the key, and debounces the key to avoid noise. A 'valid key' flag is set when a new key is found. , I<EVBOARD: PORTC CO INPUT C1 C2 II TM87OXO C4 o 1 2 3 OUTPUT C5 4587 C8 88A8 C7 CDEF Register Before After After No Key New Key Function A XXXX 0 COLUMN Temporary B XXXX 0 ROW Temporary R2 XXXX 16 KEY # Temp store for Key value R3 OLD KEY >FF KEY# Holds Key pressed now R4 DEBOUNCE 0 0 Debounce counter, old R5 GENERAL BITS AORG >FOO6 * CDDR EQU P9 PORTC EQU P8 * GETKEY MOV CLR MOVP * LOOP RLC JC ADD MOVP MOVP MOVP AND JZ KEYLSB DEC RRC JNC * NEWKEY CMP JEQ MOV * MOV 9-58 %8,B %>FO,CDDR B NOKEY %4,R2 B,PORTC PORTC,A %O,PORTC %>F,A LOOP A KEYLSB R2,R3 DEBONS R2,R3 %16,R4 key or new ?xxxxxxxO ?xxxxxxx1 One bit of register is 1 if new key Initialize row pointer Set Data direction register 4 output, 4 input Select next row Last row ? if so no key was found Add number of keys/row to key accumulator Activate row Read columns Clear row Isolate column data If no keys found then check next row Decrement column offset Find column If not column then, try again Is the new key the same as the old key If it is then debounce it Brand new key, Move it to current key value Set up debounce count

Design Aids - Sample Routines DEBONS CMP JL DJNZ * * %2,R4 GOODKY R4,GETKEY GOODKY BTJZ #01, R4, NOTNEW * DEC R4 * OR NOTNEW RETS * NOKEY MOV * RETS %l,RS %)FF,R3 Is the debounce count 1 or 0 ? If greater than 1 then debounce is not finished, go read key again If debounce count=O then key was here last time If it was one this is a new valid key, make old key Set new key flag in BIT register, the calling routine uses this flag No key was found, set key value to unique value 9.11.17 8-Bit Analog-to-Digital Converter ATOD * LOOP * ASMALL * ABIGER * * FINISH This routine converts an analog signal to a digital value using a digital-to­ analog converter and a comparator. TMS1OxO Register Before A XXXX B XXXX MOV %)80,B CLR A MOVP %)FF,P9 OR B,A MOVP A,P8 BTJOP %1,P4,ABIGER XOR B,A RRC B JNC LOOP RETS After ANALOG VALUE ZERO ANALOG INPUT IF ANALOG IS LARGER COMPARATOR = 1 Function Final digital value Trial and error test value Starting value for binary search Initialize value Port C is all outputs Set the next bit in Test value Send it to the D-A converter Is this value Less than the analog value? If Analog value is smaller, decrease test value . If Bigger go to next bit in test value If not at the end, then go test the next bit 9-59

Design Aids - Sample Routines

9.11.18 Motor Speed Controller

This routine keeps the speed of a motor constant. A pulse proportional to the speed of the motor comes from a sensor next to a slotted disk on the motor. The motor is controlled by a variable voltage generated by a D-A converter. Some mechanical considerations are necessary for an actual system. SLOTTED DISK TMS7040 Register A PULSE1 SPEED STEP SPEED1 SPEED2 8-8IT D-TO-A Before DATA PULSE MSB SPEED STEP SIZE SPEED MSB SPEED LSB After NO CHANGE NEW SPEED NEW SIZE NO CHANGE NO CHANGE MOTOR Function Temporary register Holds MSB of pulse length va- lue Holds current Voltage value for D-A How much the voltage is changed per cycle The desired time between the slots as measured by the timer (1 =MSB, 2=LSB) AORG EQU EQU EQU EQU EQU EQU EQU EQU >F006 R4 MSB of 16-bit pulse length counter Current voltage output to motor Change output voltage by this amount MSB of 16-bit speed reference RS LSB of 16-bit speed reference General purpose register for bits Step size for coarse adjustment Step size for fine adjustment

Design Aids - Sample Routines MCNTL MOVP MOVP MOVP EINT %>FF,P2 %>80+32,P3 %>3E,PO Initialize the timer value Initialize the pres caler and start timer Clear interrupts, enable 12, 13 The interrupts are now enabled * * Main program body here INT2 BTJZP * * BTJOP JMP OK INC * JNC * ERRORl OR * NOERR * INT3 * * TESTSP GOFAST OUTPUT SAME RETI MOVP PUSH MOV CMP JEQ JL ADD MOV MOVP POP CLR RETI GOSLOW SUB JMP * TESTLS MOVP INV CMP JEQ MOV JMP %>20,PO,OK Interrupt 2 routine, check for pending INT 3 %>80,P3,OK Check Capture Latch value for recent change INT3 If P3 is pending and CL just under­ flowed then INT3 came first, go directly to INT3 PULSEl Increment the MSB counter for the pulse length NOERR If overflow there was an error (Motor too slow) %Ol,BITS Set an error bit for the main routine to find %>80+32,P3 A % INCR 1, STEP Restart the timer at beginning Save register Coarse adjustment step size for voltage change SPEED1,PULSEl TESTLS GOSLOW STEP,SPEED SPEED,A A,P8 A PULSEl Compare desired speed to measured speed (MSB) If the same then compare LSBs Does motor need to go faster or slower If faster, increase voltage to motor Move new voltage value to D-A Restore register Clear MSB of pulse length STEP,SPEED Decrease the motor voltage OUTPUT Output voltage value P3,A A SPEED2,A SAME %INCR2,STEP TESTSP Get LSB of pulse length from capture latch Since it counts from FF to 00, invert value Compare desired speed to measured speed (LSB) If the same do nothing Fine adjustment step size for voltage change Set new speed according to LSB values 9-61

Design Aids - Sample Routines 9-62

Texas Instruments provides extensive development support for the TMS7000 family. TMS7000 software support is referred to as CrossWare, and includes a macro assembler and a link editor. Appendix G contains instructions for in­ stalling the TMS7000 CrossWare.

• The TMS7000 Assembler translates TMS7000 assembly language in­ structions and directives into object code. Sections 5 and 6 discuss the assembler and the TMS7000 assembly language instructions.
• When several components of a source program are assembled individ­ ually, the TMS7000 Link Editor links together the object code produced by these program modules to form one complete executable program. Section 7 discusses the link editor. TMS7000in-circuit development tools include:
• The XDS (Extended Development System) emulator, which provides realtime in-circuit emulation of the TMS7000 devices in all modes.
• The TMS7000 Evaluation Module (EVM), a single-board development system that emulates the TMS7000 devices in Single-Chip mode.
• Several prototyping units, including the TMS7742, SE70P162, SE70CP160, SE70CP162, and TMS77C82 4. These tools allow a designer to evaluate the TMS7000's performance, bench­ mark time-critical code, and determine the feasibility of using a TMS7000 in a specific application. The TMS7000 CrossWare translates programs into modules that can be executed on the XDS emulator or EVM. This section discusses key features of the hardware development tools; extensive XDS and EVM documentation is available (the preface contains literature numbers). Section Page

4 Advance Information

Development Support - The XDS Emulator The TMS7000 XDS/22 5 (Extended Development Support) emulator is a self­ contained system that provides full-speed in-circuit emulation. Key features include:

• Host-independent development system
• Supports the TMS70xO, TMS70CxO, TMS70x2, and TMS70Cx2 devices in Single-Chip and Expansion modes
• Realtime hardware breakpoint/trace/time capabilities
• Execution of programs from target memory
• Three EIA ports allow communication with peripherals
• Several possible system configurations, including standalone, host- computer, and multiprocessor configurations The host-independent configuration shown in Figure 10-1, combined with a complete set of development and debugging tools, allows you to select the TMS7000 processor best suited to your application. Since the same set of tools emulates each processor, you only need to learn the basic development format once. XDS cross-assemblers and host interfaces are available for the following sys­ tems:
• IBM PC, TI PC running MS/PC-DOS
• DEC VAX 11 running VMS
• IBM 370,3033, 43xx running MVS or CMS
• TI DX10 XDS hardware includes a chassis, power supply, and a three-board set con­ sisting of an emulator, communications board, and a breakpoint/trace/time board. 5 XDS is a registered trademark for Texas Instruments Incorporated. All rights are reserved. 10-2

Development Support - The XDS Emulator PC, OR TERMINAL WITH OlliER HOST: -VAX -IBM - Tl/eeo XDS OPTIONAL PERIPHERALS TARGET Figure 10-1. Typical XDS Configuration 10-3

Development Support - The XDS Emulator 10,1.1 Software Development A B C DR I MR N PC Pnn ROM SP ST CRUN GHALT GRUN RTR RUN SRR SS STOP THALT TRUN BTT DBTT DTIME IBTT XTIME Software written and developed on a host computer can be downloaded to the XDS/22 emulator memory space via a standard RS-232 EIA link. The XDS monitor is located in the firmware onboard the emulator. A powerful set of commands provide complete control of the emulator functions and the target system, enhancing development and testing of target hardware and software. The XDS monitor commands include an assembler that permits almost any system to be used as an intelligent terminal and prepare the source text for assembly by the XDS emulator. Table 10-1 lists the TMS7000 XDS/22 com­ mands. Table 10-1. TMS7000 XDS/22 Commands REGISTER COMMANDS TRACE COMMANDS Display or set Register 0 DT Display trace Display or set Register 1 FT Find trace sample Display or set carry bit IT Inspect trace Display registers SORt Set opcode range Display or set STI NT bit TRt Set trace qualifiers Modify registers TRIXt Trace on extended IAQ Display or set negative bit TRMt Trace memory select Display or set Program Counter UPLOAD/DOWNLOAD COMMANDS Display or set register nn DL Download to emulator Display or set ROM pointer IHC Initialize host control chars Display or set Stack Pointer IPORT Initialize EIA ports Display or sefstatus bit UL Upload to host RUN COMMANDS STATUS COMMANDS Continue run DHS Display halt status Group halt (MP mode) DPS Display processor status Group run DTS Display trace status Reset target and run ID Display foreground EMU banner Start program execution INIT Initialize emulator Software reset and run IPC Initialize peripheral control Single-step execution RESTART Restart emulator Stop execution (ARM mode) /n Display status of emulator n Total halt (MP mode) #n Select emulator from chain Total run (MP mode) BTT COMMANDS INTERNAL COMMANDS Set B/T /T conditions $CLK Set clock divider Display B/T /T parameters $INT Modify interrupt Display time $UART Modify UART type Initialize B/T/T Analyze timing t These commands are only valid when the B/T board is installed. 10-4

Development Support - The XDS Emulator Table 10-1. TMS7000 XDS/22 Commands (Concluded) BREAKPOINT COMMANDS MEMORY COMMANDS BPt Set hardware breakpoint conditions BLK Remap memory block BPMt Set BP condo on memory access OM Display program memory CASB Clear all software breakpoints EXP Remap expansion memory CSB Clear a software breakpoint FILL Fill memory with data DSB Display all software breakpoints FIND Find data in memory SIB Set internal breakpoint 1M Display or set memory SSB Set a software breakpoint MM Modify program memory MISCELLANEOUS COMMANDS MODE COMMANDS COpy Copy memory ARM Initialize alternate run mode DV Display value BGND Initialize background mode HELP Display command menu DIAG Initialize diagnostic mode ICC Initialize cursor control DISARM Disable alternate run mode LOAD Load command defaults from memory HOST Initialize host mode LOG Turn logging device on or off IMD Initialize MP mode MESG Send message (diag. mode) IMP Initialize MP mode RCC Reset cursor controls QDIAG Quit diagnostic mode SAVE Save command defaults into memory SNAP Set up snapshot display XA Execute assembler XRA Execute reverse assembler t These commands are only valid when the BIT board IS Installed. The XDS timing capabilities allow you to store trace samples that contain realtime timing stamps. Trace samples, like breakpoints, may be selectively chosen on desired memory and I/O cycles, allowing such software measure­ ments as:

• Program/memory activity
• Module execution duration
• Intermodule execution duration
• Module usage Using the hardware and software breakpoint commands and the trace func­ tion, a complete record of events can be examined. You can select a range of memory addresses and I/O addresses to set valid breakpoints. The breakpoint/trace/time (B/T/T) board allows you to set breakpoints on any memory cycle - memory read, memory write, or instruction acquisition. For I/O operations, the 8/T/T board can breakpoint on any I/O read or I/O write, if the I/O address qualifications are met. A 2047-sample trace buffer provides a history of execution before or after the breakpoint. Trace samples are stored in the trace memory and can be read back after execution has been halted. Memory and I/O cycles can also be traced. 10-5

Development Support - The XDS Emulator This cycle of using the host computer and the XDS/22 for testing provides a quick, efficient method for target system development. After debugging is complete, EPROMs can be programmed using the host computer's PROM programming capabilities. The XDS memory map for the TMS7000 family is extremely flexible. The emulator contains 64K bytes of RAM to support the entire address space of the TMS7000 devices. This 64K-byte memory space can be used to emulate on-chip ROM and external memory in the target application. Memory is allo­ cated in 256-byte blocks, X blocks as on-chip ROM and Y blocks as off-chip practical configuration desired, allowing system-level debug rather than just software or. hardware debug. The XDS unit can communicate with a host computer, terminal, PROM pro­ grammer; or printer through four EIA RS-232-C links. Communication func­ tions include: Downloading of data files from an external devices (external host, PROM programmer, or terminal) to emulator memory. Downloading of data to a PROM programmer or logging device.

• Terminal-to-host communication via passthrough mode.
• Transmission of data from emulator memory to a PROM programmer or logging device.
• Uploading of data files from the emulator to an external device (external host, PROM programmer, or terminal).

The TMS7000 XDS/22 can operate in one of four modes:

• Standalone mode is the minimum configuration, requiring only the XDS and your terminal.
• The XDS is best suited for use with a host computer and terminal in Host-Computer mode. This allows you to write programs using a familiar editor and then download them to the XDS. When debugging is complete, you can upload the code and store it on the host system.
• PC-Based mode is a variation of the host-computer mode - the host system is a single-user system such as a PC. The XDS supports host uploads/downloads over a single port, allowing a PC to function as both a terminal and a host. This configuration requires· a terminal-emulation software package such Crosstalk by Microstuf.

Development Support - The XDS Emulator

• An increasing number of designs use multiple microprocessor systems. In Multiprocessor mode, the XDS supports debugging of up to nine XDS stations linked together in a daisy-chained fashion. The XDS system is connected to the host computer via the RS-232 port of the last XDS workstation. A single CRT interface can control all of the workstations. Each workstation may be used individually or the work­ stations can be grouped or subgrouped to synchronize control over the entire target system. .

The breakpoint/trace/time (B/T /T) board allows you to set a hardware inter­ rupt or breakpoint that halts emulator execution. Breakpoints can be set on I/O and/or memory operations with three simple monitor commands. You can select a range of memory addresses and I/O addresses for valid breakpoints, or select two separate memory addresses or two separate I/O addresses. The B/T /T board can breakpoint on any memory cycle - read, write, or instruction acquisition. For I/O operations, the B/T /T board can breakpoint on any I/O read or write if the I/O address qualifications are met. The trace function provides a history of execution prior to the breakpoint. It is used to analyze a set of signals based on addresses and commands. Trace samples are stored in trace memory and can be read back after execution has been halted. Both memory and I/O cycles can be traced, including memory read, memory write, and instruction acquisitions or all memory cycles, and I/O _ read, I/O write, or any I/O cycle. The trace memory can hold 2047 words by 48 bits of trace samples. You are given the option of how many of these 2047 samples to take, or to keep wrapping around in trace memory, writing over the oldest trace sample with the newest trace sample. The B/T /T board also contains a cable which allows easy interfacing to logic analyzers. This interface provides many useful system signals not available through a target connector. The XDS/22 emulator is a table-top sized unit, suitable for most work sur­ faces. The XDS/22 has an air inlet on each side of the unit and an air exhaust port on the rear of the unit. A minimum of five inches clearance must be maintained between the XDS and neighboring equipment on the sides and rear for proper air flow. Listed below are the dimension and clearance re­ quirements. DIMENSIONS Width = 17.0 Inches (43.2 CM) Depth = 16.5 Inches (41.9 CM) Height = 7.4 Inches (18.8 CM) Target Cable = 18.0 Inches (46.0 CM) CLEARANCE REQUIREMENTS Sides 5 Inches Minimum (15.2 CM) Back 5 Inches Minimum (15.2 eM) Top None Required Front None Required 10-7

Development Support - Evaluation Modules

10.2 Evaluation Modules

The TMS7000 Evaluation. Module (EVM) provides hands-on hardware eval­ uation of TMS7000 devices. This single-board unit can function as limited feature, standalone development system. Key features include:

• Realtime in-circuit emulation
• Text editor
• Assembler
• Debug monitor
• Onboard EPROM programming utility
• Upload/download capabilities
• Single-step execution capabilities
• AUdio-cassette interface The RTC/EVM7000 emulates the TMS7000 Single-Chip mode; TMS7000 expansion modes are not supported. There are two versions of the evaluation module for the TMS7000 family: 1) RTC/EVM7000N-1 for NMOS devices 2) RTC/EVM7000C-1 for CMOS devices The EVM is equipped with eight 8K-byte sockets for the entire 64K-byte ad­ dress space of the TMS7000. 16K bytes of the EPROM are devoted to the resident firmware. User RAM can be expanded in 8K-byte increments, from 16K bytes to 32K bytes. During assembly and debug operations, the EVM RAM can be configured to emulate all TMS7000 family members; for the em­ ulation of the 2K-ROM and 4K-ROM versions, it allows assembly of text files directly from RAM. A wire-wrapped development area, with all required sig­ nals provided and labeled, is available for additional logic. The EVM crystal frequency can be modified to fit the needs of the target sys­ tem.

Several system configurations are possible:

• Standalone Mode - is the minimum configuration. The onboard text editor is used for creating TMS7000 assembly language tex1 files. The audio cassette tape interface, which has limited directory and file search capability, is used for mass storage.
• Host-Computer Mode - provides a more productive environment. The host is used to develop and save the text files. The files may then be assembled using the TMS7000 CrossWare, or they can be down­ loaded to the EVM for assembly by the onboard assembler. The EVM has two EIA RS-232 ports to support this and other possible config­ urations.
• PC-Based mode is a variation of the host-computer mode which al­ lows you to use a PC as both a terminal and a host. This requires a ter­ minal-emulation package such as Microstuf's Crosstalk.

Development Support - Evaluation Modules The EVM firmware supports three ports for loading and dumping data (text, object code) for storage and/or display. Port 1 and Port 2 conform to EIA RS-232-C standards and support baud rates ranging from 110 to 9600 BPI. Port 3 is the audio tape interface. The EVM firmware resides in 16K bytes of EPROM and is divided into three functional areas:

• Debug monitor and EPROM programmer
• Assembler
• Text editor The text editor is line oriented and provides basic character editing capabilities. Files can also be created using a host computer and downloaded to the EVM. CrossWare or the resident EVM assembler can be used to produce object code. Table 10-2 lists the TMS7000 EVM debug monitor commands. Table 10-2. TMS7000 EVM Commands MODIFY/DISPLAY REGISTER COMMANDS GENERAL UTILITIES CP Clear processor status AR Signed hexadecimal arithmetic DP Display processor status CL Display/modify cursor-left MA Display/modify Register A CU Display/modify cursor-up MB Display/modify Register B DC Display hex-byte conversion MM Display/modify memory DV Display/modify device type MP Display/modify Peripheral File HC Hex-Decimal word conversion MR Display/modify Register File HE Help HS Display/modify software handshake MS/PC/ Display/modify PC. ST. and SP SR/SP MEMORY LOAD/DUMP COMMANDS GENERAL MEMORY/REGISTER MANIPULATION COMMANDS OS Display/save machine state OM Display memory LM Load memory, 7000 format FB Find byte in memory LS Load machine state FM Fill memory LT Load memory, Tektronix format FR Fill Register File SM Save memory, 7000 format 10 Display I/O status St Save memory, Tektronix format MV Move memory EIA SUPPORT COMMAND NP Fill Memory with NOPs BR Display/modify baud rate AUDIO TAPE COMMANDS TEXT EDITOR SUPPORT COMMAND DR Audio tape directory XE Execute text editor MO Enable cassette motor 10-9

Development Support - Evaluation Modules Table 10-2. TMS7000 EVM Commands (Concluded) ASSEMBLER SUPPORT COMMANDS EPROM PROGRAMMER COMMANDS AT Display assembler label table CE Compare EPROM XA Execute assembler PE Program EPROM XL Execute line-by-line assembler RE Read EPROM XP Execute patch assembler VE Verify EPROM PROGRAM SUPPORT COMMANDS BT Set breakpoints on trap LA Show address of line B1 Set breakpoint 1 LL List line(s) from editor B2 Set breakpoint 2 LN Show line at address CB Clear breakpoints L1 Set breakpoint 1 by line number CT Clear breakpoint on trap L2 Set breakpoint 2 by line number C1 Clear breakpoint 1 RT Reset target processor C2 Clear breakpoint 2 RU Execute program without breakpoints DB Display breakpoints SS Single-step program DT Display breakpoint on trap TC Configure single-step trace EF Execute program with fixed display TR Display line trace ET Execute program with bpts/trace TS Single-step program with trace EX Execute program with breakpoints TO Load Program Counter with FS Single-step with fixed display Trap 0 vector The EVM is equipped to program '2764, '27C64, '27128, and '27C128 EP­ ROMs and the TMS7742 and SE77C42 EPROM microcomputers. The ability to program EPROMs greatly reduces evaluation and development time. These devices use a 28-pin programming socket.

Development Support - Prototyping Support The SE70P162, SE70CP160, SE70CP162, TMS7742, and the SE77C42 are protyping components that Texas Instruments offers to support form-factor emulation of a TMS7000 target processor. The SE devices are also referred to as piggybacks. The TMS7742 is an on-chip EPROM version of the 8-bit TMS7042 micro­ computer. The TMS7742 can be used to emulate the TMS7020, TMS7040, and the TMS7042 microcomputers.

10.3.1.1 TMS7020 and TMS7040 Emulation

The TMS7742 can emulate the TMS7020/40 in all operatinQ modes. If op­ erated in a memory-expansion mode, the enhanced timing mterface signals of the TMS7742 will seem transparent to any memory-expansion interface logic required for the TMS7020/40. The only feature of the TMS7020/40 that the TMS7742 cannot directly emulate is the edge- and level-sensitive inter­ rupts. If level-sensitive interrupts are desired, external circuitry is required to allow the TMS7742 to sense level interrupts. If level-sensitive interrupts are not desired, the TMS7742 can emulate the TMS7020/40 with no alterations to the system hardware or software.

10.3.1.2 TMS7042 Emulation

The TMS7742 can directly emulate the TMS7042 up to 5 MHz without any _ hardware or software modifications. Above 5 MHz (5 MHz to 8 MHz), the I SE70P162 provides direct emulation. The SE70P162 is the piggyback-EPROM prototyping device for the TMS7000 NMOS family of microcomputers. The SE70P162 can be used to emulate the TMS7020, TMS7040, and the TMS7042 microcomputers, with the same lim­ itations as the TMS7742. However, the SE70P162 can operate at a maximum frequency of 8 MHz, enabling it to emulate the TMS7042 over the full oper­ ating range of the device. The SE70CP160 is a CMOS piggyback-EPROM prototyping device. It emu­ lates the TMS70C20 and TMS70C40 microcomputers. The SE70CP162 is a CMOS piggyback-EPROM prototyping device. It emu­ lates the TMS70C42.

10.3.5 SE77C42 Description

The SE77C42 is a 4K on-chip EPROM version of the 8-bit TMS70C42 mi­ crocomputer. The SE77C42 supports prototyping for the TMS70C42. 10-11

Development Support - Prototyping Support 10-12

The TMS7000 family of single-chip microcomputers is supported by product offerings from a number of independent vendors. These support products take many forms, including cross-assemblers that run on small systems, second sources for the TMS7000 components, and PROM programming manufac­ turers that support TMS7000 EPROM programming. This section discusses a number of tools that enhance the support provided by Texas Instruments. This does not constitute product endorsement by Texas Instruments; it is merely an attempt to aid product awareness. The products listed here are representative of independent vendor supplied products. This information is not intended to be an all-inclusive list. Section Page

11.2 Cybernetic Micro Systems - IBM-PC Crossware and

11.3 Software Development Systems, Inc. - UniWare ™

11.5 Hewlett-Packard - HP64000 Microcomputer

Independent Support - Allen Ashley

11.1 Allen Ashley - Software Development Support Tools

Allen Ashley supports cross-assemblers, disassemblers, and emulators for the TMS7000 family which allow most CP/M™6, MS/DOS™7, or PC/DOS™8 systems to serve as a development station for single-chip microcontrollers.

• Cross-Assemblers: 1) MAC7000 enables any MSDOS/PCDOS system to serve as a de­ velopment station for the Texas Instruments TMS7000 series mi­ croprocessors. This software system features a macro assembler, cross-reference generator, hex file converter, screen editor, and off-loading facilities. The assembler mnemonics adhere to the as­ sembly language defined by Texas Instruments. The macro as­ sembler includes full macro and conditional assembly features, as well as the ability to include a series of source files together during a single assembly. Programs developed under MAC7000 must be off-loaded to the target processor for test; a user-configurable down loader is provided, as well as a down loader configured spe­ cifically for the XDS development module. MAC7000 is available on TI/MSDOS or IBM/PCDOS 5-1 /4-inch disk or MSDOS 8-inch (NEC APC) disk. 2) XMAC7000 includes a relocating macro assembler, linking loader, absolute macro assembler, text editor, cross-reference gen­ erator, and off-loading facilities. The relocating macro assembler features full macro and conditional assembly as well as the ability to chain a series of source files together during a single assembly. Relocation is extended to 8- or 16-bit quantities and externals and can be referenced with an offset. The two-pass linking loader produces an absolute Intel hex file. The relocation capability of XMAC7000 greatly facilitates modular program development and the re-use of previously developed program segments. The abso­ lute macro assembler is provided for projects which do not require the relocation feature. A user-configurable down loader is pro­ vided, as well as a specific down loader configured for the XDS development module. XMAC7000 is available on TI/MSDOS or IBM/PCDOS 5-1 /4-inch disk or MSDOS 8-inch (NEC APC) disk. 3) System- TMS7 enables any CP/M-80 system to serve as a de­ velopment station for the Texas Instruments TMS7000 series mi­ crocontrollers. This software system features a macro assembler, an interactive editor/assembler, a text editor, a cross-reference generator, and off-loading facilities. The assembler mnemonics adhere to the TMS7000 assembly lan­ guage defined by Texas Instruments. The macro assembler in- 6 CP/M is a registered trademark for Digital Research, Incorporated. All rights are reserved. 7 MS/DOS is a trademark of Microsoft Corporation. 8 PC/DOS is a trademark of IBM Corporation. 11-2

Independent Support - Allen Ashley cludes full macro and conditional assembly features as well as the ability to chain a series of source files together during a single as­ sembly. The interactive editor/assembler is intended for the rapid creation, modification and test of program modules. Programs developed under this system must be off-loaded to the target processor for test. Facilities are provided to implement the off-loading mechanism as a direct transfer from memory, via a byte stream over a CPU port, or via .COM or .HEX disk files. These fa­ cilities are provided in a user-configurable form as well as in a specific form to off-load to the TI EVM7000 evaluation module and the XDS7000 development system. System-TMS7 is available on CP/M 8-inch soft sector (3740), 5-inch North Star, Micropolis Mod II, Osborne I, Xerox 820, Kay­ pro II, TI PC or IBM PC diskette (the last two require CP/M-80 capability) .

• Disassembler: DASM7000 is a disassembler for the TMS7000 family of microcontrol­ lers and is available for PCDOS or IBM-compatible MSDOS computers. This disassembler converts existing machine code into an assembly lan­ guage source file for modification. DASM7000 features mnemonic disassembly with user-defined symbols and data areas. The disassembly produces an ASCII text source file suitable for input to the MAC7000 cross assembler. DASM7000 is available on 5-1 /4-inch PCDOS disk.
• Emulator: The EMU7000 is an emulator for the TMS7000 family of microcontrol­ lers and is available for PCDOS or IBM-compatible MSDOS microcom­ puters. In conjunction with the MAC7000 cross assembler, the EMU emulator provides a development environment for the creation and sim­ ulated execution of programs for the TMS7000 processor. The EMU simulator features an in-line assembler, 64K program space, symbolic debugging, up to 10 breakpoints, address trapping, single-step or free-run operation, mnemonic disassembly, and trace operation. The simulator is relatively weak for testing I/O-intensive programs; the strength of the simulator lies in the representation and control of pro­ gram logic. EMU7000 provides an inexpensive adjunct/alternative to hardware emulation. EMU7000 is available on TI/MSDOS or IBM/PCDOS 5-1 /4-inch disk. Full documentation is included in all software packages and full user support is provided by mail or phone. For more information contact: Allen Ashley, Inc.

395 Sierra Madre Villa

Pasadena, Ca. 91107 -2902 (818) 793-5748 11-3

Independent Support - Cybernetic Micro Systems

• IBM -PC Crossware Cybernetic Micro Systems' combination cross-assembler and EPROM programming board enables designers to develop assembly language programs for the TI TMS7000 family on an IBM PC. The CYS-7000 cross-assembler supports all of the TMS7000 family assembly language mnemonics, but eliminates support for macroroutines and relocatable object code. . The. software assembles instructions at a rate of 450 lines per minute. For EPROM programming needs, Cybernetic Micro Systems' CYP-27XX EPROM programming board can be connected to the PC's serial port and is able'to program most 16- to 256-Kbit EPROMs and 16-Kbit EEPROMs. The entire development package consists of one diskette and program­ ming board. The software runs on an IBM PC under PC-DOS 2.0. Source programs can be generated by any standard PC editor. Versions of this cross-assembler are also available from Cybernetic Micro Systems for the TI Professional Computer. TMS7000 Simulator The Cybernetic Micro Systems Sim7000 Simulator executes code for the TMS7000 family microcomputer on the IBM-PC type personal computer. The simulator allows TMS7000 programs to be debugged before execution on an emulator or piggyback chip. Sim7000 can sim­ ulate all the hardware functions of the TMS7000 family, including the serial port devices. The Sim7000 provides numerous features that assist the designer in debugging TMS7000 code, including symbolic exe­ cution, traps and breakpoints, access to memory spaces, and flow graph generation. This package is designed to work with the Cybernetic CYS-7000 cross assembler described above. The Sim7000.offers a display which is separated into various windows for easy viewing. These window provide the following information: Code window Shows lines for the source code Register window Display current state of the device Memory window Displays a portion of different memory spaces. Stack window Lists the contents of the Stack Flow window The control flow with various options is shown. Help window Describes a command Command window Shows the current command with prompting For more information, contact: Cybernetic Micro Systems P.O. Box 3000 San Gregorio, CA 94074 (415) 726-3000 Telex: 171-135 Attn: CYBER

Independent Support - Software Development Systems, Inc. 11.3 Software Development Systems, Inc. - UniWare Tt• TMS7000 Assembler The Uniware™9 TMS7000 Assembler generates ROMable, relocatable code for all members of Tl's 7000 Microprocessor Family. The assembler features advanced macros, file inclusion, versatile listing control, cross refer­ ence listings, and TI compatibility in instruction mnemonics, directives, and operand formats. Symbol names may be arbitrarily lo'ng and symbol capacity is unlimited. A linker and librarian are provided. The linker supports libraries, unlimited symbols, intermediate links, multiple overlays, and link-time use and definition of symbols, Code and data can be easily separated into different memory re­ gions to fit your hardware configuration. A unique absolute listing converter is also provided. After the link, this utility converts all relocatable addresses and unlinked object code on assembler list­ ings into absolute addresses and linked object code. Finally, the downloader converts your load into any of a variety of industry standard file formats for downloading to EPROM programmers, emulators, and target hardware. Custom formats and symbolics are supported. The UniWare TMS7000 Assembler runs on all IBM PC's and compatibles under MS-DOS, IBM PC-ATs and compatibles under XENIX and on virtually all UNIX based machines available soon under DEC VAXNMS. For more information please contact: Mr. James E. Challenger Software Development Systems, Inc.

4248 Belle Aire Lane

Downers Grove, IL 60515 1-800-448-7733 Outside U.S. please call 1 -312-971 -8170 FAX: 1-312-971-8513 9 UNIWARE is a trademark of Nuvatec, Inc. UNIX is a trademark of AT&T. 11-5

Independent Support - SEEQ

11.4 S'EEQ - Self-Adaptive EEROM

The SEEQ8 72710 is a full-function single-chip microcomputer, fabricated in N-channel silicon-gate technology, which contains a 1 K-by-8 5V nonvolatile electrically-erasable (EEROM) program memory. The program memory can be erased and programmed via the processor itself during normal program execution or can be programmed under control as if it were a standard 5V EEROM memory component. The EEROM can easily be expanded off-chip using the processor's Full-Expansion mode. External EEROM can be pro­ grammed with the same instruction used to alter on-chip EEROM. A security lock mechanism is implemented in EEROM memory which allows your program to inhibit external access to its proprietary program code. Once activated, this lock can be reset only by an external EEROM block-clear oper­ ation, which erases the entire program memory contents. As with other SEEQ EEROM devices, the 72710 has DiTrace8 and Silicon Signature8 features to facilitate production testing tracking. Each device is encoded with detailed processing and testing results which are stored in a special EEROM memory as it passes through the manufacturing cycle. Also stored is an unalterable identification code which contains information such as mask revision and EEROM programming parameters. An EEROM member of the TMS7000 family is desirable because a single-chip microcomputer with non-volatile program memory that can be altered under process control allows the design of low cost products with many new fea­ tures:

• • Self adaptive code for machines that learn as they perform their tasks. In-circuit reprogrammability to eliminate product disassembly for firm­ ware updates. Remote reprogrammability to eliminate service calls for firmware up- dates. . Internally stored product history including factory test results, product configuration, r~vision level, and service records. Stored initialization parameters to eliminate front panel switches and automatically configure product for one or many users. Product usage and error logging to simplify maintenance and pinpoint product failure modes. .
• Code and data security to protect proprietary programs and confidential data. For more information, contact: SEEQ Technology Incorporated

1849 Fortune Drive

San Jose, California 95131 (408).432-7400

10 SEEQ, DiTrace, and Silicon Signature are registered trademarks for SEEQ Technology

Incorporated. All rights are reserved. 11-6

Independent Support - Hewlett-Packard

11.5 Hewlett-Packard - HP64000 Microcomputer Development

The Hewlett-Packard HP64000 microcomputer development system is a real­ time user-definable system which can be configured to support the TMS7000 family of microcomputers. This user-definable system consists of the following devices which can be configured specifically for the TMS7000 family devices:

• HP642745 - User-definable emulator
• HP648515 - User-definable assembler/linker
• H P64856AF - User-definable inverse assembler
• H P64851 B - User-definable interface For more information, call the nearest Hewlett-Packard sales office listed in the telephone white pages. Ask for the Electronic Instrument department. You may also write to: Hewlett-Packard P.O. Box 617 Colorado Springs, Colorado 80901 In Colorado, call (303) 590-3340 (collect) Nationwide, call 1-800-447-3282 11-7

Independent Support - EPROM Microcomputer Support

11.6 EPROM Microcomputer Support

The following third-party companies support programming of TMS7000 EPROM microcomputers.

• Data 1/0 Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, Washington 98073-9746 (206) 881 -6444 (800) 247-5700
• PROMAC Adams MacDonald Enterprises, Inc.

800 Airport Road

Monterey, California 93940 (408) 373-3607 (800) 777-1202 Products include the PROMAC 2, 2A, 10, 16 and Sprint+. Advanced Microcomputer Systems, Inc. 2780 S.w. 14th Street Pomano Beach, Florida 33069 (305) 975-9515 Products include the AMS2000 (IBM-PC compatible PC board) and the PROM 2000-8 (Personality box for the TMS7742).

• Logical Devices, Inc. 1201 N.W. 65th Place Fort Lauderdale, Florida 33309 (305) 974-0967 (800) 331 -7766 Products include the PROMPRO-XP, PROMPRO-8X, and ALLPRO EPROM programmers. All programmers require the PM77 Adapter.

~ H

Topics covered in this section include: Section Page 12-1

Customer Information - Mask ROM Prototype and Production Flow the TMS7000 family of masked-ROM microcomputers are semi-custom de­ vices. The ROM is tailored to the customer's application requirements. The semi-custom nature of these devices requires a standard, defined interface between the customer and the factory in the production of TMS7000 devices with on-chip ROM. Figure 12-1 shows this standard prototype/production flow for customer ROM receipt. Figure 12-1. Prototype and Production Flow 1) Customer Required Information For TI to accept the receipt of a customer ROM algorithm, each of the following three items must be received by the TI factory:

Customer Information - Mask ROM Prototype and Production Flow The customer completes and submits a New Code Release Form (NCRF - available from TI Field Sales Office) describing the cus­ tom features of the device (e.g., customer information, prototype and production quantities and dates, any exceptions to standard electrical specifications, customer part numbers and symbolization, package type, etc.). If non-standard specifications are requested on the NCRF then the customer submits a copy of the specification for the microcom­ puter in their system, including the functional description and electrical specification (including absolute maximum ratings, re­ commended operating conditions, and timing values). When the customer has completed code development and after verification of this code with the development system, the standard TMS7000 tagged object code is submitted to the TI factory on an acceptable media for processing. These include:

• EPROM devices (currently supported: T12516, I N2716, TMS2732, TMS2764, and TMS27128)
• MS-DOS formatted disk compatible with IBM or TI PC
• Electronic ROM transfer: PC to PC via Xmodem, Ymodem, Zmodem or Microstufs Crosstalk protocol
• Bulk Data Transfer from a Texas Instruments Regional Tech­ nology Center (RTC) to the TI Stafford Building II facility to . the DX990. The completed NCRF, customer specification (if required). and ROM code should be given to the Field Sales Office or sent to: Texas Instruments Microcomputer Division P.O. Box 1443, MS 735 Houston, TX 77001 ATTN: TMS7000 Marketing Manager - ROM Receipt 2) TI Performs ROM Receipt Code review and ROM receipt is performed on the customer's code and a unique manufacturing ROM code number (such as C13827N) is as­ sighed to the customer's algorithm. All future correspondence should indicate this number. The ROM receipt procedure reads the ROM code information, processes it, reproduces the customer's ROM object code on the same media on which it was received, and returns the processed and the original code to the customer for verification of correct ROM receipt. 3) Customer ROM Receipt Approval The customer then verifies that the ROM code received and processed by TI is correct and that no information was misinterpreted in the trans­ fer. The customer must then return written confirmation of correct ROM receipt verification or re-submit the code for processing. This written confirmation of verification constitutes the contractual agreement for creation of the custom mask and manufacture of ROM verification pro­ totype units. 12-3

Customer Information - Mask ROM Prototype and Production Flow 4) TI Orders Masks, Manufacturing, and Ships 25 Prototypes TI generates the prototype photomasks, processes, manufactures, and tests 25 microcomputer prototypes containing the customer's ROM pattern for shipment to the customer for ROM code verification. These microcomputer devices have been made using the custom mask but are for the purposes of ROM verification only. For expediency, the proto­ type devices are tested only at room temperature (25°C). Texas In­ struments recommends that prototype devices not be used in production systems. Prototype devices are symbolized with a P pre­ ceding the manufacturing ROM code number (eg., PC13827N) to dif­ ferentiate them from production devices. 5) Customer Prototype Approval The customer verifies the operation of these prototypes in the system and responds with written customer prototype approval or disapproval. This written customer prototype approval constitutes the contractual agreement to initiate volume microcomputer production using the veri­ fied prototype ROM code. 6) Customer Release to Production With customer algorithm approval, the ROM code is released to pro­ duction and TI will begin shipment of production devices according to customer's final specification and order requirements. Two lead times are quoted in reference to the preceding flow:

• Prototype lead time - elapsed time from the receipt of written ROM re­ ceipt verification to the delivery of 25 prototype devices.
• Production lead time - elapsed time from the receipt of written customer prototype approval to delivery of production devices. For the latest TMS7000 family lead times, contact the nearest TI field sales office.

12.1.1 Reserved ROM Locations

All TMS7000 family devices with on-chip mask ROM reserve the first six bytes of the ROM space for TI use and therefore should not be used in the cus­ tomer's software algorithm. For applications targeted for on-chip mask ROM production, the customer must remember to reserve this space during the de­ velopment stage when using the XDS emulator, the EVM board, the SE77C42, the TMS7742, piggyback emulators (SE70P162, SE70CP160, SE70CP162), or a TMS7000 family member without on-chip ROM. Table 12-1 lists the valid ROM starting addresses for the mask-ROM devices.

Customer Information - Mask ROM Prototype and Production Flow Table 12-1. Valid ROM Start Addresses MEMBER ROM VALID START SPACE ADDRESS TMS7020. 70C20. 70CT20 2K bytes >F806 TMS7040. TMS7042 TMS70C40. TMS70C42 4K bytes >FOO6 TMS70CT4O 12-5

Customer Information - Mask ROM Prototype and Production Flow

12.1.2 Manufacturing Mask Options

The TMS7000 family supports two mask-programmed options, the oscillator input option (CMOS only) and the clock divide-by option (TMS7020 and TMS7040 only). These options areselected at the time of mask manufacture and therefore cannot be changed by software or hardware once the device has been manufactured. Selection· of these mask options are designated by the customer in the New Code Release Form (NCRF) when ordering TMS7000 family members win on-chip mask ROM. TMS7000 family members without on-chip mask ROM have this designation as part of their standar<;l part number symbolization. The oscillator input options OSC-ON and OSC-OFF define how the TMS7000 internal oscillator driver circuits operate. Both NMOS and CMOS devices may have a crystal, ceramic resonator, R-C circuit, or another approximately 50% duty cycle external clock as their external clock source. The crystal input op­ tion, OSC-ON, allows the external clock source to oscillate continously in all operational modes. The oscillator input option, OSC-OFF, is available for CMOS devices only. It causes the external clock source to be effectively dis­ abled from driving the onboard oscillator of the CMOS device when the HALT low-power mode is entered. The OSC-OFF option significantly reduces the low-power current requirements for all CMOS devices. The R-C option is supported only on the CMOS devices. (TMS70COO, TMS70C20, TMS70CT20, TMS70C40, TMS70CT40, TMS70C02, and TMS70C42). All NMOS processors have the crystal option defined as the only form of oscillator option. The clock divide-by option defines the internal oscillator divide-by for con­ verting the external oscillator frequency, fosc' to the internal machine cycle frequency. The +2 clock option defines that the internal machine cycle will be external oscillator frequency divided by two (for example, an 5 MHz ex­ ternal crystal would generate an internal machine cycle of 2.5 MHz). The +4 clock option defines that the internal machine cycle frequency will be the ex­ ternal oscillator frequency divided by four (for example, a 10 MHz external crystal would generate an internal machine frequency of 2.5 MHz). Table 12-2 defines the clock divide-by option supported by each family member. Table 12-2. Clock Divide Options CLOCK FAMILY MEMBERS DIVIDE-BY +2 NMOS TMS7000, TMS7020, TMS7040, TMS7002, TMS7042, TMS7742, SE70P162 CMOS TMS70COO, TMS70C20, TMS70CT20, TMS70C40, TMS70CT40, TMS70C02, TMS70C42, SE70CP160,SE70CP162,SE77C42 +4 NMOS TMS7000, TMS7020, TMS7040

Customer Information - Mechanical Package Information

12.2 Mechanical Package Information

The TMS7000 microcomputer family devices are packaged in four package types according to the type of material and outline used for the package: plastic dual-inline package (DIP), plastic leaded chip carrier (PLCC), ceramic sidebraze package, and ceramic sidebraze piggyback package. Package types are designated in the device symbolization by the suffix on the customer's ROM code number for devices manufactured with customer ROM code (eg., C12799N) and by the suffix of the standard device number for devices with­ out on-chip ROM. Table 12-3 indicates the package type, suffix indicator, and family members supported on that package type. Table 12-3. Package Types PACKAGE TYPE SUFFIX FAMILY MEMBERS INDICATOR 28-pin DIP N2 CMOS TMS70CT20, TMS70CT40 (70-mil pin spacing) 40-pin plastic DIP N NMOS TMS7000. TMS7020, TMS7040 (100-mil pin spacing) TMS7002. TMS7042 CMOS TMS70COO. TMS70C20, TMS70C40 TMS70C02, TMS70C42 40-pin ceramic sidebraze JD NMOS TMS7742 (100-mil pin spacing) JD CMOS TMS77C82 40-pin ceramic piggyback JD NMOS SE70P162 (100-mil pin spacing) JD CMOS SE70CP160,SE70CP162 44-pin PLCC FN CMOS TMS70COO. TMS70C20, TMS70C40 (50-mil pin spacing) TMS70C02, TMS70C42 12-7

Customer Information - Mechanical Package Information 28-pin N2 plastic package INDEX 0.51 10.0201 L 5.08 (0.200) MAX ISee Notes 8 and CI ISee Notes Band CI ISee Note A) r--O. 78 10.030) 1.27 (0.050) 4 PLACES ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICAllY IN JNCHES NOTES: A. Each pin centerline is located within 0.25 LO.010I of its true longitudinal position. B. This dimension does not apply for solder-dipped leads. C. When solder-dipped leads are specified, dipped &lea of the lead ell tends f,om the lead tip to at least 0,51 (0.0201 above seating plane. Figure 12-2. 28-Pin Plastic Package. 70-MIL Pin Spacing (Type N2 Package Suffix) 12-8

"" ~ o 1,27' 0,13 10.0500:0.005) I 12.065 15.24 ~ 0,25) [§l [0] [§l [§l t'l t'l t'l [§l [§l ~1 ~ t'l ~T' 1.524:tO.051 DI. 1 r to.060tO.002J 4.3180:0.254 (0.110±0.010) Innnnnnnnnnnnnnnnnnnni 1I U lIli1JlI ~ 1I11]1 YlililIlI·lIl1l1 ~ l ~ ~1.016"!O.127 PIN SPACING 0457'0051 1,270 ISee Note a) NOM ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES. NOTE A: Each pin centerline is located within 0,254 (O.010) of Its true longitudinal position. Figure 12-5. 40-Pin Ceramic Piggyback Package, 100-MIL Pin Spacing (Type JD Package Suffix) (") I/) rot o CD ..., III rot ::l CD (') III ::l (') III III (') III IC CD III rot o ::l

Customer Information - Mechanical Package Information EITHER INDEX A 0.02010 •• IIMINL~:r.,MAX ~O:oo -SEATING PlANE-r ~ ~ to.,o}},., MIN 10,457 ± 0,0761 0.05011,271 MAX PIN SPACING 0.07011.781 T.P. (5 •• Note bl NOTES: B. All linear dimensions are in inches and parenthetically in millimeters. Inch dimensions govern. b. Each pin centerlina is located within 0.010 (0,26) of its true longitudinal position. Figure 12-6. 40-Pin N2 Plastic Package. 0,070 "Pin Center Spacing. 0.600" Pin Row Spacing 12-11

Customer Information-Mechanical Package Information v 0

• 3 2 1 2. 27 2. 25 19 ~ 12 13 IS I. 17 ,. I B .~f" 0,25 (0.0101 R MAX (SH Not. AI A 3 PLACES I SEATING PLANE (5 •• Note CI NO. OF TERMINALS MIN A B MAX MIN C MAX MIN MAX 0,81 (0.0321 ~ 0,66 (0.0261 g,r 1,52 (0.0601 MIN l....l I ~64 (0.0251 MIN l...i LEAD DETAIL ALL LINEAR DIMENSIONS ARE IN MILLIMETERS ANO PARENTHETICALLY IN INCHES NOTES:A. Centerline of center pin each side IS within 0.10 10.004) of package centerline as determmed by dimenSion B. B. location of each pin is within 0,127 10..005) of true pOSition with respect to center pin on each side. C. The lead contact points are planar within 0,10 (0.0041. Figure 12-7. 44-Pin Plastic-Leaded Chip Carrier FN Package 12-12

Customer Information - Numbering and Symbol Conventions

12.3.1 Device Prefix Designators

To provide expeditious system evaluations by customers during the product development cycle, Texas Instruments assigns a prefix designator wrth four options: TMS, TMP, TMX, and SE. TMX, TMP, and TMS are representative of the evolutionary stages of product development from engineering prototypes through fully qualified production devices. FiQure 12-8 depicts this evolutionary development flowchart. Pro­ duction devices shipped by Texas Instruments have the TMS designator sig­ nifying that they have demonstrated the high standards of Texas Instruments quality and reliability. I TM7m I o I TMSxxxx I Experimental devices that are not represent­ ative of the final device's electrical speci­ fications and has not completed reliability verification. Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliablity verification. Fully qualified production devices. Figure 12-8. Development Flowchart TMX devices are shipped against the following disclaimer: _ 1 ~ Experimental product and its reliability has not been characterized. Product is sold "as is". Product is not warranted to be exemplary of final production version if or when released by Texas Instruments. TMP devices are shipped against the following disclaimer: 1 ) Customer understands that the product purchased hereunder has not been fully characterized and the expectation of reliability cannot be de­ fined; therefore, Texas Instruments standard warranty refers only to the device's specifications. No warranty of merchantability or fitness is expressed or implied. TMS devices have been fully characterized and the quality and reliability of the device has been fully demonstrated. Texas Instruments' standard warranty applies .. The SE prefix designation is given to the system evaluator devices used for prototypmgpurposes. This designation applies only to the prototype members of the TMS7000 family (the NMOS SE70P162 and the CMOS SE70CP160, SE70CP162, and SE77C42 devices.) SE devices are shipped against the fol­ lowing disclaimer: System evaluators and development tools are for use only in a proto­ type environment and their reliability has not been characterized. 12-13

Customer Information - Numbering and Symbol Conventions

12.3.2 Device Numbering Convention

Figure 12-9 illustrates the numbering and symbol nomenclature for the TMS7000 family . ,.----ROM TYPE: 0 -ROM/ROMLESS 7· EPROM TECHNOLOGY: BLANK· NMOS C • CMOS P • NMOS PIGGYBACK CP • CMOS PIGGYBACK CT • CMOS 28 PIN DIP r ROM ON CHIP: 0 • ROMLESS l· lK 4·4K TMS70C20NL L TEMPERATURE RANGE: H • ooc TO 55°C L· ooc TO 70°C A· -40°C TO +85°C PACKAGE TYPE: N • PLASTIC JD • CERAMIC. SIDE·BRAZED FN • PLASTIC·LEADED CHIP CARRIER Nl . 28 PIN. 70·MIL DIP N2 • 40 PIN. 70·MIL DIP '----ADDED FUNCTIONS: 0 • STANDARD 1 • SERIAL PORT. 128·BYTE RAM 2· SERIAL PORT. l56·BYTE RAM Figure 12-9. TMS7000 Family Nomenclature - 12.3.3 Device Symbols The TMS7000 family members can be divided into two categories for de­ scription of symbols. with the distinction being made on the presence (or ab­ sence) of on-chip ROM.

12.3.3.1 TMS7000 Family Members with On-Chip ROM

TMS7000 family members with on-chip ROM are semicustom devices ,where the ROM is mask programmed according to the customer's requirements. These devices follow the prototyping and production flow outlined in Section 12.3. Since they are semicustom devices, they receive a unique identification. There are two types of symbolization for TMS7000 family members with on­ chip ROM: 1) TI standard symbolization and 2) TI standard symbolization with customer part number.

Customer Information - Numbering and Symbol Conventions llNE1: (a). lINE 2: (d)0198111 LINE 3: (e) 24855 (b)C12345N (e) DBUA8327 (00198311 (g)PHH..UPINES KEY: (a)TEXAS INSTRUMENTS TRADEMARK (b)CUSTOMER'S ROM CODE I: PACKAGE 'T'tPE (e )TRACI<ING MARK I: DATE CODE (d)TI MICROCODE COPYRIGHT (e)lOT CODE LINE 1: (a)." LINE 2: LINE 3: (e) 0198111 lINE ... (gI24855 (f)COPYRIGHT OF ROM CODE (g)A8SEMBL Y SITE Figure 12-10. TI Standard Symbolization KEY: (b) 1234567811012 ! a) TEXAS INSTRUMENTS TRADEMARK b) CUSTOMER PART NUMBER (e)C12345N (d) DBUA8327 (c) CUSTOMER'S ROM CODE I: PACKAGE 'T'tPE (d) TRACKING MARK I: DATE CODE (f)0198311 (a)TI MICROCODE COPYRIGHT ( f ) COPYRIGHT OF ROM CODE (h) PHILLIPINES (g) lOT CODE (h) A8SEMBl. Y SITE Figure 12-11. TI Standard Symbolization with Customer Part Number

12.3.3.2 TMS7000 Family Members without On-Chip ROM

TMS7000 family members without on-chip ROM are standard device types, and therefore have a standard identification. Examples of TMS7000 family members without on-chip ROM include: TMS7000NL-2 TMS7000NL-4 LINE 1: (al. liNE 2: (d)0198111 LINE 3: (e) 24655 (blTM87OC02NA (e)DBUA8827 ( f ) PHlLLIPINES KEY: TMS7002NL TMS70C02NA (a) TEXAS INSTRUMENTS TRADEMARK (b) STANDARD DEVICE NUMBER (0) TRACKING MARK I: DATE CODE (d) TI MICROCODE COPYRIGHT (e) lOT CODE (f) A8SEMBl. Y SITE Figure 12-12. TI Standard Symbolization for Devices without On-Chip ROM 12-15

Customer Information - Development Support Tools XDS Upgrade Kit: XDS MODEL # Model 22 OPERATING SYSTEM PC/MS-OOS OX10 OX10 OX10 OX10 VMS MVS CMS MEDIUM 5 1/4" floppy T50 hard disk

1600 BPI mag tape

(Emulator board upgrade from TMOS706221 0 to TMOS7062230) PART NUMBER TMOS7082230 _ 12.4.3 TMS7000 Evaluation Modules 12-16 PART NUMBER RTC/EVM7000N-l RTC/EVM7000C-l DEVICES SUPPORTED TMS7020. TMS7040. TMS7042 TMS70C20. TMS70C40. TMS70CT20 TMS70CT40. TMS70C42

TMS7000 Bus Activity Tables

TMS7000 Bus Activity Tables This section describes the internal and external bus activity during each in­ struction execution and hardware operation (for example, interrupts). The external bus activity is the information seen on the expansion bus. The in­ ternal bus refers to the address and data buses that are part of the TMS7000 internal architecture. The information on the address and data buses, as well as the control pins, can be monitored externally when the device operates in any mode but Single-Chip. The internal and external buses' activity is docu­ mented on a cycle-by-cycle basis. The information in this section is useful to:

• Understand the external expansion bus for the purpose of designing an interface
• Calculate instruction execution times
• Gain a better understanding of microcomputer operation The information on the bus activity tables is the same for NMOS and CMOS devices except for the IDLE instruction. This difference is noted in Table A-S. Topics covered in this appendix include: Section Page Table A-1 contains an alphabetical listing of the TMS7000 instructions and indexes into the appropriate bus activity tables. A-1

Appendix A - TMS7000 Bus Activity Tables A.1 TMS7000 Operating Modes. The TMS7000 is a microcoded microcomputer with four operating modes:

• In the Single-Chip mode, there are four 8-bit I/O ports (Ports A, B, C, and D) that provide 32 general purpose I/O lines.
• In Peripheral-Expansion mode, one 8-bit port (Port C) becomes a multiplexed address and data bus and four output lines (the four most significant bits of Port B) become the bus control signals. This is called the external expansion bus. The 8-bit address/data bus allows the. TMS7000 to access up to 256 bytes of externally memory-mapped pe­ ripherals (excluding the dedicated on-chip Peripheral-File locations).
• Full-Expansion mode is similar to Peripheral-Expansion mode, except that another Port D becomes the MSB of a 16-bit address (Port C sup­ plies the LSB). This means that the TMS7000 can access up to 64K bytes externally minus the number of bytes of on-chip ROM.
• Microprocessor mode is the same as Full-Expansion mode, except that the on-chip ROM' (if any) is ignored and the entire 64K bytes are mapped off chip. A.2 TMS7000 Addressing Modes A-2 Because the TMS7000 implements a microcoded architecture, the microcode that fetches the instructions and their operands can be shared by many in­ structions. The instruction can be grouped according to the types of operands the instructions require and how the instructions are fetched. Each instruction group is based on one of the addressing modes supported by the TMS7000:
• Double Operand Functions (DOPFUN) ADD, ADC, AND, BTJO, BTJZ, CMP, DAC, DSB, MOV, MPY, OR, SBB, SUB, XOR These instructions require two operands for execution.
• Miscellaneous Functions (MISCFUN) DINT, EINT, IDLE, LDSP, NOP, POP ST, PUSH ST, RETI, RETS, SETC, STSP These instructions need no operands because the instruction function is implied in the opcode.
• . Long Addressing Functions (LAFUN) BR, CALL, CMPA, LDA, STA These instructions require a 16-bit address which is used to address the entire 64K-byte address range of the TMS7000.

Appendix A - TMS7000 Bus Activity Tables

• Single Operand Functions - Special (SOPFUNS) CLR, DEC, INC, INV, MOV A B, MOV A RN, MOV B RN, SWAP, TSTA/CLRC, TSTB,XCHB These instructions need one operand for execution.
• Single Operand Functions - Normal (SOPFUNN) DECD,DJNZ, POP,PUSH,RL,RLC, RR,RRC These instructions need one operand for execution. Two groups of sin­ 'gle operand instructions are needed because of the way CPU control is implemented and the number of supported single operand instructions.
• Double Operand Functions - Peripheral (DOPFUNP) ANDP, BTJOP, BTJZP, MOVP, ORP, and XORP. These instructions require two operands and interact with the TMS7000 peripheral file registers.
• Move Double (MOVD) MOVD Moves a register pair to a register pair and is the only instruction in this group.
• Relative Jumps (RJMP) JMP, IN/JLT, JZ/JEQ, JC/JHS, JP/JGT, JPZ/JGE, JNZ/JNE, JNC, JL These conditional and unconditional jumps alter program flow by adding or subtracting an 8-bit value with the program counter. Traps (TRAP) Trap 0 through Trap 23. These instructions are used to perform subroutine calls. A-3

Appendix A - TMS7000 Bus Activity Tables A.3 Instruction Execution A-4 There are three phases of i'nstruction execution: 1) Opcode fetch (instruction acquisition mode) 2) Operand addressing (addressing mode) 3) Functional operation on the operands (functional mode) The Bus Activity Tables, which list the number of cycles executed in each phase, are grouped according to these three phases:

• The instruction acquisition sequence is common to all instructions, so they are presented separately: . Table A-2 A-3 A-4 Page
• To determine the number of addressing mode and functional mode cycles, locate the instruction's functional group (Table A-1) and refer­ ence the appropriate table. Table A-1 lists the TMS7000 instructions in alphabetical order with the corresponding addressing mode. Table A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 Page Double Operand Functions, Peripheral - Addressing Modes .. A-21 Double Operand Functions, Peripheral - Functional Modes ... A-22 Add all these cycles together to olltain the bus activity present during that in­ struction's execution. Each table indicates whether a read or a write is performed during that cycle. The R/iN signal is high for reads and low (logic zero) for writes. The memory control signals, ALATCH and ENABLE, are asserted during both reads and writes. Note that the ENABLE signal is asserted only during external reads and writes. . Accesses other than internal RAM are long memory cycle (two-cycle) ac­ cesses. The timing of these accesses for NMOS and CMOS devices is speci­ fied in the Memory Interface Timing specifications in Section 4. These long memory cycle accesses have been indicated by their grouping within the ta-

Appendix A - TMS7000 Bus Activity Tables bles (two-cycle accesses are not separated by a horizontal line). For these cycle pairs, the first cycle uses the C and D ports for the address bus (C only for Peripheral-Expansion mode). In the second cycle, Port C becomes a data bus. Figure A-1 illustrates the read/write information. This timing diagram is the same for NMOS and CMOS devices, but the interface timing specifications are different. Although short memory cycles (RAM cycles) influence the external bus ac­ tivity, no valid information is seen and the timing cannot be specified. The following terms are used throughout this appendix: LSB MSB Rs Rd least significant byte of a 16-bit value most significant byte of a 16-bit value (Rn source) the first operand listed (Rn destination) the second operand listed. The resulting value is stored at the Rd address. A-5

Appendix A - TMS7000 Bus Activity Tables CLKOUT (B7) ALATCH (84) HI AOOR (00-07) LO ADDR (CO-C7) ENABLE (B6) RO/WR (B5) EXTERNAL WAllE RAM READ i 1l'-td(CH-EL) : I~ ~I d(CH-JL) : INTERNAL READ . -ntW(JH) I I ~ \\1 in in : ~td(AH-JL) : I I : '---- : I I i!t _th(EH-AH) I Figure A-1. Read and Write Timing Diagram A.3.1 An Example Using the Bus Activity Tables A-6 Example A-1 illustrates the execution steps produced by the instruction ADD R5, R6. To construct the cycles required to execute the instruction, begin with the opcode fetch as shown in Example A-1. These three cycles: 1) Fetch the instruction opcode, 2) Increment the program counter, and 3) Prefetch register B.

Appendix A - TMS7000 Bus Activity Tables Example A-1. Execution Steps for ADD (Instruction Acquisition) ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS R/W All Instructions 1 Opcode address Irrelevant data R

2 Opcode address Instruction opcode R

3 Register B address Register B contents R

t t The first two cycles fetch the ADD instruction's opcode and increment the program counter. The third state prefetches register B to speed up instructions that reference register B. Note: This information is from Table A-2. Example A-2. Execution Steps for ADD (Addressing Modes) ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS R/W Rn, Rn 1 Opcode address + 1 Irrelevant data R

2 Opcode address + 1 Rs address R

3 Rs address Rs data R

4 Opcode address + 2 Irrelevant data R

5 Opcode address + 2 Rd address R

6 Rd address Operand data R

Note: The addressing mode is entered next and is found in Table A-5. The ADD instruction is a double operand function, requiring two operands. Double operand functions are described in Table A-5 and Table A-6. Cycles 1 and 2 of this mode read the R5 operand address. Cycle 3 reads the register contents. Note: The internal register read (or write) is a one cycle operation. All other reads/writes are two cycles long, requiring that the address bus be held stable for two complete machine cycles. Each machine cycle corresponds to one clock period of the CLKOUT signal (pin 2), starting with the rising edge of this signal. Cycles 4 and 5 read the Rd address, (R6) where the resultant value is placed. Cycle 6 reads the con­ tents of register R6. Now, both operands are inside the CPU and the indicated function can be performed as shown Example A-3 for functional modes (ex­ cerpted from Table A-6). Example A-3. Execution Steps for ADD (Functional Modes) INSTRUCTION ADDRESS BUS DATA BUS ADD Register address Register data A-7

Appendix A - TMS7000 Bus Activity Tables A-8 Once both operands are inside the CPU, only one cycle is needed to perform the add operation. The result is written back to register R6 during this cycle. A total of 10 cycles is required to perform an ADD RS, R6.

Appendix A - TMS7000 Bus Activity Tables Table A-1. Alphabetical Index of Instruction Groups INSTRUCTION ADDRESS TABLE FUNCTION MODE NUMBER ADC DOPFUN Table A-5 Add with carry ADD DOPFUN Table A-5 Add AND DOPFUN Table A-5 And ANDP DOPFUNP Table A-15 And value with peripheral port BTJO DOPFUN Table A-5 Test bit and jump if one BTJOP DOPFUNP Table A-15 Test peripheral bit and jump if one BTJZ DOPFUN Table A-5 Test bit and jump if zero BTJZP DOPFUNP Table A-15 Test peripheral bit and jump if zero BR LAFUN Table A-9 Long branch CALL LAFUN Table A-9 Subroutine call CLR SOPFUNS Table A-11 Clear CLRC SOPFUNS TableA-11 Clear status carry bit CMP DOPFUN Table A-5 Compare value CMPA LAFUN Table A-9 Compare value with Register A DAC DOPFUN Table A-5 Decimal add with carry DEC SOPFUNS Table A-11 Decrement value DECD SOPFUNN Table A-13 Decrement double register pair DINT MISCFUN Table A-7 Disable interrupts DJNZ SOPFUNN Table A-13 Decrement and jump if not zero DSB DOPFUN Table A-5 Decimal subtract EINT MISCFUN Table A-7 Enable interrupts IDLE MISCFUN Table A-7 Idle (PC is held unchanged) INC SOPFUNS TableA-11 Increment INV SOPFUNS Table A-11 Invert JMP REL JUMPS Table A-19 Unconditional relative jump -J<cnd> REL JUMPS Table A-19 Conditional relative jumps (IN/JLT. JZ/JEQ. JL. JC/JHS. JP/JGT. JPZ/JGE. JNZ/JNE. JNC) LDA LAFUN Table A-9 Load Register A from long address LDSP MICSFUN Table A-7 Load Stack Pointer MOV DOFUN Table A-5 Move a data value MOV SOPFUNS Table A-11 Move with implied operand MOVD MOVD Table A-17 Move a 16-bit value to register pair MOVP DOPFUNP Table A-15 Move a data value to/from port MPY DOPFUN Table A-5 Multiply two 8-bit values NOP MISCFUN Table A-7 No operation A-9

Appendix A - TMS7000 Bus Activity Tables Table A-1. Alphabetical Index of Instruction Groups (Concluded) INSTRUCTION ADDRESS TABLE FUNCTION MODE NUMBER OR DOPFUN Table A-5 OR two values together ORP DOPFUNP TableA-15 OR port value with another value POP SOPFUNN Table A-13 POP a value off the stack POPST MISCFUN Table A-7 POP stack value into Status Register PUSH SOPFUNN TableA-13 PUSH a value onto the stack PUSHST MISCFUN Table A-7 PUSH Status Register onto stack RETI MISCFUN Table A-7 Return from interrupt RETS MISCFUN Table A-7 Return from subroutine RL SOPFUNN Table A-13 Rotate left RLC SOPFUNN Table A-13 Rotate left through carry bit RR SOPFUNN Table A-13 Rotate right RRC SOPFUNN Table A-13 Rotate right through carry bit SBB DOPFUN Table A-5 Subtract with borrow SETC MISCFUN Table A-7 Set carry bit STA LAFUN Table A-9 Store Register A to long address STSP MISCFUN Table A-7 Store Stack Pointer to Register B SUB DOPFUN Table A-5 Subtract SWAP SOPFUNS Table A-11 Swap nibbles of an 8-bit value TSTA SOPFUNS Table A-11 Test Register A and set status TSTB SOPFUNS Table A-11 Test Register B and set status TRAP n TRAP Table A-20 Trap to subroutine XCHB SOPFUNS Table A-11 Exchange value with Register B XOR DOPFUN Table A-5 Exclusive OR XORP DOPFUNP Table A-15 Exclusive OR with peripheral port Table A-2. Instruction Acquisition Mode - Opcode Fetch ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS R/W All Instructions 1t Opcode address

2 Opcode address

3~ Register B address t Go to Interrupt code listed for cycle 3 If an Interrupt IS pending. ~ Go to addressing modes (Table A-5 through Table A-20). Irrelevant data Instruction opcode Register B contents Notes: 1. This mode is executed for all instructions to fetch the instruction's opcode. R R R 2. Register B is prefetched to speed up the.execution of instructions that reference register B. A-10 3. The Program Counter is incremented during cycles 1 and 2 of this mode. 4. An interrupt check is performed during cycle 2. If an interrupt is detected, cycle 3 is not executed. Control is passed immediately to the interrupt handling code shown next.

Appendix A - TMS7000 Bus Activity T~bles Table A-3. Instruction Acquisition Mode - Interrupt Handling FUNCTION CYCLE ADDRESS BUS DATA BUS R/W Interrupts 1t Irrelevant data Irrelevant data -

2 Irrelevant data Irrelevant data -

3 Irrelevant data Irrelevant data -

4 Irrelevant data Irrelevant data -

5 SP register Status register W

6 Irrelevant data Irrelevant data -

(Reset entry) 7 Irrelevant data Irrelevant data -

8 Irrelevant data Irrelevant data -

9 Address> FFOO + vector Irrelevant data R

10 Address >FFOO + vector lSB INT vector R

11 Address> FFOO + vector Irrevelent data R

12 Address> FFOO + vector MSB INT vector R

13 SP contents PCH contents W

14 Irrelevant data Irrelevant data -

15 S P + 1 contents PCl contents W

I

16 Irrelevant data Irrelevant data -

17 Irrelevant data Irrelevant data -

t Jump to cycle number 5 If opcode was IDLE (>01). If It was an IDLE instruction, do not decrement PC because desired return is past the IDLE instruction. Notes: 1. The Program Counter is decremented during cycles number 3 and 4. This is done because the instruction that the PC had pointed at has not been executed. 2. The Status Register is saved on the stack during Cycle 5. The Program Counter is saved during cycles 13 and 15. 3. The vector is selected by hardware depending upon which interrupt was asserted. Table A-4. Instruction Acquisition Mode - Reset FUNCTION CYCLE ADDRESS BUS DATA BUS R/W Reset 1 Irrelevant data Irrelevant data R

2 Irrelevant data Zeroes -

3t Address >0100 Zeroes W

4 Address >0100 Zeroes W

t Jump to Interrupt cycle 7 (see Reset Entry). Notes: 1. A read operation is done the first cycle even though the address and data buses contain ir- relevant data. This read is done to protect memory in case a long write was in progress when the Reset action occurred. 2. The write to address >0100 is done to disable all interrupts. 3. The Stack Pointer is initialized to >01. 4. The Program Counter is stored in the register pairs A and B. 5. The RESET function is initiated when the RESET line of the TMS7000 device is held at a logic zero level for at least five clock cycles. When an active signal is detected on RESET, the sequence shown above is entered immediately after the current machine cycle is done. A-ll

Appendix A - TMS7000 Bus Activity Tables Table A-5. Double Operand Functions - Addressing Modes (ADD,ADC,AN D,BT JO, BT JZ,CM P,DAC,DSB,M OV,M f'V,OR,SB B,SU B,XOR) FUNCTIONt CYCLE ADDRESS BUS DATA BUS R/W Rn, A 1 Opcode address + 1 Irrelevant data R

2 Opcode address + 1 Rn address R

3 Rn address Rn data R

4 Register A address Register A data R

%n, A 1 Opcode address + 1 Irrelevant data R

2 Opcode address + 1 Immediate value (%n) R

3 Register A address Register A data R

Rn, B 1 Opcode address + 1 Irrelevant data R

4 Register B address Operand data R

Rn, Rn 1 Opcode address + 1 Irrelevant data R

6 Rd address Rd data R

%n, B 1 Opcode address + 1 Irrelevant data R

2 Opcode address + 1 Immediate data R

3 Register B address Register B data R

B,A 1 Register A address Register A data R %n, Rn 1 Opcode address + 1 Irrelevant data R

3 Opcode address + 2 Irrelevant data R

4 Opcode address + 2 Rn address R

_ t See functional modes in Table A-6. Rn address Rn data R A-12

Appendix A - TMS7000 Bus Activity Tables Table A-6. Double Operand Functions - Functional Modes INSTRUCTIONSt CYCLE ADDRESS BUS DATA BUS RjW MOV 1 Register address Register data W AND 1 Register address Register data W OR 1 Register address Register data W XOR 1 Register address Register data W ADD 1 Register address Register data W ADC 1 Register address Register data W SUB 1 Register address Register data W SBB 1 Register address Register data W CMP 1 Irrelevant data Irrelevant data - DAC 1 Register address Register data W

2 Register address Register data R

3 Register address Register data Vii

t DSB 1 Register address Register data W

3 Register address Register data W

MPY (Note 1) 1 Register B address Register B data W

4 Register B address Register B data R

5 Register B address Register B data W

9 iterations 6 Irrelevant data Irrelevant data -

7 Irrelevant data Irrelevant data -

8 Register A address MSB mult. product W

9 Irrelevant data Irrelevant data -

BTJO,BTJZ (Note 2) 1 Irrelevant data Irrelevant data -

2 Opcode address + 1 Irrelevant data R

3 Opcode address + 1 Jump PC offset R

4 Opcode address + 1 Jump PC offset R

5 Irrelevant data Irrelevant data -

t Jump to instruction acquisition sequence. Notes: 1. MPY- This microcode iterates to perform the multiply. The functional portion of the MPY instruction requires 40 states for execution. 2. BT JO, BT JOP - Not all states are executed. Either state 2 or state 3 is executed, but not both. The same applies to states 6 and 7. A-13

Appendix A - TMS7000 Bus Activity Tables Table A-7. Miscellaneous Functions - Addressing Modes ADDRESSING MODE ADDRESS BUS DATA BUS SP contents Stack value t See functional modes in Table A-B. Table A-B. Miscellaneous Functions - Functional Modes ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS R/W EINT 1 I rrelevant data Irrelevant data - DINT 1 Irrelevant data Irrelevant data - SETC 1 Irrelevant data Irrelevant data -t POP ST 1 SP contents Stack data R

2 Irrelevant data Irrelevant data -t

STSP 1 Irrelevant data Irrelevant data -

2 Register B address SP contents W

t RETS 1 Irrelevant data Irrelevant data -

3 Irrelevant data Irrelevant data -t

RETI 1 Irrelevant data I rrelevant data -

3 Irrelevant data I rrelevant data -

4 SP contents Register data R

5 Irrelevant data I rrelevant data -t

LDSP 1 Irrelevant data Irrelevant data -t PUSH ST 1 Irrelevant data I rrelevant data -

2 SP contents Status register W

t IDLE 1 Irrelevant data Irrelevant data - 2 Irrelevant data Irrelevant data -t . .. t Jump to instruction acquIsition sequence . Notes: 1. NOP does not have an execution state. From the addressing mode control is passed back A-14 to the instruction acquisition microcode. 2. The bus activity shown for the IDLE instruction corresponds to the NMOS parts only. For these parts, the microcode loops by jumping back to its own instruction acquisition. For the CMOS parts, an IDLE corresponds to a microcode halt. Because of this, it may take up to 6 cycles longer to interrupt out of an NMOS idle.

Appendix A - TMS7000 Bus Activity Tables Table A-9. Long Addressing Functions - Addressing Modes (BR.CALL.CMPA.LDA.STA) ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS @n 1 Opcode address + 1 Irrelevant data

2 Opcode address + 1 MSB of long address

3 Opcode address + 2 Irrelevant data

4 Opcode address + 2 LS B of long address

5 Irrelevant data Irrelevant data

t *Rn 1 Opcode address + 1 Irrelevant data

2 Opcode address + 1 Rn address

3 Rn address LSB of long address

4 Rn - 1 address MSB of long address

t @n(B) 1 Irrelevant data Irrelevant data

2 Opcode address + 1 Irrelevant data

3 Opcode address + 1 MSB of long address

4 Opcode address + 2 Irrelevant data

5 Opcode address + 2 LSB of long address

6 Irrelevant data Irrelevant data

7 Irrelevant data Irrelevant data

t t See functional modes In Table A-1 O. R/W R R R R R R R R R R R R A-15

Appendix A - TMS7000 Bus Activity Tables Table A-10. long Addressing Functions - Functional Modes (BR.CAll.CMPA.lDA.STA) ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS lOA 1 Operand address Irrelevant data 2 Operand address . Operand data t Register A address Operand data STA 1 Register A address Register Acontents

2 Operand address Register A contents

3 Operand address Register A contents

t BR 1 Irrelevant data Irrelevant data

2 Irrelevant data Irrelevant data

t CMPA 1 Operand address I rrelevant data

2 Operand address Operand data

3 Register A address Register A contents

4 Irrelevant data Irrelevant data

t CAll 1 Irrelevant data Irrelevant data

2 SP contents PCH contents

3 I rrelevant data Irrelevant data

4 SP + 1 PCl

5 I rrelevant data Irrelevant data

6 I rrelevant data Irrelevant data

t . .. t Jump to instruction acquIsition sequence . R/W R R W R W R R R W W Table A-11. Single Operand Functions. Special - Addressing Modes RN.SWAP.TSTA/ClRC.TSTB.XCHB) ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS R/W A 1 t Register A address Register A contents R B 1 Register B address Register B eontents R t Rn 1 Opcode address + 1 I rrelevant data R t t See functional modes In Table A-12. A-16

Appendix A - TMS7000 Bus Activity Tables Table A-12. Single Operand Functions. Special - Functional Modes RN.SWAP.TSTA/CLRC.TSTB.XCHB) ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS R/W DEC 1 Register address Register data INC 1 Register address Register data INV 1 Register address Register data CLR 1 Register address Register data t XCHB 1 Register B address Register data

2 Register address Register data

t SWAP 1 Irrelevant data Irrelevant data

3 Irrelevant data Irrelevant data

t Register address Register data MOVA.B 1 Register A address Register A data

2 Register B address Register A data

t MOV A,Rn 1 Register A address Register A data t Register address Register A data MOV B.Rn 1 t Register address Register B data TSTA/CLRC 1 Register A address Register A data t Register address Register data TSTB 1 t Register B address Register data t Jump to instruction acquisition sequence. Table A-13. Single Operand Functions. Normal - Addressing Modes W W W W W W W R W R W W R W W ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS R/W A 1 Register A address Register A data R t B 1 Register B address Register B data R t Rn 1 Opcode address + 1 Irrelevant data R t t See functional modes In Table A-14. A-17

Appendix A - TMS7000 Bus Activity Tables Table A-14. Single Operand Functions. Normal - Functional Modes INSTRUCTION CYCLE ADDRESS BUS PUSH 1 Irrelevant data

2 SP contents

t POP 1 SP contents t Register data RR 1 Register data RRC 1 Register data RL 1 Register data RLC 1 Register data t DECO 1 Register data

2 Irrelevant data

3 Irrelevant data

4 Register address

5 Register address

t DJNZ 1 Register address

2 Opcode address + 1

:t:

3 Opcode address + 1

t

4 Opcode address + 1

5 Irrelevant data

6 Irrelevant data

t

7 Irrelevant data

t . . t Jump to instruction acquIsition sequeoce . :j: If result is not = O. jump to state 4. § If jump PC offset is positive, jump to state 7. A-18 DATA BUS R/W Irrelevant data - Register data W Register data R Register data W Register data W Register data W Register data W Register data W Register data W Irrelevant data - I rrelevant data - Register data R Register data W Register data-1 W Irrelevant data R Jump PC offset R Jump PC offset R Irrelevant data - Irrelevant data - I rrelevant data -

Appendix A - TMS7000 Bus Activity Tables Table A-15. Double Operand Functions. Peripheral - Addressing Modes ADDRESSING MODE CYCLE ADDRESS BUS DATA BUS R/W A. Pn 1 Register A address Register A data

2 Opcode address + 1 I rrelevant data

3 Opcode address + 1 Pn address

4 Pn address Irrelevant data

5 Pn address Pn data

t B. Pn 1 Opcode address + 1 Irrelevant data

2 Opcode address + 1 Pn address

3 Pn address Irrelevant data

4 Pn address Pn data

t %n. Pn 1 Opcode address + 1 Irrelevant data

2 Opcode address + 1 %n -immediate data

4 Opcode address + 2 Pn address

5 Pn address Irrelevant data

6 Pn address Pn data

t Pn. A 1 Register A address Register A data t Pn. B 1 Opcode address + 1 Irrelevant data t t See functional modes in Table A-16. Notes: 1. Addressing modes" A. Pn" and "Pn. A" fetch their operands the same way. 2. Addressing modes "B. Pn" and "Pn. B" fetch their operands the same way. R R R R R R R R R R R R R R R R R R R R R R R R A-19

Appendix A - TMS7000 Bus Activity Tables Table A-16. Double Operand Functions, Peripheral - Functional Modes (ANDP,BTJOP,BTJZP,MOVP,ORP,XORP) INSTRUCTION CYCLE ADDRESS BUS MOVP X, Pn 1 Pn address

2 Pn address

t MOVP Pn, A 1 Register A address MOVP Pn, B 1 Register B address t ANDP 1 Pn address t ORP 1 Pn address t XORP 1 Pn address t BTJOP 1 Irrelevant data t t ~f. ~ 6 Irrelevant data t t BTJZP 1 Irrelevant data t t t . .. t Jump to instruction acquIsition sequence . t If bit tested is equal to a 1, jump to state 4. § If jump PC offset is positive, jump to state 7. ~ If bit tested is equal to a 0, jump to state 4. DATA BUS Peripheral register data Peripheral register data Register data Register data Peripheral register data Peripheral register data Peripheral register data Peripheral register data Peripheral register data Peripheral register data Irrelevant data Irrelevant data Jump PC offset Jump PC offset I rrelevant data Irrelevant data Irrelevant data Irrelevant data Irrelevant data Jump PC offset Jump PC offset Irrelevant data Irrelevant data Irrelevant data Notes: 1. MOVP X, Pn - X is either register A or B, or an a-bit immediate value %n. A-20 R/W W iN W W iN W iN W iN W R R R R R R

Appendix A - TMS7000 Bus Activity Tables Table A-17. Move Double - Addressing Mode (MOVD) INSTRUCTION CYCLE ADDRESS BUS DATA BUS R/W %n. Rn 1 Opcode address + 1 Irrelevant data R

2 Opcode address + 1 MSB of immediate data R

4 Opcode address + 2 LSB of immediate data R

t Rn. Rn 1 Opcode address + 1 Irrelevant data R

2 Opcode address + 1 Rn source address R

3 Rn source address Rn data - LSB R

4 Rn - 1 source addr. Rn - 1 data - MSB R t %n(B). Rn 1 Irrelevant data Irrelevant data -

3 Opcode address + 1 MSB of immediate data R

5 Opcode address + 2 LSB of immediate data R

7 I rrelevant data Irrelevant data -

t t See functional mode in Table A-18. Table A-18. Move Double - Functional Mode (MOVD) INSTRUCTION CYCLE ADDRESS BUS DATA BUS R/W MOVD 1 Irrelevant data Irrelevant data -

2 Opcode address + 2/3 Irrelevant data R

3 Opcode address + 2/3 Destination Rn address R

4 I rrelevant data Irrelevant data -

5 Dest. Rn address LSB register data iN 7 Dest. Rn -1 address MSB register data W t t Jump to instruction acquisition sequence. Notes: 1. MOVD - States 2 and 3 will be Opcode address + 2 for the "%n. Rn" and the "Rn. Rn" ad- dressing modes. States 2 and 3 will be Opcode address + 3 for the "%n(B). Rn n addressing mode. A-21

Appendix A - TMS7000 Bus Activity Tables TableA-19. Relative Jumps - Addressing and Functional Modes RELATIVE JUMPS CYCLE ADDRESS BUS

1 Opcode address + 1

t

4 Irrelevant data

t t . .. t Jump to instructIon acqUIsition sequence . ~ If jump condition is true. jump to state 3. § If jump offset is positive go to state 6. DATA BUS Irrelevant data Jump PC offset Jump PC offset Irrelevant data Irrelevant data Irrelevant data R/W R R R Notes: 1. Cycle 1 tests the jump condition. If the jump is true, go to state 3, else execute state 2 and return to the instruction acquisition sequence. 2. Cycle 4 tests whether the jump offset is positive or negative. If the jump offset is positive, go to state 6. Table A-20. Traps - Addressing and Functional Modes (Trap 0 through Trap 23) TRAPS CYCLE ADDRESS BUS DATA BUS R/W Trap 0-7 (Group A) 1 Irrelevant data Irrelevant data - Trap 8-15 (Group B) 1 Irrelevant data Irrelevant data - Trap 16-23 (Group C) 1 Irrelevant data Irrelevant data -

3 Address >FFOO+Opcode Irrelevant data R

4 Address >FFOO+Opcode LS B trap vector R

5 Address >FFOO+Opcode-1 Irrelevant data R

6 Address>FFOO+Opcode-1 MSB trap vector R

7 SP contents PCH contents W

9 SP + 1 contents PCl contents W

10 Irrelevant data Irrelevant data -

11 Irrelevant data Irrelevant data -

t . . t Jump to InstructIon acqUIsItIon sequence . A-22

TMS7000 NMOS to CMOS Conversion Guide

TMS7000 NMOS to CMOS Conversion Guide This Appendix provides information to help convert from a present TMS7000 NMOS design to a CMOS design. For additional information see the appro­ priate sections in this manual. The basic areas of concern when converting from the TMS7000 NMOS de­ vices to the TMS7000 CMOS devices fall into three categories; Software, Hardware, and Electrical Specifications. The following sections will outline the issues that need attention when converting from the NMOS to the CMOS devices. Device conversions covered in this appendix include:

• B.1 Converting from a TMS70xO device to a TMS70CxO device
• B.2 Converting from a TMS70x2 device to a TMS70Cx2 device 8-1

Appendix B - TMS7000 NMOS to CMOS Conversion Guide B.1 Converting from a TMS70xO Device to a TMS70.CxO Device The following areas require attention when converting from a TMS70xO de­ sign to a TMS70CxO design: B.1.1 Software The instruction set is identical between the TMS70xO NMOS devices and the TMS70CxO CMOS device. The only functional difference involves the IDLE instruction. The IDLE instruction has no effect on the NMOS devices other than holding the device in a steady state. When an IDLE instruction is executed on a TMS70CxO device, it will go into either the Wake-Up or HALT low power mode. The actual mode depends on what value is programmed into the IDLE bit (Bit 5) of the Timer 1 Control Register. (0 for Wake-Up, 1 for HALT). B.1.2 Hardware B-2 The on-chip hardware differences between the TMS70xO and the TMS70CxO devices are summarized below:

• RESET: On the TMS70xO NMOS devices, the output data bits of Ports A C, and D are set to ail 1 s after a RESET. On CMOS devices, only Port A's output data bits are set to all 1 's; Ports C and D output data bits are not altered during a RESET. This means that the output value of Ports C and D are not changed by a RESET. During initial Power-up, the user program should account for this on the TMS70CxO devices.
• INTERRUPTS: The external Interrupts (INT1 and INT3) of the TMS70xO devices are edge and level triggered. INT3 on the TMS70CxO devices is also edge and level triggered. INT1 on the TMS70CxO devices is edge triggered only. If your present application uses the level sensitive feature of INT1, ex­ ternal circuitry may be required to use the TMS70CxO device in a similar manner.

Appendix B - TMS7000 NMOS to CMOS Conversion Guide B.1.3 Electrical Specifications The Electrical Specification differences between the TMS70xO and TMS70CxO devices may be compared by referencing the Electrical Specifica­ tion sections for both device types located in Section 4 of this data manual. Some of the more common differences are listed below: Operating Ranges Vee: TMS70CxO: 2.5 V - 6.0 V TMS70xO: 4.5 V - 5.5 V Fosc (Vee = 5 V ± 10%): TMS70CxO: 5 MHz TMS70xO: 5 MHz (10 MHz /4 option) lee (Vee = 5 V, Fosc = 5 MHz) : TMS70CxO: 12 mA TMS70xO: 150 mA Input Levels: (Vee = 5 V) VIH: TMS70CxO = 3.5 V TMS70xO = 2.0 V VIL: TMS70CxO (Vee = 5 V) = 1.5 V TMS70xO (Vee = 5 V) = 0.8 V IOL: TMS70CxO (Vee = 5 V +/-10%) = 2.0 mA TMS70xO (Vee = 5 V +/-10%) = 3.2 mA B.2 Converting from a TMS70x2 Device to a TMS70Cx2 Device The following areas require attention when converting from a TMS70x2 de­ sign to a TMS70Cx2 design: B.2.1 Software The instruction set is identical between the TMS70x2 NMOS devices and the TMS70Cx2 CMOS device. The only functional difference involves the IDLE instruction. The IDLE instruction has no effect on the NMOS devices other than holding the device in a steady state. When an IDLE instruction is executed on a TMS70Cx2 device, the CMOS device will go into one of the Wake-Up or HALT low power modes. The actual mode depends on what values are pro­ grammed into the following control bits: Timer 1 Control Register 0 Timer 2 Control Register 0 Serial Control Register 0 - Bit 5 (T1 HALT) - Bit 5 (T2HAL T) - Bit 7 (SPH) B-3 III

Appendix B -TMS7000 NMOS to CMOS Conversion Guide B.2.2 Hardware 8-4 The on-chip hardware differences between the TMS70x2 and the TMS70Cx2 devices are summarized below: PERIPHERAL FilE: The Peripheral (Control) files differ greatly between the NMOS arid CMOS devices. Major differences include the locations of the SMODE, SCLTO, and SSTAT control registers along with the additional Timer and Interrupt control registers associated with the TMS70Cx2 devices. RESET: On the TMS70x2 NMOS devices, the output data bits of Ports A, C, and 0 are set to all 1 s after a RESET. On CMOS devices, only Port A's output data bits are set to all 1 's; Ports C and D output data bits are not altered during a RESET. This means that the output value of Ports C and D are not changed by a RESET. During initial Power-up, the user program should ac­ count for this on the TMS70Cx2 devices. I/O PINS: Port A pins 5 and 6 on the TMS70x2 are input only. These .same pins on the TMS70Cx2 devices are fully bi-directional. The one pinout dif­ ference involves the SCLK function. It is multiplexed on the A6 pin on the TMS70x2 devices and the A4 pin on the TMS70Cx2 devices .

Appendix B -TMS7000 NMOS to CMOS Conversion Guide EXTERNAL INTERRUPTS: The external Interrupts (INT1 and INT3) of the TMS70x2 devices are edge only triggered. The external Interrupts on the TMS70Cx2 devices are programmable to be individually triggered in one of the following ways:

• Falling edge only
• Falling edge and level sensitive
• Rising edge only
• Rising edge and level sensitive The TMS70Cx2 devices may be programmed to function identically to the NMOS TMS70x2 devices by programming both external interrupts on the TMS70Cx2 device to be Falling edge only. TIMERS: The different Timers of the TMS70x2 and TMS70Cx2 devices are summarized below:
• TMS70x2: Timers 1 and 2 are 8-bit timers with 5-bit prescale. Both Timers have associated 8-bit Capture registers. The minimum resol- ution is fosc/16.
• TMS70Cx2: Timers 1 and 2 are 16-bit timers with 5-bit prescale. Both timers have 16-bit capture registers. The minimum resolution is fosc/4. Additional user selectable features of the CMOS devices allow each timer to toggle an individual I/O pin on the reload pulse for each Timer, and each timer may be individually selected to halt on an IDLE instruc­ tion. Also, stopping Timer 1 or 2 will clear the current interrupt flag of the timer stopped. SERIAL PORT: The different Serial Ports of the TMS70x2 and TMS70Cx2 devices are summarized below: TMS70x2: The Peripheral files SMODE, SClTO, and SSTAT are all ad­ dressed at the same location. The SClK signal is always active during UART operation, and is multiplexed on the A6 pin. TMS70Cx2: The Peripheral files SMODE, SClTO, and SSTAT are ad­ dressed at different locations. The SClK pin is user selectable as the SClK signal or as a general purpose I/O pin, and is multiplexed on the A4 pin .. Also, the UART or the TMS70Cx2 may be selected to shut down during IDLE. 6-5

Appendix B - TMS7000 NMOS to CMOS Conversion Guide B.2.3 Electrical Specifications 8-6 The Electrical Specification differences between the TMS70xO and TMS70CxO devices may be compared by referencing the Electrical Specifica­ tion sections for both device types located in Section 4 of this data manual. Some of the more common differences are listed below: Operating Ranges Vee: TMS70Cx2: 2.5 V -6.0 V TMS70x2: 4.5 V -5.5 V Fosc (Vee = 5 V ± 10%): TMS70Cx2: 6 MHz TMS70x2: 8 MHz lee (Vee = 5 V, Fosc = 6 MHz) :. TMS70Cx2: 21 mA TMS70x2: 210 mA Input Levels: (Vee = 5 V) VIH: TMS70Cx2 = 3.5 V TMS70x2 = 2.0 V VIL: TMS70Cx2 (Vee = 5 V) = 1.5 V TMS70x2 (Vee = 5 V) = 0.8 V IOL: TMS70Cx2 (Vee == 5 V +/-10%) = 2.0 mA TMS70x2 (Vee = 5 V +/-10%) == 3.2 mA

The TMS70x1 devices include the TMS7001, TMS7041, and the SE70P161. These devices contain the same features as the TMS70xO devices, and en­ hance communication ability with the addition of a serial I/O port. The TMS7041 has 4K bytes of on-chip ROM; the TMS7001 has no on-chip ROM. Each TMS70x1 member has 128 bytes of on-chip RAM, and has the capability (through memory-expansion modes) to access up to 64K bytes of address space. The SE70P161 is a prototyping component for the TMS7001. It is pin-com­ patible with the TMS7041, and uses the same instruction set. The SE70P161 is commonly referred to as a piggyback device because it's packaging allows a standard TMS2764 or TMS27128 EPROM device to be plugged into the top. This two-chip unit acts as a form-fit and function emulator for the TMS7041 microcontroller. The TMS70x1 devices are not recommended for new designs. For designs that require an on-chip UART, we recommend using the enhanced features and performance of the TMS70x2, TMS70Cx2, or the TMS7742-EPROM de­ vices. Topics covered in this appendix include: Section Page C-1

Appendix C - TMS70x1 Devices C.1 Key Features

• Family member with 4K bytes of on-chip ROM as well as a ROMless version
• 128-byte on-chip RAM Register File
• Flexible on-chip serial port: Asynchronous, Isosynchronous, and Serial I/O modes Two multiprocessor communication formats Fully software programmable Internal or external baud-rate generator Separate baud-rate timer, useable as a third timer
• 32 TTL-compatible I/O pins: 22 bidirectional pins 8 output pins 2 high-inpedance input pins
• Full-feature data/program stack
• Memory-mapped ports for easy addressing
• 256-byte Peripheral File
• Memory expansion capability 64K-byte address space
• 8-bit instruction word
• Eight powerful addressing formats, including: Register-to-register arithmetic Indirect addressing on any register pair Indexed and indirect branches and calls
• 2's complement arithmetic
• Single-instruction binary-coded decimal (BCD) add and subtract
• Two external, maskable interrupts
• Flexible interrupt handling Priority servicing of simultaneous interrupts Software execution of hardware interrupts Precise timing of interrupts with the capture latch Software monitoring of Interrupt status
• NMOS,5V ± 10% power supply
• 40-pin, 600-mil, dual-in line package, 100-mil, pin-to-pin spacing packages

Appendix C - TMS70x1 Devices C.2 TMS70x1 Pinouts and Pin Descriptions B5/R/W B7/CLKOUT BO AO A7/EC1 INT3 INTl RESET A6/SCLK/EC2 A5/RXD XTAL2/CLKIN XTAL1 Figure C-1. B5/R/W B7/CLKOUT BO AO A7/EC1 INTl RESET A6/SCLK/EC2 A5/RXD XTAL2/CLKIN XTAL1 ! 1 [ 2 [ 5 ! 6 [ 8 ! 9 (10 ! 13 114 ! 15 [ 17 r 18 o Vee o A12 o A7 o A6 o A5 o A4 o A3 o A2 o Al o AO o DO o 01 o D2 o Vss VSS B6/ENABLE B4/ALATCH B3/TXD MC co DO VCC TMS70x1 Pinout U 40 VSS

39 B6/ENABLE

Figure C-2. SE70P161 Pinout C-3

Appendix C - TMS70x1 Devices Table C-1. TMS70x1 and SE70P161 Pin Descriptions SIGNAL PIN I/O DESCRIPTION AO LSb 6 I/O Port A. Pins Ao-A4 and A7 are general-purpose bidirectional A1 7 I/O pins. Pin A7/EC1 may also be used to clock the on-chip Timer 1 A2 8 I/O event counter. Pin A5/RXO is used as the UART receiver. Pin A3 9 I/O A6/SCLK/EC2 is the serial clock I/O pin and Timer 2 event counter A4 10 I/O A5/RXO 16 I A6/SCLK/EC2 15 I/O A7/EC1 11 I/O BO 3 0 Port B. Bo-B7 are general-purpose output-only pins. B4-B7 B1 4 0 become memory expansion control signals in Peripheral-Expansion. B2 5 0 Full-Expansion. and Microprocessor modes. Pin B3 is used as the B3/TXO 37 0 UART transmitter. B4/ALATCH 38 0 B5/R/iiii 1 0 B6/ENABLE 39 0 B7/CLKOUT 2 0 CO 28 I/O Port C. Co-C7 can be individually selected in software as C1 29 1/0 general-purpose input or output pins in Single-Chip mode. Co-C7 C2 30 I/O become the LSB address/data bus in Peripheral-Expansion. Full- C3 31 I/O Expansion. and Microprocessor modes. C4 32 1/0 C5 33 I/O C6 34 1/0 C7 35 1/0 DO 27 1/0 Port O. 00-07 can be individually selected in software as 01 26 I/O general-purpose input or output pins in Single-Chip or Peripheral- 02 24 1/0 Expansion modes. 00-07 become the MSB address/data bus in Full- 03 23 1/0 Expansion and Microprocessor modes. 04 22 1/0 05 21 1/0 06 20 1/0 07 19 I/O INT1 13 I Highest-priority maskable interrupt INT3 12 I Lowest-priority maskable interrupt RESET 14 I Reset MC 36 I Mode control pin. Vee for Microprocessor mode XTAL2/CLKIN 17 I Crystal input for control of internal oscillator XTAL1 18 0 Crystal output for control of internal oscillator Vee 25 Supply voltage (positive) VSS 40 Ground reference C-4

Appendix C - TMS70x1 Devices C.3 TMS70x1 Architecture The following sections describe the features and functions of the TMS70x1 microcomputers. The TMS70x1 devices are not recommended for new de­ signs. For designs that require an on-chip UART, we recommend using the enhanced features and performance of the TMS70x2, TMS70Cx2, or the TMS7742-EPROM devices. C.3.1 On-Chip RAM and Registers The TMS70x1 devices contain the same on-chip registers as the TMS70x2 devices, with the exception of on-chip RAM. The TMS70x1 devices have 128 bytes of on-chip RAM, a 256-byte Peripheral File, a Stack Pointer (SP), a Status Register (ST), and a 16-bit Program Counter (PC). C.3.2 On-Chip General-Purpose I/O Ports The TMS70x1 devices have 32 I/O pins organized as four 8-bit parallel ports, A, B, C, and D. These ports are memory mapped identically and accessed via the same control registers as on the TMS70x2 devices (see Section 3.2). C.3.3 Memory Modes The TMS70x1 devices can address up to 64K bytes of ROM and RAM. Four memory modes can be selected by a combination of software and hardware: Single-Chip, Peripheral Expansion, Full Expansion, and Microprocessor modes. These modes are identical to the other TMS7000 family memory modes (see Section 3.3). I C.3.4 I/O Control Registers The TMS70x1 devices contain identical I/O control registers in the same me­ mory-mapped locations that are on the TMS70x2 devices. The only difference is that bit 7 of serial control register 1 (SCTL 1) is a don't care for the TMS70x1 devices, whereas on the TMS70x2 devices, this bit is the Timer 3 start/stop bit. (See Section 3 for more information.) C.3.5 Interrupts The TMS70x1 devices contain the same interrupt sources that are on the _ TMS70x2 devices. However, the external interrupts on the TMS70x1 devices are edge and level active rather than edge-only as on the TMS70x2 devices. C.3.6 Clock Options Clock options for the TMS70x1 are +2 and +4 of the oscillator frequency. (See Section 3.4 for more information.) C-5

Appendix C - TMS70x1 Devices C.3.7 Programmable Timer/Event Counters The TMS70x1 devices contain the same three timer/event counters found in the TMS70x2 devices. These timers function the same on each device with the exception of the start/stop function of Timer 3. The TMS70x1 devices do not have a start/stop function for Timer 3. (See Section 3.6 for more infor­ mation.) C.3.S Serial Port The TMS70x1 devices' serial port uses the same control registers and operates identically to the serial port of the TMS70x2 devices, with the exception of the asynchronous mode baud rate. The TMS70x1 operates half as fast in the asynchronous mode as do the TMS70x2 devices. This is because the TMS70x2 devices require 8 SCLK pulses to send a bit of data, while the TMS70x1 devices require 16 SCLK pulses. (See Section 3.8 for more infor­ mation.) These are the baud-rate equations for TMS70x1 devices using Asynchronous or Isosynchronous communications. Asynchronous baud rate 64 x (PR + 1) x (TR + 1) x te(C) Isosynchronous baud rate 4 x (PR + 1) x (TR + 1) x te(C) C.4 Standard Instruction Set/Development Support _C.5 C-6 The TMS70x1 devices use the same instruction set as all other TMS7000 fa­ mily devices. Also, the TMS70x1 uses identical development tools such as the XDS, EVM, assemblers, and linkers, as do the other TMS7000 devices. Electrical Specifications The electrical specifications and memory interface timings of the TMS70x1 devices are identical to those of the TMS70xO devices (see Section 4 for electrical specifications and memory interface timings).

The TMS7000 Assembler recognizes the ASCII character set listed in Table 0-1. Table 0-2 lists characters that the assembler does not recognize. but may be recognized and acted upon by other programs. The device service routine for the card reader accepts and stores into the calling program's buffer all the characters listed. 0-1

Appendix 0 - Character Sets Table D-1. ASCII Character Set (Lo~ nibb e) -0 SI D-2 7- (I-r h nl~le)

Appendix 0 - Character Sets Table 0-2. Control Characters HEX DECIMAL CHARACTER VALUE VALUE 00 0 NUL 01 1 SOH 02 2 STX 03 3 ETX 04 4 EOT 05 5 ENQ 06 6 ACK 07 7 BEL 08 8 BS 09 9 HT OA 10 LF OB 11 VT OC 12 FF 00 13 CR OE 14 SO OF 15 SI 10 16 OLE 11 17 C01 12 18 CO2 13 19 C03 14 20 C04 15 21 NAK 16 22 SYN 17 23 ETB 18 24 CAN 19 25 EM 1A 26 SUB 1B 27 ESC 1C 28 FS 10 29 GS

1 E 30 RS

Appendix 0 - Character Sets D-4

Hexadecimal Instruction Table/Opcode Map

...

01<i1 0110 0111 1000 1001 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F Appendix E Hexadecimal Instruction Table/Opcode Map 0000 0001 0010 0011 0100 1010 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 NOP IDLE MOV MOV MOV RnA %nA Rn,B AND AND AND RnA %nA Rn,B OR OR OR RnA %n,A Rn,B EINT XOR XOR XOR RnA %n,A Rn,B DINT BTJO BTJO BTJO RnA %n,A Rn,B SETC BTJZ BTJZ BTJZ RnA %n,A Rn,B POP ADD ADD ADD ST RnA %nA Rn,B STSP ADC ADC ADC RnA %n,A Rn,B RETS SUB SUB SUB RnA %nA Rn,B RETI SBB SBB SBB RnA %nA Rn,B MPY MPY MPY RnA %nA Rn,B LDSP CMP CMP CMP RnA %nA Rn,B PUSH DAC DAC DAC ST RnA %nA Rn,B DSB DSB DSB RnA %nA Rn,B -A Register A B - Register A Rn - Register File register Pn - Peripheral File register %n - Immediate Addressing @n - Direct Addressing "Rn - Indirect Addressing MOV Rn,Rn AND Rn,Rn OR Rn,Rn XOR Rn,Rn BTJO Rn,Rn BTJZ Rn,Rn ADD Rn,Rn ADC Rn,Rn, SUB Rn,Rn SBB Rn,Rn MPY Rn,Rn CMP Rn,Rn DAC Rn,Rn DSB Rn,Rn 5 6 7 8 MOVP PnA MOV MOV MOV MOVP %n,B BA %n,Pn A,Pn AND AND AND ANDP %n,B B,A %n,Pn A,Pn OR OR OR ORP %n,B BA %n,R APn XOR XOR XOR XORP %n,B BA %n,R APn BTJO BTJO BTJO BTJOP %n,B BA %n,R A,Pn BTJZ BTJZ BTJZ BTJZP %n,B BA %n,R A,Pn ADD ADD ADD MOVD %n,B BA %n,R %n,Rn ADC ADC ADC %n,B BA %n,R SUB SUB SUB LDA %n,B BA %n,R @n SBB SBB SBB STA %n,B BA %n,R @n MPY MPY MPY BR %n,B BA %n,R @n eMP CMP CMP CMPA %n,B B,A %n,R @n DAC DAC DAC CALL %n,B BA %n,R @n DSB DSB DSB %n,B BA %n,R

9 A B C 0 E F

Pn,B B,Rn JLT 14 MOVP MOVP DEC DEC DEC JZ/ TRAP B,Pn %n,Pn A B Rn JEO 13 ANDP ANDP INC INC INC JC/ TRAP B,Pn %n,Pn A B Rn JHS 12 ORP ORP INV INV INV JP/ TRAP B,Pn %n,Pn A B Rn JGT 11 XORP XORP CLR CLR CLR JPZ/ TRAP B,Pn %n,Pn A B Rn JGE 10 BTJOP BTJOP XCHB XCHB XCHB JNZ/ TRAP B,Pn %n,Pn A B Rn JNE 9 BTJZP BTJZP SWAP SWAP SWAP JNC/ TRAP B,Pn %n,Pn A B Rn JL 8 MOVD MOVD PUSH PUSH PUSH TRAP TRAP Rn,Rn %n(B), A B Rn 23 7 Rn PDP POP POP TRAP TRAP A B Rn 22 6 LDA LDA DJNZ DJNZ DJNZ TRAP TRAP "Rn @n(B) A B Rn 21 5 STA STA DECD DECD DECD TRAP TRAP °Rn @n(B) A B Rn 20 4 BR BR RR RR RR TRAP TRAP °Rn @n(B) A B Rn 19 3 CMPA CMPA RRC RRC RRC TRAP TRAP "Rn @n(B) A B Rn 18 2 CALL CALL RL RL RL TRAP TRAP "Rn @n(B) A B Rn 17 1 RLC RLC RLC TRAP TRAP A B Rn 16 0 E-1

Appendix E -Hexadecimal Instruction Table/Opcode Map E-2

~ c ~ c c ~ 12 ~ ~ c ~ A '~ C

§ Indexed AB ,-r Condition Bits Interrupt Enable B,A DUAL OPERAND Rn, %n, Rn, %n, Rn, %n, A A B B Rn Rn 19 29 39 59 49 79 18 28 38 58 48 78 13 23 33 53 43 73 16 26 36 56 46 76 17 27 37 57 47 77 1D 2D 3D 5D 4D 7D 1E 2E 3E 5E 4E 7E 1F 2F 3F 5F 4F 7F Appendix F Instruction Opcode Set Ot~ STATU PERIPHERAL EXTENDED -er WORD A B, A, Pn, B, Pn, %n, t t § 'II )} Rn Rn Pn A Pn B Pn X X X 83 93 A3 X X 86 96 A6 X X 87 97 A7 X 8C 9C AC 8E 9E AE X BO X X 8D 9D AD X X X

06 X X

X X

05 X X

X X EO 8A 9A AA X OD F-1

Appendix F - Instruction Opcode Set F-2 MOV MOVD MOVP MPY NOP OR ORP POP PUSH RETI RETS RL RLC RR RRC SBB SETC STA STSP SUB SWAP TSTA TSTB TRAP XCHB XOR XORP SINGLE OPERAND A B Rn AB CO

89 C9 D9

88 C8 D8

~ Indirect § Indexed ff Condition Bits Interrupt Enable BA DUAL OPERAND Rn. %n, Rn. %n. Rn. %n, A A B B Rn Rn 12 22 32 52 42 72 1C 2C 3C 5C 4C 7C 14 24 34 54 44 74 1B 2B 3B 5B 4B 7B 1A 2A 3A 5A 4A 7A 15 25 35 55 45 75 Oth TATU PERIPHERAL EXTENDED -er WORD Rn An Pn A Po B Pn DO D1 X 88 98 A8 X 82 80 92 91 A2 X X X 34 94 A4 X 08 X DE X DB OA X X X X X 07 X 8B 9B AB X 09 X X X 80 X C1 X E3- X EF X X 35 95 A5 X

"----- ~-~-

This section contains step-by-step instructions for installing, verifying, and relinking the TMS7000 Family Macro Assembler and Link Editor. This CrossWare can be installed on five operating systems: Digital Equipment Corporation VAX-1110

• VMS operating system - page G-2 TIIIBM PC"
• MS-DOS12 (TI PC) and PC-DOS (IBM PC) operating systems - page G-8 IBM Mainframes11
• MVS operating system - page G-15
• CMS operating system - page G-27 TI990 13
• DX10 operating system - page G -32 These style and symbol conventions are used throughout this section:
• The symbol <CR> indicates that a carriage return should be entered; <enter> indicates that the enter key should be pressed.
• Angle brackets « and» indicates a word which must be typed out; for example, <directory> indicates that you should type a directory name. The brackets themselves are not entered .
• ~ Screen displays are shown in a special font.
• Portions of a display that are user responses are underscored. Texas Instruments suggests that you conform to these procedures as closely as possible during the initial installation, allowing you to verify the installation with a minimum of trouble. 10 VAX-11 and VMS are trademarks of Digital Equipment Corporation. 11 MVS, CMS, and PC-DOS are trademarks of International Business Machines. 12 MS is a trademark of Microsoft Corporation. 13 TI 990 and DX10 are trademarks of Texas Instruments, Inc. G-1

Appendix G - CrossWare Installation G.1 VAX/VMS CrossWare Installation The TMS7000 CrossWare tape was created with the VMS BACKUP utility. The package is contained in two directories, shipped in two save sets. G.1.1 Restore Procedures G-2 In the following examples, M FAO represents the tape drive name and DUA2 represents the hard disk drive name. Actual tape and disk drive names may differ.

• Mount the Tape Place the tape on a tape drive. Mount it by entering: ALLOC MFAO: <CR> MOUNT MFAO:/OVER=ID/FOR/DEN=1600 <CR> If the mount is successful, the screen displays: ASM7 MOUNTED ON MFAO
• Restore the Macro Assembler Use the BACKUP utility to read the ASM7 save set from the tape: BACKUP/LOG MFAO:ASM7 DUA2:[<directory>J*.* <CR> The CrossWare package can reside in either your directory or a system direc­ tory. The following examples copy the package into your directory, copying the ASM7 directory structure on the tape into [<directory>] on disk DUA2. A README file explaining the Macro Assembler validation procedure is con­ tained in this directory: [<directory>.ASM7]README.DAT If you do not want to install the Link Editor, skip the next step and unload the tape.
• Restore the link Editor Use the BACKUP utility to copy the LINKER save set from the tape: BACKUP/LOG MFAO:LINKER.BCK DUA2:[<directory>]*.* <CR> The string ' .. .' within the brackets is for a directory name, required for the system to construct subdirectories. The LlNKER.BCK directory structure on the tape is copied into [<directory>] on disk DUA2. A README file explaining the Link Editor validation procedure is contained in this directory: [<directory>.LINKER]README.DAT

Appendix G - CrossWare Installation

• Dismount the Tape Dismount the tape by entering: DISMOUNT MFAO: <CR> Remove the tape from the drive. Deallocate the tape drive by entering: DEALLOCATE MFAO: <CR> G.1.2 Installing Command Files Two command procedures have been provided to ensure correct system-de­ pendent parse features. If your VAX/VMS system runs under Version 2.5, use the PARSE.C25 command procedure by renaming it PARSE. COM. If your system runs under Version 3.0, use the default PARSE.COM. Set the default directory to the directory the Assembler and Linker have been restored to. Edit the Assembler and Linker command files, replacing existing pathnames with the pathnames that the Assembler and Linker have been re­ stored to. Edit the file: [<directory> .ASM7] XASM. COM Substitute the appropriate file pathnames in three places:
• Two calls to the PARSE command, which appear within the first 20 lines as: Change them to:
• One RUN statement, which appears near the bottom of the file as: $ RUN[MOORE.ASM7]ASM7000 Change it to: $ RUN DUA2: [<directory>.ASM7]ASM7000 Edit 1he file: [<directory> . LINKER] LINKER. COM Substitute the appropriate file path names in three places:
• Two calls to PARSE, marked in the file by a preceding line , ••••• * .. :. The. actual command appears similar to the PARSE commands in the assembler command file. Change them to: $ @DUA2:[<directory>.LINKER]PARSE 'PI' ...
• One RUN statement near the end of the file. Change it to: $ RUN DUA2:[<directory>.LINKER]LINKER G-3

Appendix G - CrossWare Installation G.1.3 Providing Transparent Access It is not feasible to set the default directory (SET DEF) each time the Assem­ bler or link Editor is executed. Use the following procedure to provide trans-, parent access for all users. Once the directories are on disk, make the following assignments into the LOGIN.COM file: $ X7 :== @DUA2:[<directory>.ASM7]XASM.COM $ XLINK :== @DUA2:[<directory>.LINKER]LINKER.COM This defines the X7 and XLiNK commands, which execute the Macro Assem­ bler and link Editor. Execute the Macro Assembler by entering X7 at the ter­ minal in System Mode. Similarly, execute the link Editor by entering XLiNK. G.1.4 Verifying Installation G-4 This verification procedure is not designed to perform an exhaustive test, it simply verifies that the installation procedures were executed correctly. It also provides familiarity with the basic operation and data flow of this package. 1) Create a test directory. Copy the TEST.ASM, TEST1.ASM, TEST2.ASM, and TEST1.CON files from [.ASM7] and [.L1NKER] into the directory by entering these commands: $ CREATE/DIR [<userid>.TEST] <CR> $ SET DEF [<userid>.TEST] <CR> $ copy [<directory>.ASM7]TEST.ASM ~ <CR> $ COpy [<directory>.LINKER]TEST1.ASM ~ <CR> $ COpy [<directory>.LINKER]TEST2.ASM ~ <CR> $ COpy [<directory>.LINKER]TEST1.CON ~ <CR> 2) In System Mode, enter: X7 <CR> For the first input parameter, enter TEST. ASM, TESTl. ASM, and TEST2 . ASM, respectively, for the three assembler runs (ASM is the default extension). The command procedure parses the path name and generates de­ faults for the output listing and object files. Take the defaults by pressing the carriage return, or specify alternate file path names following the prompts: $ X7 TEST <CR> Object file (TEST.MPO): <CR> Listing file {TEST.LIS}: <CR> Messages (~TTA3:): <CR> $ X7 TESTl Object file (TEST1.MPO): <CR> Listing file (TEST1.LIS): <CR> Messages (-TTA3:): <CR> $ X7 TEST2 Obj ect file (TEST2. MPO): <CR> Listing file (TEST2.LIS): <CR> Messages {-TTA3:}: <CR> and TEST2.LlS files in the directory [<userid> .TEST].

Appendix G - CrossWare Installation 3) In System Mode, enter: XLINK <CR> As the first input parameter, enter: TEST1. CON For the second and third parameters, the command procedure parses the pathname and generates defaults for the output. load, and map files. This procedure links the object files for TEST1 and TEST2 into a single executable object file in TEST1.LOD (CON is the default for the first parameter): $ XLINK TESTl <CR> Linked object file (TEST1.LOD): <CR> Map file (TEST1.MAP): <CR> This creates the files TEST1.LOD and TEST1.MAP. These files should agree with the precompiled versions in the product directories for the Macro As­ sembler and Link Editor. G.1.5 Relinking the Macro Assembler and link Editor There should be no reason to relink the Macro Assembler or Link Editor, but command files have been provided to allow for this contingency. To relink the Macro Assembler, edit the LlNKASM.COM procedure file to put the correct pathname for the runtime library in the logical assignment state­ ment. In System Mode, execute LlNKASM.COM to relink the ASM7.EXE file: $ SET DEF [<directory>.ASM7J <CR> $ @LINKASM <CR> Similarly, to relink the Link Editor, edit the LlNKLlNK.COM procedure file to put the correct path name for the runtime library in the logical assignment statement. In System Mode, execute LlNKLlNK.COM to relink the LlNK­ ER.EXE file: $ SET DEF [<directory>.LINKERJ <CR> $ @LINKLINK <CR> G-5

Appendix G - CrossWare Installation G.1.6 Product Directories G-6 The following listing contains the product directories found in the CrossWare package. These two directories contain a total of 28 files. SET DEF [<directory>] <CR> DIR <CR> Directory [<directory>] ASM7.DIR;1 LINKER.DIR;l Total: 2 files DIR [<default directory>.ASM7] <CR> Directory [<directory>.ASM7] ASM.OBJ; 1 ASM7000 .EXE; 1 LINKASM. COM; 1 PARSE .c25; 1 PARSE. COM; 1 README. LIS; 1 ASMRTS . OLB; 1 TEST. ASM; 1 TEST.LIS;l TEST.MPO;l XASM.COM;l Total: 11 files DIR [<default directory>.LINKER] <CR> Directory [<directory>.LINKER.] LINKER.COM;l LINKER.EXE;l LINKER.OBJ;l PARSE.COM 1 TESTl.CON 1 TEST1.MPO 1 LINK.COM;l PARSE.C25;1 TEST1.ASM; 1 TEST1.MAP; 1 TEST2.MPO;1 Total: 17 files README.LIS;l TESTl.LIS;l TEST2.ASM;1 LINK- LINKRTS.OLB;l TESTI. LOD; 1 TEST2.LIS;1

Appendix G - CrossWare Installation G.1.7 Using the MUS Directive The directory pathname under VAX/VMS can be less than or equal to nine characters. However, the M LI B directive issues an Invalid Macro Library Pathname error message when the directory path name is more than eight characters. The following code segment shows the correct response when using eight characters for the macro directory pathname. NO$IDT TMS7000 ASSEMBLER VAX/VMS 2.1 83.088 14:30:25 8/1/84 PAGE 0001 0001 * 0002 * 7000 Format 1 test procedure 0003 * This is a test file with pathname eight 0004 * characters long 0005 0000 MLIB 'DUAl: [MD0273.ABCDEFGH] , 0006 * 0007 0000 PSEG 0008 * 0009 Xl B,A 0001 * 0002 0000 69 ADC B,A

0010 Xl R2,A

0001 * "a" 9 0002 0001 19 ADC R2,A 0002- 02

0011 Xl R2,B

0001 * "a" 9 0002 0003 39 ADC R2,B 0004 02

0012 Xl %Ol,A

0001 * "a" 9 0002 0005 29 ADC %Ol,A 0006 01 NO ERRORS, NO WARNINGS G-7

Appendix G - CrossWare Installation G.2 TI and IBM PC MS/PC-DOS CrossWare Installation The TMS7000 CrossWare package is shipped on a double-sided, dual-density diskette. The Macro Assembler and link Editor execute in batch mode on MS-DOS (TI PC) and PC-DOS (IBM PC) systems. At least 256K bytes of memory space must be available. . Instructions are included for both hard disk systems and dual floppy drive systems. The examples use these symbols for drive names: A: Floppy disk drive for hard disk systems or source drive for dual floppy drive systems. B: Destination or system disk drive for dual floppy drive systems. E: Winchester (hard disk) for hard disk systems. G .2.1 Diskette Files The diskette contains the following files: Executable Modules: LlNKER.EXE XASM7.EXE Executes the Link Editor Executes the Macro Assembler Macro Assembler Test Files: TEST1.ASM TEST1.lST TEST1.MPO TEST2.ASM TEST2.lST TEST2.MPO Source file for Assembler test program #1 Correct output listing file for Assembler test program #1 Correct output object file for Assembler test program #1 Source file for Assembler test program #2 Correct output listing file for Assembler test program #2 Correct output object file for Assembler test program #2 Link Editor Test Files: TEST.CTl TEST. MAP TEST.lOD Linker test program (link control file) Correct output listing file for the Linker test program Correct output object file for the Linker test program G.2.2 Restoring the Macro Assembler and link Editor G-8 These instructions are for both hard disk systems and dual floppy drive sys­ tems. On a dual floppy drive system, the MS/PC-DOS system diskette should be in drive B. 1) Make a backup diskette of the product diskette.

• On PC-DOS systems, place a blank diskette in drive A. Enter: FORMAT A: <CR> DISKCOPY A: A: <CR> Follow the prompts, removing and inserting the source and destination diskettes as directed.

Appendix G - CrossWare Installation

• On MS-DOS systems, insert the source (product) diskette in drive A. Enter: DISKCOPY A: A:/F/V <CR> The IF switch tells MS-DOS to format the new (destination) diskette before copying begins. The IV switch tells MS-DOS to verify that the source and destination diskettes are identical after the diskcopy is com­ plete. When MS- DOS first prompts for the destination diskette, remove the source diskette and insert a blank diskette. Follow the prompts, re­ moving and inserting the source and destination diskettes as directed. When MS/PC-DOS prompts: COPY ANOTHER (YIN)? respond with N,. 2) Copy the Macro Assembler onto the hard disk or the system disk: On hard disk systems, enter: COPY A:XASM7.EXE E:*.*/V <CR> On dual floppy drive systems, enter: COPY A:XASM7.EXE B:*.*/V <CR> 3) Copy the Link Editor onto the hard disk or the system disk: On hard disk systems, enter: COPY A:LINKER.EXE E:*.*/V <CR> On dual floppy drive systems, enter: COPY A:LINKER.EXE B:*.*/V <CR> G.2.3 Executing the Macro Assembler To execute the Macro Assembler enter: XASM7 The command line parser prompts for the source, listing, and object file names: Source File Listing File Object File Enter the source file name (if the source file does not have an extension, then type the file name with an explicit '.'). Enter the output listing file name. Enter the output object file name. MS/PC-DOS creates defaults for the listing and object files and/or their ex­ tensions. The default extensions are:
• Source file - .ASM
• • Listing file - .LST Object file - .M PO G-9

Appendix G - CrossWare Installation A source file name can be followed by a semicolon, either on the command line or in response to a prompt; this causes the Macro Assembler to generate the default files without displaying further prompts. . Examples: XASM7 <filename>.SRC; Uses <filename> with extension SRC. Generates defaults for the listing file <filename.lST> and object file <filename>.MPO. XASM7 <filename>; Uses <filename> with default extension ASM. Generates defaults for the listing and object files as indicated above. XASM7 <filename>,<newname>; Uses <filename> with default extension.ASM. Generates listing file <newname>.lST and object file <newname>.MPO. XASM7 <filename>,<newname> Uses <filename> with default extension ASM. Generates listing file <newname>.lST and prompts for object file name. G.2.4 Executing the Link Editor G-10 To execute the Linker enter: LINKER The command line parser will prompt for the control, linkmap, and load file names. Control File Map File Load File Enter the control file name with extension (if the control file does not have an extension, type the file name with an explicit '.'). Enter the linkmap file name with extension. Enter the load module file name with extension. MS/PC-DOS generates defaults for the linkmap and load files and/or their extensions. The default extensions are:

• Control file - .CTl
• Linkmap file - .MAP
• load file - .lOD A source file name can be followed by a semicolon, either on the command line or in response to a prompt; this causes the Macro Assembler to generate the default files without displaying further prompts. Examples: LINKER <filename>.SRC; Uses <filename> with extension SRC. Generates defaults for the linkmap and load files as indicated above. LINKER <filename>; Uses <filename> with default extension CTL. Generates defaults for the linkmap and load files as indicated above. LINKER <filename>,<newname>; . Uses <filename> with default extension, CTL.

Appendix G - CrossWare Installation Generates linkmap file <newname>.MAP and load file <new­ name>.LOD. LINKER <filename>,<newname> Uses <filename> with default extension CTL. Generates linkmap file <newname>.MAP and prompts for the load file name. G.2.5 Testing the Macro Assembler Hard Disk Systems: 1) Copy the TEST1.ASM and TEST2.ASM files from the backup diskette onto the hard disk using the MS/PC-DOS COPY utility: COpy A:*.ASM E:*.*/V <CR> 2) Execute the Macro Assembler using TEST1.ASM and TEST2.ASM as source files. In response to the system prompt. enter: XASM7 TEST1; The Assembler generates the default object file TEST1.MPO and default listing file TEST1.LST. 3) Compare the listing and object files just created to those on backup diskettes. Only lines which contains the date and time the files were created should be different.

• On MS-DOS systems, use the FILCOM utility: FILCOM TEST1.MPO A:TEST1.MPO <CR> FILCOM TEST1.LST A:TEST1.LST <CR> FILCOM TEST2.MPO A:TEST2.MPO <CR> FILCOM TEST2.LST A:TEST2.LST <CR> MS/DOS will display the lines that are different.
• On PC-DOS systems, use the TYPE utility to print the contents of each file on the screen and visually check for differences: TYPE TEST1.MPO <CR> TYPE A:TEST1.MPO <CR> TYPE TEST1.LST <CR> TYPE A:T.ESTl.LST <CR> TYPE TEST2.MPO <CR> TYPE A:TEST2.MPO <CR> TYPE TEST2.LST <CR> TYPE A:TEST2.LST<CR> G-11

Appendix G - CrossWarelnstaliation G-12 Floppy Drive Systems: 1) Insert the backup diskette into the default floppy drive. 2) Execute the Macro Assembler using TEST1.ASM and TEST2.ASM as source files. It is important to use a different name for the object and listing files, otherwise the Assembler will write over these files on the backup diskette, and there will be no correct files to compare the created files to. In response to the system prompt, enter: XASM7TEST1,MYTEST1; The Assembler generates object file MYTEST1.MPO and listing file MYTEST1.LST. 3) Compare the listing and object files just created to those on backup diskettes. Only lines which contains the date and time the files· were created should be different.

• On MS-DOS systems, use the FILCOM utility: FILCOM TEST1.MPO MYTEST1.MPO <CR> FILCOM TEST1.LST MYTEST1.LST <CR> FILCOM TEST2.MPO MYTEST2.MPO <CR> FILCOM TEST2.LST MYTEST2.LST <CR> MS/DOS will display the lines that are different.
• On PC-DOS systems, use the TYPE utility to print the contents of each file on the screen and visually check for differences: TYPE TEST1.MPO <CR> TYPE MYTEST1.MPO <CR> TYPE TEST1.LST <CR> TYPE MYTEST1.LST <CR> TYPE TEST2.MPO <CR> TYPE MYTEST2.MPO <CR> TYPE TEST2.LST <CR> TYPE MYTEST2.LST<CR>

Appendix G - CrossWare Installation G.2.6 Testing the link Editor Hard Disk Systems: 1) Copy the TEST.CTl, TEST1.MPO, and TEST2.MPO files from the backup diskette onto the hard disk using the MS/PC-DOS COPY utility: COpy A:TEST.CTL E:*.*/V <CR> COpy A:TEST*.MPO E:*.*/V <CR> 2) Execute the Link Editor using TEST.CTl as the control file. In response to the system prompt, enter: LINKER TEST; The linker generates the default linkmap file TEST. MAP and default load file TEST.LDD. Compare the listing and object files just created to those on backup diskettes. Only lines which contains the date and time the files were created should be different.

• On MS-DOS systems, use the FllCOM utility: FILCOM TEST.MAP A:TEST.MAP <CR> FILCOM TEST.LaD A:TEST.LOD <CR> MS/DOS will display the lines that are different.
• On PC-DOS systems, use the TYPE utility to print the contents of each file on the screen and visually check for differences: TYPE TEST.MAP <CR> TYPE A:TEST.MAP <CR> TYPE TEST.LOD <CR> TYPE A:TEST.LOD <CR> Floppy Drive Systems: 1) Insert the backup diskette into the default floppy drive. 2) Execute the Link Editor using TEST.CTl as the control file. It is important to use a different name for the map and load files, otherwise the linker will write over these files on the backup diskette, and there will be no correct files to compare the created files to. In response to the system prompt, enter: LINKER TEST,MYTEST; The Linker generates linkmap file MYTEST.MAP and load file MYTEST.lOD.
• On MS-DOS systems, use the FllCOM utility: FILCOM TEST.MAP MYTEST.MAP <CR> FILCOM TEST.LOD MYTEST.LOD <CR> MS/DOS will display the lines that are different. G-13

Appendix G - CrossWare Installation G-14

• On PC-DOS systems, use the TYPE utility to print the contents of each file on the screen and visually check for differences: , TYPE TEST. MAP <CR> TYPE MYTEST.MAP <CR> TYPE TEST.'LOD <CR> TYPE MYTEST.LOD <CR>

Appendix G - CrossWare Installation G.3 IBM/MVS CrossWare Installation This section explains how to install the TMS7000 CrossWare package on an IBM/MVS system. G.3.1 Tape Transfer to Datasets Section G.3.1.1 describes the files that are shipped on the product tape. They are grouped according to file type, i.e., all JCL files are in a dataset, all load modules are in a dataset. and all object modules are in a dataset. Section G.3.1.2 provides instructions for creating the partitioned datasets that will contain these files. Section G.3.1.3 contains the JCL needed to restore these files into the partitioned datasets on the virtual machine. To submit a file, enter edit mode using the desired file, and type SUBMIT on the command line. This submits the file as a batch job. G.3.1.1 Module Descriptions The following lists describe the files provided on the tape, grouped according to modules:

• CNTL - Control Files (JCL) Invokes the assembler test program Relinks the TMS7000 family Assembler Invokes the Link Editor test program Relinks the TMS7000 family Link Editor ASSEMBLE LlNKASM LINKER LlNKLINK RANDINIT Invokes a utility that initializes random files (for the As­ sembler)
• LOAD - Load Modules AS M 7000 LINKER RANDINIT The Assembler load module The Link Editor load module Random file initialization utility load module
• TEXT - Object Modules ASM7000 LINKER TEST1 TEST2 Assembler object file Link Editor object file Benchmark test Assembler object code Assembler test object code
• RUNTIME - Runtime Support Modules Contains the object modules for the TI Pascal runtime support needed to re­ link the Assembler and the Linker. They are not listed here, since there are about 240 members in this set.
• TEST - Source Modules TEST1 TEST2 Test program used for Assembler and Link Editor Test program used for Assembler and Link Editor G-15

Appendix G - CrossWare Installation G.3.1.2 Creating the Datasets Use the MVS dataset utility to create partitioned datasets with the following names and characteristics. (A different library n'ame may be used to replace LlBNAME.)

• Create dataset LlBNAME.ASM7000.CNTL (library of JCL files) Device Type 3350 Organization PO Record Format FB Record Length '80 Block Size 3200 1 st Extent Tracks 10 Secondary Tracks 0 Directory Blocks 10
• Create dataset LlBNAME.ASM7000.LOAD (library of load modules) Device Type 3350 Organization PO Record Format U Record Length 80 Block Size 13030 1 st Extent Tracks 3 Secondary Tracks 0 Directory Blocks 30
• Create dataset LlBNAME.ASM7000.TEST (library of source code test programs) Device Type 3350 Organization PO Record Format FB Record Length 80 Block Size 2960 1 st Extent Tracks 1 Secondary Tracks 0 Directory Blocks 20
• Create dataset LlBNAME.ASM7000.TEXT (library of object modules) Device Type 3350 Organization PO Record Format FB Record Length 80 Block Size 2960 1 st Extent Tracks 1 Secondal)' Tracks 0 Directory Blocks 10
• Create dataset LlBNAME.ASM7000.RUNTIME (library of runtime support object modules) Device Type 3350 Organization PO Record Format U Record Length 80 Block Size 10030 1 st Extent Tracks 1 Secondary Tracks 0 Directory Blocks 50 G-16

Appendix G - CrossWare Installation G.3.1.3 Restoring the Tape Use an editor to create a sequential file called TRESTORE which contains the JCL shown below. This JCL restores the tape. Insert the name of the tape (written on the tape label) in <TAPE NAME>. If a different library name was used for LlBNAME, insert it as the partitioned dataset name wherever the JCL uses LlBNAME. The member names provided should remain the same for the sake of clarity. IIRESTOR JOB <job card> IITAPEDMP PROC DSNX='DUMMY',LNO=1,FB=U,BSZ=3200 IISTEPl EXEC PGM=IEBCOPY IISYSPRINT DD SYSOUT=% IIINPDS DD DSNAME=&DSNX,DISP=OLD IIBACKUP DD DSNAME=<TAPE NAME>,UNIT=TAPE,DISP=OLD, II LABEL=(&LNO,NL), II DCB=(RECFM=&FB,LRECL=80,BLKSIZE=&BSZ,DEN=3), II VOL=(,RETAIN) IISYSUTl DD UNIT=SPACE,DISP=(NEW,DELETE),SPACE=(80,(60,45)) IISYSUT2 DD UNIT=SPACE,DISP=(NEW,DELETE),SPACE=(80,(60,45)) II PEND IIDOITl EXEC TAPEDMP, DSNX='LIBNAME.ASM7000.CNTL',LNO=1,FB=FB, II BSZ=3200 IISYSIN DD * II COPY OUTDD=INPDS,INDD=BACKUP IIDOIT2 EXEC TAPEDMP, DSNX='LIBNAME.ASM7000.LOAD',LNO=2,FB=FB, II BSZ=3200 IISYSIN DD * II COPY OUTDD=INPDS,INDD=BACKUP IIDOIT3 EXEC TAPEDMP, DSNX='LIBNAME.ASM7000.TEXT',LNO=3,FB=FB, II BSZ=3200 IISYSIN DD * II COPY OUTDD=INPDS,INDD=BACKUP IIDOIT4 EXEC II IISYSIN II IIDOIT5 II IISYSIN II II DSNX='LIBNAME.ASM7000.RUNTIME' ,LNO=4,FB=FB, BSZ=3200 DD * COPY OUTDD=INPDS,INDD=BACKUP EXEC DSNX='LIBNAME.ASM7000.RUNTIME',LNO=4,FB=FB, BSZ=3200 DD * COPY OUTDD=INPDS,INDD=BACKUP TAPEDMP, TAPEDMP, G-17

Appendix G - CrossWare Installation G.3.2 Installing the Assembler and Link Editor G-18 The JCL in Section G.3.1.3 installs the following software components:

• Assembler Load Modules LIBNAME. ASM7000. LOAD (ASM7000) Contains the complete load module for the Macro Assembler. It may be executed as is, or used to relink the As­ sembler (see Section G.3.3). LIBNAME.ASM7000.LOAD(RANDINIT) The JCL uses this load module to initialize random files used by the Macro Assembler.
• Assembler Object Modules LIBNAME.ASM7000.TEXT(ASM7000) LIBNAME. ASM7000. RUNTIME This load module and this dataset relink the Assembler.
• Assembler Control Files LIBNAME.ASM7000.CNTL(ASSEMBLE) Executes the Macro Assembler. (See verification procedures, Section G.3.4.) LIBNAME .ASM7000. CNTL (LINKASM) Relinks the Macro Assembler.
• Link Editor Load Modules LIBNAME .ASM7000 • LOAD (LINKER) Load module for the Link Editor. No other load modules are necessary for Link Editor execution.
• Link Editor Object Modules LIBNAME.ASM7000.TEXT(LINKER) LIBNAME. ASM7000 • RUNTIME This file and this dataset relink the Link Ed­ itor.
• Link Editor Control Files LIBNAME. ASM7000. CNTL (LINKER) Executes the Link Editor. (See ver­ ification procedure, Section G.3.4.) LIBNAME .ASM7000. CNTL (LINKLINK) Relinks the Link Editor.

Appendix G - CrossWare Installation G.3.3 Relinking the Assembler and Link Editor Assembler Execute the following steps to rei ink the Assembler. 1) Edit the control file LlBNAME.ASM7000.CNTL(LlNKASM). 2) Change LlBNAME to the correct partitioned dataset name where appropriate. In the data definition card below, insert the name of the dataset for the output load module. (It may be easier to use the load module library created above for verification.) Replace the load module name in the NAME card with the desired member name. The (R) specifies to replace an earlier version of the load module. //SYSLMOD DD DISP=OLD,DSN=LIBNAME.ASM7000.LOAD NAME ASM7000(R) 3) Save the edited file and submit the JCL to the system. A condition code of zero indicates a successful link. Be sure to use the correct load module in the verification procedures in Section G.3.4. Link Editor The Link Editor load module may be executed as is. If the Link Editor is to be relinked on the new system, execute the following procedure: 1) Edit the control file LlBNAME.ASM7000.CNTL(LlNKLlNK). 2) Change LlBNAME to the correct partitioned dataset name where appropriate. In the data definition card below, insert the name of the dataset for the output load module. Replace the load module name in the NAME card with the member name desired. The (R) specifies to replace an earlier version of the load module. //SYSLMOD DD DISP=OLD,DSN=LIBRARY.ASM7000.LOAD NAME LINKER(R) 3) Save the edited file and submit the JCL file to the system. A condition code of zero indicates a successful link. Use this load module in the Link Editor for verification procedures in Section G.3.4. G-19

Appendix G - CrossWare Installation G.3.4 Verifying Installation G-20 These verification procedures are not designed to perform an exhaustive test. They simply verify that the installation procedures were executed correctly. They also provide familiarity with the package's basic operation and data flow. Software Components Used for Assembler Verification

• Control Files LIBNAME.ASM7000.CNTL(ASSEMBLE) Contains the JCL to execute the Assembler installation verification.
• Load Modules LIBNAME. ASM7000. LOAD (RANDINIT) Initializes the random files (direct access files) used by the Macro Assembler. If random file initialization is performed automatically on an open to a random file, this step is not neces­ sary, and may be deleted from the JCL. If, however, the random file initializa­ tion is not performed automatically, the random files must be explicitly initialized as direct access files. LIBNAME.ASM7000.LOAD(ASM7000) Contains the load module for the Assembler. If the Assembler has been relinked, use the new load module name for verification.
• Test Programs LIBNAME.ASM7000.TEST(TEST1) LIBNAME.ASM7000.TEST(TEST2) Contain the test program module. These tests consist of assembly language programs containing directives, macro definitions, macro calls, and assembly instructions for each opcode. Software Components Used for Link Editor Verification
• Control File LIBNAME.ASM7000.CNTL(LINKER) Contains the JCL to execute the Link Editor installation verification.
• Load Module LIBNAME.ASM7000.LOAD(LINKER) Contains the TMS7000 Link Editor. If the Link Editor was rei inked on this system, use the new load module name.
• Test Programs LIBNAME. ASM7000. TEST This dataset contains two object modules, TEST1 and TEST2. This test links these modules together.

Appendix G - CrossWare Installation Assembler Verification Procedure This procedure assembles a test program that contains all instruction opcodes, basic directives, macro definitions, and macro calls. 1) If the Assembler has been relinked, edit the file: LlBNAME.ASM7000.CNTL(ASSEMBLE). Substitute the correct load module and dataset names in the following JCL card: //ASSEM PROC ASM=ASM7000,STACK=lOK,HEAP=lOOK //STEPLIB DO DISP=SHR,LIBNAME.ASM7000.LOAD 2) Allocate an object output dataset called LlBNAME.ASM7000.0BJECT and specify it in the following DO card: //ASMGO.OBJECT DO DSN=LIBNAME.ASM7000.0BJECT(TESTl) ,DISP=OLD 3) Save the file and submit the JCL to the system. A condition code of 0 indi­ cates a successful assembly. There should be no error messages from the re­ sults of this assembly and the file LlBNAME.ASM7000.TEXT(TEST1). The same procedure can be followed for source file TEST2 by simply replacing member name TEST1 with TEST2 in the ASMGO.OBJECT and ASMG­ O.SYSIN DO cards. Link Editor Verification Procedure This test may be performed with the test object modules provided on the tape, or it may be used in tandem with the Assembler test by using the object mo­ dules produced from testing the Assembler. Substitute the appropriate dataset and member names for the test modules desired. 1) If the Link Editor has been relinked, edit the JCL file, changing these JCL cards to the new load module dataset name: //LINKER PROC LKED=LINKER,STACK=20K,HEAP=400K,TMPSIZE=1, //STEPLIB DO DSN=LIBNAME.ASM7000.LOAD,DISP=SHR 2) Create an output load module dataset called LlBNAME.ASM7000.LOAD3 and place the name in the following DO card: //TESTIT EXEC LINK- ER.OBJLIB='LIBNAME.ASM7000.LOAD3' ,OBJMEM=' LOAD3 , The next DO card in the JCL for executing the Link Editor (see Section G.3.6) is: MYOBJXXX DO DSN=LIBNAME.ASM7000.TEXT,DISP=OLD G-21

Appendix G - CrossWare Installation The MYOBJXXX DD card specifies the object input modules. If you want to test other object modules, substitute LlBNAME.ASM7000.0BJECT for the dataset name and TEST1 and TEST2 for the member names in the INCLUDE statements in the JCL. 3) Save the edited file and submit the JCL to the system. A condition code of o indicates a successful link. The load object code will be in the file LI B­ NAM E.ASM7000. LOAD3 (LOAD3). G.3.5 JCL for Executing the Assembler This JCL is contained in the file LlBNAME.ASM7000.CNTL(ASSEMBLE). IIASSEM JOB 'NAME II*MAIN ORG=OOOOO 000 000 0000000-00 IIASSEM PROC ASM=ASM7000,STACK=10K,HEAP=100K II OBJLIB='&&OBJLIB' ,OBJMEM=ASM7000 000102 0512P C', 11* 11* 11* TMS7000 MACRO ASSEMBLER VERSION 2.1 IIASMGO EXEC PGM=&ASM,PAR='&STACK,&HEAP' 11* PROGRAM FILE IISTEPLIB DD DISP=SHR,DSN=LIBNAME.ASM7000.LOAD 11* SOURCE FILE II INPUT DD DDNAME=SYSIN 11* INPUT FILE IIOBJECT DD DSN=&OBJLIB(&OBJMEM), II DISP=(NEW,KEEP) II UNIT=SPACE,SPACE=(CYL,(3,1,10)), II DCB=(RECFM=FB,LRECL=80,BLKSIZE=2960) 11* OUTPUT FILE IIOUTPUT DD SYSOUT=A 11* TEMPORARY FILE IITEMPFILE DD DISP=(NEW,DELETE), II UNIT=SPACE,SPACE=(CYL,l), II DCB=(RECFM=FB,LRECL=80,BLKSIZE=2960) IINEWLIB DD UNIT=SPACE,SPACE=(TRK,l),DISP=(NEW,PASS), II DCB=(DSORG=DA) II PEND II*FORMAT PR,DDNAME=OBJECT,CONTROL=SINGLE II EXEC ASSEM IIASMGO.OBJECT II IIASMGO.OUTPUT IIASMGO.SYSIN II G-22 DD DSN=LIBNAME.ASM7000.TEXT(TEST1), DISP=OLD DD SYSOUT=A,DCB=RECFM=FBA DD DSN=LIBNAME.ASM7000.TEST(TEST1) ,DISP=SHR

Appendix G - CrossWare Installation G.3.6 JCL for Executing the Link Editor This JCL is contained in the file LlBNAME.ASM7000.CNTL(LlNKER). IILINKER JOB 'NAME 000 000 0000000-00 000102 0512P C', II*MAIN ORG=OOOOO IILINKER PROC LKED=LINKER,STACK=20K,HEAP=100K,TMPSIZE=1 II OBJLIB='TEMPLIB' ,OBJMEM=TEMPNAME IlL INK EXEC PGM=&LKED,PARM= (&STACK, &HEAP) IISTEPLIB DO DSN=LIBNAME.ASM7000.LOAD,DISP=SHR IIOUTPUT DO SYSOUT=A IIINPUT DO DDNAME=SYSIN IITEMPFILE DO DISP=NEW,UNIT=SPACE,SPACE=(CYL,&TMPSIZE), II DCB=DSORG=DA IIOBJECT DO DISP=SHR,DSN=&OBJLIB(&OBJMEM) II PEND IITESTIT EXECLINKER,OBJLIB='LIBNAME.ASM7000.LOAD' ,OBJMEM='LOAD3' IIMYOBJXXX DO DSN=LIBNAME.ASM7000.TEXT,DISP=OLD IISYSIN DO * TASK JUNK DATA 0 COMMON 128 PROGRAM 256 INCLUDE MYOBJXXX(TEST1) INCLUDE MYOBJXXX(TEST2) END G.3.7 JCL for Relinking the Assembler This JCL is contained in the file LlBNAME.ASM7000.CNTL(LlNKASM). IILINKA JOB 'NAME 000 000 0000000-00 000102 0512P C' , II*MAIN ORG=OOOOO II EXEC PGM=IEWL,PARM='MAP,LIST,LET,CALL,SIXE=(118K,24K), IISYSLIB DD DISP=SHR,DSN=LIBNAME.ASM7000.RUNTIME IISYSLIN DO DISP=SHR,DSN=LIBNAME.ASM7000.TEXT(ASM7000) II DO DDNAME=SYSIN IISYSPRINTDD SYSOUT=A IISYSUT1 DO UNIT=SPACE,SPACE=(CYL,(l,l)) IISYSLMOD DO DISP=OLD,DSN=LIBNAME.ASM7000.LOAD IISYSIN DO * ' ENTRY P$MAIN INCLUDE SYSLIB(STACLIKE) INCLUDE SYSLIB(ASMTEXT) INCLUDE SYSLIB(PUTREC) INCLUDE SYSLIB(MAIN) NAME ASM7000(R) II G-23

Appendix G - CrossWare Installation G.3.S JCL for Relinking the Link Editor This JCL is contained in the file L1BNAME.ASM7000.CNTL(L1NKLlNK). IILINKA JOB 'NAME 000 000 0000000-00 000102 0512P C', II*MAIN ORG=OOOOO II EXEC PGM=IEWL,PARM='MAP,LIST,LET,CALL,SIXE=(l18K,24K), IISYSLIB DO OISP=SHR,OSN=LIBNAME.ASM7000.RUNTIME IISYSLIN DD DISP=SHR,DSN=LIBNAME.ASM7000.TEXT(LINKER) II DD DDNAME=SYSIN IISYSPRINT DD SYSOUT=A IISYSUT1 DD UNIT=SPACE,SPACE=(CYL,(l,l)) IISYSLMOD . DD DISP=OLD,DSN=LIBNAME.ASM7000.LOAD IISYSIN DD * ENTRY P$MAIN INCLUDE SYSLIB(STACLIKE) INCLUDE SYSLIB(PUTREC) INCLUDE SYSLIB(ASCII$) INCLUDE SYSLIB(MAIN) NAME LINKER(R) II G.3.9 JCL for Random File Initialization This JCL is contained in the file L1BNAME.ASM7000.CNTL(RANDINIT). IILINKA JOB 'NAME 000 000 0000000-00 000102 0512P C', II*MAIN ORG=OOOOO II EXEC PGM=RANDINIT IISTEPLIB DD DISP=SHR,DSN=LIBNAME.ASM7000.LOAO IIOUTPUT DD SYSOUT=A IIFILE1 DO OSN=LIBNAME.ASM7000.FILE,OISP=OLD,DCB=DSORG=DA IIINPUT DD * DDNAME=FILE1,LENTH=80,NUMBER~100 II G-24

Appendix G - CrossWare Installation G.3.10 Using the COPY Directive In Assembler Text: The COpy statement syntax is: [<label>] COpy <filename> where: [<comment>] [<label>] is an optional label beginning in column 1. <filename> has been defined on a DO card in the JCL. Filenames may be members of partitioned datasets or sequential files. Names may be delimited by parentheses, blanks, or peri­ ods. [<comment>] is an optional comment. IDT 'TEST' * COPY STATEMENT TEST PROGRAM COpy DATASET (MEMBER) COpy SEQUEN END In the JCL: //DATASET //SEQUEN DD DSN=LIBNAME.DATA.LIBRARY DD DSN=LIBNAME. DATA. LIBRARY (FILE1) This example copies the file named MEMBER from the dataset LlB­ NAME.DATA.LlBRARY and the sequential file FILE1 from the same dataset. G-25

Appendix G - CrossWare Installation G.3.11 Using the MUB Directive In Assembler Text: G-26 The M LI B statement syntax is: [<label> ] MLlB '<pathname>, [<comment>] where: [<label>] is an optional label beginning in column 1. <pathname> is a quote enclosed filename, previously defined on a DO card in the JCL. The filename must be a partitioned data­ set. Only one name may be specified for each MLiB di­ rective. [<comment>] is an optional comment. lOT 'TEST' * MLlB STATEMENT TEST PROGRAM A BSS 2 B DATA >1000 MLlB 'DATASET' MAC 1 A,B END In the JCL: //DATASET DO DSN=LlBNAME.DATA.LlBRARY In this example, the MLiB statement causes the Assembler to search for the member MAC1 in the dataset L1BNAME.DATA.L1BRARY (since it is not a valid opcode or an internally defined macro). The Assembler first searches for a special member of the dataset named MLiST to determine if it should replace any opcodes. MLiST contains a list of all macros defined as members of the dataset.

Appendix G - CrossWare Installation G.4 IBM/CMS CrossWare Installation This section contains directions for installing the TMS7000 Macro Assembler and Link Editor on an IBM/CMS system. The CrossWare tape was created with the CMS TAPE DUMP command. G.4.1 Tape Files The product tape contains the following files: ASM7000 ASM7000 ASM7000 ASMDEFX LINKER LINKER LlNK7000 LlNKDEFX RELOAD TEST TEST TEST TEST1 TEST1 TEST1 TEST TEST TEST TIPL ASCII$ RUNTIME STACLIKE MODULE OBJECT EXEC EXEC MODULE OBJECT EXEC EXEC EXEC ASM7000 LlST7000 OBJ7000 ASM7000 LlST7000 OBJ7000 LlNKCTL OUTPUT OBJECT EXEC TEXT TXTLIB TXTLIB Assembler executable module Assembler object file Exec to invoke the assembler Exec to set up assembler filedefs Linker executable module Linker object file Exec to invoke the linker Exec to set up linker filedefs Exec to re-generate executable modules Sample assembler source Sample assembler output listing Sample assembler output object Sample assembler source Sample assembler output listing Sample assembler output object Sample link control file Sample linker map listing Sample linker output object Exec needed to generate load modules IBM object file needed to re-link I BM object library for re-link I BM object library for re-link G.4.2 Restoring the Macro Assembler and Link Editor 1) Mount the tape. Set up a virtual tape drive with a density of 6250 BPI. The tape drive must be attached to the userid that is restoring the tape. CMS usually reserves vir­ tual addresses 181 through 184 for tape devices. If, for example, a userid is attached to a tape drive at virtual address 181, CMS will display the following message on that userid's terminal: TAPE 181 ATTACHED G-27

Appendix G - CrossWare Installation 2) Use the TAPE SCAN command to display a list of the files on the tape: TAPE SCAN <enter> This list should be the same as the list in Section G.4.1, followed by the message: END-OF-FILE OR END-OF-TAPE Rewind the tape before reading the files from it: TAPE REW <enter> 3) Use the TAPE LOAD command to read in the files on the tape. Caution: Files loaded from tape replace files with the same filename, fi­ letype, and filemode. The command syntax is: TAPE LOAD <filename> <filetype> <filemode> Two methods are recommended for using this command:

• Read one file at a time by specifying the individual filename, filetype, and filemode. This example loads file ASM7000 MODULE onto minidisk F. TAPE LOAD ASM7000 MODULE K <enter>
• Read all the files at once (placing them on the same minidisk). This example loads all the files on the tape to minidisk A. TAPE LOAD ~ ~ A <enter> Rewind the tape after loading the files. G.4.3 Executing the Macro Assembler G-28 To execute the TMS7000 Macro Assembler, enter: ASM7000 <filename> <filemode> <filename> is the name of the source file; it must have a filetype of ASM7000. The <filemode> is optional. If no filemode is specified, CMS will search all accessible disks and uses the first occurrence of <f ilename> ASM7000. If a filemode is specified, the Macro Assembler uses the file <f ilename> ASM7000 <f ilemode> as input. The Macro Assembler creates three output files and places them on the A disk; it is the user's responsibility to assure there is enough available disk space. The Macro Assembler output files are: <filename> <filename> <filename> LIST7000 A Listing file OBJ7000 A Object file MESSAGE A Run-time support message file

Appendix G - CrossWare Installation G.4.4 Executing the Link Editor To execute the TMS7000 Link Editor, enter: LINK7000 <filename> <filemode> <filename> is the name of the source file; it must have a filetype of LlNKeTL. The <filemode> is optional. If no filemode is specified, CMS will search all accessible disks and uses the first occurrence of <filename> LINKCTL. If a filemode is specified, the Link Editor uses the file <f i len­ arne> LINKCTL <filemode> as input. The Link Editor creates three output files and places them on the A disk; it is the user's responsibility to assure there is enough available disk space. The Link Editor output files are: <filename> <filename> <filename> OBJECT OUTPUT MESSAGE A Output object module A Linker map listing A Run-time support message file G.4.S Testing the Macro Assembler This test procedure verifies that the Macro Assembler has been installed cor­ rectly. These examples use files TEST ASM7000 and TEST1 ASM7000 as source files, and create the LlST7000, OBJ7000, and MESSAGE output files described in Section GA.3. The examples assume that the files were loaded from the tape onto the A disk. 1) Copy the correct versions of the output files onto another disk (the Macro Assembler will write over these files on the A disk; copying them to another disk saves them for comparison). This example copies the files onto the B disk; if the B disk is not available, use the next available read/write disk. COPYFILE TEST LIST7000 ~ = = ~ <enter> COPYFILE TEST OBJ7000 ~ = = ~ <enter> COPYFILE TESTI LIST7000 ~ = = ~ <enter> COPYFILE TESTl OBJ7000 ~ __ ~ <enter> 2) Execute the Macro Assembler: ASM7000 TEST <enter> ===> TMS 7000 Macro Assembler Started ===> Assembly for I TEST I complete , RC ASM7000 TESTl <enter> ===> TMS 7000 Macro Assembler Started ===> Assembly for I TESTl I complete , RC A revision code of 0 indicates a successful assembly. ( 0 ). ( 0 ). Compare the output files created by the Macro Assembler to the output files that were shipped on the tape: COMPARE TEST LIST7000 ~ TEST LIST7000 ~ <enter> COMPARE TEST OBJ7000 ~ TEST OBJ7000 ~ <enter> G-29

Appendix G - CrossWare Installation COMPARE TEST 1 LIST7000 ~ TESTI LIST7000 ~ <enter> COMPARE TESTI OBJ7000 ~ TESTI OBJ7000 ~ <enter> In each comparison, only lines containing times or dates should differ. For example, COMPARE TEST LIST7000 ~ TEST LIST7000 ~ <enter> COMPARING TEST LIST7000 A WITH TEST LIST7000 B TEST LIST7000 A <line with time and/or date> TEST LIST7000 B <same line with different time and/or date> G.4.6 Testing the Link Editor G-30 This test procedure verifies that the Link Editor has been installed correctly. These examples use the file TEST LlNKCTL as a source file, and create the OUTPUT, OBJECT, and MESSAGE output files described in Section G.4.4. The examples assume that the files were loaded from the tape onto the A disk. 1) Copy the correct versions of the output files onto another disk (the Link Editor will write over these files; copying them to another disk saves them for com­ parison). This example copies the files onto the B disk; if the B disk is not available, use the next available read/write disk. COPYFILE TEST OUTPUT COPYFILE TEST OBJECT 2) Execute the Link Editor: LINK7000 TEST <enter> = -= - = -= - <enter> <enter> ===> RC = ( 0 ). A revision code of 0 indicates a successful link. 3) Compare the output files created by the Link Editor to the output files that were shipped on the tape: COMPARE TEST OUTPUT ~ TEST OUTPUT ~ <enter> COMPARE TEST OBJECT ~ TEST OBJECT ~ <enter> In each comparison, only lines containing times or dates should differ. For example, COMPARE TEST OUTPUT ~ TEST OUTPUT ~ <enter> COMPARING TEST OUTPUT A WITH TEST OUTPUT B

Appendix G - CrossWare Installation TEST OUTPUT A <line with time and/or date> TEST OUTPUT B <same line with different time and/or date> G.4.7 Macro Assembler and Link Editor Regeneration If the ASM7000 or L1NK7000 execs are accidentally destroyed, they can be regenerated from the object files (ASM7000 OBJECT and LINKER OBJECT) by executing the RELOAD exec. RELOAD calls the TIPL exec to include the proper run-time files. G.4.8 Using the MUB Directive The CMS implementation of the MUB directive requires that macro libraries are logically grouped by filetype. For example, the macro definition files might be: MACl MAC2 MAC3 MACRO A MACRO A MACRO A In the assembler source file, the MLiB directive would look like this: MLIB or MLIB or MLIB 'MACRO' 'MACRO A' 'MACRO *' In the first MLiB example, the filemode is not given. CMS will search all mi­ nidisks in Search Order. In the second example, the filemode specifies the A disk, so only the A disk will be searched for macros. If this method is used, all macros called by the source file must be located on the A disk (or, if an­ other disk is specified, on that disk). The third example is the same as the first example. G.4.9 Using the COPY Directive The CMS implementation of the COPY directive requires that the file(s) to be copied into the source file must have the same filetype as the source file. Otherwise, the copied file will not be copied into during assembly time, and no assembler error or warning will be issued. However, the copied file does not have to be in the same minidisk as the source file. In the assembler source file, the COPY directive syntax is: COPY SUBl G-31

Appendix G - CrossWare Installation G.5 TI 990/DX10 CrossWare Installation TMS7000 CrossWare for TI 990/DX10 is available on several types of media, including magnetic tape and hard discs. The magnetic tapes were created with the backup directory command (BD). The hard discs were created with the copy directory command (CD). The CrossWare contains the TMS7000 Macro Assembler, Link Editor a utility to convert absolute TMS7000 object modules to a form acceptable to the standard PROM utility, and the PROM utility. (Absolute TMS7000 object modules can be generated by either the Assembler, using the AORG directive, or by the Linker, using the PROGRAM <absolute value> directive.) The DVS7000 directory, contained on mag tape or hard disk, contains the following files: PROCS PROGRAM README ASM CONVRT LINK M$LC PROM QUIT G.S.1 Macro Assembler and Link Editor Installation G-32 1) If your CrossWare package is contained on magnetic tape, you must transfer it to a hard disc before you can use it. Mount the tape and enter the following: RD <CR> RESTORE DIRECTORY SEQUENTIAL ACCESS NAME: DIRECTORY PATHNAME: LISTING ACCESS NAME: OPTIONS: MTOl <dlrectory>.DVS7000 <directory>.LST7000 ADD This places the files on the tape into the directory <directory>.DVS7000. To create a hard disc copy, execute a Copy Directory command: CD <CR> The resulting directory is named DVS7000. 2) The directory DVS7000 may be used by: a) Copying it to the system disc, . b) Changing the directory name with the Modify File command (MFN), or c) Leaving it on the hard disc. 3) At this point, you should read the instructions in <directory>.DVS7000.­ README.

Appendix G - CrossWare Installation G.5.2 Executing the Macro Assembler To execute the TMS7000 Macro Assembler, enter: ASM. The following prompts will appear: ASSEMBLE 7000 SOURCE MODULE SOURCE FILE: OBJECT FILE: LISTING FILE: FOREGROUND/BACKGROUND: <access <access <access K name> name> name> The Macro Assembler creates defaults for the listing and object files and/or their extensions. The default extensions are:

• Source file - .ASM
• Listing file - .lST
• Object file - .MPO G.5.3 Executing the Link Editor To execute the TMS7000 Link Editor, enter: LINK. The following prompts will appear: LINK EDIT OBJECT MODULES CONTROL FILE: LINKED OBJECT FILE: LINK LISTING FILE: FOREGROUND/BACKGROUND: <access name> <access name> <access name> K The Link Editor creates defaults for the listing and object files and/or their extensions. The default extensions are:
• Control file - .CTl
• Linkmap file - .MAP
• Load file - .lOD G.5.4 Using the OX Conversion Utility To invoke the DX conversion utility, type: CONVRT. The following prompts will appear: 7000 TO 9900 FORMAT CONVERSION UTILITY REV 1.0 INPUT FILE: <access name> OUTPUT FILE: <access name> G.5.5 Using the OX PROM Utility To invoke the DX PROM utility, type: PROM. The following prompts will ap­ pear: PROM PROGRAMMING UTILITY CRU ADDRESS: <valid CRU address> INITIAL PROM TYPE: <valid PROM/EPROM ~ 990/12 CRU?: NO G-33

Appendix G - CrossWare Installation G-34

ADDR: Port A Data-Direction Register ALU: Arithmetic Logic Unit APORT: Port A Data Register assembler: Any program that converts mnemonic and symbolic machine code into machine language ASYNC: Communications Mode, bit 1 in the serial mode register (SMODE) Asynchronous Communication mode: A mode used by the serial port to communicate with peripheral devices. Requires framing bits but does not require a synchronizing clock. BPORT: Port B Data Register BRKDT: Break Detect, bit 6 in the serial port Status Register (SSTAT) C bit: Carry bit in the Status Register CDDR: Port C Data-Direction Register CHAR1, CHAR2: Number of Bits per Character, bits 2 and 3 in the serial mode register (SMODE) CLK: Serial Clock Source. bit 6 in serial control register 1 (SCTL 1 ) CPORT: Port C Data Register CRC: Customer Response Center CrossWare: Texas Instruments macro assemblers and linkers DDDR: Port D Data-Direction Register DDR: Data Direction Register Direct Memory Addressing mode: Uses a 16-bit address that contains an operand DIP: Dual-inline package directive: A mnemonic instruction to the assembler, executed during as­ sembly DPORT: Port D Data Register H-1

-H-2 Dual Register Addressing mode: Uses a source and a destination register as 8-bit operands EC1: Timer 1 event counter EC2: Timer 2 event counter ER: Error Reset, bit 4 of serial control register 0 (SCTLO). EVM: Evaluation module expression: A sequence of symbols, constants, and operators, to which a numerical value can be assigned during assembly Extended Addressing mode: An addressing mode which uses a 16-bit address FE: Framing Error, bit 6 of the serial port status register (SSTAT) FFE: form factor emulator; an EPROM or piggyback device which to emu­ lates or replaces a masked-ROM device Fosc: External oscillator frequency Full-Expansion mode: A TMS7000 operating mode which extends ad­ dressing capability to the full 64K-byte limit Halt mode: A low-power mode entered by the CMOS devices in which the on-chip timer logic is disabled I bit: Global interrupt enable bit (in the Status Register) Immediate Addressing mode: ~ Uses an immediate 8-bit address Indexed Addressing mode: Generates a 16-bit address by adding the contents of register B to a 16-bit direct memory address IOCNTO: I/O control register 0 IOCNT1: I/O control register 1 IOCNT2: I/O control register 2 Isosynchronous Communication mode: A hybrid communications pro­ tocol which combines features of Asynchronous and Serial I/O communi­ cations; uses framing bits and a serial clock link control file: Contains commands which control the link process linker: Collects and interconnects relocatable elements to produce an abso­ lute element mask option: A device option, such as a clock option, which is placed on a manufacturing template, or mask, copying the actual circuit onto the silicon device; cannot be changed by software. MC pin: Mode Control pin. When this pin is set to 1 (5 V), the Micro­ processor mode of device operation is entered

Microprocessor mode: A mode of operation intended for applications which do not justify the use of on-chip ROM. All memory accesses except for internal RAM and on-chip Peripheral File locations are addressed externally. MULTI: Multiprocessor mode, bit 0 of the serial mode register (SMODE) N bit: Sign bit in the status register NCRF: New Code Release Form OE: Overrun Error, bit 4 in the serial port status register (SSTAT) PC: Program Counter PE: Parity Error, bit 3 in the serial port status register (SSTAT) PEN: Parity Enable, bit 4 in the serial mode register (SMODE) Peripheral-ExPlinsion mode: An operating mode which allows use of on-chip ROM and also allows addressing off-chip locations (peripheral de­ vices) Peripheral File Addressing mode: Refers to instructions which perform I/O tasks; either the source or the destination is a peripheral file register Peripheral File instructions: MOVP, ANDP, ORP, XORP, BTJOP, and BTJZP PEVEN: Parity Even, bit 5 of the serial mode register (SMODE) PF: Peripheral File piggyback: A device used as a form-factor emulator for masked-ROM de­ vices PLA: Programmed logic Array PLCC: Plastic-leaded chip carrier Program Counter Relative Addressing mode: Used by all jump in­ structions; adds an offset to the PC value to form the address RF: Register File RTC: Regional Technology Center RXBUF: Receiver Buffer RXD: Receive Data, line A5 RXEN: Receiver Enable, bit 2 in serial control register 0 (SCTlO). RXRDY: Receiver Ready, bit 1 in the serial status register (SSTAT). RXSH F: RX Shift register SCAT: Strip Chip Architecture Technology SCLK: serial clock source, pin A6 SCTLO: Serial port control register 0 H-3-

-H-4 SCTL1: Serial port control register 1 Serial I/O Mode: A serial-port communication mode which uses an ex­ ternal clock to synchronize the receiver and the transmitter; Stop bits are also used - Single Register Addressing mode: Uses a single register that contains an 8-bit operand Single-Chip mode: An operation mode in which the device functions as a standalone microcomputer with no off-chip memory expansion bus SIO: Serial .1/0 or Communications mode, bit 6, serial mode register (SMODE) SLEEP: Sleep, bit 5, serial control register 1 (SCTL 1 ) SMODE: Sorial port mode register SP: Stack Pointer SST AT: Serial port status register ST: Status Register START: Timer 3 start bit 7, serial control register 1 (SCTL 1) STOP: Stop, bit 7, serial mode register (SMODE) TM P: Prefix for devices that conform to the final electrical specifications but have not completed quality and reliability verification TMS: Device prefix for fully qualified production devices TMX: Device prefix for experimental devices that are not representative of the device's final electrical specifications TXBUF: Transmitter Buffer. write-only PF register P23 TXD: Transmission data, uses line B3 TXEN: Transmit Enable, bit O. serial control register 0 (SCTLO) TXRDY: Transmitter Ready, bit 0, serial port Status Register (SSTAT) TXSH F: transmitter shift register T1 CTL: Timer 1 control register T1 CTLO: Timer 1 control register O/LSB capture reload register value T1 CTL1: Timer 1 control register 1 /MSB readout reload register T1 DATA: Timer 1 data register T1LSDATA: Timer 1 LSB decrementer latch/LSB decrementer value T1 MSDATA: Timer 1 MSB decrementer latch/MSB readout latch T10UT: Timer 1 output

T2CTL: Timer 2 control register T2CTLO: Timer 2 control register O/lSB capture latch value T2CTL1: Timer 2 control register 1/MSB readout reload register T2DATA: Timer 2 data register T20UT: Timer 2 output T2LSDATA: Timer 2 lSB decrementer latch/lSB decrementer value T2MSDATA: Timer 2 MSB decrementer latch/MSB readout latch T3DATA: Timer 3 data register T3EN B: Timer 3 Enable, bit 2, serial control register 1 (SCTl1) T3FLG: Timer 3 Flag, bit 3, serial control register 1 (SCTl1) UR: Software UART reset, bit 6, serial control register 0 (SCTlO) Wake-Up mode: A low-power mode entered by the CMOS devices in which the oscillator and timer logic remain active WU bit: Wake- Up, bit 4, serial control register 1 (SCTl1) WUT: Wake-Up temporary flag XDS: Extended Development Support Z bit: zero bit, Status Register i H_'..J.·. -,

A absolute code 5-14, 7-2 ADC Add with Carry Instruction 6-10, 6-16,9-35 ADD Add Instruction 6-10, 6-17, 9-35 addition instructions 6-16,6-17,6-30, 6-38, 9-35, 9-48 ADDR 3-16 address space 3-3 address/data bus 3-6, 3-10, 3-19 addressing modes 6-3 Direct Memory 6-7 Dual Register 6-4 Immediate 6-6 Indexed 6-8 Peripheral File 6-5 Program Counter Relative 6-6 Register File Indirect 6-7 Single Register 6-4 ALATCH 3-10,3-19 AND Logical AND Instruction 6-10,6-18 ANDP 3-62 AND Peripheral Register 3-17 AN 0 Peripheral Register Instruction 3-62,6-10,6-19 APORT 3-15 architecture See Section 3 arithmetic operators 5-8, 8-6 SASG Assign Values to Variable Components Verb 8-7,8-18 assembler 5-1 -5-59, 7-1 assembler cross-reference listing 5-52 assembler output 5-48 assembler source listing 5-48 assembler symbol table 8-7 assembly language 5-1, 6-1 -6-70 Index assembly process 5-1 assembly-time constants 5-5 AST 8-7 ASYNC bit 3-55 Asynchronous Communication attribute component (of a variable) 8-8 A6/SCLK/EC2 3-10,3-45,3-47 B bidirectional I/O logic 3-7 binary integers 5-4 binary mode (macro variables) 8-8 Boolean operators 8-6 BPORT 3-16 BR Branch Instruction 6-11,6-20,9-40 breakpoint/trace/time board 10-7 BRKDT bit 3-59 BTJO Bit Test and Jump If One Instruction 6-10,6-21 BTJOP Bit Test and Jump If One - Peripheral Instruction 6-10, 6-22 BTJZ Bit Test and Jump If Zero Instruction 6-10,6-23 BTJZP Bit Test and Jump If Zero - Peripheral Instruction 6-11, 6-24 bus activity tables A-1 bus control signals 3-10, 3-19 ALATCH 3-10 CLKOUT 3-10 ENABLE- 3-1 ° R/W- 3-1 ° BYTE 5-48 B3/TXD 3-1 ° Index-1

c C (carry) bit 3-4,6-27,6-60,9-33 CAll Call Instruction 6~11, 6-25, 9-37 capture latch 3-44 cascade bit 3-47 CDDR 3-16 ceramic resonator 4-7, 4-14 character constants 5-5 character sets See Appendix 0 character strings 5-7 CHAR1, CHAR2 bits 3-55 ClK bit 3-57,3-61 ClKIN 12-6 ClKOUT 3-10,.3-19 clock options 3-22-3-25, 12-6 +2 option 12-6 +4 option 12-6 crystal oscillator 3-24 R-C oscillator 3-24 clock source 3-65 ClR Clear Instruction 6-11. 6-26 ClRC Clear the Carry Bitlnstruction 6-11, 6-27 CMODE bit 3-55 CMOS devices 3-44 See also Section 2 and Section 4 clock options 3-24 CMP Compare Instruction 6-11, 6-28, 9-33 CMPA Compare Accumulator Extended In- struction 6-11,6-29,9-33 command field 5-2, 5-3 comment field 5-2, 5c3 common-relocatable code 5-20, 7-2 communication mode 3-57 Communication modes 3-51 Asynchronous 3-51, 3-55, 3-65, 9-19 Isosynchronous 3-51, 3-55, 3-66, 9-19 Serial I/O 9-19 compare instructions 6-28, 6-29 conditional jumps 6-41 conditional processing 8-20, 8-22, 8-23 constants 5-4, 5-8, 8-6 assembly-time 5-5 characters . 5-5 Index-2 hexadecimal integers 5-5 counter 3-74 CPORT 3-16 cross-assembler 10-2 CrossWare ordering information 12-16 CrossWare installation G-1 IBM/CMS G-27. IBM/MVS G-15 list of supported operating systems G-1 MS/PC-DOS G-8 T1990/DX10 G-32 VAXNMS G-2 crystal clock source 3-22 crystal oscillator clock option 3-24, 12-6 D DAC Decimal Add with Carry . Instruction 6-11, 6-30 DATA 5-48 Data Register 3-16 Data-Direction Register 3-16 data-relocatable code 5-27, 7-2 DOOR 3-16,3-20 DEC Decrement Instruction 6-11,6-31 DECO Decrement Double Instruction 6-11, 6-32 decimal integer constants 5-4 decimal integers 5-4 DEF 5-48, 7-6 $DEF keyword 8-11 defining symbols 7-6 development support 10-1 -10-11 ordering information 12-16 device initialization 3-26 DINT Disable Interrupts Instruction 6-11, 6-33 Direct Memory Addressing mode 6-7, 9-37 directives 5-12 for linking programs 5-12 DEF 5-23 lOAD 5-33 REF 5-40 SREF 5-43 miscellaneous 5-12 COPY 5-19

that affect assembler output 5-12 lOT 5-31 LIST 5-32 OPTION 5-36 PAGE 5-37 TITL 5-45 UNL 5-46 that affect the location counter 5-12 AORG 5-14 BES 5-15 BSS 5-16 CEND 5-18 CSEG 5-20 DEND 5-24 DORG 5-25 DSEG 5-27 EVEN 5-30 PEND 5-38 PSEG 5-39 RORG 5-41 that initialize constants 5-12 BYTE 5-17 DATA 5-22 EQU 5-29 TEXT 5-44 divide-by-2 clock option 3-22, 12-6 divide-by-4 clock option 3-22, 12-6 division instructions 9-55, 9-56, 9-57 DJNZ Decrement Register and Jump If Not Zero Instruction 6-34 Decrement Relative and Jump If Not Zero Instruction 6-12 dollar sign ($) 5-6 DPORT 3-20 DSB Decimal Subtract with Borrow Instruc-, tion 6-12,6-35 Dual Register Addressing mode 6-4 dummy section 5-25 E EINT Enable Interrupts Instruction 3-35, 6-12, 6-36 $ELSE See also $IF Alternate Conditional Block Verb 8-22 emulation 10-2 ENABLE- 3-10,3-19 END 5-48,8-5 End Macro Definition Verb 8-24 END linker command 7-4 $ENDIF . See also $IF Terminate Conditional Block Verb 8-23 EPROM devices 2-12, 2-18, 2-19, 2-22, 2-23 EQU 5-48 ER bit 3-57 error messages assembler 5-49, 5-51 macros 8-29 evaluation modules 10-8-10-10 evaluation of arithmetic expressions 5-9 event counter 3-38 EVM 10-8-10-10 ordering information 12-16 expressions 5-8 arithmetic evaluation 5-9 using arithmetic operators 5-8 using externally defined symbols 5-11 using logical operands 5-9 using parentheses 5-9 using relocatable symbols 5-10 well-defined 5-10 Extended addressing modes 6-3 Direct 9-37 Indexed 9-37 Register File Indirect 9-37 Extended Development Support (XDS) 10-2-10-7 external clock 3-16, 12-6 external clock source 3-22, 3-24 External Event-Counter mode 3-16 external interrupts 3-35, 3-36 external references 5-58 externally defined symbols 5-11 F FE bit 3-59 FORMAT linker command 7-4 frame bit 3-65 Full-Expansion mode 3-20 memory map 3-21 Index-3

G global interrupt enable bit 3-4 H Halt mode 3-25 hardware UART 3-51 -3-78, 9-27 hexadecimal integer constants 5-5 host interface 10-2 I (global interrupt enable) bit 3-4, 3-35, 9-33 . I/O control registers 3-32 I/O ports 3-6-3-9 Full-Expansion mode 3-20 Peripheral-Expansion mode 3-18 Single-Chip mode 3-15 IADD 3-59 IBM/CMS G-27 IBM/MVS G-15 IDLE 3-25 Idle Until Interrupt Instruction 3-25, 6-12,6-37 lOT 5-48,7-6 $IF Begin Conditional Block Verb 8-6, 8-20 Immediate Addressing mode 3-17 6-6 INC ' Increment Instruction 6-12,6-38 INCLUDE linker command 7-4 Indexed Addressing mode 6-8, 9-37 instruction timing A-1 Intel protocol 3-71 Intel 8051 3-51 interrupts 3-26-3-37,9-41 CPU interface to interrupt logic 3-31 DINT instruction 6-33 edge-sensitive 3-30 EINT instruction 6-36 external 3-35, 3-36 level 0 3-26 . level-sensitive 3-30 logic for maskable interrupts 3-30 multiple 3-35 priority 3-26 RETI instruction 6-53 Index-4 timer interrupts 3-49 INTn ACK 3-31 INTn ACTIVE 3-31 INTn clear bit 3-34 INTn enable bit 3-33 INTn flag bit 3-33, 3-49 INT4 3-58 INV Invert Instruction 6-12,6-39 10CNTO register 3-11, 3-15, 3-18, 3-20, 3-21,3-32 IOCNT1 register 3-32, 3-33 lOCNT2 register ·3-32, 3-34 IPC 9-36 Isosynchronous Communication J J<cnd> Jump on Condition Instruction 6-41 JC 6-12 JEQ 6-12 JGE 6-12 JGT 6-12 JHS 6-12 JL 6-12 JMP Jump Unconditional Instruction 6-12, 6-40 JNC 6-12 JNE 6-12 JNZ 6-12 JP 6-12 JPZ 6-12 jump instructions 6-21, 6-22, 6-23, JZ 6-12 K keywords 8-11,8-12 . parameter attribute components 8-12 $PCALL 8-12 $POPL 8-12 $PSYM 8-12 symbol attribute components 8-11 $DEF 8-11 $MAC 8-11 $REF 8-11 $REL 8-11

L $STR 8-11 $UNDF 8-11 label field 5-2, 5-3, 5-6 LDA Load Register A Instruction 6-12, 6-42 LDSP , Load Stack Pointer Instruction 6-13, 6-43 length component (of a variable) 8-8 link control file 7-3 Link Editor 7-1-7-7 linker commands 7-3 linking directives 7-6 DEF 5-23, 7-6 IDT 5-31,7-6 REF 5-40, 7-6 SREF 5-43, 7-6 linking program modules 7-1 LIST 5-48 Location Counter 5-3 logical AND 8-6 logical NOT 8-6 logical operands 5-9 logical OR 8-6 low-power modes 3-25,3-44 Halt 3-25 M Halt mode 3-25 Wake- Up 3-25 Wake-Up mode 3-25 $MAC keyword 8-11 MACLIB files 8-2 $MACRO Macro Definition Verb 8-2,8-5,8-7, 8-16 macro assembler 5-1 macro libraries 8-2 macro symbol table 8-7 macros 8-1 assembler symbol table 8-7 assigning parameter values 8-13 8-16 ' calls 8-1 conditional processing 8-20, 8-22, 8-23 constants 8-6 declaring variables 8-17 definition 8-2,8-16 error messages 8-29 keywords 8-11 MACLI B files 8-2 macro libraries 8-2 MLIB directive 8-2 MLIST files 8-3 MST 8-8 search order 8-2 strings 8-6 substitution 8-1 symbol components 8-10 symbols 8-7 variable components 8-8 variables 8-7 binary mode access 8-8 definition 8-7 macro symbol table 8-7 parameters 8-7 string mode access 8-8 unqualified variables 8-9 variable qualifiers 8-9 verbs 8-15 mask options 3-22, 12-6 mechanical data 12-7 memory modes 3-11-3-21 Full-Expansion 3-20 Microprocessor 3-21 Microprocessor mode 9-2 Peripheral-Expansion 3-18 Single-Chip 3-15 Microprocessor mode 3-21 interface example 9-2 memory map 3-21 MLIB 8-2 MLIST files 8-3 mnemonics 5-1 Mode Control (MC) pin 3-11 model statements 8-25 Motorola protocol 3-69 Motorola 6801 3-51 MOV Move Instruction 6-13,6-44 MOVD Move Double Instruction 6-13,6-45 move instructions 6-44, 6-45, 6-46 MOVP 3-15 Move to/from Peripheral Register In­ struction 3-18, 6-13, 6-46 MPY Multiply Instruction 6-13, 6-47, 9-39 MS/PC-DOS G-8 Index-5

MST 8-7,8-8 MULTI bit 3-54 multiple interrupts 3-35 multiplication instructions 6-47,9-39, 9-54 multiprocessing 10-6 multiprocessor communication modes 3-68 Intel protocol 3-71 Motorola protocol 3-69 mUltiprocessor protocols 3-51, 3-54 Inte! 8051 3-51 Motorola 6801 3-51 N N (sign) bit 3-4, 9-33 naming a program module 7-6 NMOS devices See Section 2 and Section 4 NMOS to CMOS Conversion Guide B-1 NOP No Operation Instruction 6-13,6-48 o object code 5-48, 5-53, 5-58 object program 5-1 object record format 5-57 OE bit 3-59 offset calculation 6-6 on-chip RAM 3-3 on-chip timer/event counter 3-10 operand field 5-2, 5-3, 5-6, 5-8 operators 8-6 OR Logical OR Instruction 6-13, 6-49 ORP OR Peripheral Register 3-17 OR Peripheral Register Instruction 3-62,6-13,6-50 oscillator options 3-24, 12-6 output data flip-flops 3-26 Index-6 p packaging 12-7 PAGE 5-48 parameter attribute component keywords 8-12 parameters 8-13 as macro variables 8-7 parentheses 5-9 parity enable 3-55 PC 3-5 $PCALL keyword 8-12 PCH (Program Counter High) 3-5 PCL (Program Counter Low) 3-5 PE bit 3-59 PEN bit 3-55 Peripheral File 3-3 Peripheral-Expansion mode 3-18 memory map 3-18 Peripheral-File Addressing mode 6-5 Peripheral-File instructions 3-3, 3-17, 9-43 PEVEN bit 3-55 PF 3-3 piggyback devices 2-17,2-19 POP POP from Stack Instruction 6-13, 6-14,6-51 $POPL keyword 8-12 port symbols 5-6 power-down mode 3-25 power-up reset 3-29 predefinded symbols 5-6 prescaler 3-48. 3-74 PRE3(1), PRE3(0) bits 3-60 Program Counter 3-5 Program Counter Relative Adressing mode 6-6 programmable timer/event counters 3-38-3-50 program-relocatable code 5-41, 7-2 prototyping 12-2 prototyping devices 2-18,2-19,2-22, 2-23,10-11 $PSYM keyword 8-12 Pulse flip-flop 3-30, 3-33 PUSH Push on Stack Instruction 6-14, 6-52

R RfW- 3-10,3-19 RAM 3-3 R-C oscillator clock option 3-24, 12-6 Realtime Clock mode 3-45 receiver 3-51 receiver buffer 3-62 REF 5-48, 7-6, 7-7 $REF keyword 8-11 referencing externally defined symbols 5-40, 5-43, 7-7 Register A 3-3, 6-42, 6-61, 6-66 Register B 3-3, 3-4, 6-67, 6-68 Register File 3-3 Register File Indirect Addressing mode 6-7,9-37 register symbols 5-6 registers 3-3-3-5 write-only 9-43 $REl keyword 8-11 relational operators 8-6 relocatable code 7-2 relocatable symbols 5-10 relocation types 5-41 common-relocatable 5-20, 5-27, 5-41 data-relocatable 5-20, 5-27, 5-41 program-relocatable 5-20,5-27, 5-41 RETI Return from Interrupt Instruction 3-35, 6-14, 6-53 RETS Return from Subroutine Instruction 6-14,6-54,9-38 RF 3-3 Rl RlC Rotate left Instruction 6-14, 6-55, 9-35 Rotate left Through Carry Instruction 6-14,6-56,9-35 rotate instructions 6-55,6-56,6-57, 6-58,9-35 RR Rotate Right Instruction 6-14,6-57, 9-35 RRC Rotate Right Through Carry Instruction 6-14, 6-58, 9-35 RX 3-51, 3-62 RXBUF 3-55 RXBUF register 3-53,3-62 RXD bit 3-16, 3-53 RXEN 3-57 RXRDY 3-62 RXRDY bit 3-59 RXSHF register 3-53 RO 3-3 R1 3-3 s SBB Subtract with Borrow Instruction 6-14, 6-59, 9-35 SClKEN bit 3-57 SCTlO 3-56 SCTlO register 3-53, 3-56 ER 3-57 PRE3(1). PRE3(0) 3-60 RXEN 3-57 SClKEN 3-57 SPH 3-57 TXEN 3-56 UR 3-57 SCTl1 register 3-60 ClK 3-61 SLEEP 3-61 START 3-61 T3ENB 3-60 T3FlG 3-61 WU 3-61 search order (macros) 8-2 Serial If 0 mode 3-51,3-57,3-67,9-19 serial port 3-51 -3-78, 9-27 Asynchronous Communication mode 3-51 Communication modes 3-54 hardware UART example 9-19 initialization 3-72 interrupts 3-78 INT4 3-78 Isosynchronous Communication mode 3-51 multiprocessor protocols 3-51, 3-54 Index-7

RXBUF 3-53,3-62 SCTlO 3-53 SCTl1 3-60 SMODE 3-53, 3-54 SSTAT 3-53,3-58 TXBUF 3-53,3-62 T3DATA 3-53,3-61 Serial I/O 3-51 Serial I/O mode 3-51 software UART example 9-19 4-80 serial port communication modes 3-65 SETC Set Carry Instruction 6-14, 6-60 SE70CP160 4-72,4-75,10-11 key features 2-22 pin descriptions 2-26 pinouts 2-25 SE70CP160 devices external interrupts 3-35 SE70CP162 4-76,4-8~ 10-11 key features 2-23 pin descriptions 2-26 pinouts 2-25 SE70CP162 devices external interrupts 3-35 SE70P162 4-2~4-3~ 10-11 key features 2-19 pin descriptions 2-21 pinouts 2-20 SE70P162 devices external interrupts 3-35 SE77C42 4-66 key features 2-24 shifting 9-39 sign bit 3-4 Single Register Addressing mode 6-4 Single-Chip mode 3-3,3-10,3-15 memory map 3-15 SLEEP bit 3-61, 3-68 SMODE 3-56 SMODE register 3-53, 3-54 ASYNC 3-55 CHAR1, CHAR2 3-55 CMODE 3-55 MULTI 3-54 PEN 3-55 PEVEN 3-55 STOP 3-55 software UART 9-20 SOURCE 3-45 source program 5-1 source statement format 5-2, 5-48 Index-8 SP 3-4 SPH bit 3-57 SREF 5-48,7-6,7-7 SSTAT register 3-53,3-58 BRKDT 3-59 FE 3-59 IADD 3-59 OE 3-59 PE 3-59 RXRDY 3-59 TXE 3-59 TXRDY 3-58 ST 3-4 STA Store Register A Instruction 6-15, 6-61 stack 3-4, 9-36 stack operations 3-4, 6-51, 6-52, 6-62, 9-36,9-53 initialization 3-4 Stack Pointer 3-4, 6-43, 6-62 initialization after reset 3-29 START bit 3-61, 3-65 Status Register 3-4, 9-33 carry bit 3-4 global interrupt enable bit 3-4 sign bit 3-4 zero bit 3-4 STOP bit 3-55, 3-65 $STR keyword 8-11 string component (of a variable) 8-8 string mode (macro variables) 8-8 strings 5-5, 8-6 single quotes 5-5 STSP Store Stack Pointer Instruction 6-15, 6-62 SUB Subtract Instruction 6-15,6-63, 9-35 subroutine instructions 6-25, 6-54, 6-65, 9-37 subtraction instructions 6-31, 6-32, SWAP Swap Nibbles Instruction 6-15, 6-64,9-35 symbol attribute component keywords 8-11 symbol components (of a macro variable) 8-10 symbolic addressing 5-47 symbols 5-5, 5-6, 5-8 character string 5-7 externally defined 5-11

T tag characters 5-54-5-57 TASK linker command 7-4 terms (as symbols) 5-7 TEXT 5-48 TI990jDX10 G-32 timer clock 3-48 timer interrupts 3-49 timer output function 3-50 Timer 1 3-10, 3-38, 3-39 Timer 1 capture latch 3-44 Timer 1 data and control registers 3-40 Timer 2 3-10, 3-16, 3-38, 3-41 Timer 2 data and control registers 3-42 Timer 3 3-38, 3-51, 3-53: 3-61, 3-73 TITL 5-48 TMS70CTxO devices pin descriptions 2-10 pi'nouts 2-9 TMS70CT20 and TMS70CT40 4-45 TMS70CxO devices 4-31, 4-44 clock options 3-24 external interrupts 3-35 interrupts 3-26 key features 2-5, 2-6 memory map 3-11 pin descriptions 2-8 pinouts 2-7 port configuration 3-7 timer operation 3-48 TMS70Cx2 devices 4-49, 4-64 clock options 3-25 external interrupts 3-35 initialization routine 3-28 interrupts 3-26 key features 2-15 memory map 3-12 peripheral memory map 3-14 pin c;lescriptions 2-17 pinouts 2-16 Port A 3-10 port configuration 3-9 timer operation 3-49 timer output function 3-50 TMS70xO devices 4-2, 4-7 external interrupts 3-35 interrupts 3-26 key features 2-4 memory map 3-11 pin descriptions 2-8 pinouts 2-7 port configuration 3-7 timer operation 3-48 TMS70x1 devices C-1-C-6 TMS70x2 devices 4-8,4-15,9-27 external interrupts 3-35 initialization routine 3-28 interrupts 3-26 key featu res 2 -11 memory map 3-12 peripheral memory map 3-13 pi n descri ptions 2 -1 4 pinouts 2-13 PortA 3-10 port configuration 3-8 timer operation 3-48 TMS7000 family devices summary 2-1 TMS77C42 4-65 TMS77C82 pin descriptions 2-17 pinouts 2-16 TMS7742 4-16,4-24,10-11 external interrupts 3-35 key features 2-12,2-18 pin descriptions 2-14 pinouts 2-13 TM70CxO devices peripheral memory map 3-12 TM70xO devices peripheral memory map 3-12 transmitter 3-51 transmitter buffer 3-62 TRAP Trap to Subroutine Instruction 6-15, 6-65,9-37 TSTA Test Register A Instruction 6-15, 6-66 TSTB Test Register B Instruction 6-15, 6-67 TX 3-51, 3-62 TXBUF 3-55 TXBUF register 3-53, 3-62 TXD bit 3-53 TXE bit 3-59 TXEN bit 3-56 TXRDY bit 3-58 TXSHF register 3-53 T1CTL 3-25,3-43,3-48 T1 DATA 3-43,3-48 T2CTL -3-43,3-48 T2DATA 3-43, 3-48 Index-9

T3DATA register 3-53,3-61,3-74 T3EN B bit 3-60 T3FLG bit 3-61 u UART 3-51 -3-78, 9-20 $UNDF keyword 8-11 UNL 5-48 unqualified variables (in macros) 8-9 UR bit 3-57 USART 3-51 v value component (of a variable) 8-8 WAR Declare Variables Verb 8-17 variable components attribute 8-8 length 8-8 string 8-8 value 8-8 variable qualifiers 8-9 variables 8-7 VAX/VMS G-2 verbs 8-15 $ASG 8-18 $ELSE 8-22 $END 8-24 $ENDIF 8-23 $IF 8~20 $MACRO 8-16 Index-10 $VAR 8-17 w Wake-Up mode 3-25 well-defined expressions 5-10 write-only registers 9-43 WU bit 3-61, 3-69 WUT flag 3-69 x XCHB Exchange with Register B Instruction 6-15, 6-68 XDS ordering information 12-16 XDS emulator 10-2-10-7 XOR Exclusive Or Instruction 6-15,6-69 XORP 3-62 Exclusive OR Peripheral Register In­ struction 3-62,6-15,6-70 XOR Peripheral Register 3-17 XTAL1 3-22,12-6 XTAL2 12-6 XTAL2/CLKIN 3-22 z Z (zero) bit 3-4,9-33

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CANADA: Nepean, Ontario (613) 726·1970 Customer Response Center TOLL FREE: (800) 232-3200 OUTSIDE USA: (214)995-6611 (8:00 a.m. - 5:00 p.m. CST) TI AUTHORIZED DISTRIBUTORS IN USA Arrow Electronics Diplomat Electronics General Radio Supply Company Graham Electronics Hall·Mark Electronics Kierulff Electronics Marshall Industries Milgray Electronics Newark Electronics Time Electronics R.V. Weatherford Co. Wyle Laboratories Zeus Component, Inc. (Military) TI AUTHORIZED DISTRIBUTORS IN CANADA Arrow Electronics Canada Future Electronics TI AUTHORIZED DISTRIBUTORS IN USA -OBSOLETE PRODUCT ONLY­ Rochester Electronics, Inc. Newburyport, Massachusetts (617) 462·9332 ALABAMA: Arrow (205) 837-6955; Hall-Mark (205) 837-8700; KieruHf (205) 883-6070; Marshall (205) 881·9235. ARIZONA: Arrow (602) 968-4800; Hall-Mark (602) 437-1200; Kierulff (602) 437-0750; Marshall (602) 968-6181; Wyle (602)866-2888 CALIFORNIA: Los Angeles/Orange County: Arrow (818) 701·7500, (714) 838-5422; Hall-Mark (818) 716-7300, (714) 669-4700, (213) 217-8400; Kierulff (213) 725-0325, (714) 731-5711, (714) 220-6300; Marshall (818) 407·0101, R.V. Weatherford (714) 966-1447, (213) 849-3451, Wyle (213) 322-8100, (818) 880-9001, (714) 863-9953; Zeus (714) 632-6880; Sacramento: Arrow (916) 925-7456; Hall-Mark (916) 722·8600; Marshall (916) 635-9700; Wyle (916) 638-5282; San Diego: Arrow (619) 565·4800; Hall-Mark (619) 268-1201; Kierulff (619) 278·2112; . Marshall (619) 578-9600; Wyle (619) 565-9171; San Francisco Bay Area: Arrow (408) 745-6600; (415) 487-4600; Hall-Mark (408)946-0900; Kierulff (408) 971-2600; Marshall (408) 943-4600: Wyte (408) 727-2500; Zeus (408) 998·5121. COLORADO: Arrow (303) 696-1111; Hall·Mark (303) 790-1662; Kierulff (303) 790-4444; Wyle (303) 457-9953. CONNECTICUT: Arrow (203) 265-7741; Diplomat (203) 797-9674; Hall·Mark (203) 269-0100; Kierulff (203) 265-1115; Marshall (203) 265-3822; Milgray (203) 795-0714. FLORIDA: Ft Lauderdale: Arrow (305) 429·8200; Diplomat (305) 974-8700; HalJ-Mark (305) 971-9280; Kierulff (305) 486·4004; Marshall (305) 928-0661; Orlando: Arrow (305) 725-1480; Hall-Mark (305) 855-4020; Marshall (305) 841-1878; Milgray (305) 647-5747; Zeus (305) 365-3000; Tampa: Arrow (813) 576-8995; Diplomat (813) 443·4514; Hall·Mark (813) 530-4543; Kierulff (813) 576-1986. GEORGIA: Arrow (404) 449-8252; Hall-Mark (404) 447-8000; Kierulff (404) 447-5252; Marshall (404) 923-5750 TEXAS INSTRUMENTS ILLINOIS: Arrow (312) 397-3440; Diplomat (312) 595-1000; Hall-Mark (312) 860-3800; Kierulff (312) 250-0500; Marshall (312) 490·0155; Newark (312) 784-5100. INDIANA: Indianapolis: Arrow (317) 243-9353; Graham (317) 634-8202; Hall-Mark (317) 872-8875; Marshall (317) 297-0483; Ft. Wayne: Graham (219) 423-3422. IOWA: Arrow (319) 395-7230 KANSAS: Kansas City: Arrow (913) 541-9542; Hall-Mark (913) 888·4747; Marshall (913) 492·3121. MARYLAND: Arrow (301) 995-0003; Diplomat (301)995-1226; Hall-Mark (301)988-9800; Kierulff (301) 636-5800; Milgray (301) 995-6169; Marshall (301) 840·9450; Zeus (301) 997-1118. MASSACHUSETTS: Arrow (617) 933-8130; Diplomat (617)667-4670; Hall-Mark (617)667-0902; Kierultt (617) 667-8331; Marshall (617) 272·8200; Time (617) 532-6200; Zeus (617) 863·8800. MICHIGAN: Detroit: Arrow (313) 971·8220; Marshall (313) 525-5850; Newark (313) 967-0600; Grand Rapids: Arrow (616) 243-0912. MINNESOTA: Arrow (612) 830-1800; Hall·Mark (612) 941-2600; Kierulff (612) 941-7500; Marshall (612) 559·2211. MISSOURI: St. Louis: Arrow (314) 567·68S8; Hall-Mark (314) 291-5350; Kierulff (314) 739-0855. NEW HAMPSHIRE: Arrow (603) 668-6968. NEW JERSEY: Arrow (201) 575-5300, (609) 596-8000; Diplomat (201) 785-1830; General Radio (609) 964-8560; Hall-Mark (201)575-4415, (609)235-1900; Kierulff (201) 575-6750, (609) 235-1444; Marshall (201)882·0320, (609)234-9100; Milgray (609) 983-5010. NEW MEXICO: Arrow (505) 243-4566. NEW YORK: Long Island: Arrow (516) 231-1000; Diplomat (S16) 454-6400; Hall-Mark (516) 737-0600; Marshall (516) 273·2053; Milgray (516) 420-9800; Zeus (914) 937-7400; Rochester: Arrow (716) 427-0300; Marshall (716) 235·7620; Diplomat (716) 359-4400; Syracuse: Arrow (315) 652-1000; Marshall (607) 798-1611. NORTH CAROLINA: Arrow (919) 876-3132, (919) 725-8711; Hall-Mark (919) 872.Q712; Kierulff (919) 872·8410; Marshall (919) 878-9882. OHIO: Cleveland: Arrow (216) 248-3990; Hall-Mark (216) 349·4632; Kierulff (216) 831-5222; Marshall (216) 248-1788. Columbus: Arrow (614) 885-8362; Hall-Mark (614) 888·3313; Dayton: Arrow (513) 435-5563; Graham (513) 435-8660; Kierulff (513) 439-0045; Marshall (513) 236-8088_ OKLAHOMA: Arrow (918)665-7700; Kierulff (918) 252·7537. OREGON: Arrow (503) 684·1690; Kierulff (503)641-9153; Wyle (503)640-6000; Marshall (503) 644-5050. PENNSYLVANIA: Arrow (412) 856-7000, (215) 928-1800; General Radio (215) 922·7037_ RHODE ISLAND: Arrow (401) 431-0980 TEXAS: Austin: Arrow (512) 835-4180; Hall-Mark (512)258-8848; Kierulff (512) 835-2090; Marshall (512) 837-1991; Wyle (512) 834-9957; Dallas: Arrow (214) 380-6464; Hall-Mark (214)553-4300; Kierulff (214) 343-2400; Marshall (214) 233-5200; Wyle (214) 235-9953; Zeus (214) 783-7010; Houston: Arrow (713) 530-4700; Hall-Mark. (713) 781-6100; Kierulff (713) 530·7030; Marshall (713) 895-9200; Wyle (713)879-9953. UTAH: Arrow (801) 972-0404; Diplomat (801) 486-4134; Hall·Mark (801) 268·3779; KieruJff (801) 973-6913; Wyle (801) 974-9953. WASHINGTON: Arrow (206) 643-4800; Kierullf (206) 575-4420; Wyle (206) 453-8300; Marshall (206) 747-9100. WISCONSIN: Arrow (414) 792-0150; Hall-Mark (414) 797-7844; Kierulff (414) 784-8160; Marshall (414) 797-8400. CANADA: Calgary: Future (403) 235-5325; Edmonton: Future (403) 438-2858; Montreal: Arrow Canada (514) 735-5511; Future (514) 694-7710; Ottawa: Arrow Canada (613) 226-6903; Future (613) 820-8313; Quebec City: Arrow Canada (418) 687-4231; Toronto: Arrow Canada (416) 661-0220; Future (416) 638-4771; Vancouver: Future (604) 294-1166 Winnipeg: Future (204) 339·0554 sa

Printed in U .S.A . 1603672·9702 -Ij} TEXAS INSTR U MENTS SPND001C