TMS664164

TMS664414 TI | Alldatasheet

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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization... 1048576 x 16 Bits x 4 Banks 2097152 x 8 Bits x 4 Banks 4194304 x 4 Bits x 4 Banks /C00683.3-V Power Supply (± 10% Tolerance) /C0068Four Banks for On-Chip Interleaving for x8/x16 (Gapless Access) Depending on Organizations /C0068High Bandwidth – Up to 125-MHz Data Rates /C0068Burst Length Programmable to 1, 2, 4, 8 /C0068Programmable Output Sequence – Serial or Interleave /C0068Chip-Select and Clock-Enable for Enhanced-System Interfacing /C0068Cycle-by-Cycle DQ Bus Mask Capability /C0068Only x16 SDRAM Configuration Supports Upper-/Lower-Byte Masking Control /C0068Programmable CAS Latency From Column Address /C0068Performance Ranges: /C0068Pipeline Architecture (Single-Cycle Architecture) /C0068Single Write/Read Burst /C0068Self-Refresh Capability (Every 16 /C0109s) /C0068Low-Noise, Low-Voltage Transistor-Transistor Logic (LVTTL) Interface /C0068Power-Down Mode /C0068Compatible With JEDEC Standards /C006816K RAS-Only Refresh (Total for All Banks) /C00684K Auto Refresh (Total for All Banks)/64 ms /C0068Automatic Precharge and Controlled Precharge /C0068Burst Interruptions Supported: – Read Interruption – Write Interruption – Precharge Interruption /C0068Support Clock-Suspend Operation (Hold Command) /C0068Intel PC100 Compliant (-8 and -8A parts) SYNCHRONOUS CLOCK CYLE TIME ACCESS TIME CLOCK TO OUTPUT REFRESH INTERVAL tCK3 tCK2 tAC3 tAC2 tREF ’664xx4-8 8 ns 10 ns 6 ns 6 ns 64 ms ’664xx4-8A 8 ns 15 ns 6 ns 7.5 ns 64 ms ’664xx4-10 10 ns 15 ns 7.5 ns 7.5 ns 64 ms

description

The TMS664xx4 series are 67108864-bit synchronous dynamic random-access memory (SDRAM) devices which are organized as follow: /C0068Four banks of 1 048 576 words with 16 bits per word /C0068Four banks of 2097152 words with 8 bits per word /C0068Four banks of 4194304 words with 4 bits per word All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface. The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed microprocessors and caches. The TMS664xx4 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP) (DGE suffix). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998

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TMS664xx4 (LVTTL) DGE PACKAGE (TOP VIEW) 4M x 16 8M x 8 16M x 4 VCC VCC VCC 1 54 VSS VSS VSS DQ0 DQ0 NC 2 53 NC DQ7 DQ15 ROW ADDR COL ADDR VCCQ VCCQ VCCQ 3 52 V SSQ VSSQ VSSQ x4 A0–A13 A0–A9 DQ1 NC NC 4 51 NC NC DQ14 x8 A0–A13 A0–A8 DQ2 DQ1 DQ0 5 50 DQ3 DQ6 DQ13 x16 A0–A13 A0–A7 VSSQ VSSQ VSSQ 6 49 V CCQ VCCQ VCCQ DQ3 NC NC 7 48 NC NC DQ12 A10 Auto Precharge DQ4 DQ2 NC 8 47 NC DQ5 DQ11 VCCQ VCCQ VCCQ 9 46 V SSQ VSSQ VSSQ BANKS BANK-SELECT DQ5 NC NC 10 45 NC NC DQ10 BANKS ADDRESS DQ6 DQ3 DQ1 11 54-Pin 44 DQ2 DQ4 DQ9 4 A13–A12 VSSQ VSSQ VSSQ 12 Plastic 43 V CCQ VCCQ VCCQ DQ7 NC NC 13 TSOP–II 42 NC NC DQ8 VCC VCC VCC 14 (Pitch = 0.8 mm) 41 V SS VSS VSS DQML NC NC 15 40 NC NC NC W W W 16 39 DQM DQM DQMU CAS CAS CAS 17 38 CLK CLK CLK RAS RAS RAS 18 37 CKE CKE CKE CS CS CS 19 36 NC NC NC A13, BS0 A13, BS0 A13, BS0 20 35 A11 A11 A11 A12, BS1 A12, BS1 A12, BS1 21 34 A9 A9 A9 A10, AP A10, AP A10, AP 22 33 A8 A8 A8 A0 A0 A0 23 32 A7 A7 A7 A1 A1 A1 24 31 A6 A6 A6 A2 A2 A2 25 30 A5 A5 A5 A3 A3 A3 26 29 A4 A4 A4 VCC VCC VCC 27 28 V SS VSS VSS

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PIN NOMENCLATURE W Write Enable RAS Row-Address Strobe CAS Column-Address Strobe CKE Clock-Enable CLK System Clock CS Chip-Select DQ[0:3] SDRAM Data Input/Data Output (x4) DQ[0:7] SDRAM Data Input/Data Output (x8) DQ[0:15] SDRAM Data Input/Data Output (x16) DQMU/DQML Data/Output Mask Enables for x16 DQM Data/Output Mask Enables for x8/x4 NC No External Connect VCC Power Supply (3.3 V Typical) VCCQ Power Supply for Output Drivers (3.3 V Typical) VSS Ground VSSQ Ground for Output Drivers A[0:13] Address Inputs Four Banks Column A0 –A9 Column Addr (x4) A0 –A8 Column Addr (x8) A0 –A7 Column Addr (x16) A10 Auto Precharge A12 – A13 Bank-Select Row A0 – A11 Row Addrs A12 – A13 Bank-Select functional block diagram (four banks) CLK CKE CS (DQM) DQMx RAS CAS W A0–A13 AND Control Mode Register Array Bank 0 DQ Buffer DQ0–DQ7 (x8) DQ0–DQ15 (x16) or Array Bank 1 Array Bank 2 Array Bank 3 or DQ0–DQ3 (x4)4

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998

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device numbering conventions (SDRAM family nomenclature) xx6 4 –xx Product Family: 6 = Synchronous Dynamic Random-Access Memory Density, Refresh, Interface: 64 = 64M 4K Auto-Refresh LVTTL Organization/Special Architecture: 41 = x 4 Pipeline 81 = x 8 Pipeline 16 = x 16 Pipeline Number of Banks: 4 = Four Banks Speed: 8 tCK3 =8 n s 8A tCK3 =8 n s 10 tCK3 = 10 ns TMS Prefix: TMS = Commercial / MOS operation All inputs to the ’664xx4 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs (DQ0–DQ3 for x4, DQ0–DQ7 for x8, and DQ0–DQ15 for x16) are also referenced to the rising edge of CLK. The ’664xx4 has four banks that are accessed independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles refresh all banks alternately. Five basic commands or functions control most operations of the ’664xx4: /C0068Bank activate/row-address entry /C0068Column-address entry/write operation /C0068Column-address entry/read operation /C0068Bank deactivate /C0068Auto-refresh/self-refresh entry Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or gate) the CLK input. The device contains a mode register that must be programmed for proper operation. Table 1 through Table 3 show the various operations that are available on the ’664xx4. These truth tables identify the command and/or operations and their respective mnemonics. Each truth table is followed by a legend that explains the abbreviated symbols. An access operation refers to any READ (READ-P) or WRT (WRT-P) command in progress at cycle n. Access operations include the cycle upon which the READ (READ-P) or WRT (WRT-P) command is entered and all subsequent cycles through the completion of the access burst.

Figure 1. State Diagram

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Table 1. Basic Command Truth Table†‡ —t CESP and tRC from self-refresh (SLFR) exit. turns on four rows (one from each bank; therefore, 4096 REFR commands fully refresh the memory).

Table 2. Clock-Enable (CKE) Command Truth Table† † For execution of these commands, A0–A13 (n) and DQMx (n) are don’t care entries. ‡ On cycle n, the device executes the respective command (listed in Table 1). On cycle (n+1), the device enters the power-down mode. cycle of a WRT (WRT-P) operation. either the DESL or NOOP command must be applied before any other command.

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Table 3. Data/Output Mask Enable (DQM) Command Truth Table†‡ ‡ CS (n), RAS (n), CAS (n), W (n), and A0–A13 (n) are don’t care entries. cycle of a WRT (WRT-P) operation.

are in the high-impedance state until the next read access is initiated. Table 4. 2-Bit Burst Sequences Table 5. 4-Bit Burst Sequences

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Table 6. 8-Bit Burst Sequences subsequent changes to the CAS latency are prohibited. The ’664xx4 contains four independent banks that can be accessed individually or in an interleaved fashion. Table 1 for a description of the bank-deactivation, and Figure 25 and Figure 26 for examples of the operation).

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 four-bank row-access operation One of the features of the four-bank operation is access to information on random rows at a higher rate of operation than is possible with a standard DRAM. This is accomplished by activating one of the banks with a row address and, while the data stream is being accessed to/from that bank, activating one of the other banks with other row addresses. When the data stream to/from the first activated bank is complete, the data stream to/from the second activated bank can begin without interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next round of accesses or the entry of new row addresses for other banks which currently are deactivated. In this manner, operation can continue in an interleaved fashion. Figure 29A is an example of four-bank, row-interleaving, read bursts with automatic deactivate with a CAS latency of 3 and a burst length of 8. Figure 29B is an example of four-bank, row-interleaving, read bursts with automatic deactivate with a CAS latency of 3 and a burst length of 4. four-bank column-access operation The availability of four banks allows the access of data from random starting columns between banks at a higher rate of operation. After activating each bank with a row address (ACTV command), A12–A13 for the four-bank column-access operation can be used to alternate READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all specified timing requirements are met. Figure 30 is an example of four-bank, column-interleaving, read bursts with a CAS latency of 3 and a burst length of 2. bank deactivation (precharge) All banks can be deactivated simultaneously (placed in precharge) by using the DCAB command. A single bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB command except that A10 must be low and A12–A13 select the bank to be precharged (see Table 1; Figure 27 and Figure 31 provide examples). A bank can also be deactivated automatically by using A10 during a READ or WRT command. If A10 is held high during the entry of a READ or WRT command, the accessed bank, selected by A12–A13, is automatically deactivated upon completion of the access burst. If A10 is held low during READ- or WRT-command entry, that bank remains active following the burst. The READ and WRT commands with automatic deactivation are denoted as READ-P and WRT-P . See Figure 29A and Figure 29B for examples. chip-select CS (chip-select) can be used to select or deselect the ’664xx4 for command entries, which might be required for multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device does not respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). Using CS does not affect an access burst that is in progress; the DESL command can restrict only RAS, CAS, and W inputs to the ’664xx4.

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998

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Masking of individual data cycles within a burst sequence can be accomplished by using the MASK command (see Table 3). If DQM (or DQML/DQMU of x16) is held high on the rising edge of CLK during a write burst, the incident data word (referenced to the same rising edge of CLK) on DQ0–DQ7 [or (DQ0–DQ7)/(DQ8–DQ15) of x16] is ignored. If DQM (or DQML/DQMU of x16) is held high on the rising edge of CLK for a read burst, DQ0–DQ7 [or (DQ0–DQ7)/(DQ8–DQ15) of x16], referenced to the second rising edge of CLK, are in the high-impedance state. The application of DQM (DQML/DQMU) to data-output cycles (READ burst) involves a latency of two CLK cycles, but the application of DQM to data-in cycles (WRITE burst) has no latency. The MASK command (or its opposite, the ENBL command) is performed on a cycle-by-cycle basis, allowing the user to gate any individual data cycle or cycles within either a read-burst or a write-burst sequence. Figure 14, Figure 38 and Figure 39 show examples of data/output masking. CLK-suspend/power-down mode For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution of a READ (READ-P) or WRT (WRT-P) operation, the state of the DQ bus occurring at the immediate next rising edge of CLK is frozen at its current state and no further inputs are accepted until CKE is returned high. This is known as a CLK-suspend operation and its execution is denoted as a HOLD command. The device resumes operation from the point at which it was placed in suspension, beginning with the second rising edge of CLK after CKE is returned high. See Figure 42 and Figure 43 for examples. If CKE is brought low when no READ (READ-P) or WRT (WRT-P) command is in progress, the device enters power-down mode. If all banks are deactivated when power-down mode is entered, power consumption is reduced to the minimum. Power-down mode can be used during row-active or auto-refresh periods to reduce input-buffer power. After power-down mode has been entered, no further inputs are accepted until CKE returns high. To ensure that data in the device remains valid during the power-down mode, the self-refresh command (SLRF) must be executed concurrently with the power-down entry (PDE) command. When exiting power-down mode, new commands can be entered on the first CLK edge after CKE returns high, provided that the setup time (t CESP ) is satisfied. Table 2 shows the command configuration for a CLK-suspend/power-down operation; Figure 18 and Figure 19 show examples of the procedure.

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CKE is brought high to exit self-refresh mode (see Figure 19). continuing with normal device operations. This ensures that the SDRAM is fully refreshed. A read or write can be interrupted before the burst sequence is complete with no adverse effects to the operation. all timing requirements are met. The interruption of READ-P and WRT-P operations is not supported. Table 7. Read-Burst Interruption command is met and new output cycles begin (see Figure 3). nCCD , and (nCCD +1), assuming there is any output on these cycles (see Figure 4). burst, whichever occurs first (see Figure 5 and Figure 22).

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NOTE A: For this example, assume CAS latency = 3 and burst length > 2. Figure 5. Read Burst Interrupted by DEAC Command Table 8. Write-Burst Interruption READ, READ-P Data that was input on the previous cycle is written and no further data inputs are accepted (see Figure 6).

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NOTE A: For the purposes of this example, CAS latency = 2 and burst length > 2. Figure 8. Write Burst Interrupted by DEAC/DCAB Command device initialization. See Figure 24.

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 3 3.3 3.6 V VCCQ Supply voltage for output drivers‡ 3 3.3 3.6 V VSS Supply voltage 0 V VSSQ Supply voltage for output drivers 0 V VIH High-level input voltage 2 VCC + 0.3 V VIL Low-level input voltage – 0.3 0.8 V TA Operating ambient temperature 0 70 °C ‡ VCCQ /C0118 VCC /C0041 0.3 V

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998

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electrical characteristics over recommended ranges of supply voltage and operating ambient temperature (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = –2 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 0.4 0.4 V II Input current (leakage) 0 V ≤ VI ≤ VCC + 0.3 V, All other pins = 0 V to VCC ±10 ±10 ±10 mA IO Output current (leakage)

0 V ≤ VO ≤ VCCQ

Output disabled ±10 ±10 ±10 mA ICC1 Operating Burst length = 1, tRC /C0119 tRC MIN CAS latency = 2 115 125 95 mA ICC1 g current RC RC IOH /IOL = 0 mA (see Notes 3, 4, and 5) CAS latency = 3 125 135 125 mA ICC2P Precharge standby current CKE /C0118 VIL MAX, tCK = 15 ns (see Note 6) 1 1 1 mA ICC2PS y in power-down mode CKE and CLK /C0118 VIL MAX, tCK = ∞ (see Note 7) 1 1 1 mA ICC2N Precharge standby current in CKE /C0119 VIH MIN, tCK = 15 ns (see Note 6) 40 40 40 mA ICC2NS non-power-down mode tCK =/C0049 (see Note 7) 5 5 5 mA ICC3P Active standby current in CKE /C0118 VIL MAX, tCK = 15 ns (see Notes 3 and 6) 8 8 8 mA ICC3PS power-down mode CKE and CLK /C0118 VIL MAX, tCK = ∞ (see Notes 3 and 7) 8 8 8 mA ICC3N Active standby current in CKE /C0119 VIH MIN, tCK = 15 ns (see Notes 3 and 6) 50 55 50 mA ICC3NS non-power-down mode CKE /C0119 VIH MIN, CLK /C0118 VIL MAX, tCK = ∞ (see Notes 3 and 7) 15 15 15 mA ICC4 Burst current Page burst, IOH /IOL = 0 mA All banks activated CAS latency = 2 165 165 120 mA ICC4 Burst current All banks activated, (see Notes 8, 9, and 10) CAS latency = 3 225 245 165 mA ICC5 Auto-refresh tRC /C0119 tRC MIN CAS latency = 2 150 150 150 mA ICC5 current RC RC (see Notes 4 and 7) CAS latency = 3 150 150 150 mA ICC6 Self-refresh current CKE /C0118 VIL MAX 1 1 1 mA NOTES: 2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 3. Only one bank is activated. 4. tRC /C0119 tRC MIN 5. Control, DQ, and address inputs change state twice during tRC . 6. Control, DQ, and address inputs change state once every 30 ns. 7. Control, DQ, and address inputs do not change state (stable). 8. 4-bank ping-pong, burst length = 4, nCCD = 4 cycles, data pattern 0011. 9. Column address and bank address increment every 4 cycles. 10. A tCK of 10 ns is used to obtain ICC4 for CL3 of the -8A speed grade.

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating ambient temperature (unless otherwise noted) (see Note 2) (continued) PARAMETER TEST CONDITIONS UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = –2 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 0.4 0.4 V II Input current (leakage) 0 V ≤ VI ≤ VCC + 0.3 V, All other pins = 0 V to VCC ±10 ±10 ±10 mA IO Output current (leakage) Output disabled ±10 ±10 ±10 mA ICC1 Operating Burst length = 1, tRC /C0119 tRC MIN CAS latency = 2 105 95 105 mA ICC1 g current RC RC IOH /IOL = 0 mA (see Notes 3, 4, and 5) CAS latency = 3 135 105 115 mA ICC2P Precharge standby current CKE /C0118 VIL MAX, tCK = 15 ns (see Note 6) 1 1 1 mA ICC2PS y in power-down mode CKE and CLK /C0118 VIL MAX, tCK = ∞ (see Note 7) 1 1 1 mA ICC2N Precharge standby current in CKE /C0119 VIH MIN, tCK = 15 ns (see Note 6) 40 40 40 mA ICC2NS non-power-down mode tCK =/C0049 (see Note 7) 5 5 5 mA ICC3P Active standby current in CKE /C0118 VIL MAX, tCK = 15 ns (see Notes 3 and 6) 8 8 8 mA ICC3PS power-down mode CKE and CLK /C0118 VIL MAX, tCK = ∞ (see Notes 3 and 7) 8 8 8 mA ICC3N Active standby current in CKE /C0119 VIH MIN, tCK = 15 ns (see Notes 3 and 6) 55 55 60 mA ICC3NS non-power-down mode CKE /C0119 VIH MIN, CLK /C0118 VIL MAX, tCK = ∞ (see Notes 3 and 7) 15 15 15 mA ICC4 Burst current Page burst, IOH /IOL = 0 mA All banks activated CAS latency = 2 140 120 140 mA ICC4 Burst current All banks activated, (see Notes 8, 9, and 10) CAS latency = 3 165 175 200 mA ICC5 Auto-refresh tRC /C0119 tRC MIN CAS latency = 2 150 150 150 mA ICC5 current RC RC (see Notes 4 and 7) CAS latency = 3 150 150 150 mA ICC6 Self-refresh current CKE /C0118 VIL MAX 1 2 2 mA NOTES: 2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 3. Only one bank is activated. 4. tRC /C0119 tRC MIN 5. Control, DQ, and address inputs change state twice during tRC . 6. Control, DQ, and address inputs change state once every 30 ns. 7. Control, DQ, and address inputs do not change state (stable). 8. 4-bank ping-pong, burst length = 4, nCCD = 4 cycles, data pattern 0011. 9. Column address and bank address increment every 4 cycles. 10. A tCK of 10 ns is used to obtain ICC4 for CL3 of the -8A speed grade.

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998

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capacitance over recommended ranges of supply voltage and operating ambient temperature f = 1 MHz (see Note 11) PARAMETER MIN MAX UNIT C i(S) Input capacitance, CLK input 2.5 4 pF C i(AC) Input capacitance, address and control inputs: A0–A13, CS, DQMx, RAS, CAS, W 2.5 5 pF C i(E) Input capacitance, CKE input 5 pF C o Output capacitance 4 6.5 pF NOTE 11: VCC = 3.3 ± 0.3 V and bias on pins under test is 0 V. ac timing requirements†‡ ’664xx4-8 ’664xx4-8A ’664xx4-10 UNIT MIN MAX MIN MAX MIN MAX UNIT tCK2 Cycle time, CLK CAS latency = 2 10 15 15 ns tCK3 Cycle time, CLK CAS latency = 3 8 8 10 ns tCH Pulse duration, CLK high 3 3 3 ns tCL Pulse duration, CLK low 3 3 3 ns tAC2 Access time, CLK high to data out (see Note 12) CAS latency = 2 6 7.5 7.5 ns tAC3 Access time, CLK high to data out (see Note 12) CAS latency = 3 6 6 7.5 ns tOH2 Hold time, CLK high to data out with 50-pF load CAS latency = 2 3 3 3 ns tOH3 Hold time, CLK high to data out with 50-pF load CAS latency = 3 3 3 3 ns tLZ Delay time, CLK high to DQ in low-impedance state (see Note 13)1 1 2 ns tHZ Delay time, CLK high to DQ in high-impedance state (see Note 14) 8 8 10 ns tIS Setup time, address, control, and data input 2 2 2 ns tIH Hold time, address, control, and data input 1 1 1 ns tCESP Power down/self-refresh exit time (see Note 15) 8 8 10 ns tRAS Delay time, ACTV command to DEAC or DCAB command 48 100000 48 100000 50 100000 ns tRC Delay time, ACTV, REFR, or SLFR command to ACTV, MRS, REFR, or SLFR command 68 68 80 ns tRCD Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 16) 20 20 30 ns tRP Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 20 20 30 ns tRRD Delay time, ACTV command in one bank to ACTV command in the other bank 16 16 20 ns tRSA Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 16 16 20 ns † See Parameter Measurement Information for load circuits (see Figure 9). ‡ All references are made to the rising transition of CLK, unless otherwise noted. NOTES: 12. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced from the rising transition of CLK that is CAS latency – one cycle after the READ command. An access time is measured at output reference level 1.5 V. 13. tLZ is measured from the rising transition of CLK that is CAS latency – one cycle after the READ command. 14. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 15. See Figure 18 and Figure 19. 16. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS .

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 23POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ac timing requirements†‡ (continued) ’664xx4-8 ’664xx4-8A ’664xx4-10 UNIT MIN MAX MIN MAX MIN MAX UNIT tAPR Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command tRP – (CL –1) * tCK ns tAPW Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command tRP + 1 tCK ns tT Transition time 1 5 1 5 1 5 ns tREF Refresh interval 64 64 64 ms nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 1 1 cycle nCCD Delay time, READ or WRT command to an interrupting command 1 1 1 cycle nCDD Delay time, CS low or high to input enabled or inhibited 0 0 0 0 0 0 cycle nCLE Delay time, CKE high or low to CLK enabled or disabled 1 1 1 1 1 1 cycle nCWL Delay time, final data in of WRT command to READ, READ-P, WRT, or WRT-P command 1 1 1 cycle nDID Delay time, ENBL or MASK command to enabled or masked data in0 0 0 0 0 0 cycle nDOD Delay time, ENBL or MASK command to enabled or masked data out2 2 2 2 2 2 cycle nHZP2 Delay time, DEAC or DCAB command to DQ in high-impedance state CAS latency = 2 2 2 2 cycle nHZP3 Delay time, DEAC or DCAB command to DQ in high-impedance state CAS latency = 3 3 3 3 cycle nWCD Delay time, WRT command to first data in 0 0 0 0 0 0 cycle † See Parameter Measurement Information for load circuits (see Figure 9). ‡ All references are made to the rising transition of CLK, unless otherwise noted.

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Figure 9. ac Load Circuit

Figure 10. Input-Attribute Parameters

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Figure 11. Output Parameters NOTE A: tRRD is specified for command execution in one bank to command execution in another bank. Figure 12. Command-to-Command Parameters

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NOTE A: For this example, assume CAS latency = 2 and burst length = 2. Figure 15. Read Automatic-Deactivate (Autoprecharge) NOTE A: For this example, the burst length = 2. Figure 16. Write Automatic-Deactivate (Autoprecharge) Figure 17. CLK-Suspend Operation (Assume Burst Length = 4)

Figure 18. Power-Down Operation

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NOTES: A. Assume both banks are deactivated before the execution of SLFR. B. Before/after self-refresh mode, 4K burst auto-refresh cycles are recommended to ensure that the SDRAM is fully refreshed. Figure 19. Self-Refresh Entry/Exit

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NOTE A: For this example, assume CAS latency = 3, and burst length = 4. Figure 22. Read Followed by Deactivate NOTE A: For this example, assume CAS latency = 3, and burst length = 1. Figure 23. Read With Auto-Deactivate

NOTE A: Refer to the section titled “Setting the Mode Register”. Figure 24. Power-Up Sequence

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† Column-address sequence depends on programmed burst type and starting address C0 (see Table 5). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 125 MHz. Figure 25. Read Burst (CAS latency = 3, burst length = 4)

† Column-address sequence depends on programmed burst type and starting address C0 (see Table 6). NOTE A: This example illustrates minimum tRCD and nWR for the ’664xx4 at 125 MHz. Figure 26. Write Burst (burst length = 8)

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† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 4). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 125 MHz. Figure 27. Write-Read Burst (CAS latency = 3, burst length = 2)

† Column-address sequence depends on programmed burst type and starting address C0 (see Table 6). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 125 MHz. Figure 28. Read-Write Burst With Automatic Deactivate (CAS latency = 3, burst length = 8)

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 Temp late R elease D ate: 7–11–94

38 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443•

(D/Q) (0 –3) ADDR a bcde f gh i j k lmnop q r s . . . Q 0 R0 C0 † C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7 Q 1 R1 C1 C1 + 1 C1 + 2 C1 + 3 C1 + 4 C1 + 5 C1 + 6 C1 + 7 Q 2 R2 C2 C2 + 1 C2 + 2 ... † Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 6). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 125 MHz. Figure 29. [A] Four-Bank Row-Interleaving Burst Length of 8 With Automatic Deactivate (CAS latency = 3, burst length = 8) PARAMETER MEASUREMENT INFORMATION CKE CS A0–A9 A10 A11 A12 A13 CAS RAS DQMx DQ CLK C2R2 R1R0 srqponmlkjihgfedcba ACTV_3READ-P_2ACTV_2READ-P_1ACTV_1READ-P_0ACTV_0 W tRCD tRCD tRCD

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443• 39 BURST TYPE BANK ROW BURST CYCLE (D/Q) (0 –3) ADDR a bcd e f gh i j k l m nop q r s . . . Q 0 R0 C0 † C0 + 1 C0 + 2 C0 + 3 Q 1 R1 C1 C1 + 1 C1 + 2 C1 + 3 Q 2 R2 C2 C2 + 1 C2 + 2 C2 + 3 Q 3 R3 C3 C3 + 1 C3 + 2 C3 + 3 Q 0 R4 C4 C4 + 1 C4 + 2 ... † Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 5). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 125 MHz. Figure 29. [B] Four-Bank Row-Interleaving Burst Length of 4 With Automatic Deactivate (CAS latency = 3, burst length = 4) (Cont’d) PARAMETER MEASUREMENT INFORMATION C3R3 R4R3 C1R1 READ-P_1 ACTV_1 READ-P_0 ACTV_0 READ-P_3 ACTV_3 READ-P_2 ACTV_2 READ-P_1 ACTV_1 READ-P_0 ACTV_0 W CKE CS A0–A9 A10 A11 A12 A13 CAS RAS DQMx DQ CLK C5C4R4 R2R0 srqponmlkjihgfedcba tRCD tRCD tRCD tRCD tRCD tRCD

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† Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 4). Figure 30. Four-Bank Column-Interleaving Read Bursts (CAS latency = 3, burst length = 2)

† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 125 MHz. Figure 31. Read-Burst Bank 0, Write-Burst Bank 1 (CAS latency = 3, burst length = 4)

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† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum nCWL, tRRD, and tRCD for the ’664xx4 at 125 MHz. Figure 32. Write-Burst Bank 3, Read-Burst Bank 0 With Automatic Deactivate

† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 100 MHz. Figure 33. Use of DQM for Output and Data-In Cycle Masking (Read-Burst Bank 1, Write-Burst Bank 0,

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† Column-address sequence depends on programmed burst type and starting address C0 (see Table 6). NOTE A: This example illustrates minimum tRC , tRCD , and tRP for the ’664xx4 at 100 MHz. Figure 34. Refresh Cycles (Refreshes Followed by Read Burst, Followed by Refresh)

† Column-address sequence depends on programmed burst type and starting address C0 (see Table 5). B. This example illustrates minimum tRCD and tRSA for the ’664xx4 at 125 MHz. Figure 35. Mode-Register Programming

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† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTES: A. This example illustrates minimum tRCD and tAPW for the ’664xx4 at 100 MHz. banks are deactivated (still in power-down mode). Figure 36. Use of CKE for Clock Gating (Hold) and Standby Mode

† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). Figure 37. Read-Burst Bank 0, Write-Burst Bank 1 (With Lower Bytes Masked Out During the READ

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† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD and a minimum nWR write burst for the ’664xx4 at 100 MHz. Figure 38. Use of DQM for Output and Data-In Cycle Masking (Read-Burst Bank 1, Write-Burst Bank 0,

† Column-address sequence depends on programmed burst type and starting addresses C0, C1, C2, and C3 (see Table 4). NOTE A: This example illustrates minimum tRCD and minimum tRRD for the ’664xx4 at 125 MHz. Figure 39. Four-Bank Column-Interleaving Read Bursts (With Upper Bytes to be Masked) (Only for x16)

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† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 6). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 125 MHz. Figure 40. Read Burst — Single Write With Automatic Deactivate (CAS latency = 3, burst length = 8)

† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 6). NOTE A: This example illustrates minimum tRCD for the ’664xx4 at 125 MHz. Figure 41. Read Bursts With Automatic Deactivate (read latency = 3, burst length = 8) (for x16)

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† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). those rising clocks at cycle DQMx = Hi. B. This example illustrates minimum tRCD for the ’664xx4 at 100 MHz. Figure 42. Use of CKE for Clock Gating (Hold/Suspend) and DQM = Hi Showed No Effect

† Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTES: A. This example illustrates that the DQM mask is also delayed when a HOLD/Suspend is in progress. B. This example illustrates minimum tRCD for the ’664xx4 at 100 MHz. Figure 43. DQMx Mask Delay As the Hold/Suspend In Progress

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A– APRIL 1998 – REVISED JULY 1998

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Speed Code (-8, -8A, -10) Package Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code -SS LLLLMYBW TMS664xx4 DGE TI Assembly Site Code P

TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A– APRIL 1998 – REVISED JULY 1998 55POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA DGE (R-PDSO-G54) PLASTIC SMALL-OUTLINE PACKAGE Gage Plane 0.396 (10,06) 0.404 (10,26) 0.006 (0,15) NOM 0.455 (11,56) 0.471 (11,96) 0.016 (0,40) 0.024 (0,60) Seating Plane 4040070-6/C 12/95 0.010 (0,25) 0.879 (22,32) 0.871 (22,12) 0.047 (1,20) MAX 0.012 (0,30) 0.018 (0,45) 0°–5° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion.

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