TMS55175

TMS55165 TI | Alldatasheet

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262144 BY 16-BIT MULTIPORT VIDEO RAM

Table 1. Device Option Table Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI and EPIC are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date.

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A0 –A8 Address Inputs RAS Row-Address Strobe CAS Column-Address Strobe DSF Special Function Select TRG Output Enable, Transfer Select WEL , WEU Write Enable, Byte Select, Write Mask Select DQ0 –DQ15 DRAM Data I/O SC Serial Clock SE Serial Enable SQ0 –SQ15 Serial Data Output QSF Special Function Output VCC Power Supply VSS Ground NC/GND No Connect/Ground (Important: not connected internally to VSS ) SC SE VSS SQ15 DQ15 SQ14 DQ14 VCC SQ13 DQ13 SQ12 DQ12 VSS SQ11 DQ11 SQ10 DQ10 VCC SQ9 DQ9 SQ8 DQ8 DSF VSS NC / GND CAS QSF VSS VCC VSS SQ0 DQ0 SQ1 DQ1 VCC SQ2 DQ2 SQ3 DQ3 VSS SQ4 DQ4 SQ5 DQ5 VCC SQ6 DQ6 SQ7 DQ7 VSS WEL WEU RAS VCC DGH PACKAGE (TOP VIEW)

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description

The TMS551xx multiport video RAMs are high-speed dual-ported memory devices. Each consists of a dynamic random-access memory (DRAM) organized as 262 144 words of 16 bits each interfaced to a serial-data register [serial-access memory (SAM)] organized as 256 words of 16 bits each. These devices support three basic types of operation: random access to and from the DRAM, serial access from the serial register, and transfer of data from the DRAM to the SAM. Except during transfer operations, these devices can be accessed simultaneously and asynchronously from the DRAM and SAM ports. The TMS551xx multiport video RAMs provide several functions designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports (see Table 2). On the DRAM port, greater pixel draw rates are achieved by the block-write function. The TMS5516x devices’ 4-column block-write function allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent column-address locations, up to a total of 64 bits of data per CAS cycle time. Similarly, the TMS5517x devices’ 8-column block-write function allows 16 bits of data to be written to any combination of eight adjacent column-address locations, up to a total of 128 bits of data per CAS cycle time. Also on the DRAM port, the write-per-bit (or write mask) function allows masking of any combination of the 16 DQs on any write cycle. The persistent write-per-bit function uses a mask register that, once loaded, can be used on subsequent write cycles without reloading. All TMS551xx devices offer byte control. Byte control can be applied in write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The TMS551xx devices offer enhanced page-mode operation that results in faster access time. The TMS551x6 devices also offer extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and the standard DRAM cycles. The TMS551xx devices offer a split-register-transfer (DRAM to SAM) function. This feature enables real-time register load implementation for continuous serial-data streams without critical timing requirements. The serial register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the DRAM. For applications not requiring real-time register load (for example, loads done during CRT-retrace periods), the full-register-transfer operation is retained to simplify system design. The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up to 55 MHz. A separate output, QSF, is included to indicate which half of the serial register is active. Refreshing the SAM is not required because the data register that comprises the SAM is static. All inputs, outputs, and clock signals on the TMS551xx devices are compatible with Series 74 TTL. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility. All TMS551xx employ TI’s state-of-the-art EPIC scaled-CMOS, double-level polysilicon/polycide gate technology combining very high performance with improved reliability. All TMS551xx are offered in a 64-pin small-outline gull-wing-leaded package (DGH suffix) for direct surface mounting. The TMS551xx video RAMs and other TI multiport video RAMs are supported by a broad line of graphics processors and control devices from Texas Instruments.

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4-column functional block diagram (TMS5516x) Output Buffer Input Buffer Input Buffer DQ0 – DQ15 DSF SQ0 –SQ15 1 of 4 Sub-Blocks (see next page) 1 of 4 Sub-Blocks (see next page) 1 of 4 Sub-Blocks (see next page) RAS CAS WEx TRG Special- Function Logic Serial- Output Buffer Timing Generator SE Split- Register Status Row Buffer Column Buffer A0 –A8 QSF SE SC Refresh Counter Serial- Address Counter 1 of 4 Sub-Blocks (see next page)

TMS55165, TMS55166, TMS55175, TMS55176 SMVS463 – DECEMBER 1995 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 4-column functional block diagram (TMS5516x) (continued) 1 of 4 Sub-Blocks Row Decoder Color Register Address Mask W/B Latch W/B UnlatchMUX Write- Per-Bit Control Serial-Data Pointer Serial-Data Register 512 × 512 Memory Array Sense AMP Column Dec. Special- Function Logic Input Buffer DQx DQx+1 DQx+2 DQx+3 RAS CAS TRG WEx DSF DRAM Output Buffer DRAM Input Buffer Timing Generator SQx SQx+1 SQx+2 SQx+3 Serial- Output Buffer SE SE Refresh Counter A0 –A8 QSF SC Split- Register Status Serial- Address Counter Row Buffer Column Buffer

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8-column functional block diagram (TMS5517x) Split- Register Status Output Buffer Input Buffer Row Buffer Column Buffer DQ0 – DQ15 A0 –A8 SQ0 –SQ15 1 of 2 Sub-Blocks (see next page) 1 of 2 Sub-Blocks (see next page) QSF SE RAS CAS WEx TRG Special- Function Logic Serial- Output Buffer Timing Generator SE SC Serial- Address Counter Refresh Counter Input Buffer DSF

TMS55165, TMS55166, TMS55175, TMS55176 SMVS463 – DECEMBER 1995 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 8-column functional block diagram (TMS5x17x) (continued) SE 1 of 2 Sub-Blocks Refresh Counter Serial- Address Counter Color Register Address Mask W/B Latch W/B UnlatchMUX Write- Per-Bit Control Special- Function Logic DQx DQx + 1 DQx + 2 DQx + 3 RAS CAS TRG WEx A0 –A8 DSF QSF DRAM Output Buffer DRAM Input Buffer Timing Generator SQx + 4 SQx + 5 SQ x+ 6 SQx + 7 Serial Output Buffer SE SC Column Buffer Row Buffer DQx + 4 DQx + 5 DQx + 6 DQx + 7 SQx SQx + 1 SQx + 2 SQx + 3 Row Decoder Serial-Data Pointer Serial-Data Register 512 × 512 Memory Array Sense AMP Column DEC Split- Register Status Input Buffer

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Table 2. Function Table or the first falling edge of WEx, whichever occurs later. ‡ Logic L is selected when either or both WEL and WEU are low. § The column address, the block address, or the tap point is latched on the falling edge of CAS depending upon which function is executed. ¶ CBRS cycle should be performed immediately after the power-up initialization for stop-point mode. ||CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. /C0107 CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. /C0104 For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8.

Table 3. Pin Description Versus Operational Mode † For proper device operation, all VCC pins must be connected to a 5.0-V supply and all VSS pins must be tied to ground. the falling edge of RAS and the falling edge of CAS. block address that selects one of the 64 blocks in the active row. SAM is in use, the low half of the SAM is loaded with the low half of the DRAM half row, and vice versa. not valid tap points in split-register-transfer operations. onto the chip to initiate DRAM and transfer functions. RAS also functions as a DRAM output enable.

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column-address strobe (CAS) The falling edge of CAS latches the states of the column address and DSF onto the chip to control DRAM and transfer functions. CAS also functions as a DRAM output enable. special-function select (DSF) DSF is latched on the falling edge of RAS and the falling edge of CAS to determine which functions are invoked on a particular cycle (see Table 2). output enable, transfer select (TRG) TRG selects either DRAM or transfer operation as RAS falls. Holding TRG high on the falling edge of RAS selects the DRAM operation. Dropping TRG low on the falling edge of RAS selects the transfer operation. TRG also functions as DRAM output enable. write enable, write-per-bit select, byte select (WEL, WEU) WEL and WEU select either the write mode or the read mode in a CAS cycle. Dropping either or both WEL and WEU low selects the write mode. Holding both WEL and WEU high selects the read mode. Holding either or both WEL and WEU low on the falling edge of RAS selects the write-per-bit operation. WEL and WEU provide byte control in DRAM operations. WEL controls the lower byte (DQ0–DQ7), and WEU controls the upper byte (DQ8 –DQ15). Byte control can be applied in write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. DRAM data I/O, write mask, column mask (DQ0–DQ15) DQ0 –DQ15 function as the DRAM input/output port in DRAM operations. In normal DRAM write cycles, all 16 bits of write data are latched on either the falling edge of CAS or the first falling edge of WEx, whichever occurs later. Similarly, the DQs are latched as write mask in load-mask-register cycles, as color data in load-color-register cycles, and as column mask in block-write cycles. In non-persistent write-per-bit cycles, the DQs are latched as the write mask on the falling edge of RAS. Data out is in the same polarity as data in. The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fan-out of one Series 74 TTL load. The outputs are in the high-impedance (floating) state until RAS, CAS, and TRG have all been brought low in read cycles. For the TMS551x5 devices, the outputs remain valid until CAS is brought high, TRG is brought high, or WEx is brought low. For the TMS551x6 devices, the outputs remain valid until both RAS and CAS are brought high, TRG is brought high, or WEx is brought low. serial clock (SC) The rising edge of SC increments the internal serial-address counter and accesses serial data at the next SAM location. serial enable (SE) SE functions as the output enable for SQ0–SQ15 and QSF. SE low enables the serial-data output. SE high disables the serial-data output. Holding SE high does not disable the serial clock SC. The rising edge of SC automatically increments the internal serial-address counter regardless of the state of SE. serial data outputs (SQ0–SQ15) SQ0 –SQ15 function as the SAM output port. The 3-state output buffer provides direct TTL compatibility (no pullup resistors) with a fan-out of one Series 74 TTL load. Serial data is accessed from the SAM on the rising edge of SC. SE low enables the outputs. The outputs are in the high-impedance (floating) state when disabled. special-function output (QSF) QSF is an output pin that indicates which half of the SAM is being accessed. QSF is low when the internal serial-address counter points to the lower (least significant) 128 bits of the SAM. QSF is high when the internal serial-address counter points to the higher (most significant) 128 bits of SAM. QSF is in the high-impedance state when SE is high.

Table 4. DRAM Function Table † DQ0 –DQ15 are latched on either the falling edge of CAS or the first falling edge of WEx, whichever occurs later. ‡ Logic L is selected when either or both WEL and WEU are low. § The column address, the block address, or the tap point is latched on the falling edge of CAS depending upon which function is executed. ¶ CBRS cycle should be performed immediately after the power-up for stop-point mode. ||CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. /C0107 CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. /C0104 For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8.

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ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles are available. high-impedance state during the CBR type refresh cycles regardless of the state of TRG. addresses are generated internally during the hidden refresh. number of columns that can be accessed. bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS transitions low. from CAS low) if ta(CA) max (access time from column address) has been satisfied. cycles including DRAM read, page-mode read, and read-modify-write cycles. † See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table. Figure 1. DRAM Read Cycle With RAS-Controlled Output (TMS551x6)

† See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table. Figure 2. DRAM Read Cycle With CAS-Controlled Output (TMS551x6) † See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table. ‡ See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table. Figure 3. DRAM Page-Read Cycle With Extended Data Output (TMS551x6)

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DQ0 –DQ15 referenced to CAS (see Figure 4). † Either WEx can be brought low prior to CAS to initiate an early-write cycle. ‡ See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table. Figure 4. Example of an Early-Write Cycle

† See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table. Figure 5. Example of a Late-Write Cycle are two write-per-bit modes: the nonpersistent write-per-bit and the persistent write-per-bit.

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data is written to that DQ (see Figure 6). † See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table. Figure 6. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation

write cycles until another LMR cycle is performed, a CBR with reset is executed, or power is removed. DQ pins and latched on either the falling edge of CAS or the first falling edge of WEx, whichever occurs later. mode, it remains in this mode and is reset only by a CBR refresh (option reset) cycle (see Figure 7). Figure 7. Example of a Persistent Write-Per-Bit Operation

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up to four DQs per column (see Figure 8). Figure 8. 4-Column Block-Write Operation and 12–15 of the corresponding registers control the other quadrants in a similar fashion (see Figure 9).

Figure 9. 4-Column Block Write With Masks

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columns 0–3, block 1 comprises columns 4–7, block 2 comprises columns 8–11, etc., as shown in Figure 10. Figure 10. 4-Column-Block Column-Organization quadrants have the same block selected. use of the write-mask capability, allowing additional performance options. Column-address bits A0 and A1 are ignored. Block 0 (columns 0–3) is selected for all one-megabit quadrants.

1. DQ3 is not written and retains its previous data due to the write-mask bit 3 being a 0.

the 4-column block-write operation shown in the example.

Figure 11. Example of Fourth Quadrant After 4-Column Block-Write Operation

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Figure 12. 8-Column Block-Write Operation Each byte has an 8-bit column mask to mask off any or all of the eight columns from being written with data. provide write-masking options. Write data (color data) is provided by eight bits from the on-chip color register. in a similar fashion (see Figure 13).

Figure 13. 8-Column Block Write With Masks 0 –7, block 1 comprises columns 8–15, block 2 comprises columns 16–23, etc., as shown in Figure 14. Figure 14. 8-Column-Block Column-Organization

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use of the write-mask capability allowing additional performance options. and retains its previous data due to the write-mask bit 3 being 0. in Figure 15 after the 8–column block-write operation shown in the example. Figure 15. Example of Upper Byte After 8-Column Block-Write Operation

power is lost or until another load-color-register cycle is performed (see Figure 16 and Figure 17).

1. Refresh address: A0–A8 are latched on the falling edge of RAS.
2. Row address: A0–A8 are latched on the falling edge of RAS.
3. Block address A2–A8 (TMS5516x) or A3–A8 (TMS5517x) are latched on the falling edge of CAS.
4. Color data: DQ0–DQ15 are latched on the falling edge CAS or the first falling edge of WEx, whichever occurs first.
5. Write-mask data: DQ0–DQ15 are latched on the falling edge RAS.
6. Column-mask data: DQ0–DQ15 are latched on the falling edge CAS or the first falling edge of WEx, whichever occurs first.

Figure 16. Example of Block Writes

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1. Refresh address: A0–A8 are latched on the falling edge of RAS.
2. Row address: A0–A8 are latched on the falling edge of RAS.
3. Block address A2–A8 (TMS5516x) or A3–A8 (TMS5517x) are latched on the falling edge of CAS.
4. Color data: DQ0–DQ15 are latched on the falling edge CAS or the first falling edge of WEx, whichever occurs first.
5. Write-mask data: DQ0–DQ15 are latched on the falling edge RAS.
6. Column-mask data: DQ0–DQ15 are latched on the falling edge CAS or the first falling edge of WEx, whichever occurs first.

Figure 17. Example of a Persistent Block Write determines whether the full-register-transfer operation or the split-register-transfer operation is performed. Table 5. SAM Function Table † Logic L is selected when either or both WEL and WEU are low.

Figure 18. Full-Register-Transfer Read A full-register transfer can be performed in three ways: early load, real-time load (or midline load), or late load. Figure 19. Example of Full-Register-Transfer Read Operations

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other half can be loaded from the memory array. Figure 20. Split-Register-Transfer Read are latched at the falling edge of CAS. Column-address bit A8 selects which half of the row is to be transferred. Column-address bit A7 is ignored, and the split-register transfer is internally controlled to select the inactive half. tap points in split-register-transfer operations.

0 A7 = 0 † 511

0 A7 = 1 † 511

0 A7 = 0† 511

† A7 shown is internally controlled. Figure 21. Example of a Split-Register-Transfer Read Operation requirement (see Figure 22).

the state of QSF. QSF also changes state when a boundary between two register halves is reached. Figure 22. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read Figure 23. Example of Successive Split-Register-Transfer Read Operations

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and then wraps around to the least significant bit (bit 0), as shown in Figure 24. Figure 24. Serial-Pointer Direction for Serial Read split-register-transfer (see Figure 25). Figure 25. Serial Pointer for Split-Register Read – Case I bit 128 or bit 0, respectively (see Figure 26). Figure 26. Serial Pointer for Split-Register Read – Case II be used to improve 2-D drawing performance in a nonscanline data format. cycle. The last serial-address location of each partition is the stop point (see Figure 27). Figure 27. Example of SAM With Partitions

A4 –A7, which are used to define the SAM’s partition length. The other row-address inputs are don’t cares. Stop-point mode should be initiated immediately after the power-up initialization (see Table 6). Table 6. Programming Code for Stop-Point Mode

16 X L L L L X 16 15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175,

32 X L L L H X 8 31, 63, 95, 127, 159, 191, 223, 255

64 X L L H H X 4 63, 127, 191, 255

and switches to the opposite half of SAM (see Figure 28). Figure 28. Example of Split-Register Operation With Programmable Stop Points

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mode, the column-address bits AY7 and AY8 are internally swapped to assure compatibility (see Figure 29). normal functions. Consistent use of CBR cycles ensures that the TMS551xx remains in nomal mode. Figure 29. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point after the power-up initialization cycles are performed. SC cycles are required to initialize the SAM port.

TMS55165, TMS55166, TMS55175, TMS55176 SMVS463 – DECEMBER 1995 33POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† TMS551xx † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions TMS551xx UNIT MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VSS Supply voltage 0 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) –1.0 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST SAM ’551xx-60 ’551xx-70 UNITPARAMETER TEST CONDITIONS † PORT MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = –1 mA 2.4 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 5.8 V, All other pins at 0 V to VCC ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC See Note 3 ± 10 ± 10 µA ICC1 Operating current‡ See Note 4 Standby 180 165 mA ICC1A Operating current‡ tc(SC) = MIN Active 225 205 mA ICC2 Standby current All clocks = VCC Standby 5 5 mA ICC2A Standby current‡ tc(SC) = MIN Active 70 65 mA ICC3 RAS only refresh current See Note 4 Standby 180 165 mA ICC3A RAS only refresh current‡ tc(SC) = MIN, See Note 4 Active 225 205 mA ICC4 Page mode current‡ tc(P) = MIN, Standby ’551x5 135 115 mAICC4 Page-mode current‡ c(P) , See Note 5 Standby ’551x6 140 140 mA ICC4A Page mode current‡ tc(SC) = MIN, Active ’551x5 175 155 mAICC4A Page-mode current‡ c(SC) , See Note 5 Active ’551x6 185 185 mA ICC5 CBR current See Note 4 Standby 180 165 mA ICC5A CBR current‡ tc(SC) = MIN, See Note 4 Active 225 205 mA ICC6 Data-transfer current See Note 4 Standby 200 180 mA ICC6A Data-transfer current‡ tc(SC) = MIN Active 250 225 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open NOTES: 3. SE is disabled for SQ output leakage tests. 4. Measured with one address change while RAS = VIL; tc(rd), tc(W) , tc(TRD) = MIN 5. Measured with one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6) PARAMETER MIN MAX UNIT C i(A) Input capacitance, address inputs 6 pF C i(RC) Input capacitance, address strobe inputs 7 pF C i(W) Input capacitance, write enable input 7 pF C i(SC) Input capacitance, serial clock 7 pF C i(SE) Input capacitance, serial enable 7 pF C i(DSF) Input capacitance, special function 7 pF C i(TRG) Input capacitance, transfer register input 7 pF C o(O) Output capacitance, SQ and DQ 7 pF C o(QSF) Output capacitance, QSF 9 pF NOTE 6: V CC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.

TMS55165, TMS55166, TMS55175, TMS55176 SMVS463 – DECEMBER 1995 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7) PARAMETER TEST ALT. ’551xx-60 ’551xx-70 UNITPARAMETER CONDITIONS † SYMBOL MIN MAX MIN MAX UNIT ta(C) Access time, DQx from CAS low td(RLCL) = MAX tCAC 17 20 ns ta(CA) Access time, DQx from column address td(RLCL) = MAX tAA 30 35 ns ta(CP) Access time, DQx from CAS high td(RLCL) = MAX tCPA 35 40 ns ta(G) Access time, DQx from TRG low tOEA 15 20 ns ta(R) Access time, DQx from RAS low td(RLCL) = MAX tRAC 60 70 ns ta(SE) Access time, SQx from SE low C L = 30 pF tSEA 12 15 ns ta(SQ) Access time, SQx from SC high C L = 30 pF tSCA 15 20 ns tdis(CH) Disable time, random output from CAS high (see Note 8) C L = 50 pF tOFF 3 15 3 20 ns tdis(G) Disable time, random output from TRG high (see Note 8) C L = 50 pF tOEZ 3 15 3 20 ns tdis(RH) Disable time, random output from RAS high (see Note 8) C L = 50 pF 3 15 3 20 ns tdis(SE) Disable time, serial output from SE high (see Note 8) C L = 30 pF tSEZ 3 10 3 20 ns tdis(WL) Disable time, random output from WEx low (see Note 8) C L = 30 pF tWEZ 0 15 0 20 ns † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. NOTES: 7. Switching times for RAM-port output are measured with a load equivalent to 1 TTL load and 50 pF. Data out reference level: VOH / VOL = 2 V/0.8 V. Switching times for SAM-port output are measured with a load equivalent to 1 TTL load and 30 pF. Serial-data out reference level: VOH / VOL = 2 V/0.8 V. 8. tdis(CH), tdis(RH), tdis(G), tdis(WL), and tdis(SE) are specified when the output is no longer driven.

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timing requirements over recommended ranges of supply voltage and operating free-air temperature† ALT. ’551xx-60 ’551xx-70 UNITSYMBOL MIN MAX MIN MAX UNIT t (P) Cycle timepage mode read write ’551x5 tPC 35 40 ns tc(P) Cycle time, page-mode read, write ’551x6 tPC 30 30 ns tc(rd) Cycle time, read tRC 110 130 ns tc(rdW) Cycle time, read-modify-write tRMW 150 175 ns tc(RDWP) Cycle time, page-mode read-modify-write tPRMW 80 90 ns tc(SC) Cycle time, serial clock (see Note 9) tSCC 18 22 ns tc(TRD) Cycle time, transfer read tRC 110 130 ns tc(W) Cycle time, write tWC 110 130 ns tw(CH) Pulse duration, CAS high tCPN 10 10 ns t (CL) Pulse duration CAS low (see Note 10) ’551x5 tCAS 10 10 000 10 10 000 ns tw(CL) Pulse duration, CAS low (see Note 10) ’551x6 tCAS 17 10 000 20 10 000 ns tw(GH) Pulse duration, TRG high tTP 20 20 ns tw(RH) Pulse duration, RAS high tRP 40 50 ns tw(RL) Pulse duration, RAS low (see Note 11) tRAS 60 10 000 70 10 000 ns tw(RL)P Pulse duration, RAS low (page mode) tRASP 60 100 000 70 100 000 ns tw(SCH) Pulse duration, SC high tSC 5 8 ns tw(SCL) Pulse duration, SC low tSCP 5 8 ns tw(TRG) Pulse duration, TRG low 15 20 ns tw(WL) Pulse duration, WEx low tWP 10 10 ns tsu(CA) Setup time, column address before CAS low tASC 0 0 ns tsu(DCL) Setup time, data valid before CAS low, early write tDSC 0 0 ns tsu(DQR) Setup time, write mask valid before RAS low, non-persistent write-per-bit tMS 0 0 ns tsu(DWL) Setup time, data valid before first WEx low, late write tDSW 0 0 ns tsu(RA) Setup time, row address before RAS low tASR 0 0 ns tsu(rd) Setup time, both WEx high before CAS low, read tRCS 0 0 ns tsu(SFC) Setup time, DSF before CAS low tFSC 0 0 ns tsu(SFR) Setup time, DSF before RAS low tFSR 0 0 ns tsu(TRG) Setup time, TRG before RAS low tTHS 0 0 ns tsu(WCH) Setup time, WEx low before CAS high, write tCWL 15 15 ns tsu(WCL) Setup time, first WEx low before CAS low, early write tWCS 0 0 ns tsu(WMR) Setup time, WEx low before RAS low, write-per-bit tWSR 0 0 ns tsu(WRH) Setup time, WEx low before RAS high, write tRWL 15 15 ns th(CHrd) Hold time, both WEx high after CAS high, read (see Note 12) tRCH 0 0 ns th(CLCA) Hold time, column address after CAS low tCAH 10 10 ns th(CLD) Hold time, data valid after CAS low, early write tDH 15 15 ns th(CLQ) Hold time, DQ output after CAS low (TMS551x6) tDHC 4 5 ns † Timing measurements are referenced to VIL max and VIH min. NOTES: 9. Cycle time assumes tt = 3 ns. 10. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this can require additional CAS low time [tw(CL)]. 11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this can require additional RAS low time [tw(RL)]. 12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.

TMS55165, TMS55166, TMS55175, TMS55176 SMVS463 – DECEMBER 1995 37POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)† ALT. ’551xx-60 ’551xx-70 UNITSYMBOL MIN MAX MIN MAX UNIT th(CLW) Hold time, first WEx low after CAS low, early write tWCH 10 15 ns th(RA) Hold time, row address after RAS low tRAH 10 10 ns th(RDQ) Hold time, write mask valid after RAS low, non-persistent write-per-bittMH 10 10 ns th(RHrd) Hold time, both WEx high after RAS high, read (see Note 12) tRRH 0 0 ns th(RLCA) Hold time, column address valid after RAS low (see Note 13) tAR 30 30 ns th(RLD) Hold time, data valid after RAS low (see Note 13) tDHR 35 35 ns th(RLW) Hold time, WEx low after RAS low, write tWCR 30 35 ns th(RSF) Hold time, DSF after RAS low tFHR 30 35 ns th(RWM) Hold time, WEx low after RAS low, write-per-bit tRWH 10 10 ns th(SFC) Hold time, DSF after CAS low tCFH 10 10 ns th(SFR) Hold time, DSF after RAS low tRFH 10 10 ns th(SHSQ) Hold time, SQ after SC high tSOH 4 5 ns th(TRG) Hold time, TRG after RAS low tTHH 10 10 ns th(WLD) Hold time, data valid after first WEx low, late write tDH 15 15 ns th(WLG) Hold time, TRG high after WEx low (see Note 14) tOEH 10 10 ns td(CACH) Delay time, column address valid to CAS going high tCAL 30 45 ns td(CAGH) Delay time, column address to TRG high in real-time-load and late-load full-register transfer tATH 20 20 ns td(CARH) Delay time, column address valid to RAS high tRAL 30 35 ns td(CASH) Delay time, column address to first SC high after TRG high, early-load full-register transfer tASD 25 25 ns td(CAWL) Delay time, column address valid to first WEx low, read-modify-write tAWD 50 60 ns td(CHRL) Delay time, CAS high to RAS low tCRP 0 0 ns td(CLGH) Delay time, CAS low to TRG high, read 17 20 ns td(CLQSF) Delay time, CAS low to QSF switching, full-register transfer (see Note 15) tCQD 30 30 ns td(CLRH) Delay time, CAS low to RAS going high tRSH 17 20 ns td(CLRL) Delay time, CAS low to RAS low, CBR refresh tCSR 0 0 ns td(CLSH) Delay time, CAS low to first SC high after TRG high, early-load full-register transfer tCSD 20 20 ns td(CLTH) Delay time, CAS low to TRG high, real-time-load and late-load full-register transfer tCTH 15 15 ns td(CLWL) Delay time, CAS low to first WEx low, read-modify-write (see Note 16)tCWD 37 45 ns td(CLZ) Delay time, CAS low to DQ in the low-impedance state tCLZ 3 2 ns td(DCL) Delay time, data to CAS low tDZC 0 0 ns td(DGL) Delay time, data to TRG low tDZO 0 0 ns td(GHD) Delay time, TRG high before data applied at DQ tOED 10 15 ns † Timing measurements are referenced to VIL max and VIH min. NOTES: 12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle. 13. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference. 14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 15. TRG must disable the output buffers prior to applying data to the DQ pins. 16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is VOH / VOL = 2 V/0.8 V.

TMS55165, TMS55166, TMS55175, TMS55176 SMVS463 – DECEMBER 1995

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)† ALT. ’551xx-60 ’551xx-70 UNITSYMBOL MIN MAX MIN MAX UNIT td(GHQSF) Delay time, TRG high to QSF switching, full-register transfer (see Note 16) tTQD 25 25 ns td(GLRH) Delay time, TRG low to RAS high tROH 10 15 ns td(GLZ) Delay time, TRG low to DQ in the low-impedance state tOELZ 3 3 ns td(MSRL) Delay time, last SC high at boundary (127 or 255) to RAS low, split-register transfer 15 20 ns td(RHCL) Delay time, RAS high to CAS low, CBR refresh tRPC 0 0 ns td(RHMS) Delay time, RAS high to last SC high at boundary (127 or 255), split-register-transfer 15 20 ns td(RLCA) Delay time, RAS low to column address valid tRAD 15 30 15 35 ns ’551x5 tCSH 60 70 ns td(RLCH ) Delay time, RAS low to CAS high ’551x6 tCSH 53 60 ns() yg CBR tCHR 10 10 ns td(RLCL) Delay time, RAS low to CAS low (see Note 17) tRCD 20 43 20 50 ns td(RLQSF) Delay time, RAS low to QSF switching, full-register transfer (see Note 16) tRQD 65 70 ns td(RLSH) Delay time, RAS low to first SC high after TRG high, early-load full-register transfer tRSD 65 70 ns td(RLTH) Delay time, RAS low to TRG high (see Note 18) tRTH 50 55 ns td(RLWL) Delay time, RAS low to first WEx low, read-modify-write tRWD 80 95 ns td(SCQSF) Delay time, last SC high at boundary (127 or 255) to QSF switching, split-register transfer (see Note 16) tSQD 20 25 ns td(SCTR) Delay time, SC high to TRG high, full-register transfer tTSL 5 5 ns td(THRH) Delay time, TRG high to RAS high (see Note 18) tTRD –10 –10 ns td(THRL) Delay time, TRG high to RAS low (see Note 18) tTRP 40 50 ns td(THSC) Delay time, TRG high to SC high (see Note 18) tTSD 20 25 ns trf(MA) Refresh time interval, memory tREF 8 8 ms tt Transition time tT 3 50 3 50 ns † Timing measurements are referenced to VIL max and VIH min. NOTES: 16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is VOH / VOL = 2 V/0.8 V. 17. The maximum value is specified only to assure RAS access time. 18. Real-time-load and late-load full-register transfer

Figure 30. Read-Cycle Timing With CAS-Controlled Output

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† For TMS551x5, RAS high does not disable the output. For TMS551x6, both RAS and CAS must be high to disable the output. Figure 31. Read-Cycle Timing With RAS-Controlled Output

Figure 32. Early-Write-Cycle Timing Table 7. Early-Write-Cycle State Table

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Figure 33. Late-Write-Cycle Timing (Output-Enable-Controlled Write) Table 8. Late-Write-Cycle State Table

† DQ0 –DQ15 are all latched on the first falling edge of WEx. Thus tsu(DWL) and th(WLD) are referenced only to the first falling edge of WEx. Figure 34. Read-Modify-Write-Cycle Timing Table 9. Read-Modify-Write-Cycle State Table

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† For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8. Figure 35. Block-Write-Cycle Timing (Early Write) Table 10. Block-Write-Cycle State Table

† For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8. Figure 36. Block-Write-Cycle Timing (Late Write) Table 11. Block-Write-Cycle State Table

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Figure 37. Load-Write-Mask-Register-Cycle Timing (Early-Write Load)

Figure 38. Load-Write-Mask-Register-Cycle Timing (Late-Write Load)

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Figure 39. Load-Color-Register-Cycle Timing (Early-Write Load)

Figure 40. Load-Color-Register-Cycle Timing (Late-Write Load)

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mode (normal, block write, etc.). Figure 41. Enhanced-Page-Mode Read-Cycle Timing (TMS551x5)

mode (normal, block write, etc.). Figure 42. Extended-Data-Output Read-Cycle Timing (TMS551x6)

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Figure 43. Enhanced-Page-Mode Write-Cycle Timing Table 12. Enhanced-Page-Mode Write-Cycle State Table

Figure 44. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing Table 13. Enhanced Page-Mode Read-Modify-Write-Cycle State Table

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Figure 45. Extended-Data-Output Read-Followed-by-Write-Cycle Timing (TMS551x6)

of TRG is ignored after the th(TRG) specification is satisfied. Figure 46. Enhanced-Page-Mode Block-Write-Cycle Timing Table 14. Enhanced-Page-Mode Block-Write-Cycle State Table

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Figure 47. RAS-Only Refresh-Cycle Timing

Figure 48. CBR-Refresh-Cycle TIming Table 15. CBR-Cycle State Table

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Figure 49. Hidden-Refresh-Cycle Timing Table 16. Hidden-Refresh-Cycle State Table

data register are written into from the 256 corresponding columns of the selected row. D. Early-load operation is defined as th(TRG ) min < th(TRG ) < td(RLTH) min. Figure 50. Full-Register-Transfer Read Timing, Early-Load Operations

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are written into from the 256 corresponding columns of the selected row. D. Late-load operation is defined as td(THRH ) < 0 ns. Figure 51. Full-Register-Transfer Read Timing, Real-Time Load Operation/Late-Load Operation

Figure 52. Split-Register-Transfer Read Timing

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to avoid the initiation of a register-data transfer operation. Figure 53. Serial-Read Timing (SE = VIL)

to avoid the initiation of a register-data transfer operation. Figure 54. Serial-Read Timing (SE-Controlled Read)

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cycle and the first split-register cycle. half. After the td(MSRL) is met, the split-register-transfer into the inactive half must also satisfy the minimum td(RHMS) requirement. rising edge of the serial clock of the last bit (bit 127 or 255). Figure 55. Split-Register Operating Sequence

TMS55165, TMS55166, TMS55175, TMS55176 SMVS463 – DECEMBER 1995 65POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 MECHANICAL DATA DGH (R-PDSO-G64) PLASTIC SMALL-OUTLINE PACKAGE 4040068/B 10/94 0,00 MIN2,38 MAX 26,42 26,17 0,25 0,45 Seating Plane 0,40 0,70 11,96 14,00 12,12 14,50 Gage Plane 0,15 NOM 0,25 0,80 M0,12 0°–5° 0,10 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold flash or protrusion. Maximum mold protrusion is 0,125.

TMS55165, TMS55166, TMS55175, TMS55176 SMVS463 – DECEMBER 1995

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Speed Code (-60, -70) Package Code Lot Traceability Code Month Code Assembly Site Code Die Revision Code Wafer Fab Code -SS LLLL PYB TMS57175 DGH TI MW Year Code

67POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Split- Register Status Serial- Address Counter Output Buffer Input Buffer Input Buffer Row Buffer Column Buffer DQ0 – DQ15 A0 –A8 DSF SQ0 –SQ15 1 of 4 Sub-Blocks (see next page) 1 of 4 Sub-Blocks (see next page) 1 of 4 Sub-Blocks (see next page) 1 of 4 Sub-Blocks (see next page) QSF SE RAS CAS WEx TRG Special- Function Logic Refresh Counter Serial- Output Buffer Timing Generator SE SC

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DQ0 – DQ15 A0 –A8 DSF SQ0 –SQ15 1 of 2 Sub-Blocks (see next page) 1 of 2 Sub-Blocks (see next page) QSF SE RAS CAS WEx TRG Special- Function Logic Serial- Output Buffer Timing Generator SE SC Serial- Address Counter Refresh Counter

69POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 MECHANICAL DATA DGE (R-PDSO-G64/70) PLASTIC SMALL-OUTLINE PACKAGE 4040070-5/C 4/95 0.002 (0,05) MIN 0.011 (0,28) 0.013 (0,33) 0.047 (1,20) MAX 0.920 (23,36) 0.930 (23,63) 0.010 (0,25) Seating Plane 0.016 (0,40) 0.024 (0,60) 0.396 (10,06) 0.404 (10,26) 0.006 (0,15) NOM Gage Plane 0.455 (11,56) 0.471 (11,96) 0°–5° 0.004 (0,10) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion.

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