TMS5220

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The Engineering Staff of “ TEXAS INSTRUMENTS INCORPORATED WO Semiconductor Group TMS 5220 VOICE SYNTHESIS PROCESSOR DATA MANUAL TEXAS INSTRUMENTS

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6.5 Speak External eee ete tee e teen t tee ene ene 7

66 Reset ee cee eee tee eee 7

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1. INTRODUCTION

1.1 SCOPE

This manual describes in detail the functional characteristics of a linear predictive coding (LPC) speech synthesis device, the TMS 5220. In addition to this document, the user may wish to refer to the TMS 6100 128K bit ROM electrical specification,

1.2 KEY FEATURES

© ~~ High-quality voice communication from a microcomputer system e Low-data-rate LPC encoding © Low-cost P-channel MOS technology . +5 V and —5 V supplies only e Interrupt-based service requests @ = TTL compatible 1.3. DEVICE OPERATION The TMS 5220 Voice Synthesis Processor (VSP) enables verbal communication with a microcomputer based system. The VSP is fabricated using P-channel MOS technology and is TTL compatible. Speech data that has been compressed using pitch-excited linear predictive coding (LPC), is supplied to the VSP either by the CPU or by direct serial access of a Voice Synthesis Memory (VSM). The VSP decodes this data to construct a time-varying digital filter model of the vocal tract. This model is excited with a digital representation of either glottal air impulses (voiced sounds) or the rush of air (unvoiced sounds). The output of this model is passed through an eight- bit digital-to-analog converter to produce a synthetic speech waveform. The VSP has been designed to minimize the data rate required to produce synthetic speech and to simplify the interface with the host CPU. The CPU may service the device either in a polled fashion, by monitoring device status, or by respond- ing to interrupt service requests generated by the VSP. A simplified block diagram of the VSP is shown in Figure 1. 2. SYSTEMCLOCK This manual describes all VSP timing based on an 8-kHz sample rate {limiting the output frequency to 4 kHz) and a 40-Hz frame rate (the rate at which new speech data is fetched and processed). This requires the internal RC oscillator in the VSP to run at 640 kHz. The user has the mask-programmable option of balancing the internal oscillator with a resistor (completing the RC network). The 640-kHz clock is divided by four to produce two major phases, PHI-1 and PHI-2, with corresponding precharge clocks, PHI-3 and PHI-4 (see Appendix A). All control and timing operations within the VSP occur on one of the two 6.25-microsecond major phases. Twenty of these 6.25-microsecond bit times comprise each sample period (8-kHz sample rate). Twenty-five of these 125-microsecond sample periods make up one 3.25-millisecond interpolation inter- val, eight of which (ICO-IC7) make up the 25-millisecond frame period. During ICO, new speech data is transferred to the Synthesizer, at a 40-Hz frame rate. 3. CPU INTERFACE The CPU interface consists of an eight-bit bidirectional data bus (DO-D7), separate selects for read operations and write operations (RS & WS), a ready line for synchronization (READY) and an interrupt line (INT) to indicate a status change on the VSP that requires CPU attention.

——_ TIMING ROMCLK READY COMMAND VS MEMORY D0-D7 | CONTROL mo DATA i 1 M1

16 BYTE SPEECH SPK OUT

FIGURE 1 — VOICE SYNTHESIS PROCESSOR BLOCK DIAGRAM

3.1 RS AND WS

VSP activity on the memory data bus is controlled by the select lines as shown below. TABLE 1 — RS AND WS FUNCTION RS WS BUFFER CONDITION H H High impedance state H L Input to VSP. Some other device must be driving the bus (typically the CPU) L H Output from VSP. No other device should be driving the bus at this time. L L Illegal condition. Results not predictable. It is important to note that no device can successfully complete a Read cycle (from the VSP) while WS is active (low) nor can a successful Write cycle (to the VSP) be carried out while RS is active (low). Device behavior cannot be pre- dicted if both WS and RS go active simultaneously. System logic should be designed to prevent this condition from occurring.

3.2 READY

The VSP is a “Slow Memory“? device requiring wait states from the CPU to successfully complete a memory cycle. The effect of inserting wait states into memory access cycles is to extend the minimum allowable access time by one clock period for each wait state. The VSP controls the number of wait states executed by the CPU with the READY signal. The logic timing for typical read and write cycles to the VSP is shown in Figure 2. RS \\ / READY | | j DATA BU O FROM CP P 6 S yy mcPu RRL KKK KY FROM VS RRR WRITE CYCLE READ CYCLE FIGURE 2 — READ AND WRITE CYCLES TO THE VSP The READY line on the VSP goes high 100 ns after RS or WS goes active (low) to let the CPU know that the data trans- fer cycle cannot yet be completed. When the VSP has established stable data on the data bus (in the case of RS) or has completed latching data in from the data bus (in the case of WS), the READY line will go low indicating that the CPU may complete the data transfer cycle.

3.3 INTERRUPTS

The interrupt line (INT) indicates changes in the status of the VSP that may require CPU attention. INT goes active (low) when any of the following occur: e. Talk Status (TS) makes a one-to-zero transition indicating the end of speech processing. © Buffer Low (BL) makes a zero-to-one transition indicating that more phrase data needs to be supplied to the FIFO for Speak External Command. © Buffer Empty (BE) makes a zero-to-one transition indicating that the CPU failed to supply data fast enough for a Speak External Command.2 INT goes inactive (high) when the Status Register is read, or if the Reset instruction is executed. 4. VOICE SYNTHESIS MEMORY (VSM) — (TMS 6100) In addition to receiving speech data from the CPU, the VSP may directly access up to 16 TMS 6100's (128K-bit serial ROM) with no external hardware required. This is accomplished with a four-bit parallel bus (ADD8,4,2,1), (ADDS is multiplexed as the Data Out line out of the TMS 6100 as well as the most-significant bit of the 4-bit address bus in- to the TMS 6100), two control lines (MO, M1), and a synchronizing clock (ROMCLK). Isiow Memory devices are those devices that cannot properly respond to system memory cycles within the minimum access time as deter- mined by the CPU clock rate. 2,An interrupt will be generated at the initiation of a Speak External Instruction if BE was previously low, 3

1. I/O STRUCTURE The VSP has two input holding registers, a Command Register and a 128-bit FIFO Buffer, and two output holding registers, the Data Register and the Status Register. On a Write cycle from the CPU, when WS becomes active (low), the control logic of the VSP routes data from the Memory Data Bus to either the FIFO Buffer (if a Speak External command is executing) or the Command Register (all other cases). Once this data has been latched in, the VSP signals completion of the data transfer to the CPU by lowering the READY Line to its active (low) condition. Similarly, on a Read cycle, when RS goes active (low), the VSP puts either the contents of the Data Register on the bus (if the preced- ing command was a Read Byte command) or the contents of the Status Register (all other cases).

5.1 COMMAND REGISTER

The Command Register receives command data from the Memory Data Bus and holds it for the Controller to interpret and execute. The VSP behaves as an attached processor to the host CPU and performs its synthesis tasks when appro- priate commands are sent by the host CPU, For details on available commands and format, see Section 6.

5.2 FIFO BUFFER

The 128-bit FIFO Buffer is organized as a 16-byte parallel-in, serial-out buffer. This buffer is used to hold speech data passed from the CPU to be processed by a Speak External command in the VSP. As required by the synthesis section, data is shifted out serially starting with the LSB from the “First-In’ byte. When this byte has been exhausted, the stack ripples down one byte and begins shifting out bits from the new “First-In” byte. A Stack Pointer keeps track of the location of the “Last-In" byte and data from the CPU is always loaded just above this location. When the stack becomes less than half full (i.e., eight byte locations are void of data), the buffer-low status condition (BL) becomes true. This signals the CPU that more data should be provided to the VSP. Under worst-case conditions, the buffer will be completely empty in one more frame period (25 milliseconds), and invalid data will be processed as external speech data. As a Fail-Safe measure, if the buffer does reach such a condition, the buffer empty status (BE) becomes true and the Talk Status Latch is reset causing speech to terminate immediately. To resume speech with data provided by the CPU, another Speak External command must be issued.

5.3 DATAREGISTER

The eight-bit Data Register is organized as a serial-in parallel-out Holding Register. This register is used by the VSP to formulate a byte of data from serial data fetched from the VSM during the execution of a Read Byte command. Data is loaded to the Data Register so that the last bit loaded is in the least-significant-bit location (D7). When the Data Register has been loaded and RS goes active (low), this byte is transferred to the Memory Data Bus (DO = MSB). The READY Line goes low when the data is stable.

5.4 STATUS REGISTER

The three bits of the Status Register provide up-to-date information to the CPU on the state of the VSP. The Status Register may be read at any time except immediately after passing a Read Byte command to the VSP. When RS goes active (low) the VSP routes the status data to the Memory Data Bus (DO = TS; D1 = BL; D2 = BE) and lowers the Ready Line when the data is stable. TS — Talk Status is active (high) when the VSP is processing speech data. Talk Status goes active at the initiation of a Speak command or after nine bytes of data are loaded into the FIFO following a Speak External command. It goes inactive (low) when the stop code (Energy = 1111) is processed, or immediately by a buffer empty condition or a reset command. Audio output is interpolating to zero during this frame and is terminated on the next frame boundary. BL — Buffer Low is active (high) when the FIFO Buffer is more than half empty. Buffer Low is set when the “Last-In” byte is shifted down past the half-full boundary (becomes the eighth data byte) of the stack. Buffer Low is cleared when data is loaded to the stack so that the “Last-In” byte lies above the half-full boundary and becomes the ninth data byte of the stack. BE — Buffer Empty is active (high) when the FIFO Buffer has run out of data while executing a Speak External command. Buffer Empty is set when the last bit of the "’Last-In’ byte is shifted out to the Synthesis Section. This causes Talk Status to be cleared. Speech is terminated at some abnormal point and the Speak External command execution is terminated. Data from the Memory Data Bus is once again routed to the Command Register.

1. DESCRIPTION OF COMMANDS The VSP operates under the control of the CPU to a minimal degree. The CPU passes commands to the VSP which initiates an activity but the CPU is not involved in carrying out that activity. Commands available for use by the CPU and the formats of these commands are shown below: TABLE 2 — VSP COMMANDS AND COMMAND FORMAT DATA BUS COMMAND CODE (D0-D7)* OPERATION X000XXXX Nop X001XXXX Read Byte X010XXXX Nop X110XXXX Speak External XO11XXXX Read and Branch X100AAAA* Load Address X101XXXX Speak X111XXXX Reset +A = Address X = Don't care When WS becomes active (low), assuming a Speak External command is not presently executing, the data on the memory data bus is latched into the command register. Once the transfer has been completed, the VSP activates (low level) the READY line to release the CPU and begins interpreting and executing the command. Command execution for each instruction is described below. If the user tries to pass a command to the VSP while another command is executing, the new command will not be accepted until the previous command is completed. The VSP keeps the CPU executing wait states until it is ready to accept a new command. Appendix C lists execution times for each command. The VSP uses the READY flag to tell the CPU to execute wait states until the present command has been fully executed.

6.1 READ BYTE

The Read Byte command allows the CPU to access data stored in the TMS 6100 VSM. Read Byte causes the next eight bits to be read from the VSM (ignoring byte boundaries). These bits are packed into the data register so that the last bit read from VSM is in the least-significant-bit position (D7). When RS goes active (low), and before initiation of a new instruction, this data byte is placed on DO-D7. This eight-bit transfer from the VSM requires 80 microseconds. If RS should become active before the data register is completely loaded and ready to be transferred, the VSP keeps the CPU executing wait states (by not lowering the READY line) until the data transfer from VSM is complete and the Data Byte is stable on the Memory Data Bus. At this time the READY line is activated and the CPU may accept the Data Byte to complete the memory cycle.

6.2 READ AND BRANCH

The Read and Branch command causes the VSP to initiate a Read and Branch function on the VSM (see VSM descrip- tion). The VSP is not able to access the VSM for 240 microseconds after executing this command. 6.3. LOAD ADDRESS The Load Address command allows the CPU to alter the Address Register of the TMS 6100 to point to new speech data. Load Address causes the VSP to load the four address bits from the VSP Address Register to one nibble of the VSM Address Register by initiating a VSM Load Address function (see VSM description). If the next command follow- ing is a Read Byte, Speak, or Reset command, a dummy Read function is passed to the VSM before that next command is executed. Bit D7 is loaded into ADD1 which is the LSB of the VSM address. Bit D4 is loaded into ADD8.

6.4 SPEAK

The Speak command allows speech to be generated from phrase data stored in the VSM. The Speak command gener- ates an internal signal that immediately causes Talk Status to be set and initiates speech synthesis calculations using the next available data from the VSM. Audio output begins on the following frame boundary. The VSP continues to fetch data from the VSM and generates speech output until a stop code (Energy = 1111) is received and recognized. At such time the audio output begins to interpolate down to the zero energy level. On the next frame boundary, speech has ended and the Talk Status is cleared. This completes execution of the Speak command. Execution of the Speak command may also be halted by the execution of Reset command. This causes audio output to halt immediately (without waiting for a frame boundary) and Talk Status to be cleared.

6.5 SPEAK EXTERNAL

The Speak External command allows the CPU to supply speech data to the VSP from some memory other than the VSM. Upon receipt of a Speak External command, the VSP purges the FIFO buffer (BL and BE becomes active [high] } and directs data written into the VSP to this buffer. The VSP idles waiting for the CPU to fill the buffer before speech begins. When the buffer low status becomes false (by the CPU loading a minimum of nine bytes to the FIFO), Talk Status is set and speech synthesis calculations begin using data from the FIFO. Data continues to be taken from the FIFO until a stop code is encountered or the buffer empty abnormal termination occurs. While the Speak External command is executing, all data written to the VSP is routed to the FIFO buffer. A Reset command is not recognized as a command.

6.6 RESET

The Reset command allows the CPU to halt the Speak command and to put the VSP into a known state. Reset clears Talk Status, halting speech activity immediately. The 128-bit FIFO Buffer is purged (BL and BE become active [high] ) and the I/O paths are set to their default condition (Memory Data Bus > Command Register; Status Register > Memory Data Bus). A Load Address function is given to the VSM (using dummy address data) followed by a “Dummy Read’ function, The Reset command cannot halt the Speak External command. Flow diagrams for each instruction are given in Appendix B, System timing diagrams may be found in Appendix C. 7. POWER-UP CLEAR The VSP contains internal circuitry to ensure a clear condition 95 percent of the time upon power-up, provided the (Vsg — Vpp) rise time to +10 volts is less than 2 milliseconds. If more than one power supply is used, the voltages need to be supplied to the VSP simultaneously. The Power-Up Clear sequence is finished 15 milliseconds after (Vgs — Vpp) reaches +10 volts. The events caused by the Power-Up Clear are similar to the Reset command and are noted below: e Talk Status is cleared and any speech activity is halted. e The T State Counter is reset. e The FIFO is purged (BL & BE go active [high] ) possibly causing the INT line to become active (low). e 1/O multiplexers are set to allow data to be written to the Command Register, and Data Read from the Status Register. e The TMS 6100 is put into a known state by issuing a Load Address (using arbitrary address data) followed by a “Dummy Read”. If the user requires higher reliability in securing initialization, he should execute his own initialization sequence. A 100- percent assurance can be given that the VSP is in a clear state by writing nine bytes of all “ones” to the VSP followed by a Reset command, provided that (Vgg — Vpp) rise time to +10 volts is less than 2 milliseconds. 8. SPEECH SYNTHESIS As previously mentioned, speech data fed to the VSP is encoded using pitched-excited LPC. The process of recover- ing this data is described briefly here and in more detail in the following sections. (This information is intended solely for the reader’s information. Proper application of the VSP does not depend on a thorough understanding of this process). A simplified block diagram of the speech synthesis element of the VSP is shown in Figure 4.

PARAMETER | _) — LOOK-UP RAM ROM CODED CODED PARA PARAMETER METER DATA INPUT REGISTER DECODE LOGIC & INTERPOLATION PARAMETER conoition |) CONTROLLER INTERPOLATER LATCHES all EXCITATION SIGNAL Lec GENERATOR ATT woiceoa [| __) Nerwon UNVOICED) pa FIGURE 4 — SYNTHESIZER BLOCK DIAGRAM Coded speech parameter data is fed serially from either the VSM or the FIFO buffer to the Parameter Input Register. Here the Controller unpacks the data and performs various tests (i.e., is the repeat bit set, is pitch zero, is energy zero). Once unpacked the coded parameter data is stored in RAM to be used as the index value to select the appropriate value from the Parameter Look-Up ROM. The outputs of the Parameter Look-Up ROM are the target values for the interpolation logic to reach in this frame period. During each of the eight interpolation periods the interpolation logic sends new pitch and energy parameters to the signal generator which produces the filter excitation sequence, and new K-parameter values to the LPC lattice network. So, at the end of each sample period there is a new value of digitized synthetic speech available to the D/A converter.

8.1 CODED SPEECH PARAMETERS

The 12 synthesis parameters (pitch, energy and reflection coefficients K1-K10), are stored in the VSM in coded form. Each parameter occupies between 3-6 bits. These coded values select a 10-bit actual parameter from the parameter Look-Up ROM. Depending on the influence of each parameter on speech quality, between 8 and 64 possible values are stored in the Look-Up ROM for decoding and use in synthesis calculations. Table 3 summarizes parameter coding for the TMS 5220. TABLE 3 — PARAMETER CODING PARAMETER LEVELS CODE BITS ENERGY 15* 4 PITCH 64 6 K1 32 5 K2 32 5 K3 16 4 K4 16 4 KS 16 4 K6 16 4 K7 16 4 K8 8 3 kg 8 3 K10 8 3 12 247 49+REPEAT=50BITS 8 *Energy = 1111 is the stop code,

A full set of coded parameters for each frame would require a data rate of 40 Hz X 50 bits = 2000 bits per second. Three special cases, in which a full frame is not necessary, allow the data rate to be considerably reduced: (1) Since the vocal tract changes shape relatively slowly, it is often possible to repeat previous reflection coefficient data. To facilitate the repeat feature, a control bit has been added to each frame (an additional bit following energy). If the repeat bit is 1, only energy and pitch data are accessed from the VSM and the previous K1-K10 values are retained. (2) Unvoiced speech requires fewer filter reflection coefficients. When Pitch = 000000, only K1-K4 are fetched from the VSM and stored in the Parameter RAM. K5-K10 are zeroed. (3) When Energy = 0000 no other data is required. Energy = 0000 during interword or intersyllable pauses. The com- bination of these three cases has reduced average data rate for male speech to approximately 1200 bits per second. Figure 5 shows the four possibilities of frame data string lengths. Fa in z fil @ 3 ENERGY _ PITCH K1 K2 K3 K4 KS K6 K7 Ks Kg K10 VOICED FRAME TTT Too unvoiceo Frame [_[ofoooooo] | | | (PITCH = 0) ia nepear Frame [| 1] ZERO ENERGY FRame L000] STOP CODE Frame LLU 4BITS 1BITEBITS 5BITS SBITS 4BITS 4BITS 4BITS 4BITS 4BITS 3BITS 3BITS 3BITS FIGURE 5 — FRAME DATA STRING LENGTHS One complete set of parameters (12), used as target values during interpolation, is stored in coded form in the synthe- sizer. The storage medium is a 50-bit RAM of variable word length, e.g., six bits for pitch, three bits for K10. Data is supplied to the RAM via the parallel outputs of a serial shift register which accepts data from some VSM. The Parameter RAM outputs are used as inputs for the Parameter ROM.

8.2 D/A CONVERSION

The VSP contains an eight-bit digital-to-analog converter with 2% linearity LSB resolution. Every 125 microseconds the most-significant 10 bits of the 14-bit lattice filter output are sampled. From this sample, the seven low-order bits and the sign bit (MSB) are sent to the D/A converter. The remaining two bits are combined logically with the sign bit and used to clip the driver to either a full ON or full OFF condition. Table 4 shows the analog output from the D/A con- verter for various inputs from the lattice filter. 9

TABLE 4 — DIGITAL-TO-ANALOG CONVERTER OUTPUT Y LATCH OUTPUT D/A INPUT ANALOG OUTPUT Yu13 Yui2 Yuu YL10-YL4 (ua) i) 1 1 x 11119191 o >+127 0o 1 oO x 11111111 0o tY) 0 1 x 11919111 oO 127 0 0 0 1119911 44001111 0 126 0 0 i} 1111110 11111110 5.86 +1 i) 0 it} 0000001 10000001 738 oO 0 0 it} 0000000 10000000 744 4 1 1 1 1111111 01411111 750 -2 1 1 1 1111110 01111110 755.8 128 1 1 1 000000 00000000 1500 <-128 1 1 0 x 00000000 1500 1 0 1 x 00000000 1500 1 i} i} xX 00000000 1500 “No output, resting level.

8.3 AUDIO OUTPUT

The output of the D/A converter (see Table 4) is a current source designed to deliver 0 to 1.5 milliamperes with resolu- tion to 5.9 microamperes. This output has been optimized to drive the EXT AUD input of the SN76489AN sound generator chip. With a 1.8-kilohm resistor in series, the VSP delivers 2.7 volts (1 = 1.5 milliamperes) when the Y latch output is less than —128. When the Y latch output is greater than +127, the audio output is clipped to 0 volts. When no speech generation is taking place, the Y latch output is —1 making the audio output drive 750 microamperes. (Speaker output must be ac-coupled to audio amplifier). 9. ELECTRICAL CHARACTERISTICS

9.1 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHER-

WISE NOTED)* Any pin with respect to VSG we eect eect e reese =20V t0 40.3 V Power Dissipation 6.1 ete eee eee eee ees 600 mW Operating temperature range 6. cece eee eee eee vevessee O°C to 70°C Storage temperature range 2. eee eee eee eee ee eees 30°C to 125°C “Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

9.2 RECOMMENDED OPERATING CONDITIONS

Po ramameren mn Nom Max [unit | [SwmoirvotweVes— SSCS [ Supply vole, VaEF SS [Operational frequency (External RQ) SSS*dSC RFR we] NOTE 1: The algebraic convention, where the more-positive (less-negative) limit is designated as maximum, is used in this data sheet for logic voltages levels only. 10

9.3 ELECTRICAL CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED OPERATING CONDITIONS

OH _ROMGLK, ADD 1-8, NO, TQH = 100 uA 7 00-07, WS, FS, INT TOL= 1.6 mA Ot _ROMCLK, ADD 1-8, MO, MI ToL = 100 nA [Timer Supply current tomVaer SSSCSCSC—S~C“~SC“~SCSC‘“~‘dSSSSSCSCS | [ci put capacitance, @xceptdetabus) ————SSSSCSCSCSCSCSCSC“CS~S~S tid [co Ourpureapectnce,excent tobe id [Cap _Databustood eapecionce SSCS SSSC~«

9.4 STATIC DISCHARGE PROTECTION

All inputs and outputs are guarded against electrostatic damage by state-of-the-art protection devices incorporated ‘on the chip.

1. MECHANICAL DATA 11.1 28-PIN 600-MIL PLASTIC PACKAGE (100-MIL PIN SPACING) 2 2 285 = = goo € 2 €,ees g © [s|e 8h 8 sorts ger. 2 gS ois $ 3 a 3 @ ) 3 g T = 3 3 s S es gS gs as 25 x Se 3 55 ca on 8 e 2§ | EB gs oe a> 28 238 g~ —s g Fs ot 2 Ss z 3s O +" i: ~ “F gu g Be 38 ez 8s 23 ef oo 2 3 ge e2& § x g 88 z¢ ra < =~ 3 2 ee $3 2 38 82 @ 2 eo a 88 22 o 383s 2s —_— =e Ze w a 55 = 2s $= : so Peg : ae sa 23 a : 32 e. o : als 5 “ 2 = ow

11.2 PIN ASSIGNMENTS AND FUNCTIONS

1 DBUS7 ie) Memory data bus (LSB)

2 ADD1 te) Address bus to VSM (LSB)

3 ROMCLK (o) Clock to VSM

4 Vpp 1 Drain supply voltage (5 V NOM)

5 Vss 1 Substrate supply voltage (+5 V NOM)

6 Osc ! Oscillator input

7 T11 (¢) Sync

8 SPEAKER (e} Audio output

10 PROM OUT ° Testing use only

1 VREF I Ground reference voltage (0 V NOM)

12 DBUS 2 v0 Memory data bus

13 DBUS 1 v0 Memory data bus

14 DBUS 0 vO Memory data bus (MSB)

15 mo (o) Command bit 0 to VSM

16 ML to) Command bit 1 to VSM

17 INT (o} Interrupt (active low)

18 READY (o) Transfer cycle W/CPU complete

19 DBUS 3 ie) Memory data bus

20 TEST \\ Testing use only

21 ADD8/DATA ie) Address to VSM and serial data in (MSB)

22 DBUS 4 ie) Memory data bus

23 ADD 4 ° Address bus to VSM

24 DBUS 5 ie) Memory data bus

25 ADD 2 ° Address bus to VSM

26 DBUS 6 0 Memory data bus

27 ws I Write select (active low)

28 RS I Read select (active low)

11.3 TERMINAL ASSIGNMENTS

of: [J] aa aop1 [] 2 271] ws RomcLK [] 3 26{] v6 Vop [] 4 25 [] avp2 Vss [] 5 24[] o5 osc [] 6 23[ | appa m7 22[] v4 SPEAKER | | 8 21{ | ADDs/DATA Vo }] 9 20] | TEST PROM OUT [] 10 19[] 03 Veer [] 11 18 |] READY o1[] 13 16f] m1 Do [] 14 15[] mo

‘TMS 5200 osc wool (3) 10 pF RZ vsP RC OPTION TYPICAL VALUES: SAMPLE FREQUENCY R 10 kHz R = 80-100 ka 8 kHz R= 120-200 k2 FIGURE A-1 — TMS 5200 OSCILLATOR OPTIONS A.1_ OSCILLATOR TRIMMING PROCEDURE To avoid capacitive loading of the high impedance OSC input, the following procedure is recommended for setting the TMS 5220 clock frequency. Reference to Table A-1, Comparison of System Times (page 16), shows that an RC oscilla- tor frequency of 640 kHz corresponds to a ROM clock rate of 160 kHz. This signal is buffered and not affected by measurement instrument capacities. To set the RC oscillator frequency, connect a frequency counter to the ROM clock output of the TMS 5220 and trim the reading to 160 kHz. Use of 10 pF shunt capacitor is recommended to prevent circuit layout and environmental stray noise from affecting device operation.

+e $ Le BD re 5 z 9 re $ +e o = wv 2 5 8 9 2 = z | z & sjo é rile z 3 z aed i g “lo 2 a be 2 slz 8 ys Fa SG w Fs 2 2 3 = ras 5 w < = bold = 32 = F (3) 54 = Qs z = fa x a i & re 8 eG Py w a 3 Ko 6 1 = . & te = p 3 5 3 < Ld ro 7 w nes 3 Fe z le} <2 9 g c 20 6 6 is} Qe re a a Ee oo a & € ¢ rae) Q bas q Se = oN Ss ° 2 = 2 seg es fe} x = Qa 28 c & 8&8 8a fo - & @ ¢ oZ GE = fF =F ef oF & a = a

TABLE A-1 — A COMPARISON OF SYSTEM TIMES FRAME RATE 50 Hz 40 Hz FRAME PERIOD 20 ms 25 ms INTERPOLATION RATE 400 Hz 320 Hz INTERPOLATION INTERVAL 2.5 ms 3.125 ms SAMPLE RATE 10 kHz 8 kHz SAMPLE PERIOD 100 ps 125 us ROM CLOCK RATE 200 kHz 160 kHz ROM CLOCK PERIOD Sus 6.25 us RC OSC RATE 800 kHz 640 kHz RC OSC PERIOD 1250 ns 1562.5 ns NOTE: All timing references in this data manual are based on an 8-kHz sample rate.

TMS 5220 INTERNAL COMMAND EXECUTION EXECUTE POWER-UP CLEAR (RESET) ROUTINE RS a ACTIVE (LOW) Y ‘BOTH RS Y INVALID & WS ACTIVE CONDITION N MAKE READY ACTIVE (Low) FIGURE B-1 — POWER ON 17

RDB FLAG TRANSFER TO DATA BUS. SET? COMPLETE? CLR RDB FLAG N MAKE READY LINE TRANSFER INACTIVE (HIGH) STATUS REG. TO DATA BUS MAKE READY LINE INACTIVE (HIGH) N — TURN BUS OFF N TURN BUS = OFF FIGURE B-2 — READ SELECT ACTIVE

x ANAND Y TRANSFER DATA BUS NI EXECUT| IG TO FIFO N MAKE READY INACTIVE (HIGH) Is ANY COMMAND. STILL EXE- CUTING ? N Com) TRANSFER DATA BUS TO COMMAND REGISTER MAKE READY INACTIVE (HIGH) BEGIN EXECUTION OF NEW COMMAND FIGURE B-3 — WRITE SELECT ACTIVE

INPUT: DATA BUS ~ FIFO FIFO > SPEECH DATA OUTPUT: STATUS REG > DATA BUS SPEECH DATA REQ FIFO PURGE FIFO FORCING BL & BE ACTIVE CPU MUST WRITE 8 DATA BYTES TO FIFO N SET TALK STATUS INITIATE SPEECH SYNTHESIS, FETCHING DATA FROM FIFO AS REQUIRED. ¥ HALT SPEECH SYNTHESIS DEACTIVATE TALK STATUS TS=0 RESET |/O PATHS TO DEFAULT. HAS INPUT: SPEECH SYNTH. DATA BUS > COMMAND REG. BEEN COMPLETED VSM > SPEECH DATA (STOP CODE OUTPUT: ENCOUNTERED) ? STATUS REG + DATA BUS SPEECH DATA REQ VSM N FIGURE B-4 — SPEAK EXTERNAL COMMAND 20

SYNTHESIS & CLEAR TALK STATUS PURGE FIFO RESET I/O PATHS TO DEFAULT INPUT: DATA BUS -> COMMAND REG. VSM SPEECH DATA OUTPUT STATUS REG + DATA BUS SPEECH DATA REQ— VSM EXECUTE A LOAD ADDRESS FUNCTION ON THE VSM W/ARBITRARY DATA EXECUTE A DUMMY READ FUNCTION ON vsM FIGURE B-5 — RESET COMMAND

SYNTHESIS, FETCHING DATA FROM THE VSM AS REQUIRED FIGURE B-6 — SPEAK READ AND BRANCH INITIATE A VSM READ AND BRANCH FUNCTION WAIT 240 MICROSECONDS FIGURE B-7 — READ AND BRANCH

Write Cycle for Read and Branch, Load Address, Speak, Speak External and Reset Commands timing requirements PARAMETER MIN NOM MAX [UNIT TWSL-DV__ Delay time from WS low to data valid [7 os | TRL-DX __Delay time from READY low to data invalid | o—*«| as | tRH-WSH __ Delay time from READY high to WS high [ 6 sas | twait Read-and-branch command wait time from READY high until next allowable* command [8S | ws | twait Load-address command wait time from READY high until next allowable* command [Css | + ‘Speak command wait time from READY Preceded by load-address command ; wait high until next allowable* command Not preceded by load-address command [ «| twait Reset command wait time from READY high until next allowable* command [800s | twait Speak external command wait time from READY high until next allowable* command [2s | switching characteristics PARAMETER [ min Nom Max [UNIT tWSL-RH Delay time from WS low to READY high [100 | os | twiR) READY high pulse width [Ls as | All timing is based on a clock frequency of 8 kHz. * If @ new command is issued prior to the completion of the present command (before the end of twajt), then the READY signal will go high and stay high until the present command is finished executing in the VSP. _ pn en RS IN ‘ SIN w nN H _A Re. peel WSL-AH tWSL-RH -o| _ READY OUT H > ‘WsL-DV—ol atl tRL-DX DATA BUS IN = HI-Z VALID DATA REQUIRED AZ FIGURE C-1

WRITE CYCLE FOR EXTERNAL SPEECH DATA timing requirements PARAMETER [ MIN Nom MAX [UNIT {WSL-DV _ Delay time from WS low to data valid tRL-DX Delay time from READY low to data invalid ee 'RH-WSH__Delay time from READY high to WS high ee [ait Walt time fom'WS Fgh uni next allowable aeeese to] switching characteristics PARAMETER MIN TYP MAX [UNIT TWSL-RH__Delay time from WS low to READY high [100 ns | wih) READY high pulse width All timing is based on a clock frequency of 8 kHz, * If a new command is issued to the VSP prior to the completion of the present command then the READY command will go high (as usual) and remain high until the completion of the present command as defined by tyair above. nit _—_ _ f>— "RH wsH of 1 WS IN x 7# * NI feet 'WsL-RH 'WSL-RH ol ~- ——_ ' READY OUT I x Ye 4 7 wip) 1 > 'WSL.DV—# et etx DATA BUS IN —— fr HZ FIGURE C-2

READ CYCLE FOR STATUS TRANSFERS timing requirements PARAMETER [win Nom max | UNIT TRH-RSH ___Delay time from READY high to RS high | 6 ——*ids_as | twait Wait time from FS high to next allowable command (es switching characteristics PARAMETER MIN TYP MAX | UNIT TRSL-RH __Delay time from RS low to READY high [SSS=«*00 ss _'| TRH-DV Delay time from READY high to data valid (stable) [ews | tRSL-DX Delay time from RS low to data bus driven (output unstable) tRH-DV—-2 | us | tRSH-DZ Delay time from Mis high to data output disabled [t~“C~ésNSTT nts * If @ new command is issued to the VSP prior to the completion of the present command, then after the READY signal goes high, in its normal response time, it will remain high until the present command has been fully executed by the VSP. ‘RS IN ! ‘4. 1 1 UN ween cpecceee _ a a a + t BY WS IN 1 ' an beet tRSLRH ' ! ' — ' READY OUT iA \\ 1 1 e——'RH.DV——ot r bo——-#+- 'RSL-0X. Hq ao tRSH-DZ a ereres, DATA BUS our $A FIGURE C-3

PARAMETER [wun _Nom max | unir tWSL-DV__ Delay time from WS low to data valid TRH-WSH Delay time from READY high to WS high [es] tWSH-DX Delay time from WS high to data invalid pons | 'tRH-RSH Delay time from READY high to RS high [es] TWSH-RSL__ Delay time from WS high to RS low es switching characteristics PARAMETER MIN TYP MAX | UNIT WSL-RH __Delay time from WS low to READY high [100s | tRSL-RH Delay time from RS tow to READY high [100 ns | twiR) READY high pulse width (write) [Gs | revious load address TRSH-DZ __Delay time from RS high to data output disabled [4 as | RSIN Xk 1 He fe—wsr-nsi—of 1 t WS IN | leet ] H RSL-RH \\ READY OUT 4 x Yi \\ wiR) 1 ke wst-ov tWSH-DX TRSH-DZ—4e-—0} oNIOUT EO, Rs taal Kvatio ourrur Y VALID DATA REQUI HL-Z: 6 INour LID DATA REQUIRED -_— KUNSTABLEX VALID OUTPUT FIGURE C-4

RMS PITCH K(1) K(2) K(3) K(4) K(5) K(6) K(7) K(8) K(9) (10) 30 —0,80420 0.48553. 31 0.74058 0.54464 32 -0,66019 0.59878 33 -0,56116 0.64796 34 0.44296 0.69227 35 -0,30706 0.73190 36 © -0,15735 (0.76714 37° -0,00005 0.79828 38 0.15725 (0.82567 39 0.30696 0.84965 40 0.44288 0.87057 41 0.56109 0.88875 42 0.66013 0.90451 44 0.74054 0.91813 46 0.80416 0.92988 48 0.85350 0.98830 101 105 109 114 118 122 127 132 137 142 148 153 159