TMS427809A

TMS417809A TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 29

Technical content

TMS417809A, TMS427809A, TMS427809AP

2097152 BY 8-BIT EXTENDED DATA OUT

DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 This data sheet is applicable to all TMS417809As and TMS427809A/Ps symbolized by Revision “E” and subsequent revisions as described in the device symbolization section. /C0068Organization...2 0 9 7152 by 8 Bits /C0068Single Power Supply (5 V or 3.3 V) /C0068Performance Ranges: ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tCAC tAA tHPC MAX MAX MAX MIN ’417809A-50 50 ns 13 ns 25 ns 20 ns ’417809A-60 60 ns 15 ns 30 ns 25 ns ’417809A-70 70 ns 18 ns 35 ns 30 ns ’427809A/P-50 50 ns 13 ns 25 ns 20 ns ’427809A/P-60 60 ns 15 ns 30 ns 25 ns ’427809A/P-70 70 ns 18 ns 35 ns 30 ns /C0068Extended-Data-Out (EDO) Operation /C0068CAS -Before-RAS (CBR) Refresh /C0068Long Refresh Period and Self-Refresh Option (TMS427809AP) /C0068High-Impedance State Unlatched Output /C0068High-Reliability Plastic 28-Lead 400-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DZ Suffix) and 28-Lead 400-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGC Suffix) /C0068Ambient Temperature Range 0°C to 70°C AVAILABLE OPTIONS DEVICE POWER SUPPLY REFRESH CYCLES TMS417809A 5 V 2048 in 32 ms TMS427809A 3.3 V 2048 in 32 ms TMS427809AP 3.3 V 2048 in 128 ms These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS417809A is offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). The TMS427809A/P is offered in a 28-lead plastic surface-mount TSOP package (DGC suffix). These packages are designed for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PIN NOMENCLATURE A[0:10] Address Inputs DQ[0:7] Data In/Data Out CAS Column-Address Strobe NC No Internal Connection OE Output Enable RAS Row-Address Strobe VCC 3.3-V or 5-V Supply VSS Ground W Write Enable DZ/DGC PACKAGE (TOP VIEW) VCC DQ0 DQ1 DQ2 DQ3 W RAS NC A10 VCC VSS DQ7 DQ6 DQ5 DQ4 CAS OE V SS The TMS417809A and TMS427809A series are 16777216-bit dynamic random access memory (DRAM) devices organized as 2097152 words of 8 bits each. The TMS427809AP series is a low-power, self-refresh, 16777216-bit DRAM organized as 4194304 words of four bits.They employ TI state-of-the-art technology for high performance, reliability, and low power.

description

Copyright  1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997

2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

logic symbol (TMS417809A and TMS427809A/P)† DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 RAS CAS W OE RAM 2M x 8 20D10/21D0 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21[COL] G24 23C22 23,21D 24 ,25EN A,Z26 A8 20 A9 21 G25 A,22D ∇ 26 A 0 2 097 151 20D20A10 9 20D19/21D9 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram (TMS417809A and TMS427809A/P) Timing and Control Column- Address Buffers Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers R o w D e c o d e 256K Array 256K Array 256K Array 256K Array 256K Array 256K Array DQ0–DQ7 RAS CAS W OE A10 operation extended data out Extended data out (EDO) allows data output rates up to 50 MHz for 50-ns devices. When keeping the same row address while selecting random column addresses, the time for row-address setup-and-hold and for address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by t RASP , the maximum RAS low time. The EDO does not place the data-in/data-out pins (DQ pins) in the high-impedance state with the rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO operation benefits. address: A0–A10 Twenty-one address bits are required to decode each of the 2097152 storage-cell locations. Eleven row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Ten column-address bits are set up on A0 through A9. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip-enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip-select, activating the output buffers and latching the address bits into the column-address buffers. output-enable (OE) OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two methods of placing the DQs into the high-impedance state and maintaining that state during CAS high time. The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE from CAS ) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further transitions on OE until CAS falls again (see Figure 8).

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997

4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

write-enable (W) The read- or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled as long as CAS is high (see Figure 8). data in/data out (DQ0–DQ7) Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the latter of the falling edges of CAS or W strobes data into the on-chip data latch with setup-and-hold times referenced to the latter edge. The DQs drive valid data after all access times are met and the data remains valid except in cases described in the W and OE descriptions. RAS -only refresh A refresh operation must be performed once every 32 ms (128 ms for TMS427809AP) to retain data. This can be achieved by strobing each of the 2048 rows (A0–A10). A normal read- or write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS -only refresh. hidden refresh A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS -only refresh cycle. The external address is ignored and the refresh address is generated internally. CAS -before-RAS (CBR) refresh CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR ) and holding it low after RAS falls (see parameter tCHR ). For successive CBR-refresh cycles, CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. battery-backup refresh TMS427809AP A low-power battery-backup refresh mode that requires less than 350 /C0109A of refresh current is available on the TMS427809AP . Data integrity is maintained using CBR refresh with a period of 62.5 /C0109s while holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels IL< 0.2 V, VIH >V CC – 0.2 V). self-refresh (TMS427809AP) The self-refresh mode is entered by dropping CAS low prior to RAS going low, then CAS and RAS are both held low for a minimum of 100 /C0109s. The chip is refreshed internally by an on-board oscillator. No external address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS are brought high to satisfy tCHS . Upon exiting self-refresh mode, a burst refresh (refreshes a full set of row addresses) must be executed before continuing with normal operation to ensure that the DRAM is fully refreshed. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full V CC level. These eight initialization cycles must include at least one refresh (RAS -only or CBR) cycle.

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions TMS417809A TMS427809A/P MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 3 3.3 3.6 V VSS Supply voltage 0 0 V VIH High-level input voltage 2.4 6.5 2 VCC + 0.3 V VIL Low-level input voltage‡ –1 0.8 – 0.3 0.8 V TA Ambient temperature 0 70 0 70 °C ‡ The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997

6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TMS417809A PARAMETER TEST CONDITIONS † ’417809A-50 ’417809A-60 ’417809A-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltageIOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltageIOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, ± 10 ± 10 ± 10 µAII Input current (leakage) All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , ± 10 ± 10 ± 10 µAIO O utput current (leakage) CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VCC = 5.5 V, Minimum cycle 130 110 100 mA VIH = 2.4 V (TTL), After one memory cycle, 2 2 2 ICC2 Average standby current RAS and CAS high mAICC2 Average standby current VIH = VCC – 0.2 V (CMOS), mA After one memory cycle, 1 1 1 RAS and CAS high VCC = 5.5 V, Minimum cycle, ICC3 ‡§ Average refresh current RAS cycling, 130 110 100 mAICC3 ‡§ g (RAS -only refresh or CBR)CAS high (RAS only), 130 110 100 mA RAS low after CAS low (CBR) ICC4 ‡¶ Average EDO current VCC = 5.5 V, tHPC = MIN, 110 90 80 mAICC4 ‡¶ Average EDO current RAS low, CAS cycling 110 90 80 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and ambient conditions (unless otherwise noted) (continued) TMS427809A/P PARAMETER TEST CONDITIONS † ’427809A/P-50 ’427809A/P-60 ’427809A/P-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = – 100 µA LVCMOS VCC –0.2 VCC –0.2 VCC –0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VCC = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 3.6 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VCC = 3.6 V, Minimum cycle 120 100 90 mA VIH = 2 V (LVTTL) After one memory cycle ’427809A 2 2 2 mA Average After one memory cycle, RAS and CAS high ’427809AP 1 1 1 mA ICC2 g standby current VIH = VCC – 0.2 V (LVCMOS ), ’427809A 1 1 1 mA () , After one memory cycle, RAS and CAS high ’427809AP 150 150 150 µA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 3.6 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh), RAS low after CAS low (CBR) 120 100 90 mA ICC4 ‡¶ Average EDO current VCC = 3.6 V, t HPC = MIN, RAS low, CAS cycling 110 90 80 mA ICC6 # Average self-refresh current CAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 200 200 200 µA ICC10 # Battery back-up operating current (equivalent refresh time is 128 ms), CBR only tRC = 62.5 µs, t RAS ≤ 300 ns VCC – 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 350 350 350 µA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC# For TMS427809AP only

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997

8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A10 5 pF C i(OE) Input capacitance, OE 7 pF C i(RC) Input capacitance, CAS and RAS 7 pF C i(W) Input capacitance, W 7 pF C o Output capacitance† 7 pF † CAS and OE = VIH to disable outputs NOTE 2: V CC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3) PARAMETER ’417809A-50 ’427809A/P-50 ’417809A-60 ’427809A/P-60 ’417809A-70 ’427809A/P-70 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address (see Note 4) 25 30 35 ns tCAC Access time from CAS (see Note 4) 13 15 18 ns tCPA Access time from CAS precharge (see Note 4) 28 35 40 ns tRAC Access time from RAS (see Note 4) 50 60 70 ns tOEA Access time from OE (see Note 4) 13 15 18 ns tCLZ Delay time, CAS to output in low impedance 0 0 0 ns tREZ Output buffer turn-off delay from RAS (see Note 5) 3 13 3 15 3 18 ns tCEZ Output buffer turn-off delay from CAS (see Note 5) 3 13 3 15 3 18 ns tOEZ Output buffer turn-off delay from OE (see Note 5) 3 13 3 15 3 18 ns tWEZ Output buffer turn-off delay from W (see Note 5) 3 13 3 15 3 18 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. For TMS427809A/P, access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The maximum values of tREZ , tCEZ , tOEZ , and tWEZ are specified when the output is no longer driven. Data-in should not be enabled until one of the applicable maximum values is satisfied. EDO timing requirements (see Note 3) ’417809A-50 ’427809A/P-50 ’417809A-60 ’427809A/P-60 ’417809A-70 ’427809A/P-70 UNIT MIN MAX MIN MAX MIN MAX tHPC Cycle time, EDO page mode, read-write 20 25 30 ns tPRWC Cycle time, EDO read-write 57 68 78 ns tCSH Delay time, RAS active to CAS precharge 40 48 58 ns tCHO Hold time, OE from CAS 7 10 10 ns tDOH Hold time, output from CAS 5 5 5 ns tCAS Pulse duration, CAS active (see Note 6) 8 10000 10 10000 12 10000 ns tWPE Pulse duration, W active (output disable only) 7 7 7 ns tCP Pulse duration, CAS precharge 8 10 10 ns tOCH Setup time, OE before CAS 8 10 10 ns tOEP Precharge time, OE 5 5 5 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 6. In a read-write cycle, tCWD and tCWL must be observed.

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ac timing requirements (see Note 3) ’417809A-50 ’427809A/P-50 ’417809A-60 ’427809A/P-60 ’417809A-70 ’427809A/P-70 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write 84 104 124 ns tRWC Cycle time, read-write 111 135 160 ns tRASP Pulse duration, RAS active, fast page mode (see Note 7) 50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, RAS active, non-page mode (see Note 7) 50 10 000 60 10 000 70 10 000 ns tRP Pulse duration, RAS precharge 30 40 50 ns tWP Pulse duration, write command 8 10 10 ns tRASS Pulse duration, RAS active, self refresh (see Note 8) 100 100 100 /C0109s tRPS Pulse duration, RAS precharge after self refresh 90 110 130 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 9) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CAS precharge 8 10 12 ns tRWL Setup time, write command before RAS precharge 8 10 12 ns tWCS Setup time, write command before CAS active (early-write only) 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tCSR Setup time, CAS referenced to RAS (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 8 10 12 ns tDH Hold time, data in (see Note 9) 8 10 12 ns tRAH Hold time, row address 8 10 10 ns tRCH Hold time, read command referenced to CAS (see Note 10) 0 0 0 ns tRRH Hold time, read command referenced to RAS (see Note 10) 0 0 0 ns tWCH Hold time, write command during CAS active (early-write only) 8 10 12 ns tROH Hold time, RAS referenced to OE 8 10 10 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR Hold time, CAS referenced to RAS (CBR refresh only) 10 10 10 ns tOEH Hold time, OE command 13 15 18 ns tRHCP Hold time, RAS active from CAS precharge 28 35 40 ns tCHS Hold time, CAS referenced to RAS (self refresh only) – 50 – 50 – 50 ns tAWD Delay time, column address to write command (read-write only) 42 49 57 ns tCRP Delay time, CAS precharge to RAS 5 5 5 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 7. In a read-write cycle, tRWD and tRWL must be observed. 8. During the period of 10 µs ≤ tRASS ≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode. 9. Referenced to the later of CAS or W in write operations 10. Either tRRH or tRCH must be satisfied for a read cycle.

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.

1. The maximum value is specified only to ensure access time.

NOTE A: C L includes probe and fixture capacitance. Figure 1. Load Circuits for Timing Parameters

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 2. Read-Cycle Timing

12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 3. Early-Write-Cycle Timing

Figure 4. Write-Cycle Timing

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 5. Read-Write-Cycle Timing

NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. Access time is tCPA -, tAA -, or tCAC -dependent. C. Output is turned off by tCEZ if RAS goes high during CAS low. Figure 6. EDO Read Cycle

16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NOTE A: Output is turned off by tCEZ if RAS goes high during CAS low. Figure 7. EDO Read-Cycle With OE Control

Figure 8. EDO Read-Cycle With W Control

18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 9. EDO-Early-Write-Cycle Timing

NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 10. EDO Write-Cycle Timing

20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated. Figure 11. EDO Read-Write-Cycle Timing

Figure 12. RAS-Only Refresh-Cycle Timing

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 13. Automatic-CBR-Refresh-Cycle Timing

Figure 14. Self-Refresh-Cycle Timing

24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 15. Hidden-Refresh-Cycle (Read) Timing

Figure 16. Hidden-Refresh-Cycle (Write) Timing

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997

26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

DGC (R-PDSO-G28) PLASTIC SMALL-OUTLINE PACKAGE 4040260-2/B 02/95 0.404 (10,26) 0.396 (10,06) 0.047 (1,20) MAX 0.000 (0,00) MIN 0.721 (18,31) 0.729 (18,51) 0.012 (0,30) 0.020 (0,50) 0.016 (0,40) Seating Plane 0.006 (0,15) NOM 0.455 (11,56) 0.471 (11,96) Gage Plane 0.010 (0,25) 0.024 (0,60) 0.004 (0,10) 0°–5° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion.

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997 27POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA DZ (R-PDSO-J) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 4040094/C 11/95 0.395 (10,03) 0.405 (10,29) Seating Plane 0.445 (11,30) 0.435 (11,05) 0.008 (0,20) NOM 0.360 (9,14) 0.380 (9,65) 1.080 0.830 1.030 1.0700.820 (20,83) 1.020 (25,91) (27,18) 0.026 (0,66) 0.032 (0,81) A 0.106 (2,69) NOM 0.730 0.730 0.720 (18,29)(18,29) 0.720 (18,54)(18,54) DIM A MIN A MAX PINS 0.016 (0,41) 0.020 (0,51) 0.148 (3,76) 0.128 (3,25) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27)

32 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,13). D. The 24 pin package has the center two pins removed on both sides.

TMS417809A, TMS427809A, TMS427809AP DYNAMIC RANDOM-ACCESS MEMORIES SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997

28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

device symbolization (TMS417809A illustrated) Package Code -SS TMS417809A DZ Assembly Site Code Lot Traceability Code Year Code Die Revision Code Wafer Fab Code PLLLLYEW M Month Code TI Low-Power/Self Refresh Designator (Blank or P)

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright  1998, Texas Instruments Incorporated