TMS427400

TMS416400 TI | Alldatasheet

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS417400/P is Production Data. Electrical characteristics for TMS426400/P and TMS427400/P is Product Preview only. /C0068Organization...4 1 9 4304 × 4 /C0068Single 5 V Power Supply for TMS41x400/P (±10% Tolerance) /C0068Single 3.3 V Power Supply for TMS42x400/P (± 0.3 V Tolerance) /C0068Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC tCAC tAA CYCLE MAX MAX MAX MIN ’4xx400/P-60 60 ns 15 ns 30 ns 110 ns ’4xx400/P-70 70 ns 18 ns 35 ns 130 ns ’4xx400/P-80 80 ns 20 ns 40 ns 150 ns /C0068Enhanced Page-Mode Operation With CAS -Before-RAS (CBR) Refresh /C0068Long Refresh Period and Self-Refresh Option (TMS4xx400P) /C00683-State Unlatched Output /C0068Low Power Dissipation /C0068High-Reliability Plastic 24/26-Lead 300-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package and 24/26-Lead Surface-Mount Thin Small-Outline Package (TSOP) /C0068Operating Free-Air Temperature Range: 0°C to 70°C /C0068EPIC (Enhanced Performance Implanted CMOS) Technology AVAILABLE OPTIONS DEVICE POWER SUPPLY SELF REFRESH BATTERY BACKUP REFRESH CYCLES TMS416400 TMS416400P TMS417400 TMS417400P TMS426400 TMS426400P TMS427400 TMS427400P 5 V 5 V 5 V 5 V 3.3 V 3.3 V 3.3 V 3.3 V Yes Yes Yes Yes 4096 in 64 ms 4096 in 128 ms 2048 in 32 ms 2048 in 128 ms 4096 in 64 ms 4096 in 128 ms 2048 in 32 ms 2048 in 128 ms These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. ‡ See Available Options Table PIN NOMENCLATURE A0–A11 † Address Inputs CAS Column-Address Strobe DQ1–DQ4 Data In/Data Out OE Output Enable NC No Internal Connection RAS Row-Address Strobe VCC 5-V or 3.3-V Supply‡ VSS Ground W Write Enable DJ PACKAGE (TOP VIEW) VCC DQ1 DQ2 W RAS V CC VSS DQ4 DQ3 CAS OE V SS A11† A9216 A10 A8 198 DGA PACKAGE (TOP VIEW) VCC DQ1 DQ2 W RAS V CC VSS DQ4 DQ3 CAS OE V SS A11† A9216 A10 A8 198 † A11 is NC for TMS4x7400/P.

description

The TMS4xx400 is a set of high-speed, 16777216-bit dynamic random-access memories organized as 4194304 words of 4 bits each. The TMS4xx400P series are high-speed, low-power, self-refresh, 16777216-bit dynamic random- access memories organized as 4194304 words of 4 bits each. The TMS4xx400 and TMS4xx400P employ state-of-the-art EPIC (Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low power. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1995, Texas Instruments Incorporated EPIC is a trademark of Texas Instruments Incorporated.

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995

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description (continued) The TMS4xx400 and TMS4xx400P are each offered in a 24/26-lead plastic surface-mount TSOP (DGA suffix) package and a 24/26-lead plastic surface-mount SOJ (DJ suffix) package. These packages are characterized for operation from 0°C to 70°C. operation enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the maximum RAS low time. Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low) if tAA max (access time from column address) and tRAC have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCPA or tCAC . address: A0–A11 (TMS4x6400/P) and A0–A10 (TMS4x7400/P) Twenty-two address bits are required to decode 1 of 4194304 storage cell locations. For the TMS4x6400 and TMS4x6400P , 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address strobe (RAS). Ten column-address bits are set up on A0 through A9. For TMS4x7400 and TMS4x7400P, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the column-address buffers. write enable (W) The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. data in (DQ1–DQ4) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines. data out (DQ1–DQ4) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with the negative transition of CAS) as long as tRAC and tAA are satisfied.

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 RAS -only refresh TMS4x6400, TMS4x6400P A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6400P) to retain data. This can be achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS -only refresh. TMS4x7400, TMS4x7400P A refresh operation must be performed at least once every 32 ms (128 ms for TMS4x7400P) to retain data. This can be achieved by strobing each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS -only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally. CAS -before-RAS (CBR) refresh CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR ) and holding it low after RAS falls (see parameter tCHR ). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally. battery-backup refresh TMS4x6400P A low-power battery-backup refresh mode that requires less than 500 µA (5 V) or 350 µA (3.3 V) refresh current is available on the TMS4x6400P. Data integrity is maintained using CBR refresh with a period of 31.25 µs while holding RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels (VIL < 0.2 V, VIH > VCC – 0.2 V). TMS4x7400P A low-power battery-backup refresh mode that requires less than 500 µA (5 V) or 350 µA (3.3 V) refresh current is available on the TMS4x7400P. Data integrity is maintained using CBR refresh with a period of 62.5 µs while holding RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels (VIL < 0.2 V, VIH > VCC – 0.2 V). self refresh (TMS4xx400P) The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both held low for a minimum of 100 µs. The chip is then refreshed internally by an on-board oscillator. No external address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS are brought high to satisfy tCHS . Upon exiting self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures the DRAM is fully refreshed. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full V CC level. These eight initialization cycles must include at least one refresh (RAS -only or CBR) cycle.

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held high or a RAS-only refresh cycle is performed. time is reduced by a factor of four for this series. NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode. Figure 1. Test-Mode Cycle

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 logic symbol† RAS CAS W OE 20D10/21D0 20D19/21D9 C20 [ROW] G23/[REFRESH ROW] 24 [PWR DWN] C21[COLUMN] G24 23C22 23,21D 24,25 EN G25 A 0 4194303 RAM 4096 K × 4 A9 21 A,Z26 A,22D DQ1 DQ2 DQ3 DQ4 A10 8 20D21A11‡ 6 20D20 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12. ‡ A11 is NC for TMS4x7400 and TMS4x7400P.

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995

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R o w D e c o d e A11 Timing and Control Column- Address Buffers† Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers 256K Array 256K Array 256K Array RAS CAS W DQ1–DQ4 OE † Column addresses A10 and A11 are not used. TMS4x7400/P A10 Timing and Control Column- Address Buffers Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers R o w D e c o d e 256K Array 256K Array 256K Array 256K Array 256K Array 256K Array RAS CAS W DQ1–DQ4 OE

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions TMS41x400 TMS42x400 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 3 3.3 3.6 V VSS Supply voltage 0 0 V VIH High-level input voltage 2.4 6.5 2 VCC + 0.3 V VIL Low-level input voltage (see Note 2) –1 0.8 – 0.3 0.8 V TA Operating free-air temperature 0 70 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TMS416400/P PARAMETER TEST CONDITIONS † ’416400-60 ’416400P-60 ’416400-70 ’416400P-70 ’416400-80 ’416400P-80 UNIT MIN MAX MIN MAX MIN MAX VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VCC = 5.5 V, Minimum cycle 80 70 60 mA I Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 2 2 2 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle ’416400 1 1 1 mA After 1 memory cycle, RAS and CAS high ’416400P 500 500 500 µA ICC3 ‡§ Average refresh current (RAS-only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 80 70 60 mA ICC4 ‡¶ Average page currentVCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 70 60 50 mA ICC6 # Self-refresh currentCAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 500 500 500 µA ICC10 # Battery back-up operating current (equivalent refresh time is 128 ms); CBR only tRC = 31.25 µs, t RAS ≤ 1 µs, VCC – 0.2 V ≤ VIH ≤ 6.5 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 500 500 500 µA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change while CAS = VIH# For TMS416400P only

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS417400/P PARAMETER TEST CONDITIONS † ’417400-60 ’417400P-60 ’417400-70 ’417400P-70 ’417400-80 ’417400P-80 UNIT MIN MAX MIN MAX MIN MAX VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle currentVCC = 5.5 V, Minimum cycle 110 100 90 mA I Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 2 2 2 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle ’417400 1 1 1 mA After 1 memory cycle, RAS and CAS high ’417400P 500 500 500 µA ICC3 ‡§ Average refresh current (RAS-only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 110 100 90 mA ICC4 ‡¶ Average page current VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 70 60 50 mA ICC6 # Self-refresh currentCAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 500 500 500 µA ICC10 # Battery back-up operating current (equivalent refresh time is 128 ms); CBR only tRC = 62.5 µs, t RAS ≤ 1 µs, VCC – 0.2 V ≤ VIH ≤ 6.5 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 500 500 500 µA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change while CAS = VIH# For TMS417400P only

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995

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electrical characteristics over recommended ranges of supply voltage and operating free-air conditions (unless otherwise noted) (continued) TMS426400/P PARAMETER TEST CONDITIONS † ’426400-60 ’426400P-60 ’426400-70 ’426400P-70 ’426400-80 ’426400P-80 UNIT MIN MAX MIN MAX MIN MAX VOH High-level IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH g output voltage IOH = – 100 µA LVCMOS VCC –0.2 VCC –0.2 VCC –0.2 V VOL Low-level IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VCC = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 3.6 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write- cycle current VCC = 3.6 V, Minimum cycle 70 60 50 mA Standby VIH = 2 V (LVTTL), After 1 memory cycle, RAS and CAS high 1 1 1 mA ICC2 Standby current VIH = VCC – 0.2 V (LVCMOS ), ’426400 500 500 500 µA () , After 1 memory cycle, RAS and CAS high ’426400P 200 200 200 µA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 3.6 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh), RAS low after CAS low (CBR) 70 60 50 mA ICC4 ‡¶ Average page current VCC = 3.6 V, t PC = MIN, RAS low, CAS cycling 60 50 40 mA ICC6 # Self-refresh current CAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 250 250 250 µA ICC10 # Battery back-up operating current (equivalent refresh time is 128 ms), CBR only tRC = 31.25 µs, tRAS ≤ 1 µs, VCC – 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 350 350 350 µA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change while CAS = VIH# For TMS426400P only PRODUCT PREVIEW PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air conditions (unless otherwise noted) (continued) TMS427400/P PARAMETER TEST CONDITIONS † ’427400-60 ’427400P-60 ’427400-70 ’427400P-70 ’427400-80 ’427400P-80 UNIT MIN MAX MIN MAX MIN MAX VOH High-level IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH g output voltage IOH = – 100 µA LVCMOS VCC –0.2 VCC –0.2 VCC –0.2 V VOL Low-level IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VCC = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 3.6 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write- cycle current VCC = 3.6 V, Minimum cycle 100 90 80 mA Standby VIH = 2 V (LVTTL), After 1 memory cycle, RAS and CAS high 1 1 1 mA ICC2 Standby current VIH = VCC – 0.2 V (LVCMOS ), ’427400 500 500 500 µA () , After 1 memory cycle, RAS and CAS high ’427400P 200 200 200 µA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 3.6 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh), RAS low after CAS low (CBR) 100 90 80 mA ICC4 ‡¶ Average page current VCC = 3.6 V, t PC = MIN, RAS low, CAS cycling 60 50 40 mA ICC6 # Self-refresh current CAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 250 250 250 µA ICC10 # Battery back-up operating current (equivalent refresh time is 128 ms), CBR only tRC = 62.5 µs, t RAS ≤ 1 µs, VCC – 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 350 350 350 µA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change while CAS = VIH# For TMS427400P only PRODUCT PREVIEW PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995

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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A11 5 pF C i(OE) Input capacitance, OE 7 pF C i(RC) Input capacitance, CAS and RAS 7 pF C i(W) Input capacitance, W 7 pF C o Output capacitance 7 pF NOTE 3: V CC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’4xx400-60 ’4xx400P-60 ’4xx400-70 ’4xx400P-70 ’4xx400-80 ’4xx400P-80 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address (see Note 4) 30 35 40 ns tCAC Access time from CAS low (see Note 4) 15 18 20 ns tCPA Access time from column precharge (see Note 4) 35 40 45 ns tRAC Access time from RAS low (see Note 4) 60 70 80 ns tOEA Access time from OE low (see Note 4) 15 18 20 ns tCLZ Delay time, CAS low to output in low-impedance state 0 0 0 ns tOH Output data hold time (from CAS) 3 3 3 ns tOHO Output data hold time (from OE) 3 3 3 ns tOFF Output disable time after CAS high (see Note 5) 0 15 0 18 0 20 ns tOEZ Output disable time after OE high (see Note 5) 0 15 0 18 0 20 ns NOTES: 4. Access times for TMS42x400 measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. tOFF and tOEZ are specified when the output is no longer driven.

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature ’4xx400-60 ’4xx400P-60 ’4xx400-70 ’4xx400P-70 ’4xx400-80 ’4xx400P-80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, read (see Note 6) 110 130 150 ns tWC Cycle time, write (see Note 6) 110 130 150 ns tRWC Cycle time, read-write (see Note 6) 155 181 205 ns tPC Cycle time, page-mode read or write (see Notes 6 and 7)40 45 50 ns tPRWC Cycle time, page-mode read-write (see Note 6) 85 96 105 ns tRASP Pulse duration, RAS low, page mode (see Note 8) 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, RAS low, nonpage mode (see Note 8) 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low (see Note 9) 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data (see Note 10) 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before CAS low (early-write operation only)0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tWTS Setup time, W low before RAS low (test mode only) 10 10 10 ns tCAH Hold time, column address after CAS low 10 15 15 ns tDH Hold time, data (see Note 10) 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 11) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 11) 0 0 0 ns tWCH Hold time, W low after CAS low (early-write operation only)10 15 15 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tOEH Hold time, OE command 15 18 20 ns tROH Hold time, RAS referenced to OE 10 10 10 ns tCHS Hold time, CAS low after RAS high (self refresh) – 50 – 50 – 50 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tWTH Hold time, W low after RAS low (test mode only) 10 10 10 ns NOTES: 6. All cycle times assume tT = 5 ns. 7. To assure tPC min, tASC should be ≥ to tCP . 8. In a read-write cycle, tRWD and tRWL must be observed. 9. In a read-write cycle, tCWD and tCWL must be observed. 10. Referenced to the later of CAS or W in write operations 11. Either tRRH or tRCH must be satisfied for a read cycle.

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’4xx400-60 ’4xx400P-60 ’4xx400-70 ’4xx400P-70 ’4xx400-80 ’4xx400P-80 UNIT MIN MAX MIN MAX MIN MAX tAWD Delay time, column address to W low (read-write operation only) 55 63 70 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tCWD Delay time, CAS low to W low (read-write operation only) 40 46 50 ns tOED Delay time, OE to data 15 18 20 ns tRAD Delay time, RAS low to column address (see Note 12) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 12) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low 0 0 0 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tRWD Delay time, RAS low to W low (read-write operation only) 85 98 110 ns tCPW Delay time, W low after CAS precharge (read-write operation only)60 68 75 ns tRASS Pulse duration, self-refresh entry from RAS low 100 100 100 µs tRPS Pulse duration, RAS precharge after self refresh 110 130 150 ns tTAA Access time from address (test mode) 35 40 45 ns tTCPA Access time from column precharge (test mode) 40 45 50 ns tTRAC Access time from RAS (test mode) 65 75 85 ns ’4x6400 64 64 64 tREF Refresh time interval ’4x6400P 128 128 128 mstREF Refresh time interval ’4x7400 32 32 32 ms ’4x7400P 128 128 128 tT Transition time 3 30 3 30 3 30 ns NOTE 12: The maximum value is specified only to assure access time.

Figure 2. Load Circuits for Timing Parameters

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NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time. Figure 3. Read-Cycle Timing

Figure 4. Early-Write-Cycle Timing

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Figure 5. Write-Cycle Timing

NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Read-Write-Cycle Timing

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† Access time is tCPA , tCAC , or tAA dependent. NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time. Figure 7. Enhanced-Page-Mode Read-Cycle Timing

Figure 8. Enhanced-Page-Mode Write-Cycle Timing

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† Output can go from high-impedance state to an invalid-data state prior to the specified access time. NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated. Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing

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Figure 12. Hidden-Refresh-Cycle (Read) Timing

Figure 13. Hidden-Refresh-Cycle (Write) Timing

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Figure 14. Self-Refresh-Cycle Timing

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995

28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

DJ (R-PDSO-J24/26) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 4040092-3/B 10/94 0.340 (8,64) 0.330 (8,38) 0.106 (2,69) TYP 0.008 (0,20) NOM 0.275 (6,99) 0.260 (6,60) Seating Plane 1921 0.670 (17,02) 0.680 (17,27) 0.026 (0,66) 0.032 (0,81) 0.148 (3,76) 0.020 (0,51) 0.016 (0,41) 0.128 (3,25) 0.295 (7,49) 0.305 (7,75) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).

TMS416400, TMS416400P, TMS417400, TMS417400P TMS426400, TMS426400P, TMS427400, TMS427400P 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS SMKS881B – MAY 1995 – REVISED AUGUST 1995 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA DGA (R-PDSO-G24/26) PLASTIC SMALL-OUTLINE PACKAGE 4040265-3/C 4/95 0.304 (7,72) 0.296 (7,52) 0.047 (1,20) MAX 0.002 (0,05) MIN 0.679 (17,24) 0.671 (17,04) 0.020 (0,50) 0.012 (0,30) 0.016 (0,40) Seating Plane 0.006 (0,15) NOM 0.371 (9,42) 0.355 (9,02) Gage Plane 0.010 (0,25) 0.024 (0,60) 0.004 (0,10) 0°–5° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. device symbolization (TMS416400 illustrated) Package Code Low-Power/Self-Refresh Designator (Blank or P) -SS TMS416400 DJ Asembly Site Code Lot Traceability Code Year Code Die Revision Code Wafer Fab Code PLLLLYBW M Month Code TI

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