TMS426409A

TMS416409A NSC | Alldatasheet

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Technical content

The TMS41x409A and TMS42x409A series are 16777216-bit dynamic random-access memory (DRAM) devices organized as 4194304 words of four bits each. These devices feature maximum RAS access times of 50, 60, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.

description

TMS416409A, TMS417409A, TMS426409A, TMS427409A

4194304 BY 4-BIT EXTENDED DATA OUT

DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 This data sheet is applicable to all TMS41x409As and TMS42x409As symbolized by Revision “B”, Revision “E”, and subsequent revisions as described in the device symbolization section. /C0068Organization...4 1 9 4 3 0 4× 4 /C0068Single Power Supply (5 V or 3.3 V) /C0068Performance Ranges: ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tCAC tAA tHPC MAX MAX MAX MIN ’41x409A-50 50 ns 13 ns 25 ns 20 ns ’41x409A-60 60 ns 15 ns 30 ns 25 ns ’41x409A-70 70 ns 18 ns 35 ns 30 ns ’42x409A-50 50 ns 13 ns 25 ns 20 ns ’42x409A-60 60 ns 15 ns 30 ns 25 ns ’42x409A-70 70 ns 18 ns 35 ns 30 ns /C0068Extended-Data-Out (EDO) Operation /C0068CAS -Before-RAS (CBR) Refresh /C0068Low Power Dissipation /C00683-State Unlatched Output /C0068High-Reliability Plastic 24/26-Lead 300-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DJ Suffix) and 24/26-Lead 300-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGA Suffix) /C0068Operating Free-Air Temperature Range 0°C to 70°C AVAILABLE OPTIONS DEVICE POWER SUPPLY SELF REFRESH, BATTERY BACKUP REFRESH CYCLES TMS416409A 5 V – 4096 in 64 ms TMS417409A 5 V – 2048 in 32 ms TMS426409A 3.3 V – 4096 in 64 ms TMS427409A 3.3 V – 2048 in 32 ms The TMS416409A and TMS417409A are offered in a 24/26-lead plastic surface-mount SOJ package (DJ suffix). The TMS426409A and TMS427409A are offered in a 24/26-lead plastic surface-mount SOJ package (DJ suffix) and a 24/26-lead plastic surface-mount TSOP (DGA suffix). These packages are designed for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PIN NOMENCLATURE A0–A11 † Address Inputs DQ1–DQ4 Data In/Data Out CAS Column-Address Strobe NC No Internal Connection OE Output Enable RAS Row-Address Strobe VCC 5-V or 3.3-V Supply‡ VSS Ground W Write Enable † A11 is NC for TMS417409A and TMS427409A. ‡ See Available Options Table DJ/DGA PACKAGES (TOP VIEW) VCC DQ1 DQ2 W RAS V CC VSS DQ4 DQ3 CAS OE V SS A11† A9216 A10 A8 198 Copyright  1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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logic symbol (TMS416409A and TMS426409A)† RAS CAS W OE 20D10/21D0 20D19/21D9 C20 [ROW] G23/[REFRESH ROW] 24 [PWR DWN] C21[COLUMN] G24 23C22 23,21D 24,25 EN G25 A 0 4194303 RAM 4096 K × 4 A9 21 A,Z26 A,22D DQ1 DQ2 DQ3 DQ4 A10 8 20D21A11 6 20D20 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 logic symbol (TMS417409A and TMS427409A)† RAS CAS W OE 20D11/21D0 C20 [ROW] G23/[REFRESH ROW] 24 [PWR DWN] C21[COLUMN] G24 23C22 23,21D 24,25 EN G25 A 0 4194303 RAM 4096 K × 4 A9 21 A,Z26 A,22D DQ1 DQ2 DQ3 DQ4 A10 8 20D21/21D10 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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TMS416409A, TMS426409A R o w D e c o d e A11 Timing and Control Column- Address Buffers† Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers 256K Array 256K Array 256K Array RAS CAS W DQ1–DQ4 OE † Column addresses A10 and A11 are not used. TMS417409A, TMS427409A A10 Timing and Control Column- Address Buffers Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers R o w D e c o d e 256K Array 256K Array 256K Array 256K Array 256K Array 256K Array RAS CAS W DQ1–DQ4 OE

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 operation extended data out Extended data out (EDO) allows data output rates of up to 50 MHz for 50-ns devices. When keeping the same row address while selecting random column addresses, the time for row-address setup and hold and for address multiplex is eliminated. The maximum number of columns that can be accessed is determined by t RASP , the maximum RAS low time. Extended data out does not place the data in/data out pins (DQ pins) into the high-impedance state with the rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO operation benefit. address: A0–A11 (TMS416409A and TMS426409A) and A0–A10 (TMS417409A and TMS427409A) Twenty-two address bits are required to decode each of the 4194304 storage cell locations. For the TMS416409A and TMS426409A,12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address strobe (RAS ). Ten column-address bits are set up on A0 through A9. For the TMS417409A and TMS427409A, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the column-address buffers. output enable (OE) OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time. The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further transitions on OE until CAS falls again (see Figure 8). write enable (W) The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high (see Figure 9). data in/data out (DQ1–DQ4) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge. The DQs drive valid data after all access times are met and remain valid except in cases described in the W and OE sections.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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TMS416409A, TMS426409A A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. TMS417409A, TMS427409A A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS -only refresh cycle. The external address is ignored, and the refresh address is generated internally. CAS -before-RAS (CBR) refresh CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR ) and holding it low after RAS falls (see parameter tCHR ). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh (RAS -only or CBR) cycle. test mode The test mode (see Figure 1) is initiated with a CBR-refresh cycle while simultaneously holding the W input low. The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or write on subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed. In the test mode, the device is configured as 1024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal bits are compared for each DQ pin. If the four bits agree, DQ goes high; if not, DQ goes low. Test time is reduced by a factor of four for this series.

NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode. Figure 1. Test-Mode Cycle

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions TMS41x409A TMS42x409A MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 3 3.3 3.6 V VSS Supply voltage 0 0 V VIH High-level input voltage 2.4 6.5 2 VCC + 0.3 V VIL Low-level input voltage (see Note 2) –1 0.8 – 0.3 0.8 V TA Operating free-air temperature 0 70 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TMS416409A PARAMETER TEST CONDITIONS † ’416409A-50 ’416409A-60 ’416409A-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltageIOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage)VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VCC = 5.5 V, Minimum cycle 100 80 70 mA ICC2 Average standby VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 2 2 2 mA ICC2 gy current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 1 1 1 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 100 80 70 mA ICC4 ‡¶ Average EDO current VCC = 5.5 V, t HPC = MIN, RAS low, CAS cycling 100 90 80 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS417409A PARAMETER TEST CONDITIONS † ’417409A-50 ’417409A-60 ’417409A-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltageIOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage)VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VCC = 5.5 V, Minimum cycle 130 110 100 mA ICC2 Average standby VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 2 2 2 mA ICC2 gy current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 1 1 1 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 130 110 100 mA ICC4 ‡¶ Average EDO current VCC = 5.5 V, tHPC = MIN, RAS low, CAS cycling 110 90 80 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS426409A PARAMETER TEST CONDITIONS † ’426409A-50 ’426409A-60 ’426409A-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = – 100 µA LVCMOS VCC –0.2 VCC –0.2 VCC –0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VCC = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 3.6 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write- cycle current VCC = 3.6 V, Minimum cycle 90 70 60 mA ICC2 Average standby VIH = 2 V (LVTTL) After one memory cycle, RAS and CAS high 2 2 2 mA ICC2 standby current VIH = VCC – 0.2 V (LVCMOS), After one memory cycle, RAS and CAS high 1 1 1 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 3.6 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh), RAS low after CAS low (CBR) 90 70 60 mA ICC4 ‡¶ Average EDO current VCC = 3.6 V, t HPC = MIN, RAS low, CAS cycling 100 90 80 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS427409A PARAMETER TEST CONDITIONS † ’427409A-50 ’427409A-60 ’427409A-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = – 100 µA LVCMOS VCC –0.2 VCC –0.2 VCC –0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VCC = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 3.6 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write- cycle current VCC = 3.6 V, Minimum cycle 120 100 90 mA ICC2 Average standby VIH = 2 V (LVTTL) After one memory cycle, RAS and CAS high 2 2 2 mA ICC2 standby current VIH = VCC – 0.2 V (LVCMOS), After one memory cycle, RAS and CAS high 1 1 1 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 3.6 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh), RAS low after CAS low (CBR) 120 100 90 mA ICC4 ‡¶ Average EDO current VCC = 3.6 V, t HPC = MIN, RAS low, CAS cycling 110 90 80 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A11† 5 pF C i(OE) Input capacitance, OE 7 pF C i(RC) Input capacitance, CAS and RAS 7 pF C i(W) Input capacitance, W 7 pF C o Output capacitance‡ 7 pF † A11 is NC (no internal connection) for TMS417409A and TMS427409A. ‡ CAS and OE = VIH to disable outputs NOTE 3: V CC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 4) PARAMETER ’41x409A-50 ’42x409A-50 ’41x409A-60 ’42x409A-60 ’41x409A-70 ’42x409A-70 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address (see Note 5) 25 30 35 ns tCAC Access time from CAS (see Note 5) 13 15 18 ns tCPA Access time from CAS precharge (see Note 5) 28 35 40 ns tRAC Access time from RAS (see Note 5) 50 60 70 ns tOEA Access time from OE (see Note 5) 13 15 18 ns tCLZ Delay time, CAS to output in low impedance 0 0 0 ns tREZ Output buffer turn off delay from RAS (see Note 6) 3 13 3 15 3 18 ns tCEZ Output buffer turn off delay from CAS (see Note 6) 3 13 3 15 3 18 ns tOEZ Output buffer turn off delay from OE (see Note 6) 3 13 3 15 3 18 ns tWEZ Output buffer turn off delay from W (see Note 6) 3 13 3 15 3 18 ns NOTES: 4. With ac parameters, it is assumed that tT = 2 ns. 5. For TMS42x409A, access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 6. The maximum values of tREZ , tCEZ , tOEZ , and tWEZ are specified when the output is no longer driven. Data in should not be driven until one of the applicable maximum specifications is satisfied.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) ’41x409A-50 ’42x409A-50 ’41x409A-60 ’42x409A-60 ’41x409A-70 ’42x409A-70 UNIT MIN MAX MIN MAX MIN MAX tHPC Cycle time, EDO page mode, read-write 20 25 30 ns tPRWC Cycle time, EDO read-write 57 68 78 ns tCSH Delay time, RAS active to CAS precharge 40 48 58 ns tCHO Hold time, OE from CAS 7 10 10 ns tDOH Hold time, output from CAS 5 5 5 ns tCAS Pulse duration, CAS active (see Note 7) 8 10000 10 10000 12 10000 ns tWPE Pulse duration, W active (output disable only) 7 7 7 ns tOCH Setup time, OE before CAS 8 10 10 ns tCP Pulse duration, CAS precharge 8 10 10 ns tOEP Precharge time, OE 5 5 5 ns NOTES: 4: With ac parameters, it is assumed that tT = 2 ns. 7. In a read-write cycle, tCWD and tCWL must be observed.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) ’41x409A-50 ’42x409A-50 ’41x409A-60 ’42x409A-60 ’41x409A-70 ’42x409A-70 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write 84 104 124 ns tRWC Cycle time, read-write 111 135 160 ns tRASP Pulse duration, RAS active, fast page mode (see Note 8) 50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, RAS active, non-page mode (see Note 8) 50 10 000 60 10 000 70 10 000 ns tRP Pulse duration, RAS precharge 30 40 50 ns tWP Pulse duration, write command 8 10 10 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 9) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CAS precharge 8 10 12 ns tRWL Setup time, write command before RAS precharge 8 10 12 ns tWCS Setup time, write command before CAS active (early-write only) 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tWTS Setup time, W low before RAS low (test mode only) 10 10 10 ns tCSR Setup time, CAS referenced to RAS (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 8 10 12 ns tDH Hold time, data in (see Note 9) 8 10 12 ns tRAH Hold time, row address 8 10 10 ns tRCH Hold time, read command referenced to CAS (see Note 10) 0 0 0 ns tRRH Hold time, read command referenced to RAS (see Note 10) 0 0 0 ns tWCH Hold time, write command during CAS active (early-write only) 8 10 12 ns tROH Hold time, RAS referenced to OE 8 10 10 ns tWRH Hold time, W high after RAS low (CBR refresh) 10 10 10 ns tWTH Hold time, W low after RAS low (test mode only) 10 10 10 ns tCHR Hold time, CAS referenced to RAS (CBR refresh only) 10 10 10 ns tOEH Hold time, OE command 13 15 18 ns tRHCP Hold time, RAS active from CAS precharge 28 35 40 ns NOTES: 4. With ac parameters, it is assumed that tT = 2 ns. 8. In a read-write cycle, tRWD and tRWL must be observed. 9. Referenced to the later of CAS or W in write operations 10. Either tRRH or tRCH must be satisfied for a read cycle.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) (continued) ’41x409A-50 ’42x409A-50 ’41x409A-60 ’42x409A-60 ’41x409A-70 ’42x409A-70 UNIT MIN MAX MIN MAX MIN MAX tAWD Delay time, column address to write command (read-write only) 42 49 57 ns tCPW Delay time, W low after xCAS precharge (read-write only) 45 54 62 ns tCRP Delay time, CAS precharge to RAS 5 5 5 ns tCWD Delay time, CAS to write command (read-write only) 30 34 40 ns tOED Delay time, OE to data in 13 15 18 ns tRAD Delay time, RAS to column address (see Note 11) 10 25 12 30 12 35 ns tRAL Delay time, column address to RAS precharge 25 30 35 ns tCAL Delay time, column address to CAS precharge 18 20 25 ns tRCD Delay time, RAS to CAS (see Note 11) 12 37 14 45 14 52 ns tRPC Delay time, RAS precharge to CAS 5 5 5 ns tRSH Delay time, CAS active to RAS precharge 8 10 12 ns tRWD Delay time, RAS to write command (read-write only) 67 79 92 ns tTAA Access time from address (test mode) 30 35 40 ns tTCPA Access time, from column precharge (test mode) 35 40 45 ns tTRAC Access time, from RAS (test mode) 55 65 75 ns tT Transition time 2 30 2 30 2 30 ns tREF Refresh time interval ’4x6409A 64 64 64 ms tREF Refresh time interval ’4x7409A 32 32 32 ms NOTES: 4. With ac parameters, it is assumed that tT = 2 ns. 11. The maximum value is specified only to ensure access time.

NOTE A: C L includes probe and fixture capacitance. Figure 2. Load Circuits for Timing Parameters

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NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 3. Read-Cycle Timing

Figure 4. Early-Write-Cycle Timing

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Figure 5. Write-Cycle Timing

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Read-Write-Cycle Timing

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NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. Access time is tCPA -, tAA -, or tCAC -dependent. C. Output is turned off by tCEZ if RAS goes high during CAS low. Figure 7. EDO Read Cycle

NOTE A: Output is turned off by tCEZ if RAS goes high during CAS low. Figure 8. EDO Read-Cycle With OE Control

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Figure 9. EDO Read-Cycle With W Control

NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 10. EDO Early-Write-Cycle Timing

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NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 11. EDO Write-Cycle Timing

NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated. Figure 12. EDO Read-Write-Cycle Timing

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Figure 13. RAS-Only Refresh-Cycle Timing

Figure 14. Automatic-CBR-Refresh-Cycle Timing

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Figure 15. Hidden-Refresh-Cycle (Read) Timing

Figure 16. Hidden-Refresh-Cycle (Write) Timing

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Figure 17. Test-Mode-Entry-Cycle Timing Figure 18. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 33POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA DJ (R-PDSO-J24/26) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 4040092-3/B 02/95 0.340 (8,64) 0.330 (8,38) 0.106 (2,69) TYP 0.008 (0,20) NOM 0.275 (6,99) 0.260 (6,60) Seating Plane 1921 0.670 (17,02) 0.680 (17,27) 0.026 (0,66) 0.032 (0,81) 0.148 (3,76) 0.020 (0,51) 0.016 (0,41) 0.128 (3,25) 0.295 (7,49) 0.305 (7,75) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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DGA (R-PDSO-G24/26) PLASTIC SMALL-OUTLINE PACKAGE 4040265-3/C 11/95 0.304 (7,72) 0.296 (7,52) 0.047 (1,19) MAX 0.002 (0,05) MIN 0.679 (17,24) 0.671 (17,04) 0.020 (0,50) 0.012 (0,30) 0.016 (0,40) Seating Plane 0.006 (0,15) NOM 0.371 (9,42) 0.355 (9,02) Gage Plane 0.010 (0,25) 0.024 (0,60) 0.004 (0,10) 0°–5° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion.

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 device symbolization (TMS416409A illustrated) Package Code -SS TMS416409A DJ Assembly Site Code Lot Traceability Code Year Code Die Revision Code Wafer Fab Code PLLLLYEW M Month Code TI

TMS416409A, TMS417409A, TMS426409A, TMS427409A DYNAMIC RANDOM-ACCESS MEMORIES SMKS893B – AUGUST 1996 – REVISED APRIL 1997

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