TMS4256-8SDS

TMS4256 TI | Alldatasheet

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mas TMS4256, TMS4257 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES TEXAS INSTR (ASIC/MEMORY) 25E D. mmmmmaMtAY 1903 REVISED JANUARY 1088 'N PACKAGE SD PACKAGE © 262,144 x 1 Organization (Tor View) (Tor views ® © Single 5-V Power Supply qi Oehv. r — 8% Tolerance Required for TMS4266-8 Od Hess ABB ola — 10% Tolerance Required for TMS4256-10, wos wha CRSHS ives -12, -15, and TMS4257-10, -12, -15 RASH4 isf]ae s aS etl 2 © JEDEC Standardized Pinouts aot]s 12f]A3 Aofie StJRAS . Age = iplaa ‘Ar fan 1OEA2 © Performance Ranges: Mit? ioflas AIBN atlvoo access | Access | READ Voo(je _9f Jaz ‘Aa fie SC4A5 time | TIME | oR Vp 16L}A3 } 4 | ROW ‘COLUMN | WRITE . ‘appRESS| ADoREss| cycte | TOLERANCE puapackaae (MAX) (MAX) (MIN) vi [742665 |" eons | 40ns | 1e0ns| = 6% | (TOP VIEW "4256-10 88 "4267-10 ag? "4256-12 ‘4257-12 wos ° isla 4257-16 nefs v4Q]nc © Long Refresh Period . . . 4 ms (Max) Aofle tafas | a2t7 12a / © Operations of the TMS4256/TMS4267 Can ee101 | . Be Controlled by TI's SN74ALS2967, aT mem | SN74ALS2968, and THCT4502 Dynamic z 822 | RAM Controllers > © All Inputs, Outputs, and Clocks Fully TTL Compatible [Pit nomenciarune | © 3-State Uniatched Outputs ‘A0-AS. Address Inputs | © Common 1/0 Capability with “Early Write’” HS Column-Address Strobe Feature . D Data In NC No Connection © Page Mode ('4266) or Nibble-Mode ('4257) a Data Out © Low Power Dissipation Row-Address Strobe Vop 5-V Power Supply | © RAS-Only Refresh Mode Vss Ground © Hidden Refresh Mode Ww Write Enable © CAS-Bofore-RAS Refresh Mode 7: | @ Available with MIL-STD-8838 Processing and L{0°C to 70°C), E(-40°C to 85°C), or ‘S(-65°C to 100°C) Temperature Ranges (SMJ4266, with 10% Power Supply) PRODUCT DTA decent cn ern wy ‘Copyright © 1083, Texes instumenteIncorporeted Specentns a th tong of Tose lates Texas 43 standard warranty, Pradactonprocesig des bet INSTRUMENTS neceeeerty testing of a parameters. poy orFice BOK 1443 © HOUSTON, TEXAS 77001 i i

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description

z ‘The TMS4266 and TMS4267 ere high-speed, 262,144-bit dynamic random-access memories, organized” as 262,144 words of one bit each. Thay employ state-of-the-art SMOS (scaled MOS) N-channel double- F level polysilicon/polycide gate technology for very high performance combined with low cost and improved = reliability. : 2 The ‘4256-8 with a 5% voltage tolerance has a maximum RAS access time of 80 ns. The *4266/'4287-10, -12, and -16 with 10% voltage tolerances have maximum RAS access times of = 100 ns, 120 ns, and 150 ns, respectively. New SMOS technology permits operation from a single 5-V supply, reducing system power supply and 4 decoupling requirements, and easing board layout. [Dp peaks are 125 mA typical, and a ~ 1 V input voltage undershoot can be tolerated, minimizing system noise considerations. Allinputs and outputs, including clocks, are compatible with Series 74 TTL. All address and date-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The '4256 and ‘4257 are offered in 16-pin plastic dual-in-line, 16-pin plastic zig-zag in-line (ZIP), and 18-lead plastic chip carrier packages. They are guaranteed for operation from 0°C to 70°C. The dualin-line package is designed for insertion in mounting-hole rows on 7,62-mm (300-mil) centers. operation address (AO through A8) Eighteen address bits are required to decode 1 of 262,144 storage cell locations. Nine row-address bits are set up on pins AO through A8 and latched onto the chip by the row-address strobe (RAS). Then the nine column-addrass bits are set up on pins AO through A8 and latched onto the chip by the column-address strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the column decoder and the input and output buffers. write enable (W). The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL circuits without a pull-up resistor. The data input is disabled when the read mode Is selected. When W goes low prior to CAS, data out will remain in the high-impedance state for the entire cycle, permitting common I/O operation. . data In (D) Data is written during a write or read-modify-write cycle, Depending on the mode of operation, the falling edge of CAS or W strobes data into the on-chip data latch. This latch can be driven from standard TTL circuits without a pull-up resistor. In an early write cycle, W is brought low prior to CAS and the data is strobed in by CAS with setup and hold times referenced to this signal, in a delayed-write or read-modify- write cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times referenced to this signal. . data out (Q) ‘The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout of two Series 74 TTL loads. Date out Is the same polarity as data in, The output Is in the high-impedance (floating) state until CAS Is brought low. In a read cycle the output goes active after the access time interval ta(c) that begins with the negative transition of EAS as long as ta(A le satisfied. The output becomes valid after the access time has elapsed and remains valid while CAS is low; CAS going high returns it to a high-impedance state. In a read-modify-write cycle, the output will follow the sequence for the read cycle, TEE TETEEEEEIEEEE SESE 44 : TEXAS id INSTRUMENTS POST OFFICE 80x 1443 © HOUSTON, TEXAS 72001 j i

mM 8961725 007b483 7 TMS4256, TMS4257 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES TEXAS INSTR (ASIC/MEMORY) 25E D = T-46-23-15 refresh \\ o A refresh operation must be performed at least once every four milliseconds to retain data, This can be achieved by strobing each of the 266 rows (AQ-A7). A normal read or write cycle will refresh all bits in each row that Is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving power as the output buffer remains in the high-impedance state. 2 CRS-before-RAS refresh The CAS-before-RAS refresh Is utilized by bringing CAS low earlier than RAS (see parameter tCLRL) and holding it low after RAS falls (see parameter taLCHR). For successive CAS-before-RAS refresh cycles, - CAS can remein low while cycling RAS. The external address is ignored and the refresh address is generated internally. pa | hidden refrash Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at Vi. after @ read operation and cycling RAS after a specified precharge periad, similar to a CAS before RAS refresh cycle. The external address is also ‘gnored during the hidden refresh cycles. The data at the output pin remains valid up to the maximum CAS low pulse duration, tw(CL). page mode (TMS4256) Page-mode operation allows effectively faster memory access by keeping the same row address andstrobing . random column addresses onto the chip. Thus, the time required to set up and strobe sequential row addresses for the same page is eliminated. The maximum number of columns that can be addressed Is determined by tw(RL), the maximum RAS low pulse duration, nibble mode (TMS4257) Nibble-mode operation allows high-speed serial read, write, or read-modify-write access of 1 to 4 bite of data, The first bit Is accessed in the normal manner with read data coming out at ta(c) time. The next sequential nibble bits can be read or written by cycling CAS while RAS remains low. The first bit is determined by the row and column addresses, which need to be supplied only for the first access. Column AB and row AB (CA8, RA8) provide the two binary bits for initial selection of the nibble addresses. Thereafter, the falling edge of CAS will.access the next bit of the ciroular 4-bit nibble in the following sequence: 010 101 1,0 tt 1 J In nibble-mode, all normal memory operations (read, write, or read-modify-write) may be performed in any desired combination, —. : power-up . . To achieve proper device operation, an initial pause of 200 ys is required after power up, followed by a minimum of elght Initialization cycles. ee . Texas %y 45 INSTRUMENTS POST OFFICE SOX 1443. @ HOUSTON, TEXAS 77001 i i i

TMS4256, TMS4257 Mm 8961725 0076884 9 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES T-46-23-15 TEXAS INSTR (ASIC/MEMORY) 2SE Demme logic symbol

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(6) o re 7 . . AA i) A 0 5 A 10) 262,148 . 85 3) a . AT (9) a | ag Lt |20D17/2108, . E> C20/ROW} . . CoP c2ticoLy . oE oo 23022 . ww a oe en 7 : D 2) A220. Av (14) a . This symbol is In accordance with ANSI/IEEE Std. 91-1084 and EC Publication 617-12. . The pin numbers shown are for the 16-pin dual-in-line package. functional block diagram as as ¥ — oa ROW oe [zr sensnes |_| ses Ps ae [same [ote] com | a ae a [srsesenurs | [se sens os ROW ut — [samy [Eee scr . O Ae oat pee] LULU

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mM 8961725 007b88S 0 ‘TMS4256, TMS4257 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES T-46-23-15 TEXAS INSTR (ASIC/MEMORY) 2@5E D absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t Short clrouit output current 6.6... eee cece eect eee eee reece et ee test eee ene ee 50 MA, Operating free-air temperature range... 1. see eee eee ee eee eeeeeees sates est O° to 70°C Storage temperature range ©... eee eee ee cece eee eeeeteneeeeaseess —B5°C to 150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not impliad. Exposure to absolute-maximum-tated conditions for extended periods may affect device reliability. : NOTE 1: All voltago values in this data sheet are with respect to Vsg. fa | recommended operating conditions a Vop_ Supply voltage ('4256/°4267-10, -12, -15) [ Vss "Supply voltage CSCC | Vin High-iovel input voitage | | Vu. Low-lovel input voltage (eee Note 2) ti [TA Operating feealrtemporsivg OST NOTE 2; The algebraic convention, where the more negative (less positive) limit i¢ designated as maximum, Is used In this data sheet for logic voltage fovola only. SS Texas ¥P. a7 INSTRUMENTS POST OFFICE BOX 1443 @ HOUSTON, TEXAS 77001

M4256, TMS4257 @™ 8961725 0076486 2 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES T-46-23-15 me TEXAS INSTR (ASIC/MEMORY) 25E Do | electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) 3 CONDITIONS Te84297-10. 2 [Vou Hlehtevel ouput vonage | low=-6mA dT ee eV [Vou —towlevel outputvotage | top 42mA fe Poe TV Vi =0Vt06.8V, Vpp = 6V, 1A All other pins = O V to 6.5 V Vo = OV to 5.6 V, [ic _owmnanetimno | Voocovremnn | | so] | ‘Average operating current te = minimum cycle, [oor Smears | sang | mf | ‘Aftor 1 mamary cycle, Ipp2 Standby currant RAS and TAS high, Output open ‘te = minimum cycle; tppg Average refresh current FAS cycling, CAS high, . Output open ) toiP) = minimum eycle, lop Average page-mode current BAS tow, CAS cycling, Output open: Tein) = minimum oycle, Ipps Average nibble-mode current IAS tow, CAS cycling, mA Output open al on ‘vest i ee a [ton=—omA Cd [Vou Low-level output votage | lon=42mA oa [08 | Vi = OV to 6.5 V, Vpp = 5 V, Vo =OVt0 5.6V, [ic _mnannmonen [ Wpcoureunn | | | | Average operating current te = minimum cycle, - 001 during read or write cycle Output open ) After 1 memory cycle, ) Ipp2 Standby current FAS and CAS high, Output open Te = minimum cycle, Ipog Average refresh current RAS cycling, CAS high, * ‘Output open teip) = minimum cycle, = . Ipp4 Average page-mode current RAS tow, TAS cycling, mA Output open To) = minimum cycle, pps Average nibble-mode current RAS tow, CAS cycling, Output open EE EEE EEE!

48 TEXAS 4

POST OFFICE OX 1443 @ HOUSTON, TEXAS 77001

M@™ 8961725 O07ba87 4 TMS4256, TMS4257 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES TEXAS INSTR (ASIC/MEMORY) 25E D 215 capacitance over recommended supply voltage range and operating free-alr temperature range, f=-1MHz :) [ears SC*dCt er] [ Cia) Input capacitance, eddress Inputs TY F [/Cioy Input capacitance, data input CdCSSCSC 9° | Cuncy Input capacitance atrobe inpute Tr [ Cw) Input capacitance, write enable input |_| [Go _—Ovipwteapetnee or switching characteristics over recommended supply voltage range and operating free-alr temperature range [ie memes] Eeceres | oe | ef els | TRLGL = MAX, CL = 100 pF, [wm _Acsmsetomts] Ce asometarn gem | we | eo[ | | ‘Output disable time CL = 100 pF, [SICH attor TAS high Load = 2 Soties 74 TTL gates TMS4256-12 TEST CONDITIONS 1M84287-12 7 | MIN” MAX | MIN MAX | “OL = 100 pF, SR a a TRLCL = MAX, GL = 100 pF, [we _Accmvnesontms] eaeeerngem | me | [wo] | Output dieabie time CL = 100 pF, tdI9ICH) after TAS high Load = 2 Series 74 TTL gates Se TEXAS % 49 INSTRUMENTS POST OFFICE BOX 144 @ HOUSTON, TEXAS 77001

EEE eeEeOV7OOO_ . TMS4256, TMS4257 me 8961725 007b486 b 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES T-46-23-1 5 TEXAS INSTR (ASIC/MEMORY) 25E D eee ee eee timing requirements over recommended supply voltage range and operating free-air temperature range PARAMETER: SYMBOL TMS4257-10 3. [Re Paoode eet ine twat or we eye) [eg 70 to | [te Pece-made cycle timo trad-mociy-write eve) | teem | 98 | 188 | _ne_| g eT OS Froqwy Write cyciotime | tw tO 200 ns [rotcay) _Reed-writeread modify wike oyeie me | two | 188] 208 | ns re } 4 | a [twicl) Fuse auraton, CASIow? =~ tcag ‘| 4010000 | 60 70,000.| ns] ! [ey —Pase duaton, ASngh i 70 | oo [ewinty Povo duration, FAS iow’ | twas | 00 10,000 | 100 10.000 | n= | [eww Wie pulee duration | we [20 | | [ey Tenaton tines (ae ond Tan RAT aoa CAT] | | 3 | oe | a A | [isuio) Data soup time} ws [0 | 0 |-ns_| [anc somctsorm | ws | ef | [esncny Wt command soup tne totes SHgh | tow | 2 | 20 | ve | [evn —Witecommand stp ine before RAS oh [tw [20 [30 | wo | cs [tninay —Row-eddress hold time] wan | te —~«d 16 re [micas Columnedéross hold ino afer Btw | tn | 88 | 8 | rs _| [inictp) oats hed tw ater CAS ow | tow ‘| 20 | soi [unp) ete hak tw ater RAS ow | tog [00 | 0 | ve | [isnmioy Beta hold te atterWiow | a | 20 | 0 | | [inhi Rout-ommend hold ine afer CAB non [| tac | 0 | 0 | ms _| [ing Reed cermend hot tine ater AAS Noh | wan _| to | to | ww _| [nieuw —Witecommand hold ine ater ORF Iow [wwe [20 | 30 |_| [innuwn —Witecommend od tive ater RAStow | wea [8 | #0 |» | Continued next page. NOTE 3: Timing measurements are referenced to Vi_ max and Vip min. TAI cycle times assume ty = 6 ns. . tin a read-modify-write cycle, tcLWL 8nd teu{WCH) Must be observed. Depending on the user's transition times, this may require additional ‘TAS tow timo (ty(cL)). This spplies to page-mode read-modify-write also, Sin a read-modity-write cycle, trLWL 8nd tey{WRH) Must be observed. Depending on the user's transition times, this may require additional RAS low time (twirt)) ee wo eine i

EE eowweowowreeeererereeeeOm WB 4961725 0076869 6 TMS4256, TMS4257 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES TEXAS INSTR (ASIC/MEMORY) 25€ p __1-46-23-15 a NEE Ors timing requirements over recommended supply voltage range and operating free-air temperature range (continued) oe PARAMETER SYMBOL, TMS4257-10 [Min Max | "MIN MAX | [auch Delay time, RAS low toTATHigh [tc | eo tC |S | tcHRL “Delay time, GASigh to RAS low | tcne | Cd] ide [tcuan~ Delay time, GASiow woRAS high | tag | 40d | truchn Delay time, RAS iow toCASHohf | tcun «| 20 SY Se a Ce OS he {read-modify-write cycle only) ae tRLCL. {maximum value specified onty tRCD to guerantee access time) rh a (road-modify-write cycle only) [Ltt Refresh viene Tnterval tne Continued next page. . NOTE 3: Timing measurements are referenced to Vj, max and Vix min. ITAS-betore-RAS refresh only. Texas id att INSTRUMENTS POST OFFICE BOX 1443 © HOUSTON, TEXAS 72001 t i i ee

TMS4256, TMS4257 @™™ 8961725 0076890 4 mm 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES T-46-23-15 : ees TEXAS INSTR (ASIC/MEMORY) 25E D ou timing requirements over recommended supply voltage range and operating free-alr temperature range (continued) iC = See 1M84267-16 [MN Max] Mi MAX | 5 [ tele __Pane-mode cycle time (read or write cycle) [tpg i20 45 ne g [ciey Read eyclatmet | tac 20 age [tw Write cyeletime dT two 220250 ne | toiraw) _Read-wite/read-modify-write cycle time | two [260 aoe ne * [twichye Pulse duration, CAS high (nego mode) | tcp, S| 80 gon [rwiciy Pulse duration, ABlow? | tag 60 10,000 | 75 10,000] ne [ewiaty Pulse duration, FAShah | tw | 80 toe [ewisu) Fuse draion,FASiow! | 1nag__| 120103000 | 16010700 | “oa | [eww) Write pulse duraon | te Ta ne [te Transion tines (ee end fei) for RAS ond S| tr S| sos go |e [tauicayColumn-eddresseotuptime S| tase | One [tsuinay —Row-address sotuptme | tsa TO ne [teujo) —Datecouptime | tg ne [euieay _Read-commend setuptime | acs [ne [eauwouy Early wite-command setup time before CAS low] ewes | oT ne | [eourwowy Wite-commend eotup time before CAS Hah | tcw. | 36 ase [eauiwan) Wito-commend soto time before RAS High | taw | 36 | ase [anicicay _Colurmadérese hold time ater CASiow [toa | 20 as ne [inima) Row-address hoidtime | tan | te [ayiaucal Column-address hold time after MASiow | tan | 80 tone [thicioy —Oatahold ime atter CASiow | ton | 80a | [euimuoy Date hold time etterRASiow | tong | 90 toe [enwup) Date hold time etterWiow | ton | go ae [anichia —Resd-commend hold time afer GAStigh | tacu (| 0 | oe [enyatigy —Reed-command hold time after AShigh | tag | 10 | toe [enicuwy —Wite-commend hold tine after CASIow | won | go fase [rnupiw —_Wete-command hold time after RASiow | twor | 90 | 120 ne Continued next page. NOTE 3: Timing measurements are referenced to \\j_ max end Vi} min. : TAll cycle times assume ty = 5 ns, In a read-modify-write cycle, tcLWI, 8nd teu(WCH) must be observed. Depending on the user's transition times, this may require additional TAS tow time (twicu)). This epplies to page-mode read-modity-write also, . Sin a read-modify-write cycle, ta WL end tsu{WAH) must be observed. Depending on the user's transition times, this may require additional RAS low time (ty(AL))- . 412 F TEXAS % . INSTRUMENTS POST OFFICE BOX 1443 @ HOUSTON, TEXAS 77001 i i

| M@™ 8961725 007b891 &b mm 1MS4256, TMS4257 . 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES .

7 TEXAS INSTR (ASIC/MEMORY) 25E D __T-46-23-15

re NS INSTR A —_—— | timing requirements over recommended supply voltage range and operating free-air temperature range (concluded) F SYMBOL Cant MARC | Ta WA] toLAH Delay time, CAS low to RAS high [ tasy [eo es [auc Delay time, RAS low to CAS high? town [26 0s tcuAL Delay time, CAS low to RAS low! {tesa [10 | zoe Savicl Delay time, RAS high to CAS low a | Sci _Delay time, CAS tow to W low (read-madity-write eyele only] tcwo | 60 | 70 | ne | _ [SO ecw | we [ef sn] | ‘tRLCL 26 78 only to guarantee access time) tALWL_Delay time, RAS tow to W low (read-modity-write cycle only)| tawo | 120 «| ‘45ST © Det Retreat Unterval tne me _| NOTE 3; Timing measurements are referenced to Vi, max and Vix min. . NCAS-botore RAS refesh ony. | NIBBLE-MODE CYCLE switching characteristics over recommended supply voltage range and operating free-air temperature range . [| _ranaweren | ALT. | ms4267-10 | ms4267-12 |_1M54267-16 | SYMBOL [Min MAX | MIN MAX | MN MAX | [tsicny Nibblemode eccess trom GAS | iweac | S28] a] Ow | timing requirements over recommended supply voltage range and operating free-alr temperature range ALT. | 1ms4267-10 | 1ms4267-12 | 1™MS4267-16 | SYMBOL [MIN MAX [MIN MAX’ "MIN "MAX | [Rem Nibblemade eyeietime [we | 60 | eo | 7 | Nibble-mode read-modify- fctrdWN) write oycle time Nibble-mode delay time, a ee Nibbie-mode delay time, SCLWLN GAB to W delay Tibble-mode pulae duration, [wow tion | wes fe [| Nibble-mode pulse duration, {wiCHN) TKS high Nibble-mode write command 7 sulWCHN) setup botore CAS high NGWL NOTE 3: Timing measurements aro roferenced to Vi_ max and Viy min. . a TEXAS 4% 413 INSTRUMENTS POST.OFFICE 80x 1449 @ HOUSTON. TEXAS 77003 i i i

. MS4256, TMS4257 @™ 89b17es 007842 cm! 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES T-46-23-15 | : ee TEXAS INSTR (ASIC/MEMORY) — 25E Dennen | read cycle timing . | | | L | Vi. ae = —— tern ———d be tint) of | te truce “4 be tc —at i i. “= “ f teulRAD { b i | i ie | = twirtcay—— H ! 1 ke tiny {| f H bf twicn) ——a 1 | teulCA} fr. ara" "9% 94's" se MAA AAAS OOOOE. vi aonas BERT now SRR cow DR Bena SSSR _ | et tnicicad | fe thinttra) ve aaj bL tauren pt cera y | SOCASRAARARO OO, Se eeeanees ance : W RRRCOR CARER RY { | RRR ER ee oe — tac) —=} I Vie a tain) ————o} i eae) Vou Vou ee 414 TEXAS. % INSTRUMENTS - 0ST OFFICE BOX 1443 # HOUSTON, TEXAS 77001

M™ 4961725 0076893 T TMS4256, TMS4257 . 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES ees TEXAS INSTR (ASIC/MEMORY) 256 D me early write cycle timing T-46-23-15 . CJ bey. -___ — et t teiw) 7 | 1 wim), £9, t \\ vn t as \\. My iN 2 i al Vie = =e tb = tcin ———=y_ twin od | rt tRLCL q t ee THA —- & ty ~“h— iwicty — wt t 1 i Vie a a | eu t v 1 aca rh ; . taet tee thins | + thicLca) 1 tr twice) ——ey my] oe teulCa) tot YY ZY) F SKY NYY VY Vin OXY XX XY OOO OS - no-n8 SEX now HERO conumn wiesncewicas denny Ve t Hi { ‘ 1 int teutwary, ————l

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M@@® 4961725 OO7b894 1 oe TMS4256, TMS4257 262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES T-46-23-15 es TEXAS INSTR (ASIC/MEMORY) = 25E D <n write cycle timing g pe Su H { wie), 4 { . oe WES tI i f——* uit 7 | i Vi @ \\ rt RLct “Pe twiet) —! ‘CHR tach "1 1 f vin Fer tauinal \\ { va b-—— tniatcay-+-—et iit i aoe ‘ma | feeb teres) ! bt— wie) ——t { —_ tau(ca) i! OO AX) KRY Ry WH none BROT now DEBT coum DERRRRR Sanit CARE AARAAD vn | > teuwen —s bot. tice) — { SRXRRRKPRYPEPERRRRER | | QRRRRRRRERP PEP EYYRERRRERRRY Vl W RARER BONE SAE RRR ER Co RO 0 7 ¥ tt wi) I {| Ceewaon | HOMERS Fico one ORR vin ROKBONE CATER, VAUD DATA RR RR cater AE ORCC vu fh A teuio) er be tent H tdis(CH) . Vou Vou The enable time Tten) for a write cycle is equal in duration to the access time from GAS (tic)! in a read cycle; but the active levels at the output ere invalid, CT

416 TEXAS 4%

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