TMS418160ADZ

TMS418160A TI | Alldatasheet

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1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 This data sheet is applicable to TMS418160As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section. /C0068Organization...1 0 4 8576 by 16 Bits /C0068Single 5-V Power Supply (± 10% Tolerance) /C00681024-Cycle Refresh in 16 ms /C0068Performance Ranges: ACCESS ACCESS ACCESS READ/ TIME TIME TIME WRITE tRAC tCAC tAA CYCLE MAX MAX MAX MIN ’418160A-50 50 ns 13 ns 25 ns 90 ns ’418160A-60 60 ns 15 ns 30 ns 110 ns ’418160A-70 70 ns 18 ns 35 ns 130 ns /C0068Enhanced Page-Mode Operation With xCAS -Before-RAS (xCBR) Refresh /C00683-State Unlatched Output /C0068Low Power Dissipation /C0068High-Reliability Plastic 42-Lead 400-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DZ Suffix) /C0068Ambient Temperature Range 0°C to 70°C

description

The TMS418160A is a 16777216-bit dynamic random-access memory (DRAM) device orga- nized as 1048576 words of 16 bits. It employs state-of-the-art technology for high performance, reliability, and low power at low cost. This device features maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS418160A is offered in a 42-lead plastic surface-mount SOJ package (DZ suffix). This package is designed for operation from 0° to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PIN NOMENCLATURE A[0:9] Address Inputs DQ[0:15] Data In/Data Out LCAS Lower Column-Address Strobe UCAS Upper Column-Address Strobe NC No Internal Connection OE Output Enable RAS Row-Address Strobe VDD 5-V Supply VSS Ground W Write Enable VDD DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 NC NC W RAS NC NC V DD VSS DQ15 DQ14 DQ13 DQ12 V SS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE V SS DZ PACKAGE (TOP VIEW) Copyright  1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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logic symbol† DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 RAS LCAS UCAS W RAM 1M × 16 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21 G24 23C22 A,22D A8 27 C21 G34 Z31 24,25EN27 34,25EN37 23C32 23,21D ∇ 26,27 A, Z26 A,32D ∇ 36,37 A, Z36 OE A 0 1 048 575 A9 28 20D19/21D9 20D10/21D0 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

going low enables its corresponding DQx pin. Figure 1. Illegal Dual-xCAS Operation

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Page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the xCAS page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without intervening RAS cycles. Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the first xCAS latches the column addresses. This performance improvement is referred to as enhanced-page mode. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode because data retrieval begins as soon as the column address is valid rather than when xCAS transitions low. A valid column address may be presented immediately after tRAH (row-address hold time) has been satisfied, usually well in advance of the falling edge of xCAS. In this case, data is obtained after tCAC maximum (access time from xCAS low) if tAA maximum (access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined by tCPA . address: A0–A9 Twenty address bits are required to decode each of the 1048576 storage cell locations. Twelve row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits are set up on A0 through A7 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the column-address buffers. The column address is latched on the first xCAS falling edge with address setup and hold parameters referenced to that edge. In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time (see parameter tCP ) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum hold time, tCLCH . During tCLCH , at least one xCAS must be brought low before the other xCAS is taken high. write enable (W) Read- or write mode is selected through W. A logic high on W selects the read mode and a logic low selects the write mode. Data in is disabled when the read mode is selected. When W goes low prior to xCAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation independent of the state of OE. This permits early-write operations to be completed with OE grounded. data in (DQ0–DQ15) Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to a xCAS falling edge and the data is strobed into the on-chip data latch for the corresponding DQs with setup-and-hold times referenced to this xCAS signal. In a delayed-write- or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and hold times referenced to this signal. Also, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines (see parameter tOED ).

DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 data out (DQ0–DQ15) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access-time-interval tCAC (which begins with the negative transition of xCAS) as long as tRAC (access time from RAS) and tAA (access time from column address) are satisfied. The delay time from xCAS low to valid data out is measured from each individual xCAS to its corresponding DQx pin. output enable (OE) OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS and xCAS to be brought low (until either OE or xCAS is brought high) for the output buffers to go into the low-impedance state. RAS -only refresh A refresh operation must be performed once every 16 ms to retain data. This can be achieved by strobing each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally. xCAS -before-RAS (xCBR) refresh xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR ) and holding it low after RAS falls (see parameter tCHR ). For successive xCBR refresh cycles, xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs, followed by a minimum of eight initialization cycles, is required after power up to the full VDD level. These eight initialization cycles must include at least one refresh (RAS-only or xCBR) cycle.

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absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 4.5 5 5.5 V VSS Supply voltage 0 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) –1 0.8 V TA Ambient temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) PARAMETER TEST CONDITIONS † ’418160A-50 ’418160A-60 ’418160A-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltageIOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VDD = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage)VDD = 5.5 V, V O = 0 V to VDD , xCAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VDD = 5.5 V, Minimum cycle 180 160 150 mA ICC2 Average standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and xCAS high 2 2 2 mA ICC2 Average standby current VIH = VDD – 0.2 V (CMOS), After one memory cycle, RAS and xCAS high 1 1 1 mA ICC3 § Average refresh current (RAS -only refresh or xCBR) VDD = 5.5 V, Minimum cycle, RAS cycling, xCAS high (RAS only), RAS low after xCAS low (xCBR) 180 160 150 mA ICC4 ‡¶ Average page current VDD = 5.5 V, t PC = MIN, RAS low, xCAS cycling 110 90 80 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each page cycle, tPC capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A9 5 pF C i(OE) Input capacitance, OE 7 pF C i(RC) Input capacitance, xCAS and RAS 7 pF C i(W) Input capacitance, W 7 pF C O Output capacitance# 7 pF # LCAS and UCAS = VIH to disable outputs NOTE 3: V DD = 5 V ± 10%, and the bias on pins under test is 0 V.

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switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 4) PARAMETER ’418160A-50 ’418160A-60 ’418160A-70 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address 25 30 35 ns tCAC Access time from xCAS 13 15 18 ns tCPA Access time from xCAS precharge 30 35 40 ns tRAC Access time from RAS 50 60 70 ns tOEA Access time from OE 13 15 18 ns tCLZ Delay time, xCAS to output in the low-impedance state 0 0 0 ns tOH Output data hold time from xCAS 3 3 3 ns tOHO Output data hold time from OE 3 3 3 ns tOFF Output buffer turn-off delay from xCAS (see Note 5) 0 13 0 15 0 18 ns tOEZ Output buffer turn-off delay from OE (see Note 5) 0 13 0 15 0 18 ns NOTES: 4. With ac parameters, it is assumed that tT = 5 ns. 5. tOFF and tOEZ are specified when the output is no longer driven. Data-in should not be enabled until one of the applicable maximum specifications is satsified. ac timing requirements (see Note 4) ’418160A-50 ’418160A-60 ’418160A-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, read 90 110 130 ns tWC Cycle time, write 90 110 130 ns tRWC Cycle time, read-write 131 155 181 ns tPC Cycle time, page-mode read or write (see Note 6) 35 40 45 ns tPRWC Cycle time, page-mode read-write 76 85 96 ns tRASP Pulse duration, RAS active, page mode (see Note 7) 50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, RAS active, nonpage mode (see Note 7) 50 10 000 60 10 000 70 10 000 ns tCAS Pulse duration, xCAS active (see Note 8) 13 10 000 15 10 000 18 10 000 ns tRP Pulse duration, RAS (precharge) 30 40 50 ns tWP Pulse duration, write command 10 10 10 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data-in (see Note 9) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before xCAS precharge 13 15 18 ns tRWL Setup time, write command before RAS precharge 13 15 18 ns tWCS Setup time, write command before xCAS active (early-write only) 0 0 0 ns tWRP Setup time, write before RAS active (CBR refresh only) 10 10 10 ns NOTES: 4. With ac parameters, it is assumed that tT = 5 ns. 6. To assure tPC min, tASC should be ≥ to tCP . 7. In a read-write cycle, tRWD and tRWL must be observed. 8. In a read-write cycle, tCWD and tCWL must be observed. 9. Referenced to the later of xCAS or W in write operations

DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ac timing requirements (see Note 4) (continued) ’418160A-50 ’418160A-60 ’418160A-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tCAH Hold time, column address 10 10 15 ns tDH Hold time, data-in (see Note 9) 10 10 15 ns tRAH Hold time, row address 8 10 10 ns tRCH Hold time, read command referenced to xCAS (see Note 10) 0 0 0 ns tRRH Hold time, read command referenced to RAS (see Note 10) 0 0 0 ns tWCH Hold time, write command during xCAS active (early-write only) 10 10 15 ns tCLCH Hold time, xCAS low to xCAS high 5 5 5 ns tRHCP Hold time, RAS active from xCAS precharge 30 35 40 ns tOEH Hold time, OE command 13 15 18 ns tROH Hold time, RAS referenced to OE 10 10 10 ns tWRH Hold time, write after RAS active (CBR refresh only) 10 10 10 ns tCP Delay time, xCAS precharge 8 10 10 ns tAWD Delay time, column address to write command (read-write operation only) 48 55 63 ns tCHR Delay time, xCAS referenced to RAS (xCBR refresh only) 10 10 10 ns tCRP Delay time, xCAS precharge to RAS 5 5 5 ns tCSH Delay time, RAS active to xCAS precharge 50 60 70 ns tCSR Setup time, xCAS referenced to RAS (xCBR refresh only) 5 5 5 ns tCWD Delay time, xCAS to write command (read-write operation only)36 40 46 ns tOED Delay time, OE to data in 13 15 18 ns tRAD Delay time, RAS to column address (see Note 11) 13 25 15 30 15 35 ns tRAL Delay time, column address to RAS precharge 25 30 35 ns tCAL Delay time, column address to xCAS precharge 25 30 35 ns tRCD Delay time, RAS to xCAS (see Note 11) 18 37 20 45 20 52 ns tRPC Delay time, RAS precharge to xCAS active 5 5 5 ns tRSH Delay time, xCAS active to RAS precharge 13 15 18 ns tRWD Delay time, RAS to write command (read-write operation only) 73 85 98 ns tCPW Delay time, xCAS precharge to write command (read-write operation only) 53 60 68 ns tREF Refresh time interval 16 16 16 ms tT Transition time 2 30 2 30 2 30 ns NOTES: 4. With ac parameters, it is assumed that tT = 5 ns. 9. Referenced to the later of xCAS or W in write operations 10. Either tRRH or tRCH must be satisfied for a read cycle. 11. The maximum value is specified only to assure access time.

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NOTE A: C L includes probe and fixture capacitance. Figure 2. Load Circuits for Timing Parameters

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. tCAC is measured from xCAS to its corresponding DQx. C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 3. Read-Cycle Timing

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NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. C. tCWL must be satisfied for each xCAS to write properly to each byte. Figure 4. Write-Cycle Timing

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. C. tWCS and tWCH must be satisfied for each xCAS. D. tDS and tDH of a DQ input are referenced to the corresponding xCAS. E. tCWL must be satisfied for each xCAS to write properly to each byte. Figure 5. Early-Write-Cycle Timing

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NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Read-Write-Cycle Timing

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. tCAC is measured from xCAS to its corresponding DQx. C. Access time is tCPA -, tAA -, or tCAC -dependent. D. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. specifications are not violated. Figure 7. Enhanced-Page-Mode Read-Cycle Timing

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NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. specifications are not violated. D. tCWL must be satisfied for each xCAS to ensure proper writing to each byte. Figure 8. Enhanced-Page-Mode Write-Cycle Timing

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. specifications are not violated. D. tWCS and tWCH must be satisfied for each xCAS. E. tDS and tDH for a DQ is referenced to the corresponding xCAS. F. tCWL must be satisfied for each xCAS. Figure 9. Enhanced-Page-Mode Early Write-Cycle Timing

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NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. Access time is tCPA -, tAA -, or tCAC -dependent. C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. F. tCAC is measured from xCAS to its corresponding DQx. Figure 10. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing

NOTE A: All xCAS must be high. Figure 11. RAS-Only Refresh-Cycle Timing

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Figure 12. Hidden-Refresh-Cycle (Read) Timing

Figure 13. Hidden-Refresh-Cycle (Write) Timing

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NOTE A: Any xCAS can be used. If both LCAS and UCAS are used, both must satisfy tCSR and tCHR . Figure 14. Automatic-xCBR-Refresh-Cycle Timing

DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 23POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA DZ (R-PDSO-J42) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 4040094-6/C 4/95 0.445 (11,30) 0.435 (11,05) 0.148 (3,76) 0.395 (10,03) 0,405 (10,29) Seating Plane 0.380 (9,65) 0.360 (9,14) 0.008 (0,20) NOM 0.128 (3,25) 1.070 (27,18) 1.080 (27,43) 0.026 (0,66) 0.032 (0,81) 0.016 (0,41) 0.020 (0,51) 0.106 (2,69) NOM 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125). device symbolization Package Code -SS TMS418160A DZ Assembly Site Code Lot Traceability Code Year Code Die Revision Code Wafer Fab Code PLLLLYEW M Month Code TI

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