TMS417800A TI1 | Alldatasheet
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2097152 BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORY SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 This data sheet is applicable to all TMS417800As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section. /C0068Organization...2 0 9 7152 × 8 /C0068Single 5-V Power Supply (± 10% Tolerance) /C00682048-Cycle Refresh in 32 ms /C0068Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME EDO tRAC tCAC tAA CYCLE MAX MAX MAX MIN ’417800A-50 50 ns 13 ns 25 ns 20 ns ’417800A-60 60 ns 15 ns 30 ns 25 ns ’417800A-70 70 ns 18 ns 35 ns 30 ns /C0068Enhanced Page-Mode Operation With CAS -Before-RAS (CBR) Refresh /C0068High-Impedance State Unlatched Output /C0068Low Power Dissipation /C0068High-Reliability Plastic 28-Lead 400-Mil-Wide Surface-Mount Small Outline J-Lead (SOJ) Package (DZ Suffix) /C0068Ambient Temperature Range 0°C to 70°C
description
The TMS417800A is a 16777216-bit dynamic random-access memory (DRAM) device organized as 2097152 words of eight bits. It employs TI’s state-of-the-art technology for high performance, reliability, and low power. This device features maximum RAS access times of 50-, 60-, and 70 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS417800A is offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). This package is designed for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PIN NOMENCLATURE A[0:10] Address Inputs CAS Column-Address Strobe DQ[0:7] Data In/Data Out OE Output Enable RAS Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable VCC DQ0 DQ1 DQ2 DQ3 W RAS NC A10 VCC VSS DQ7 DQ6 DQ5 DQ4 CAS OE V SS DZ PACKAGE (TOP VIEW) Copyright 1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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logic symbol† DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 RAS CAS W OE RAM 2M x 8 20D10/21D0 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21[COL] G24 23C22 23,21D 24 ,25EN A,Z26 A8 20 A9 21 G25 A,22D ∇ 26 A 0 2 097 151 20D20A10 9 20D19/21D9 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
DYNAMIC RANDOM-ACCESS MEMORY SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram Timing and Control Column- Address Buffers Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers R o w D e c o d e 256K Array 256K Array 256K Array 256K Array 256K Array 256K Array RAS CAS W DQ0–DQ7 OE A10 operation enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup-and-hold, and for address multiplexing, is eliminated. The maximum number of columns that can be accessed is determined by t RASP , the maximum row-address strobe (RAS) low time. Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while column-address strobe (CAS) is high. The falling edge of CAS latches the column addresses and enables the output, which allows the devices to operate at a higher data bandwidth than conventional page-mode devices because data retrieval begins as soon as the column address is valid rather than when CAS goes low. This performance improvement is referred to as enhanced-page mode. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low) if tAA max (access time from column address) and tRAC (access time from RAS) have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCPA (access time from CAS precharge) or tCAC . address: A0–A10 Twenty-one address bits are required to decode each of the 2097152 storage cell locations. Eleven row-address bits are set up on inputs A0 through A10 and latched on the chip by RAS. Ten column-address bits are set up on A0 through A9. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the column-address buffers.
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write enable (W) The read- or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. data in (DQ0–DQ7) Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and the data is strobed in by CAS with setup-and-hold times referenced to this signal. In a delayed-write- or read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup-and-hold time referenced to this signal. Also, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines. data out (DQ0–DQ7) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with the negative transition of CAS) as long as tRAC and tAA are satisfied. RAS -only refresh A refresh operation must be performed once every 32 ms to retain data. The refresh operation can be achieved by strobing each of the 2048 rows (A0–A10). A normal read- or write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS -only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. The hidden-refresh operation is accomplished by holding CAS at VIL after a read- or write operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally. CAS -before-RAS (CBR) refresh CBR refresh is used by bringing CAS low earlier than RAS (see parameter tCSR ) and then holding it low after RAS falls (see parameter tCHR ). For successive CBR-refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full VCC level. The eight initialization cycles must include at least one refresh (RAS -only or CBR) cycle.
DYNAMIC RANDOM-ACCESS MEMORY SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VSS Supply voltage 0 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) –1 0.8 V TA Ambient temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) PARAMETER TEST CONDITIONS † ’417800A-50 ’417800A-60 ’417800A-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle currentVCC = 5.5 V, Minimum cycle 130 110 100 mA ICC2 Average standby VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 2 2 2 mA ICC2 gy current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 1 1 1 mA ICC3 ‡§ Average refresh current (RAS-only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 130 110 100 mA ICC4 ‡¶ Average page current VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 90 70 60 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each page-mode cycle, tPC
DYNAMIC RANDOM-ACCESS MEMORY SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A10 5 pF C i(OE) Input capacitance, OE 7 pF C i(RC) Input capacitance, CAS and RAS 7 pF C i(W) Input capacitance, W 7 pF C o Output capacitance† 7 pF † CAS = VIH to disable outputs NOTE 3: V CC = 5 V ± 10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 4) PARAMETER ’417800A-50 ’417800A-60 ’417800A-70 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address 25 30 35 ns tCAC Access time from CAS 13 15 18 ns tCPA Access time from CAS precharge 30 35 40 ns tRAC Access time from RAS 50 60 70 ns tOEA Access time from OE 13 15 18 ns tCLZ Delay time, CAS to output in the low-impedance state 0 0 0 ns tOH Output data hold time from CAS 3 3 3 ns tOHO Output data hold time from OE 3 3 3 ns tOFF Output buffer turn-off delay from CAS (see Note 5) 0 13 0 15 0 18 ns tOEZ Output buffer turn-off delay from OE (see Note 5) 0 13 0 15 0 18 ns NOTES: 4. With ac parameters, it is assumed tT = 5 ns. 5. tOFF and tOEZ are specified when the output is no longer driven. Data-in should not be driven until one of the maximum values is satisfied.
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ac timing requirements (see Note 4) ’417800A-50 ’417800A-60 ’417800A-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, read 90 110 130 ns tWC Cycle time, write 90 110 130 ns tRWC Cycle time, read-write 131 155 181 ns tPC Cycle time, page-mode read or write (see Note 6) 35 40 45 ns tPRWC Cycle time, page-mode read-write 76 85 96 ns tRASP Pulse duration, RAS active, page mode (see Note 7) 50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, RAS active, nonpage mode (see Note 7) 50 10 000 60 10 000 70 10 000 ns tCAS Pulse duration, CAS active (see Note 8) 13 10 000 15 10 000 18 10 000 ns tCP Pulse duration, CAS precharge 8 10 10 ns tRP Pulse duration, RAS precharge 30 40 50 ns tWP Pulse duration, write command 10 10 10 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 9) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CAS precharge 13 15 18 ns tRWL Setup time, write command before RAS precharge 13 15 18 ns tWCS Setup time, write command before CAS active (early-write only) 0 0 0 ns tCSR Setup time, CAS referenced to RAS (CBR refresh only) 5 5 5 ns tWRP Setup time, write before RAS active (CBR refresh only) 10 10 10 ns tCAH Hold time, column address 10 10 15 ns tDH Hold time, data in (see Note 9) 10 10 15 ns tRAH Hold time, row address 8 10 10 ns tRCH Hold time, read command referenced to CAS (see Note 10) 0 0 0 ns tRRH Hold time, read command referenced to RAS (see Note 10) 0 0 0 ns tWCH Hold time, write command during CAS active (early-write only) 10 10 15 ns tRHCP Hold time, RAS active from CAS precharge 30 35 40 ns tOEH Hold time, OE command 13 15 18 ns tROH Hold time, RAS referenced to OE 10 10 10 ns tWRH Hold time, write after RAS active (CBR refresh only) 10 10 10 ns tAWD Delay time, column address to write command (read-write operation only) 48 55 63 ns NOTES: 4. With ac parameters, it is assumed tT = 5 ns. 6. To ensure tPC MIN, tASC should be ≥ to tCP . 7. In a read-write cycle, tRWD and tRWL must be observed. 8. In a read-write cycle, tCWD and tCWL must be observed. 9. Referenced to the later of CAS or W in write operations 10. Either tRRH or tRCH must be satisfied for a read cycle.
NOTES: 4. With ac parameters, it is assumed tT = 5 ns.
- The maximum value is specified only to ensure access time.
NOTE A: C L includes probe and fixture capacitance. Figure 1. Load Circuits for Timing Parameters
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NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 2. Read-Cycle Timing
Figure 3. Early-Write-Cycle Timing
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Figure 4. Write-Cycle Timing
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 5. Read-Write-Cycle Timing
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† Access time is tCPA -, tCAC -, or tAA -dependent. NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Enhanced-Page-Mode Read-Cycle Timing
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 7. Enhanced-Page-Mode Early-Write-Cycle Timing
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NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 8. Enhanced-Page-Mode Write-Cycle Timing
† Output can go from the high-impedance state to an invalid-data state prior to the specified access time. NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated. Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
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Figure 10. RAS-Only Refresh-Cycle Timing Figure 11. Automatic CBR-Refresh-Cycle Timing
Figure 12. Hidden-Refresh-Cycle (Read) Timing
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Figure 13. Hidden-Refresh-Cycle (Write) Timing
DYNAMIC RANDOM-ACCESS MEMORY SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA DZ (R-PDSO-J) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 4040094/C 11/95 0.395 (10,03) 0.405 (10,29) Seating Plane 0.445 (11,30) 0.435 (11,05) 0.008 (0,20) NOM 0.360 (9,14) 0.380 (9,65) 1.080 0.830 1.030 1.0700.820 (20,83) 1.020 (25,91) (27,18) 0.026 (0,66) 0.032 (0,81) A 0.106 (2,69) NOM 0.730 0.730 0.720 (18,29)(18,29) 0.720 (18,54)(18,54) DIM A MIN A MAX PINS 0.016 (0,41) 0.020 (0,51) 0.148 (3,76) 0.128 (3,25) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27)
32 PIN SHOWN
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,13). D. The 24 pin package has the center two pins removed on both sides.
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-SS TMS417800A DZ Assembly Site Code Lot Traceability Code Year Code Die Revision Code Wafer Fab Code PLLLLYEW M Month Code TI
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