TMS416800

TMS416800 TI1 | Alldatasheet

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TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization...2 0 9 7 1 5 2 × 8 /C0068Single 5 V Power Supply (±10% Tolerance) /C0068Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC tCAC tAA CYCLE MAX MAX MAX MIN ’41x800-60 60 ns 15 ns 30 ns 110 ns ’41x800-70 70 ns 18 ns 35 ns 130 ns ’41x800-80 80 ns 20 ns 40 ns 150 ns /C0068Enhanced Page-Mode Operation With CAS -Before-RAS (CBR) Refresh /C0068High-Impedance State Unlatched Output /C0068High-Reliability Plastic 28-Lead 400-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package /C0068Operating Free-Air Temperature Range 0°C to 70°C /C0068Fabricated Using Enhanced Performance Implanted CMOS (EPIC ) Technology by Texas Instruments (TI )

description

The TMS41x800 series is a set of high-speed, 16777216-bit dynamic random-access memo- ries (DRAMs) organized as 2097152 words of eight bits each. It employs TI’s state-of-the-art EPIC technology for high performance, reliability, and low power. These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS416800 and TMS417800 are offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). This package is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PIN NOMENCLATURE A0–A11 † Address Inputs CAS Column-Address Strobe DQ0–DQ7 Data In/Data Out OE Output Enable RAS Row-Address Strobe VCC 5 V VSS Ground W Write Enable † A11 is NC (no internal connection) for TMS417800. VCC DQ0 DQ1 DQ2 DQ3 W RAS A11† A10 VCC VSS DQ7 DQ6 DQ5 DQ4 CAS OE V SS DZ PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1996, Texas Instruments Incorporated EPIC and TI are trademarks of Texas Instruments Incorporated.

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996

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Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the maximum row-address strobe (RAS ) low time. Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while column-address strobe (CAS) is high. The falling edge of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when CAS goes low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS . In this case, data is obtained after tCAC max (access time from CAS low) if tAA max (access time from column address) and tRAC (access time from RAS) have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCPA (access time from CAS precharge) or tCAC . address: A0–A11 (TMS416800) and A0–A10 (TMS417800) Twenty-one address bits are required to decode one of 2097152 storage cell locations. For the TMS416800, 12 row-address bits are set up on A0 through A11 and latched on the chip by the RAS. Nine column-address bits are set up on A0 through A8. For the TMS417800, 11 row-address bits are set up on inputs A0 through A10 and latched on the chip by RAS. Ten column-address bits are set up on A0 through A9. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the column-address buffers. write enable (W) The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. data in (DQ0–DQ7) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines. data out (DQ0–DQ7) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with the negative transition of CAS) as long as tRAC and tAA are satisfied.

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 RAS -only refresh TMS416800 A refresh operation must be performed at least once every 64 ms to retain data. The refresh operation can be achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS -only refresh. TMS417800 A refresh operation must be performed at least once every 32 ms to retain data. The refresh operation can be achieved by strobing each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits in each row that is selected. A RAS -only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS -only refresh. hidden refresh A hidden refresh can be performed while maintaining valid data at the output pin. The hidden refresh operation is accomplished by holding CAS at VIL after a read or write operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally. CAS -before-RAS (CBR) refresh CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR ) and then holding it low after RAS falls (see parameter tCHR ). For successive CBR refresh cycles, CAS can remain low while cycling RAS . The external address is ignored, and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full VCC level. The eight initialization cycles must include at least one refresh (RAS -only or CBR) cycle.

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996

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logic symbol for TMS416800† DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 RAS CAS W OE RAM 2M x 8 20D9/21D0 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21[COL] G24 23C22 23,21D 24 ,25EN A,Z26 A8 20 A9 21 G25 A,22D ∇ 26 A 0 2 097 151 20D19A10 9 20D18 A11 8 20D20 20D17/21D8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 logic symbol for TMS417800† DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 RAS CAS W OE RAM 2M x 8 20D10/21D0 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21[COL] G24 23C22 23,21D 24 ,25EN A,Z26 A8 20 A9 21 G25 A,22D ∇ 26 A 0 2 097 151 20D20A10 9 20D19/21D9 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996

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R o w D e c o d e Timing and Control Column- Address Buffers Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers 256K Array 256K Array 256K Array RAS CAS W DQ0–DQ7 OE A9, A10, A11 TMS417800 Timing and Control Column- Address Buffers Row- Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers R o w D e c o d e 256K Array 256K Array 256K Array 256K Array 256K Array 256K Array RAS CAS W DQ0–DQ7 OE A10

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions TMS41x800 UNIT MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VSS Supply voltage 0 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) –1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TMS416800 PARAMETER TEST CONDITIONS † ’416800-60 ’416800-70 ’416800-80 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltageIOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage)VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VCC = 5.5 V, Minimum cycle 80 70 60 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 2 2 2 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 1 1 1 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 80 70 60 mA ICC4 ‡¶ Average page current VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 70 60 50 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change while CAS = VIH

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS417800 PARAMETER TEST CONDITIONS † ’417800-60 ’417800-70 ’417800-80 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltageIOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage)VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VCC = 5.5 V, Minimum cycle 110 100 90 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 2 2 2 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 1 1 1 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 110 100 90 mA ICC4 ‡¶ Average page current VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 70 60 50 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change while CAS = VIH

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996

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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A11† 5 pF C i(OE) Input capacitance, OE 7 pF C i(RC) Input capacitance, CAS and RAS 7 pF C i(W) Input capacitance, W 7 pF C o Output capacitance 7 pF † A11 is NC (no internal connection) for TMS417800. NOTE 3: V CC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 4) PARAMETER ’41x800-60 ’41x800-70 ’41x800-80 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address 30 35 40 ns tCAC Access time from CAS 15 18 20 ns tCPA Access time from CAS precharge 35 40 45 ns tRAC Access time from RAS 60 70 80 ns tOEA Access time from OE 15 18 20 ns tCLZ Delay time, CAS to output in the low-impedance state 0 0 0 ns tOH Output data hold time from CAS 3 3 3 ns tOHO Output data hold time from OE 3 3 3 ns tOFF Output buffer turn-off delay from CAS (see Note 5) 0 15 0 18 0 20 ns tOEZ Output buffer turn-off delay from OE (see Note 5) 0 15 0 18 0 20 ns NOTES: 4. With ac parameters, it is assumed that tT = 5 ns. 5. tOFF and tOEZ are specified when the output is no longer driven.

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) ’41x800-60 ’41x800-70 ’41x800-80 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, read 110 130 150 ns tWC Cycle time, write 110 130 150 ns tRWC Cycle time, read-write 155 181 205 ns tPC Cycle time, page-mode read or write (see Note 6) 40 45 50 ns tPRWC Cycle time, page-mode read-write 85 96 105 ns tRASP Pulse duration, RAS active, page mode (see Note 7) 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, RAS active, nonpage mode (see Note 7) 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS active (see Note 8) 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS precharge 10 10 10 ns tRP Pulse duration, RAS precharge 40 50 60 ns tWP Pulse duration, write command 10 10 10 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data-in (see Note 9) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CAS precharge 15 18 20 ns tRWL Setup time, write command before RAS precharge 15 18 20 ns tWCS Setup time, write command before CAS active (early-write only) 0 0 0 ns tCSR Setup time, CAS referenced to RAS (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 10 15 15 ns tDH Hold time, data-in (see Note 9) 10 15 15 ns tRAH Hold time, row address 10 10 10 ns tRCH Hold time, read command referenced to CAS (see Note 10) 0 0 0 ns tRRH Hold time, read command referenced to RAS (see Note 10) 0 0 0 ns tWCH Hold time, write command during CAS active (early-write only)10 15 15 ns tRHCP Hold time, RAS active from CAS precharge 35 40 45 ns tOEH Hold time, OE command 15 18 20 ns tROH Hold time, RAS referenced to OE 10 10 10 ns NOTES: 4. With ac parameters, it is assumed that tT = 5 ns. 6. To ensure tPC min, tASC should be ≥ to tCP . 7. In a read-write cycle, tRWD and tRWL must be observed. 8. In a read-write cycle, tCWD and tCWL must be observed. 9. Referenced to the later of CAS or W in write operations 10. Either tRRH or tRCH must be satisfied for a read cycle.

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NOTE 11: The maximum value is specified only to ensure access time. NOTE A: C L includes probe and fixture capacitance. Figure 1. Load Circuits for Timing Parameters

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 2. Read-Cycle Timing

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Figure 3. Early-Write-Cycle Timing

Figure 4. Write-Cycle Timing

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NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 5. Read-Write-Cycle Timing

† Access time is tCPA -, tCAC -, or tAA -dependent. NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Enhanced-Page-Mode Read-Cycle Timing

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NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 7. Enhanced-Page-Mode Early-Write-Cycle Timing

NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 8. Enhanced-Page-Mode Write-Cycle Timing

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† Output can go from the high-impedance state to an invalid-data state prior to the specified access time. NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated. Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing

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Figure 12. Hidden-Refresh-Cycle (Read) Timing

Figure 13. Hidden-Refresh-Cycle (Write) Timing

TMS416800, TMS417800 2097152-WORD BY 8-BIT HIGH-SPEED DRAMS SMKS883A – OCTOBER 1995 – REVISED MARCH 1996

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DZ (R-PDSO-J28) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 4040094-3/C 4/95 0.128 (3,25) 0.148 (3,76) 0.405 (10,29) 0.395 (10,03) 0.445 (11,30) 0.435 (11,05) Seating Plane 0.380 (9,65) 0.360 (9,14) 0.008 (0,20) NOM 0.032 (0,81) 0.026 (0,66) 0.720 (18,29) 0.730 (18,54) 0.106 (2,69) NOM 0.016 (0,41) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125). device symbolization (TMS416800 illustrated) Package Code -SS TMS416800 DZ Assembly Site Code Lot Traceability Code Year Code Die Revision Code Wafer Fab Code PLLLLYC M Month Code TI W

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