TMS4024

TMS4024 TI | Alldatasheet

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BULLETIN NO, OLS 7512268, MAY 1975, © 64 Words of 9 Bits of Elastic Storage 28-PIN CERAMIC AND PLASTIC one DUAL-IN-LINE PACKAGES © =TTL-Compatibility on All Inputs {Tor View) Including Clocks © 3-State Output Buffers write 1 28 Vop © 3 Control Inputs (Read, Write, Clear) READ 2 27 Voc © DC to 250-kHz Data Rate cLock2 3 28 Vss © Status Outputs (Full, Empty) ouri « 25 INT © Synchronous and Asynchronous Operation ouT2 5 24 IN2 © 2-Cycle (4-us) Throughput ouTs 6 23° INS © Long-Term Data Retention ours 7 22 INA © Output Pins Directly Opposite outs 8 20 INS Corresponding Inputs ouTe ¢ 20 IN6 out7 10 19. IN7 description ours 1 18 Ine The TMS 4024 JC, NC is a firstin, first-out digital outs 12 7 INS storage buffer that will store up to 64 nine-bit words. FULL FLAG 13 16 clock 1 The major components of the device include a9 x 64 EMPTY FLAG 14 15 CLEAR dynamic RAM, three shift counters, and comparison and control logic. A RAM-type organization results in minimal ripple-through time. Data written at the input when the RAM is empty is available at the output two clock cycles later. The input and output are completely independent of each other. Input and output timing can be dependent on the clock timing (synchronous mode) or can be operated independently (asynchronous mode). The dynamic RAM requires two-phase continuous clocking at a specified minimum frequency. The clocks can be driven directly from TTL logic. Low-threshold, thick-oxide, MOS p-channel enhancement-type technology is employed to allow interfacing with TTL circuits without external components, The TMS 4024 is suitable for many applications as an interface between systems clocked at different speeds and in keyboard buffers, data concentrators, etc, This device is offered in 28-pin dual-in-line ceramic (JC suffix) and plastic (NC suffix) packages designed for insertion in mounting-hole rows on 600-mil centers. The TMS 4024 is characterized for operation from —25°C to 85°C. operation (refer to diagram “basic internal operation’) The TMS 4024 will process data at any desired rate from de to one-half the continuous clock frequency with every other cycle used for automatic refresh. At a nominal 500-kHz clock rate the maximum data rate is 250 kHz. Data is processed in parallel format, word by word. Writing and reading may be done either synchronously or asynchronously in relation to the clocks. Asynchronous operation is limited to data rates of less than one-third of the clock frequency, Read and write commands must have a minimum separation of one clock cycle. A positive-going transition at the read or write input is recognized as a command and must occur a minimum time before the rise of clock 2. A write command causes the data present at the input to be transferred into the buffer. Data-in must be valid for the period during which clock 2 is low. For asynchronous operation, data-in must be valid for two periods after a write command is given because a write command may be given at any time in relation to the clock. acre 378 TEXAS INSTRUMENTS 147 INCORPORATED

—_— ee operation (continued) If both read and write inputs are brought to a high logic level, the read and write operations are disabled and the data outputs float. The data present in the RAM is retained while the read and write operations are disabled. Acclear command will clear all contents of the digital storage buffer, except for the output latches. When the clear input is brought to a high level, it invalidates all other commands. Completion of a clear operation is detected by a high level at the empty status output. The clear command should be synchronized with clock 2. Status outputs (empty and full) are provided to avoid invalid operation and to facilitate cascading of the device. A high level at the full status output invalidates write commands and a high level at the empty status output invalidates read commands, functional block diagram DATA INPUTS /—_—ravainruts Nt IN2 INS IN@ INS ING IN7 ING IND a eT DECODE Fre ze RIVERS beTECTOR| jg Pa AG aE clock 1 3 33 rH ] co (16) LEAR ( © waite gl 2 oxsznam fo |_| ee reap 2 9 & 2 L_| om BE aes —_— = cLock 2 83 a a) purrer |} EMPTY ourrur BUFFERS Q1_02 03 04 05 06 07 08 03 DATA ouTPuTS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vpp (see Note 1) Ce ce . =15V t00.3V Supply voltage, Vgg (see Note1) - - ee ee . ce -20V 10 0.3 V Clock input voltage range (see Note 1) . . oo we . oo -15V t00.3V Data input voltage range (see Note 1) . ee ee woe ee ee 1S V 1003 Operating free-air temperature range. tee toe . woe 25°C to 85°C Pa a telihieee ) 375

148 TEXAS INSTRUMENTS

TMS 4024 JC, NC

9 X 64 DIGITAL STORAGE BUFFER (FIFO)

recommended operating conditions PARAMETER _ [MIN Nom wax _TuNiT ] Supply voltage, Vop lsee Note 2) [=475 8525 |v | [Supply voltae, Vss Gee Note2)—C* C8 High-level input voltage, all inputs including clocks, Vip (eee Nove 3) [eta ww iat ati scons Vy aston) {as —"g [Glock pubersetimetigy [Glock pulse fal ime, fig) 8880s] [Clock-t pulsewidth twin) | a OO [Clock:2 pulsewidth, twieg) | 700000 [Feed pulse widths twieg) 9002000 [Wie pave widths wwe 00000 [Gear pulsewidth tied) irr | [Delay time, clock 1 to clock 2 tgigtga) CS OSCSCS~wd [Delay time, clock 2toclockVtgozer) | 80s [Delay time, clock 2 0 clock Vplusclock-t pulie width aigzontwiet) | 1000s } 3 [Deley tine,readto dock tase) OO | [Delay time, write t6 lock 2, tgiwrg2) 0000 | [Datesewwp ime. tuidey Od [Dewhoidtine, wigs) | [Date input frequency, fipt Si] [Clock trequeneyifg Tt 500 | wn | 5 85 Nores: electrical characteristics under nominal operating conditions, T, = —25°C to 85°C (unless otherwise noted) [You Lowlevel output voltoge [Nou 18mAtweNows) | | A locks Loom tarsewer ee | wesw age supply current from V lcci Graco ee | mow Tem [6 aman Tm including clock All typical values are at Ta = 25°C. notes Typical values of 1DD(ave) AMF IGGiavg) #f@ —60 MA and ~B MA at BEC, each output driving 8 Series 74 TTL load with no resistor in ss 575 TEXAS INSTRUMENTS 149

TMS 4024 JC, NC switching characteristics under nominal operating conditions, Tq = —25°C to 85°C (unless otherwise noted)

1 Series 74 TTL load, [400s

[oe | tPLH 1.5 k®2 in series level flag outputs from clock 2 T All typical values are at Ta = 25°C, timing diagram and voltage waveforms twit) fe eHd(o201) 1 ' 1 cLock 2, 02 if} i (ea f c 4 etd aig) + twiot pony ' 3 | aI0122) Heep pa tal201) lo io! ' T T I f WRITE ke—er-taiwear | ; st ! READ I | tatra2t. 1 ; 1 1 > ttea | 7 DATAIN fd ewe el — ee eee ee thide tsu (da) i ret — a) DATA OUT \\ ] \\ =r PLA 7 Ppa aaa aS FULL h | LH Woo ee PoE EMPTY ‘ : ] WRITE | REFRESH ] READ | REFRESH | NOTE: Timing points are 90% (high) and 10% (low) basic internal operation Sy een Oe en ' [ fl i o | H / \\ fl 1 / \\ t [o-R/W— ojo Previously established ——eps_RAM —efe——_ Addrats counters ————ef-e Next command Jeommands ; address of RAW counters | outputs} shifted to next address, H accepted accepted | Je RAM 9} ;fmpled feFutt and-o| H outputs: On Feae empty ' | outputs I I | I | precharged ‘operation outputs: ' le— RAM outputs become ——o} sampled! ' 1 valid for reading fi fl be Internat OR {tincecnate, ead orwrite| Data written into RAM ratresh signal | starts ~ becomes | | | | me \\ | ust be valid eee 378

150 TEXAS INSTRUMENTS

TMS 4024 JC, NC a) TTL mi2v-sv “5v L TE | asea ! iS | oF sv sv sv osv TTL SNba/74 SERIES Ts 4028 TTL SHEA774 SERIES “1.5 k&2 resistor optional ~ the presence of this resistor helps to reduce power dissipation in the TMS 4024 while driving TTL b) =Mos ) 3 sv =12V-5v “sv =12V-5V TE ld r Ld io rod 1 | 7 eA 5V sv sv sv MOS DRIVE TMS 4026 MOS LOAD ame TYPICAL CHARACTERISTICS PROPAGATION DELAY TIMES FOR FULL OR EMPTY FLAGS FROM CLOCK 2 OR ACCESS TIME FROM SUPPLY CURRENT vs DUTY CYCLE CLOCK 1 vs LOAD CAPACITANCE 60 600 Ta = 25°C, twigth * Wwio2) = 18 Ta = 28°C, Nominal operating conditions | ——— fen 3 . Fr Loan =f 500 i t | < i | | € 0} Jf 100 <a. A DD ‘ oan eo : 0 i—7-—- 3 ool | ; "oe _J B oof | J ame | ~ b= too TeKo teehee Siti ice | 10} pig 100 fe ARC, 5 — oO oO 4 o 1% 2% 3% 4 8650 0 10 % 3 4 50 60 Clock Duty Gycte 6, Pod Cobvcitnes =F NOTE: TTL load, 1.5 KS series resistor oll outputs low; MOS toad, all outputs high. — esse Texas INSTRUMENTS 151 TeXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TNE ost ortice won voir » eatoae, YEAAS 78282 {ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BET ODUCT POSSE