TMS320BC53SPZ

TMS320C5X_16 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 94

Technical content

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Powerful 16-Bit TMS320C5x CPU /C006820-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation /C006825-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation /C0068Single-Cycle 16 × 16-Bit Multiply/Add /C0068224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) /C00682K, 4K, 8K, 16K, 32K × 16-Bit Single-Access On-Chip Program ROM /C00681K, 3K, 6K, 9K × 16-Bit Single-Access On-Chip Program/Data RAM (SARAM) /C00681K Dual-Access On-Chip Program/Data RAM (DARAM) /C0068Full-Duplex Synchronous Serial Port for Coder/Decoder Interface /C0068Time-Division-Multiplexed (TDM) Serial Port /C0068Hardware or Software Wait-State Generation Capability /C0068On-Chip Timer for Control Operations /C0068Repeat Instructions for Efficient Use of Program Space /C0068Buffered Serial Port /C0068Host Port Interface /C0068Multiple Phase-Locked Loop (PLL) Clocking Options (×1, ×2, ×3, ×4, ×5, ×9 Depending on Device) /C0068Block Moves for Data/Program Management /C0068On-Chip Scan-Based Emulation Logic /C0068Boundary Scan /C0068Five Packaging Options – 100-Pin Quad Flat Package (PJ Suffix) – 100-Pin Thin Quad Flat Package (PZ Suffix) – 128-Pin Thin Quad Flat Package (PBK Suffix) – 132-Pin Quad Flat Package (PQ Suffix) – 144-Pin Thin Quad Flat Package (PGE Suffix) /C0068Low Power Dissipation and Power-Down Modes: – 47 mA (2.35 mA/MIP) at 5 V, 40-MHz Clock (Average) – 23 mA (1.15 mA/MIP) at 3 V, 40-MHz Clock (Average) – 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode) – 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode) – 5 mA at 5 V, Clocks Off (IDLE2 Mode) /C0068High-Performance Static CMOS Technology /C0068IEEE Standard 1149.1† Test-Access Port (JTAG)

description

The TMS320C5x generation of the Texas Instruments (TI ) TMS320 digital signal processors (DSPs) is fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the ’C5x ‡ devices. They execute up to 50 million instructions per second (MIPS). The ’C5x devices offer these advantages: /C0068Enhanced TMS320 architectural design for increased performance and versatility /C0068Modular architectural design for fast development of spin-off devices /C0068Advanced integrated-circuit processing technology for increased performance /C0068Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.) /C0068Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation /C0068New static-design techniques for minimizing power consumption and maximizing radiation tolerance Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1996, Texas Instruments Incorporated TI is a trademark of Texas Instruments Incorporated. † IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture ‡ References to ’C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.

2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

package with total pin count. Table 1. Characteristics of the ’C5x Processors † Sixteen of the 64K parallel I/O ports are memory mapped. Pinouts for each package are device-specific.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C50, TMS320LC50, TMS320C51, TMS320LC51, TMS320C53, TMS320LC53 PQ PACKAGE (TOP VIEW) WE DDAV DDAV VSSD VSSD TMS VDDD VDDD TCK VSSD VSSD INT1 INT2 INT3 INT4 NMI DR TDR FSR CLKR VDDA VDDA VSSC VSSC DS IS PS R/ W STRB BR CLKIN2 X2 / CLKIN VDDC VDDC TDO VSSI VSSI FSX TFSX / TFRM DX TDX HOLDA XF CLKOUT1 NC IACK VDDI VDDI 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 DDDV DDDV D10 D11 D12 D13 D14 D15 MP/ MC TRST IAQ SSIV SSIV 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 82 83 DDCV DDCV BIO HOLD READY RS TCLKR TFSR / TADD CLKX TCLKX TOUT EMU1/OFF EMU0 SSCV SSCV SSAV SSAV TDI CLKMD1 A10 A11 A12 A13 A14 A15 DDIV DDIV SSAV SSAV RD NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC CLKMD2 NC NC NC NOTE: NC = No connect (These pins are reserved.)

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Functions for Devices in the PQ Package SIGNAL TYPE DESCRIPTION PARALLEL INTERFACE BUS A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0) D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0) PS , DS, IS O/Z Program, data, and I/O space select outputs, respectively STRB I/O/Z Timing strobe for external cycles and external DMA R/W I/O/Z Read/write select for external cycles and external DMA RD , WE O/Z Read and write strobes, respectively, for external cycles READY I External bus ready/wait-state control input BR I/O/Z Bus request. Arbitrates global memory and external DMA SYSTEM INTERFACE/CONTROL SIGNALS RS I Reset. Initializes device and sets PC to zero MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM HOLD I Puts parallel I/F bus in high-impedance state after current cycle HOLDA O/Z Hold acknowledge. Indicates external bus in hold state XF O/Z External flag output. Set/cleared through software BIO I I/O branch input. Implements conditional branches TOUT O/Z Timer output signal. Indicates output of internal timer IAQ O/Z Instruction acquisition signal IACK O/Z Interrupt acknowledge signal INT1–INT4 I External interrupt inputs NMI I Nonmaskable external interrupt SERIAL PORT INTERFACE (SPI) DR I Serial receive-data input DX O/Z Serial transmit-data output. In high-impedance state when not transmitting CLKR I Serial receive-data clock input CLKX I/O/Z Serial transmit-data clock. Internal or external source FSR I Serial receive-frame-synchronization input FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source TDM SERIAL-PORT INTERFACE TDR I TDM serial receive-data input TDX O/Z TDM serial transmit-data output. In high-impedance state when not transmitting TCLKR I TDM serial receive-data clock input TCLKX I/O/Z TDM serial transmit-data clock. Internal or external source TFSR / TADD I/O/Z TDM serial receive-frame-synchronization input. In the TDM mode, TFSR/TADD is used to output/ input the address of the port. TFSX /TFRM I TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode, TFSX/TFRM becomes TFRM, the TDM frame synchronization. LEGEND: I = Input O = Output Z = High impedance

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for Devices in the PQ Package (Continued) EMULATION/IEEE STANDARD 1149.1 TEST ACCESS PORT (TAP) TDI I TAP scan data input TDO O/Z TAP scan data output TMS I TAP mode select input TCK I TAP clock input TRST I TAP reset (with pulldown resistor). Disables TAP when low EMU0 I/O/Z Emulation control 0. Reserved for emulation use EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low CLOCK GENERATION AND CONTROL X1 O Oscillator output X2/CLKIN I Clock/oscillator input CLKIN2 I Clock input CLKMD1, CLKMD2 I Clock-mode select inputs CLKOUT1 O/Z Device system-clock output POWER SUPPLY CONNECTIONS VDDA S Supply connection, address-bus output VDDD S Supply connection, data-bus output VDDC S Supply connection, control output VDDI S Supply connection, internal logic VSSA S Supply connection, address-bus output VSSD S Supply connection, data-bus output VSSC S Supply connection, control output VSSI S Supply connection, internal logic LEGEND: I = Input O = Output S = Supply Z = High impedance

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64SSD V SSD V D7 V D6 CLKOUT1 D5 XF D4 HOLDA D3 BDX D2 DX D1 HD7 D0 BFSX TMS HD6 DDD DDD TCK CLKMD2 SSD SSD INT1 INT2 TDO INT3 INT4 NMI X2/CLKIN CLKMD3 STRB R/ WDR BDR HD3 FSR IS CLKR PS DDA HD2 DDA HAS DDC DDI DDI V V V V V V V V TMS320LC57 PBK PACKAGE ( TOP VIEW ) FSX HD5 HD4 V SSI V SSI V DDC BR DS V V SSC SSC VDDI HBIL HR/ W HCNTL0 HCNTL1 VDDC

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for the TMS320LC57 in the PBK Package SIGNAL TYPE DESCRIPTION PARALLEL INTERFACE BUS A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0) D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0) PS , DS, IS O/Z Program, data, and I/O space select outputs, respectively STRB I/O/Z Timing strobe for external cycles and external DMA R/W I/O/Z Read/write select for external cycles and external DMA RD , WE O/Z Read and write strobes, respectively, for external cycles READY I External bus ready/wait-state control input BR I/O/Z Bus request. Arbitrates global memory and external DMA SYSTEM INTERFACE/CONTROL SIGNALS RS I Reset. Initializes device and sets PC to zero MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM HOLD I Puts parallel I/F bus in high-impedance state after current cycle HOLDA O/Z Hold acknowledge. Indicates external bus in hold state XF O/Z External flag output. Set/cleared through software BIO I I/O branch input. Implements conditional branches TOUT O/Z Timer output signal. Indicates output of internal timer IAQ O/Z Instruction acquisition signal INT1–INT4 I External interrupt inputs NMI I Nonmaskable external interrupt SERIAL PORT INTERFACE DR I Serial receive-data input DX O/Z Serial transmit-data output. In high-impedance state when not transmitting CLKR I Serial receive-data clock input CLKX I/O/Z Serial transmit-data clock. Internal or external source FSR I Serial receive-frame-synchronization input FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source HOST PORT INTERFACE (HPI) HCNTL0 I HPI mode control 1 HCNTL1 I HPI mode control 2 HINT O/Z Host interrupt HDS1 I HPI data strobe 1 HDS2 I HPI data strobe 2 HR/W I HPI read/write strobe HAS I HPI address strobe HRDY O/Z HPI ready signal HCS I HPI chip select HBIL I HPI byte identification input HD0–HD7 I/O/Z HPI data bus LEGEND: I = Input O = Output Z = High impedance

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Functions for the TMS320LC57 in the PBK Package (Continued) SIGNAL TYPE DESCRIPTION BUFFERED SERIAL PORT BDR I BSP receive data input BDX O/Z BSP transmit data output; in high-impedance state when not transmitting BCLKR I BSP receive-data clock input BCLKX I/O/Z BSP transmit-data clock; internal or external source BFSR I BSP receive frame-synchronization input BFSX I/O/Z BSP transmit frame-synchronization signal; internal or external source EMULATION/JTAG INTERFACE TDI I JTAG-test-port scan data input TDO O/Z JTAG-test-port scan data output TMS I JTAG-test-port mode select input TCK I JTAG-port clock input TRST I JTAG-port reset (with pull-down resistor). Disables JTAG when low EMU0 I/O/Z Emulation control 0. Reserved for emulation use EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low CLOCK GENERATION AND CONTROL X1 O Oscillator output X2/CLKIN I Clock input CLKMD1, CLKMD2, CLKMD3 I Clock-mode select inputs CLKOUT1 O/Z Device system-clock output POWER SUPPLY CONNECTIONS VDDA S Supply connection, address-bus output VDDD S Supply connection, data-bus output VDDC S Supply connection, control output VDDI S Supply connection, internal logic VSSA S Supply connection, address-bus output VSSD S Supply connection, data-bus output VSSC S Supply connection, control output VSSI S Supply connection, internal logic LEGEND: I = Input O = Output S = Supply Z = High impedance

† See Table 2 for device-specific pinouts. Table 2. Device-Specific Pinouts for the PZ Package

5 TCLKX VSSI CLKX2 BCLKX

7 TFSR/TADD VSSI FSR2 BFSR

8 TCLKR VSSI CLKR2 BCLKR

47 TDR VSSI DR2 BDR

83 CLKIN2 CLKIN2 CLKIN2 CLKMD3

92 TFSX/TFRM VSSI FSX2 BFSX

94 TDX NC DX2 BDX

‡ Pin names beginning with “B” indicate signals on the buffered serial port (BSP).

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Functions for Devices in the PZ Package SIGNAL TYPE DESCRIPTION PARALLEL INTERFACE BUS A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0) D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0) PS , DS, IS O/Z Program, data, and I/O space select outputs, respectively STRB I/O/Z Timing strobe for external cycles and external DMA R/W I/O/Z Read/write select for external cycles and external DMA RD , WE O/Z Read and write strobes, respectively, for external cycles READY I External bus ready/wait-state control input BR I/O/Z Bus request. Arbitrates global memory and external DMA SYSTEM INTERFACE/CONTROL SIGNALS RS I Reset. Initializes device and sets PC to zero MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM HOLD I Puts parallel I/F bus in high-impedance state after current cycle HOLDA O/Z Hold acknowledge. Indicates external bus in hold state XF O/Z External flag output. Set/cleared through software BIO I I/O branch input. Implements conditional branches TOUT O/Z Timer output signal. Indicates output of internal timer INT1–INT4 I External interrupt inputs NMI I Nonmaskable external interrupt SERIAL PORT INTERFACE DR, DR1, DR2 I Serial receive-data input DX, DX1, DX2 O/Z Serial transmit-data output. In high-impedance state when not transmitting CLKR, CLKR1, CLKR2 I Serial receive-data clock input CLKX, CLKX1, CLKX2 I/O/Z Serial transmit-data clock. Internal or external source FSR, FSR1, FSR2 I Serial receive-frame-synchronization input FSX, FSX1, FSX2 I/O/Z Serial transmit-frame-synchronization signal. Internal or external source BUFFERED SERIAL PORT (BSP) (SEE NOTE 1) BDR I BSP receive data input BDX O/Z BSP transmit data output; in high-impedance state when not transmitting BCLKR I BSP receive-data clock input BCLKX I/O/Z BSP transmit-data clock; internal or external source BFSR I BSP receive frame-synchronization input BFSX I/O/Z BSP transmit frame-synchronization signal; internal or external source LEGEND: I = Input O = Output Z = High impedance NOTE 1: ’LC56 devices only

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for Devices in the PZ Package (Continued) SIGNAL TYPE DESCRIPTION TDM SERIAL PORT INTERFACE TDR I TDM serial receive-data input TDX O/Z TDM serial transmit-data output. In high-impedance state when not transmitting TCLKR I TDM serial receive-data clock input TCLKX I/O/Z TDM serial transmit-data clock. Internal or external source TFSR / TADD I/O/Z TDM serial receive-frame-synchronization input. In the TDM mode, TFSR/TADD is used to output/ input the address of the port TFSX /TFRM I TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode, TFSX/TFRM becomes TFRM, the TDM frame sync. EMULATION/JTAG INTERFACE TDI I JTAG-test-port scan data input TDO O/Z JTAG-test-port scan data output TMS I JTAG-test-port mode select input TCK I JTAG-port clock input TRST I JTAG-port reset (with pull-down resistor). Disables JTAG when low EMU0 I/O/Z Emulation control 0. Reserved for emulation use EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low CLOCK GENERATION AND CONTROL (SEE NOTE 2) X1 O Oscillator output X2/CLKIN I Clock/oscillator input (PLL clock input for ’C56) CLKIN2 I Clock input (PLL clock input for ’C50, ’C51, ’C52, ’C53, ’C53S) CLKMD1, CLKMD2, CLKMD3 I Clock-mode select inputs CLKOUT1 O/Z Device system-clock output POWER SUPPLY CONNECTIONS VDDA S Supply connection, address-bus output VDDD S Supply connection, data-bus output VDDC S Supply connection, control output VDDI S Supply connection, internal logic VSSA S Supply connection, address-bus output VSSD S Supply connection, data-bus output VSSC S Supply connection, control output VSSI S Supply connection, internal logic LEGEND: I = Input O = Output S = Supply Z = High impedance NOTE 2: CLKIN2 pin is replaced by CLKMD3 pin on ’LC56 devices.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 SSA DDI TDI CLKMD1 A11 A12 A13 A14 A10 A15 MP/ MC D10 D11 D12 D13 D14 V TRST CLKX HOLD READY BIO RS V V TOUT V V D15 TMS320C52, TMS320LC52 PJ PACKAGE (TOP VIEW) DDA SSI SSI SSI SSC SSI EMU1/OFF EMU0 VDDC VDDC VDDI VDDI CLKOUT1 XF HOLDA NC DX VSSI FSX CLKMD2 VSSI VSSI TDO VDDC X2 / CLKIN CLKIN2 BR STRB R/ W PS IS DS VSSC WE RD V V V NOTE: NC = No connect (These pins are reserved.)

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package SIGNAL TYPE DESCRIPTION PARALLEL INTERFACE BUS A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0) D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0) PS , DS, IS O/Z Program, data, and I/O space select outputs, respectively STRB I/O/Z Timing strobe for external cycles and external DMA R/W I/O/Z Read/write select for external cycles and external DMA RD , WE O/Z Read and write strobes, respectively, for external cycles READY I External bus ready/wait-state control input BR I/O/Z Bus request. Arbitrates global memory and external DMA SYSTEM INTERFACE/CONTROL SIGNALS RS I Reset. Initializes device and sets PC to zero MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM HOLD I Puts parallel I/F bus in high-impedance state after current cycle HOLDA O/Z Hold acknowledge. Indicates external bus in hold state XF O/Z External flag output. Set/cleared through software BIO I I/O branch input. Implements conditional branches TOUT O/Z Timer output signal. Indicates output of internal timer INT1–INT4 I External interrupt inputs NMI I Nonmaskable external interrupt SERIAL PORT INTERFACE DR I Serial receive-data input DX O/Z Serial transmit-data output. In high-impedance state when not transmitting CLKR I Serial receive-data clock input CLKX I/O/Z Serial transmit-data clock. Internal or external source FSR I Serial receive-frame-synchronization input FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source EMULATION/JTAG INTERFACE TDI I JTAG-test-port scan data input TDO O/Z JTAG-test-port scan data output TMS I JTAG-test-port mode select input TCK I JTAG-port clock input TRST I JTAG-port reset (with pulldown resistor). Disables JTAG when low EMU0 I/O/Z Emulation control 0. Reserved for emulation use EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low LEGEND: I = Input O = Output Z = High impedance

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package (Continued) SIGNAL TYPE DESCRIPTION CLOCK GENERATION AND CONTROL X1 O Oscillator output X2/CLKIN I Clock/oscillator input CLKIN2 I Clock input (PLL clock input for ’C52, ’LC52) CLKMD1, CLKMD2 I Clock-mode select inputs CLKOUT1 O/Z Device system-clock output POWER SUPPLY CONNECTIONS VDDA S Supply connection, address-bus output VDDD S Supply connection, data-bus output VDDC S Supply connection, control output VDDI S Supply connection, internal logic VSSA S Supply connection, address-bus output VSSD S Supply connection, data-bus output VSSC S Supply connection, control output VSSI S Supply connection, internal logic LEGEND: I = Input O = Output S = Supply

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C57S, TMS320LC57S PGE PACKAGE (TOP VIEW) TDO WE HD1 RD HD0 HRDY VDDA A15 NC A14 A13 A12 NC A11 A10 CLKMD1 VSSA VSSA TDI HDS1 HDS2 VDDI VDDI NC NC VSSA HCS HINT EMU0 NC EMU1/OFF VSSC VSSC TOUT BCLKX CLKX VDDC BFSR BCLKR RS READY HOLD NC BIO VDDC VDDC IAQ TRST VSSI VSSI MP/MC D15 D14 D13 NC D12 D11 D10 NC VDDD VDDD 144 143 142 CLKOUT1 141 XF 140 139 BDX 138 137 136 BFSX 135 134 133 HD5 132 CLKMD2 131 130 129 128 127 126 125 X2/CLKIN 124 CLKMD3 123 122 HD3 121 STRB 120 119 PS 118 117 116 115 114 113 112 108 107 106 105 104 103 102 101 100 HCNTL0 TMS NMI HR/W INT2 INT3 INT4 DR BDR FSR HAS HCNTL1 111 NC 110 109 NC TCK HD6 DX VSSI HD4 VDDC DDDV CLKR DDAV HBIL SSDV INT1 NC VDDC VDDI V HOLDA HD7 FSX VSSI BR R/W IS DS HD2 VSSC VSSC NC NC NC SSDV DDI SSDV DDDV SSDV DDAV NOTE: NC = No connect (These pins are reserved.) NC NC ADVANCE INFORMATION

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Functions for the TMS320C57S, TMS320LC57S in the PGE Package SIGNAL TYPE DESCRIPTION PARALLEL INTERFACE BUS A0–A15 I/O/Z 16-bit external address bus (MSB: A15, LSB: A0) D0–D15 I/O/Z 16-bit external data bus (MSB: D15, LSB: D0) PS , DS, IS O/Z Program, data, and I/O space select outputs, respectively STRB I/O/Z Timing strobe for external cycles and external DMA R/W I/O/Z Read/write select for external cycles and external DMA RD , WE O/Z Read and write strobes, respectively, for external cycles READY I External bus ready/wait-state control input BR I/O/Z Bus request. Arbitrates global memory and external DMA SYSTEM INTERFACE/CONTROL SIGNALS RS I Reset. Initializes device and sets PC to zero MP/MC I Microprocessor/microcomputer mode select. Enables internal ROM HOLD I Puts parallel I/F bus in high-impedance state after current cycle HOLDA O/Z Hold acknowledge. Indicates external bus in hold state XF O/Z External flag output. Set/cleared through software BIO I I/O branch input. Implements conditional branches TOUT O/Z Timer output signal. Indicates output of internal timer IAQ O/Z Instruction acquisition signal INT1–INT4 I External interrupt inputs NMI I Nonmaskable external interrupt SERIAL PORT INTERFACE (SPI) DR I Serial receive-data input DX O/Z Serial transmit-data output. In high-impedance state when not transmitting CLKR I Serial receive-data clock input CLKX I/O/Z Serial transmit-data clock. Internal or external source FSR I Serial receive-frame-synchronization input FSX I/O/Z Serial transmit-frame-synchronization signal. Internal or external source HOST PORT INTERFACE (HPI) HCNTL0 I HPI mode control 1 HCNTL1 I HPI mode control 2 HINT O/Z Host interrupt HDS1 I HPI data strobe 1 HDS2 I HPI data strobe 2 HR/W I HPI read/write strobe HAS I HPI address strobe HRDY O/Z HPI ready signal HCS I HPI chip select HBIL I HPI byte identification input HD0–HD7 I/O/Z HPI data bus LEGEND: I = Input O = Output Z = High impedance

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for the TMS320C57S, TMS320LC57S in the PGE Package (Continued) SIGNAL TYPE DESCRIPTION BUFFERED SERIAL PORT BDR I BSP receive data input BDX O/Z BSP transmit data output; in high-impedance state when not transmitting BCLKR I BSP receive-data clock input BCLKX I/O/Z BSP transmit-data clock; internal or external source BFSR I BSP receive frame-synchronization input BFSX I/O/Z BSP transmit frame-synchronization signal; internal or external source EMULATION/JTAG INTERFACE TDI I JTAG-test-port scan data input TDO O/Z JTAG-test-port scan data output TMS I JTAG-test-port mode select input TCK I JTAG-port clock input TRST I JTAG-port reset (with pulldown resistor). Disables JTAG when low EMU0 I/O/Z Emulation control 0. Reserved for emulation use EMU1/OFF I/O/Z Emulation control 1. Puts outputs in high-impedance state when low CLOCK GENERATION AND CONTROL X1 O Oscillator output X2/CLKIN I PLL clock input CLKMD1, CLKMD2, CLKMD3 I Clock-mode select inputs CLKOUT1 O/Z Device system-clock output POWER SUPPLY CONNECTIONS VDDA S Supply connection, address-bus output VDDD S Supply connection, data-bus output VDDC S Supply connection, control output VDDI S Supply connection, internal logic VSSA S Supply connection, address-bus output VSSD S Supply connection, data-bus output VSSC S Supply connection, control output VSSI S Supply connection, internal logic LEGEND: I = Input O = Output S = Supply Z = High impedance

18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

as shown in the functional block diagram. Table 3 explains the symbols that are used in the functional block diagram. Table 3. Symbols Used in Functional Block Diagram

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram Data Bus Program Bus Shifter(0–7) D15–D0 RBIT A15–A0 DBMR(16) MUX 16 16 ACCB(32) ACCL(16)ACCH(16)C ALU(32) SFR(0–16) MUX MUX SFL(0–16) MUX PREG(32) Multiplier TREG0(16) MUX 1616 MUX B1 (512x16) B2 (32x16) DARAM B0 (512x16) DARAM MUX from IR

7 LSB

DP(9) MUX ’C50 9K ’C51 1K ’C53 3K ’C56 6K ’C57 6K SARAM ARAU(16) MUX ARB(3) ARP(3) Program Bus 1616 CBSR2(16) CBSR1(16) AR7(16) AR6(16) AR5(16) AR3(16) AR2(16) AR1(16) AR0(16) ARCR(16) INDX(16) HDS (1–1) HRDY HAS HR/W HINT HPI HPICL HD7 HD0 HBIL HCNTL0 HCNTL1 HCSHPIAL HPICH HPIAH TOUT TCR PRD TIM Timer BDX BCLKX BDR BCLKR BFSR DFSX DXR AXR(11) BKX(11) DRR ARR(11) BKR(11) BSP TDM TCSR(8) TRTA TRAD(16) TDR TCLKX TFRM TADD TCLKR TRCV TDXR TSPC TDX CLKX2 FSX2 DX2 FSR2 CLKR2 DR2 SPC DXR DRR Serial Port 2 CLKR FSR DR FSX CLKX DX DRR DXR SPC Serial Port 1 TREG2(4) TREG1(5) BRCR(16) GREG(16) IFR(16) IMR(16) RPTC(16) PMST(16) ST1(16) ST0(16) BMAR(16) IR(16) PFC(16) MCS(16) Instruction Address 32K’C57 32K’C56 16K’C53 4K’C52 8K’C51 2K’C50 ROMProgram PASR(16) Compare PAER(16) (8x16) Stack PC(16) MUX NMI WE RD CLKIN2/CLKMD3 X2/CLKIN CLKOUT1 4INT(1–4) MP/MC IACK RS HOLDA HOLD XF BR READY STRB RW PS DS IS CLKMD2 CLKMD1 Control Data Bus Program Bus Data Bus Data Bus CBER2(16) CBER1(16) AR4(16) BO IAQ MUX MUX Data/Prog Data/Prog SFL (–6, 0, 1, 4) PLU (16) Data † Not available on all devices (see Table 1). NOTES: A. Signals in shaded text are not available on 100-pin QFP packages. B. Symbol descriptions appear in Table 3.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

The 32-bit ALU and accumulator implement a wide range of arithmetic and logical functions, the majority of which execute in a single cycle. The ALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform Boolean operations, facilitating the bit manipulation ability required of a high-speed controller. One input to the ALU always is supplied by the accumulator, and the other input can be furnished from the product register (PREG) of the multiplier, the accumulator buffer (ACCB), or the output of the scaling shifter [which has been read from data memory or from the accumulator (ACC)]. After the ALU performs the arithmetic or logical operation, the result is stored in the ACC where additional operations, such as shifting, can be performed. Data input to the ALU can be scaled by the scaling shifter. The 32-bit ACC is split into two 16-bit segments for storage in data memory. Shifters at the output of the ACC provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the ACC remain unchanged. When the postscaling shifter is used on the high word of the ACC (bits 31–16), the most significant bits (MSBs) are lost and the least significant bits (LSBs) are filled with bits shifted in from the low word (bits 15–0). When the postscaling shifter is used on the low word, the LSBs are filled with zeros. The ’C5x supports floating-point operations for applications requiring a large dynamic range. By performing left shifts, the normalization instruction (NORM) is used to normalize fixed-point numbers contained in the ACC. The four bits of the TREG1 define a variable shift through the scaling shifter for the ADDT/LACT/SUBT instructions (add to/load to/subtract from ACC with shift specified by TREG1). These instructions are useful in denormalizing a number (converting from floating point to fixed point). They are also useful for executing an automatic gain control (AGC) going into a filter. The single-cycle 1-bit to 16-bit right shift of the ACC efficiently aligns the ACC’s contents. This, coupled with the 32-bit temporary buffer on the ACC, enhances the effectiveness of the ALU in extended-precision arithmetic. The ACCB provides a temporary storage place for a fast save of the ACC. The ACCB also can be used as an input to the ALU. The minimum or maximum value in a string of numbers is found by comparing the contents of the ACCB with the contents of the ACC. The minimum or maximum value is placed in both registers, and, if the condition is met, the carry bit (C) is set to 1. The minimum and maximum functions are executed by the CRLT and CRGT instructions, respectively. scaling shifters The ’C5x provides a scaling shifter that has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU. This scaling shifter produces a left shift of 0 to 16 bits on the input data. The shift count is specified by a constant embedded in the instruction word or by the value in TREG1. The LSBs of the output are filled with zeros; the MSBs may be either filled with zeros or sign extended, depending upon the value of the sign-extension mode (SXM) bit of status register ST1. The ’C5x also contains several other shifters that allow it to perform numerical scaling, bit extraction, extended-precision arithmetic, and overflow prevention. These shifters are connected to the output of the product register and the ACC. parallel logic unit The parallel logic unit (PLU) is a second logic unit, additional to the main ALU, that executes logic operations on data without affecting the contents of the ACC. The PLU provides the bit-manipulation ability required of a high-speed controller and simplifies control/status register operations. The PLU provides a direct logic operation path to data memory space and can set, clear, test, or toggle multiple bits directly in a data memory location, a control/status register, or any register that is mapped into data memory space.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 16 × 16-bit parallel multiplier The ’C5x uses a 16 × 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation in the multiplier. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated with the multiplier: TREG0, a 16-bit temporary register that holds one of the operands for the multiplier, and PREG, the 32-bit product register that holds the product. Four product shift modes (PM) are available at the PREG’s output. These shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode. The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers (MPY). A 4-bit shift is used in conjunction with the MPY instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. Finally, the output of PREG can, instead, be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. The load-TREG0 (LT) instruction normally loads TREG0 to provide one operand (from the data bus), and the MPY instruction provides the second operand (also from the data bus). A multiplication also can be performed with a short or long immediate operand by using the MPY instruction with an immediate operand. A product is obtained every two cycles except when a long immediate operand is used. Four multiply/accumulate instructions (MAC, MACD, MADD, and MADS as defined in Table 7) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations is transferred to the multiplier during each cycle through the program and data buses. This facilitates single-cycle multiply/accumulates when used with repeat (RPT and RPTZ) instructions. In these instructions, the coefficient addresses are generated by the PC, while the data addresses are generated by the ARAU. This allows the repeated instruction to access the values sequentially from the coefficient table and step through the data in any of the indirect addressing modes. The RPTZ instruction also clears the accumulator and the product register to initialize the multiply/accumulate operation. The MACD and MADD instructions, when repeated, support filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to eliminate the oldest sample. Circular addressing with MAC and MADS instructions also can be used to support filter implementation. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The ’C5x provides a register file containing eight auxiliary registers (AR0–AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7, designated AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of these registers can be stored in data memory or used as inputs to the central arithmetic logic unit (CALU). These registers are accessible as memory-mapped locations within the ’C5x data-memory space. The auxiliary register file (AR0–AR7) is connected to the auxiliary register arithmetic unit (ARAU). The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing can be performed either by ±1 or by the contents of the INDX register. As a result, accessing tables of information does not require the CALU for address manipulation; thus, the CALU is free for other operations in parallel.

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

types of memory available on each device are shown in Table 1. I/O locations with two-word instructions. Two-word instructions allow access to the full 64K words of I/O space. these addresses are located in the device’s external program-memory space. ROM. This feature can be used to provide security for proprietary algorithms. the code is transferred, the boot loader releases control to the program for execution. The ’C5x devices provide two types of RAM: single-access RAM (SARAM) and dual-access RAM (DARAM). improve code performance. Table 4 shows the sizes of available SARAM on the applicable ’C5x devices. Table 4. SARAM Block Sizes

external program memory into on-chip RAM and then executed. When using on-chip RAM, ROM, or high-speed external memory, the ’C5x runs at full speed with no wait states. cycle. Externally, the READY line can be used to interface the ’C5x to slower, less expensive external memory. Figure 1. TMS320C50 and TMS320LC50 Memory Map

24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 2. TMS320C51 and TMS320LC51 Memory Map Figure 3. TMS320C52 and TMS320LC52 Memory Map

0800 On-Chip SARAM

Figure 4. TMS320C53, TMS320C53S, TMS320LC53, and TMS320LC53S Memory Map

26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 5. TMS320LC56 Memory Map

Figure 6. TMS320LC57 Memory Map

28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 7. TMS320C57S Memory Map

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 interrupts and subroutines The ’C5x implements four general-purpose interrupts, INT4–INT1, along with reset (RS) and the nonmaskable interrupt (NMI) which are available for external devices to request the attention of the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software-interrupt (TRAP , INTR, and NMI) instructions. Interrupts are prioritized with RS having the highest priority, followed by NMI , and INT4 having the lowest priority. Additionally, any interrupt except RS and NMI can be masked individually with a dedicated bit in the interrupt mask register (IMR) and can be cleared, set, or tested using its own dedicated bit in the interrupt flag register (IFR). The reset and NMI functions are not maskable. All interrupt vector locations are on two-word boundaries so that branch instructions can be accommodated in those locations. While normally located at program memory address 0, the interrupt vectors can be remapped to the beginning of any 2K-word page in program memory by modifying the contents of the interrupt vector pointer (IPTR) located in the PMST status register. A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle instruction, the interrupt is not processed until the instruction completes execution. This mechanism applies to instructions that are repeated (using the RPT instruction) and to instructions that become multicycle because of wait states. Each time an interrupt is serviced or a subroutine is entered, the PC is pushed onto an internal hardware stack, providing a mechanism for returning to the previous context. The stack contains eight locations, allowing interrupts or subroutines to be nested up to eight levels deep. In addition to the eight-level hardware PC stack, eleven key CPU registers are equipped with an associated single-level stack or shadow register into which the registers’ contents are saved upon servicing an interrupt. The contents are restored into their particular CPU registers once a return-from-interrupt instruction (RETE or RETI) is executed. The registers that have the shadow-register feature include the ACC and buffer, product register, status registers, and several other key CPU registers. The shadow-register feature allows sophisticated context save and restore operations to be handled automatically in cases where nested interrupts are not required or if interrupt servicing is performed serially. power-down modes The ’C5x implements several power-down modes in which the ’C5x core enters a dormant state and dissipates considerably less power. A power-down mode is invoked either by executing the IDLE/IDLE2 instructions or by driving the HOLD input low. When the HOLD signal initiates the power-down mode, on-chip peripherals continue to operate; this power-down mode is terminated when HOLD goes inactive. While the ’C5x is in a power-down mode, all internal contents are maintained; this allows operation to continue unaltered when the power-down mode is terminated. All CPU activities are halted when the IDLE instruction is executed, but the CLKOUT1 pin remains active. The peripheral circuits continue to operate, allowing peripherals such as serial ports and timers to take the CPU out of its powered-down state. A power-down mode, when initiated by an IDLE instruction, is terminated upon receipt of an interrupt. The IDLE2 instruction is used for a complete shutdown of the core CPU as well as all on-chip peripherals. In IDLE2, the power is reduced significantly because the entire device is stopped. The power-down mode is terminated by activating any of the external interrupt pins (RS , NMI, INT1, INT2, INT3, and INT4) for at least five machine cycles. bus-keeper circuitry (TMS320LC56/’C57S/’LC57) The TMS320LC56/’C57S/’LC57 devices provide built-in bus keeper circuitry which holds the last state driven on the data bus by either the DSP or an external device after the bus is no longer being driven. This capability prevents excess power consumption caused by a floating bus, thus allowing optimization of power consumption without the need for external pullup resistors.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

The ’C5x supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along with the PS , DS, and IS space select signals, allow addressing of 64K 16-bit words in each of the three spaces. I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the processor’s external address and data buses in the same manner as memory-mapped devices. The ’C5x external parallel interface provides various control signals to facilitate interfacing to the device. The R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal provides a timing reference for all external cycles. For convenience, the device also provides the RD and the WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to the ’C5x. Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are made with slower devices, the ’C5x processor waits until the other device completes its function and signals the processor via the READY line. Once a ready indication is provided back to the ’C5x from the external device, execution continues. The bus request (BR ) signal is used in conjunction with the other ’C5x interface signals to arbitrate external global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted at the beginning of the access. When an external global-memory device receives the the bus request, the external device responds by asserting the READY signal after the global memory access is arbitrated and the global access is completed. external direct-memory access (DMA) capability All ’C5x devices with single-access RAM offer a unique feature allowing another processor to read and write to the ’C5x internal memory. To initiate a read or write operation to the ’C5x single-access RAM, the host or master processor requests a hold state on the DSP’s external bus. When acknowledged with HOLDA , the host can request access to the internal bus by pulling the BR signal low. Unlike the hold mode, which allows the current operation to complete and allows CPU operation to continue (if status bit HM=0), a BR-requested DMA always halts the operation currently being executed by the CPU. Access to the internal bus always is granted on the third clock cycle after the BR signal is received. In the PQ package, the IAQ pin also indicates when bus access has been granted. In the PZ package, this pin is not present so the host is required to wait two clock cycles after driving the bus request low before beginning DMA transfer. host port interface (HPI) (TMS320C57S, TMS320LC57, TMS320LC57S only) The HPI is an 8-bit parallel port used to interface a host processor to the ’C57S/’LC57. The host port is connected to a 2k word on-chip buffer through a dedicated internal bus. The dedicated bus allows the CPU to work uninterrupted while the host processor accesses the host port. The HPI memory buffer is a single-access RAM block which is accessible by both the CPU and the host. The HPI memory also can be used as general-purpose data or program memory. Both the CPU and the host have access to the HPI control register (HPIC) and the host can address the HPI memory through the HPI address register (HPIA). Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin, HBIL, indicating whether the high or low byte is being transmitted. Two control pins, HCNTL1 and HCNTL0, control host access to the HPIA, HPI data (with an optional automatic address increment), or the HPIC. The host can interrupt the ’C57S/’LC57 by writing to HPIC. The ’C57S/’LC57 can interrupt the host with a dedicated HINT pin that the host acknowledges and clears.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 host port interface (continued) The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). In SAM, the normal mode of operation, both the ’C57S/’LC57 and the host can access HPI memory. In this mode, asynchronous host accesses are resynchronized internally and, in case of conflict, the host has access priority and the ’C57S/’LC57S waits one cycle. Host and CPU accesses to the HPI memory can be resychronized through polling of a command word or through interrupts to prevent stalling the CPU for one cycle. The HOM capability allows the host to access HPI memory while the ’C57S/’LC57 is in IDLE2 mode (all internal clocks stopped) or in reset mode. The external ’C57S/’LC57S clock even can be stopped. The host can, therefore, access the HPI RAM while the ’C57S/’LC57 is in its optimum configuration in terms of power consumption. The HPI control register has two data strobes, HDS1 and HDS2, a read/write strobe HR/W, and an address strobe HAS, to enable a glueless interface to a variety of industry-standard host devices. The HPI is easily interfaced to hosts with multiplexed address/data bus, separate address and data buses, one data strobe, and a read/write strobe, or two separate strobes for read and write. An HPI-ready pin, HRDY, is provided to specify wait states for hosts that support an asynchronous input. When the ’C57S/’LC57 operating frequency is variable, or when the host is capable of accessing at a faster rate than the maximum shared-access mode access rate, the HRDY pin provides a convenient way to adjust the host access rate automatically (no software handshake needed) to a change in the ’C57S/’LC57 clock rate or an HPI-mode switch. The HPI supports high-speed back-to-back accesses. In the shared-access mode, the HPI can handle one byte every five ’C57S/’LC57 periods (that is, 64 Mb/s with a 40-MHz ’C57S/’LC57). The HPI is designed so that the host can take advantage of this high bandwidth and run at frequencies up to (f /C0002 n) ÷ 5, where n is the number of host cycles for an external access and f is the ’C57S/’LC57 frequency. In host-only mode, the HPI supports even higher speed back-to-back host accesses: 1 byte every 50 ns (that is, 160 Mb/s) independently of the ’C57S/’LC57 clock rate. serial ports The ’C5x provides high-speed full-duplex serial ports that allow direct interface to other ’C5x devices, codecs, and other devices in a system. There is a general-purpose serial port, a time-division-multiplexed (TDM) serial port, and an auto-buffered serial port (BSP). The general-purpose serial port uses two memory-mapped registers for data transfer: the data-transmit register (DXR) and the data-receive register (DRR). Both registers can be accessed in the same manner as any other memory location. The transmit and receive sections of the serial port each have associated clocks, frame-synchronization pulses, and serial shift registers, and serial data can be transferred either in bytes or in 16-bit words. Serial port receive and transmit operations can generate their own maskable transmit and receive interrupts (XINT and RINT), allowing serial port transfers to be managed by way of software. The ’C5x serial ports are double-buffered and fully static. The TDM port allows the device to communicate through time-division multiplexing with up to seven other ’C5x devices with TDM ports. Time-division multiplexing is the division of time intervals into a number of subintervals with each subinterval representing a prespecified communications channel. The TDM port serially transmits 16-bit words on a single data line (TDAT) and destination addresses on a single address line (TADD). Each device can transmit data on a single channel and receive data from one or more of the eight channels providing a simple and efficient interface for multiprocessing applications. A frame synchronization pulse occurs once every 128 clock cycles corresponding to transmission of one 16-bit word on each of the eight channels. Like the general-purpose serial port, the TDM port is double-buffered on both input and output data. The TDM port also can be configured in software to operate as a general-purpose serial port as described above. Both types of ports are capable of operating at up to one-fourth the machine cycle rate (CLKOUT1). The buffered serial port (BSP) consists of a full-duplex double-buffered serial port interface (SPI) and an auto-buffering unit (ABU). The SPI block of the BSP is an enhanced version of the general-purpose serial port. The auto-buffering unit allows the SPI to read/write directly to ’C5x internal memory using a dedicated bus independently of the CPU. This results in minimum overhead for SPI transactions and faster data rates.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial ports (continued) When auto-buffering capability is disabled (standard mode), transfers with SPI are performed under software control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and WRINT) provided by the SPI are sent to the CPU as transmit interrupt (XINT) and receive interrupt (RINT). When auto buffering is enabled, word transfers are done directly between the SPI and the ’C5x internal memory, using ABU-embedded address generators. The ABU has its own set of circular addressing registers with corresponding address-generation units. Memory for the buffers resides in 2K words of ’C5x internal memory. The length and starting addresses of the buffers are user-programmable. A buffer-empty/-full interrupt can be posted to the CPU. Buffering is halted easily because of an auto-disabling capability. Auto-buffering capability can be enabled separately for transmit and receive sections. When auto-buffering is disabled, operation is similar to the general-purpose serial port. The SPI allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a frame-synchronization pulse for every packet. In continuous mode, the frame-synchronization pulse occurs when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequency and polarity programmable. The SPI is fully static and operates at arbitrarily low clock frequencies. The maximum operating frequency is CLKOUT1 (28.6 Mb/s at 35 ns, 40 Mb/s at 25 ns). The SPI transmit section also includes a pulse-coded modulation (PCM) mode that allows easy interface with a PCM line. Most ’C5x devices provide one general-purpose serial port and one TDM port. The ’C52 provides one general-purpose serial port and no TDM port. The ’C53SX provides two general-purpose serial ports and no TDM port. The ’LC56, ’C57S, and ’LC57 devices provide one general-purpose serial port and one buffered serial port. software wait-state generators Software wait-state generation is incorporated in the ’C5x without any external hardware for interfacing with slower off-chip memory and I/O devices. The circuitry consists of 16 wait-state generating circuits and is user-programmable to operate with 0, 1, 2, 3, or 7 wait states. For off-chip memory accesses, these wait-state generators are mapped on 16K-word boundaries in program memory, data memory, and the I/O ports. The ’C53S/’C57S and ’LC56/57 devices have software-programmable wait-state generators that are controlled by one 16-bit wait-state register PDWSR at address 0x28. The programmed number of wait states (0 through 7) applies to all external addresses at the corresponding address space (program, data, I/O) regardless of address value. timer The ’C5x features a 16-bit timing circuit with a 4-bit prescaler. This timer clocks between one-half and one thirty-second the machine rate of the device itself, depending on the programmable timer’s divide-down ratio. This timer can be stopped, restarted, reset, or disabled by specific status bits. The timer can be used to generate CPU interrupts periodically. The timer is decremented by one at every CLKOUT1 cycle. A timer interrupt (TINT) and a pulse equal to the duration of a CLKOUT1 cycle on the external TOUT pin are generated each time the counter decrements to zero. The timer provides a convenient means of performing periodic I/O or other functions. When the timer is stopped, the internal clocks to the timer are shut off, allowing the device to run in a low-power mode of operation.

boundary-scan functions supported by the ’C5x family of devices. Table 5. IEEE 1149.1 Interface/Boundary Scan/On-Chip Analysis Block Configurations breakpoints based on program fetches/reads/writes and EMU0/1 pin activity.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multiprocessing (continued) For multiprocessing applications, the ’C5x is capable of allocating global-memory space and communicating with that space via the BR and ready control signals. Global memory is data memory shared by more than one device. Global memory access must be arbitrated. The 8-bit memory-mapped global memory allocation register (GREG) specifies part of the ’C5x’s data memory as global external memory. The contents of the register determine the size of the global memory space. If the current instruction addresses an operand within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY line. The ’C5x supports direct memory access (DMA) to its external program, data, and I/O spaces using the HOLD and HOLDA signals. Another device can take complete control of the ’C5x’s external memory interface by asserting HOLD low. This causes the ’C5x to to place its address, data, and control lines in the high-impedance state and assert HOLDA. While external memory is being accessed, program execution from on-chip memory can proceed concurrently when the device is in hold mode. Multiple ’C5x devices can be interconnected through their serial ports. This form of interconnection allows information to be transferred at high speed while using a minimum number of signal connections. A complete full-duplex serial-port interconnection between multiple processors can be accomplished with as few as four signal lines. instruction set The ’C5x microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal processing operations and general-purpose applications, such as multiprocessing and high-speed control. Source code for the ’C1x and ’C2x DSPs is upward compatible with the ’C5x. For maximum throughput, the next instruction is prefetched while the current one is being executed. Because the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an instruction requires to execute varies, depending on whether the next data operand fetch is from internal or external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal or fast external program memory. addressing modes The ’C5x instruction set provides six basic memory-addressing modes: direct, indirect, immediate, register, memory mapped, and circular addressing. In direct addressing, the instruction word contains the lowest seven bits of the data-memory address. This field is concatenated with the nine bits of the data-memory page pointer (DP) to form the 16-bit data-memory address. Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, each of which contains 128 words. Indirect addressing accesses data memory through the auxiliary registers. In indirect addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively. There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by either adding or subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary register and ARP can be modified.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 addressing modes (continued) In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There are two types of immediate addressing: long and short. In short-immediate addressing, the data is contained in a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in the second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need to be stored or used more than once during the course of program execution, such as initialization values, constants, etc. The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case, operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand address or immediate value. Memory-mapped addressing provides the convenience of easy access to memory-mapped registers located on page zero of data memory. The flexibility of memory-mapped addressing results because accesses are made independently of actual DP value and without having to provide a complete address of the memory location being accessed. Commonly used on-board registers can be accessed with a simplified addressing scheme. Circular addressing is the most sophisticated ’C5x addressing mode. This addressing mode allows specified buffers in memory to be accessed sequentially with a pointer that automatically wraps around to the beginning of the buffer when the last location is accessed. A total of two independent circular buffers can be allocated at any given time. Five dedicated registers are allocated for implementation of circular addressing: a beginning-of-buffer and an end-of-buffer register for each of the two independent circular buffers and a control register. Additionally, one of the auxiliary registers is used as the pointer into the circular buffer. All registers used in circular addressing must be initialized properly prior to performing any circular buffer access. The circular-addressing mode allows implementation of circular buffers, which facilitate data structures used in FIR filters, convolution and correlation algorithms, and waveform generators. Having the capability to access circular buffers automatically with no overhead allows these types of data structures to be implemented most efficiently. repeat feature The repeat function can be used with instructions such as multiply/accumulates (MAC and MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT), and table read/writes (TBLR/TBLW). These instructions, although normally multicycle, are pipelined when the repeat feature is used, and they effectively become single-cycle instructions. For example, the table-read instruction may take three or more cycles to execute, but when the instruction is repeated, a table location can be read every cycle. The repeat counter (RPTC) is a 16-bit register that, when loaded with a number N, causes the next single instruction to be executed N + 1 times. The RPTC register is loaded by either the RPT or the RPTZ instruction, resulting in a maximum of 65,536 executions of a given instruction. RPTC is cleared by reset. The RPTZ instruction clears both ACC and PREG before the next instruction starts repeating. Once a repeat instruction (RPT or RPTZ) is decoded, all interrupts including NMI (except reset) are masked until the completion of the repeat loop. However, the device responds to the HOLD signal while executing an RPT/RPTZ loop. repeat feature (continued) The ’C5x implements a block-repeat feature that provides zero-overhead looping for implementation of FOR and DO loops. The function is controlled by three registers (PASR, PAER, and BRCR) and the BRAF bit in the PMST register. The block-repeat counter register (BRCR) is loaded with a loop count of 0 to 65,535. Then, execution of the RPTB (repeat block) instruction loads the program-address-start register (PASR) with the address of the instruction following the RPTB instruction and loads the program-address-end register (PAER)

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

with its long-immediate operand. The long-immediate operand is the address of the instruction following the last instruction in the loop minus one. (The repeat block must contain at least three instruction words.) Execution of the RPTB instruction automatically sets active the BRAF bit. With each PC update, the PAER contents are compared to the PC. If they are equal, the BRCR contents are compared to zero. If the BRCR contents are greater than zero, BRCR is decremented and the PASR is loaded into the PC, repeating the loop. If not, the BRAF bit is set low and the processor resumes execution past the end of the code’s loop. The equivalent of a WHILE loop can be implemented by setting the BRAF bit to zero if the exit condition is met. The program then completes the current pass through the loop but does not go back to the top. To exit, the bit must be reset at least four instruction words before the end of the loop. It is possible to exit block-repeat loops and return to them without stopping and restarting the loop. Branches, calls, and interrupts do not necessarily affect the loop. When program control is returned to the loop, loop execution is resumed. instruction set summary This section summarizes the operational codes (opcodes) of the instruction set for the ’C5x digital signal processors. The instruction set is a super set of the ’C1x and ’C2x instruction sets. The instructions are arranged according to function and are alphabetized by mnemonic within each category. The symbols in Table 6 are used in the instruction set opcode table (Table 7). The Texas Instruments ’C5x assembler accepts ’C2x instructions as well as ’C5x instructions. The number of words that an instruction occupies in program memory is specified in column 4 of Table 7. In these cases, different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies one word when the operand is a short immediate value or two words if the operand is a long immediate value. The number of cycles that an instruction requires to execute is listed in column 5 of Table 7. All instructions are assumed to be executed from internal program memory and internal data dual-access memory. The cycle timings are for single-instruction execution, not for repeat mode. A read or write access to any peripheral memory-mapped register in data memory locations 20h–4Fh adds one cycle to the cycle time shown because all peripherals perform these accesses over the internal peripheral bus.

Table 6. Opcode Symbols is ANDed with the conditions. If any bits are set, the conditions are met.

38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 7. TMS320C5x Instruction Set Opcodes

0010 SHFT IAAA AAAA

0001 SHFT IAAA AAAA

0011 SHFT IAAA AAAA

Table 7. TMS320C5x Instruction Set Opcodes (Continued)

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

I/O AND DATA MEMORY OPERATIONS INSTRUCTION MNEMONIC OPCODE WORDS CYCLES Block move from data to data memory Block move data to data DEST long immediate Block move data to data with source in BMAR Block move data to data with DEST in BMAR Block move data to PROG with DEST in BMAR Block move from program to data memory Block move PROG to data with source in BMAR Data move in data memory Input external access Load memory-mapped register Out external access Store memory-mapped register Table read Table write BLDD BLDD BLDD BLDD BLDP BLPD BLPD DMOV IN LMMR OUT SMMR TBLR TBLW 1010 1000 IAAA AAAA 1010 1001 IAAA AAAA 1010 1100 IAAA AAAA 1010 1101 IAAA AAAA 0101 0111 IAAA AAAA 1010 0101 IAAA AAAA 1010 0100 IAAA AAAA 0111 0111 IAAA AAAA 1010 1111 IAAA AAAA 1000 1001 IAAA AAAA 0000 1100 IAAA AAAA 0000 1001 IAAA AAAA 1010 0110 IAAA AAAA 1010 0111 IAAA AAAA 2 or 3 2 or 3 PARALLEL LOGIC UNIT INSTRUCTIONS INSTRUCTION MNEMONIC OPCODE WORDS CYCLES AND DBMR with data value AND long immediate with data value Compare DBMR to data value Compare data with long immediate OR DBMR to data value OR long immediate with data value Store long immediate to data XOR DBMR to data value XOR long immediate with data value APL APL CPL CPL OPL OPL SPLK XPL XPL 0101 1010 IAAA AAAA 0101 1110 IAAA AAAA 0101 1011 IAAA AAAA 0101 1111 IAAA AAAA 0101 1001 IAAA AAAA 0101 1101 IAAA AAAA 1010 1110 IAAA AAAA 0101 1000 IAAA AAAA 0101 1100 IAAA AAAA T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS INSTRUCTION MNEMONIC OPCODE WORDS CYCLES Add PREG to ACC Load high PREG Load TREG0 Load TREG0 and accumulate previous product Load TREG0, accumulate previous product, and move data Load TREG0 and load ACC with PREG Load TREG0 and subtract previous product Multiply/accumulate Multiply/accumulate with data shift Mult/ACC w/source ADRS in BMAR and DMOV Mult/ACC with source address in BMAR Multiply data value times TREG0 Multiply TREG0 by 13-bit immediate Multiply TREG0 by long immediate Multiply TREG0 by data, add previous product Multiply TREG0 by data, ACC – PREG Multiply unsigned data value times TREG0 Load ACC with product register Subtract product from ACC Store high product register Store low product register Set PREG shift count Data to TREG0, square it, add PREG to ACC Data to TREG0, square it, ACC – PREG Zero product register APAC LPH LT LTA LTD LTP LTS MAC MACD MADD MADS MPY MPY MPY MPYA MPYS MPYU PAC SPAC SPH SPL SPM SQRA SQRS ZPR 1011 1110 0000 0100 0111 0101 IAAA AAAA 0111 0011 IAAA AAAA 0111 0000 IAAA AAAA 0111 0010 IAAA AAAA 0111 0001 IAAA AAAA 0111 0100 IAAA AAAA 1010 0010 IAAA AAAA 1010 0011 IAAA AAAA 1010 1011 IAAA AAAA 1010 1010 IAAA AAAA 0101 0100 IAAA AAAA 110I IIII IIII IIII 1011 1110 1000 0000 0101 0000 IAAA AAAA 0101 0001 IAAA AAAA 0101 0101 IAAA AAAA 1011 1110 0000 0011 1011 1110 0000 0101 1000 1101 IAAA AAAA 1000 1100 IAAA AAAA 1011 1111 0000 00PM 0101 0010 IAAA AAAA 0101 0011 IAAA AAAA 1011 1110 0101 1000

0100 BITX IAAA AAAA

integrate and debug software and hardware modules.

42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

(SPRU052), which contains information about TMS320-related products from other companies in the industry. To receive copies of TMS320 literature, contact the Literature Response Center at 800/477-8924. availability, contact the nearest TI field sales office or authorized distributor. Table 8. TMS320C5x, TMS320LC5x Development Support Tools through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below. PC-DOS and OS/2 are trademarks of International Business Machines Corp. SPARC is a trademark of SPARC International, Inc. WIN is a trademark of Microsoft Corporation. HP is a trademark of Hewlett-Packard Company. XDS is a trademark of Texas Instruments Incorporated.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 device and development support tool nomenclature (continued) TMS Fully-qualified production device Support tool development evolutionary flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development support tools have been characterized fully, and the quality and reliability of the device has been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, N, FN, or GB) and temperature range (for example, L). Figure 8 provides a legend for reading the complete device name for any TMS320 family member.

44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 8. TMS320 Device Nomenclature numbers SPRA012, SPRA016, and SPRA017). describes in detail the fifth-generation TMS320 products, is currently available. code and object code for many DSP algorithms and utilities. The BBS can be reached at 713/274-2323.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 45POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating ambient-air temperature range (unless otherwise noted) (’320C5x only)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 3: All voltage values are with respect to VSS . recommended operating conditions (’320C5x only) MIN NOM MAX UNIT VDD Supply voltage 4.75 5 5.25 V VSS Supply voltage 0 V X2/CLKIN, CLKIN2 3 VDD +0.3 VIH High-level input voltage CLKX, CLKR, TCLKX, TCLKR 2.5 VDD +0.3 V All other inputs 2 VDD +0.3 VIL Low level input voltage X2/CLKIN, CLKIN2, CLKX, CLKR, TCLKX, TCLKR – 0.3 0.7 VVIL Low-level input voltage All other inputs – 0.3 0.8 V IOH High-level output current (see Note 4) – 300‡ mA IOL Low-level output current 2 mA TC Operating case temperature 0 85 °C TA Operating ambient temperature –40 85 °C ‡ This IOH can be exceeded when using a 1-kW pulldown resistor on the TDM serial port TADD output; however, this output still meets VOH specifications under these conditions. NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended ranges of supply voltage and operating ambient-air temperature (unless otherwise noted) (’320C5x only) PARAMETER TEST CONDITIONS MIN TYP ‡ MAX UNIT VOH High-level output voltage (see Note 4) IOH = 300 mA 2.4 3 V VOL Low-level output voltage (see Note 4) IOL = 2 mA 0.3 0.6 V IOZ High impedance output current (VDD = 5 25 V) BR (with internal pullup) – 500 20 mAIOZ High-impedance output current (VDD = 5.25 V) All other 3-state outputs –2 0 20 mA TRST (with internal pulldown) –1 0 800 II Input current (VI=V SS to VDD ) TMS, TCK, TDI (with internal pullups)– 500 10 mAII Input current (VI = VSS to VDD ) X2/CLKIN –5 0 50 mA All other inputs –1 0 10 fx = 40 MHz, V DD = 5.25 V 60 IDD( ) Supply current core CPU fx = 57 MHz, V DD = 5.25 V 67 mAIDD(core) Supply current, core CPU fx = 80 MHz, V DD = 5.25 V 94 mA fx = 100 MHz, VDD = 5.25 V 110 fx = 40 MHz, V DD = 5.25 V 40 IDD( i ) Supply currentpins fx = 57 MHz, V DD = 5.25 V 45 mAIDD(pins) Supply current, pins fx = 80 MHz, V DD = 5.25 V 63 mA fx = 100 MHz, VDD = 5.25 V 75 IDD(standby)Supply current, standby IDLE2, divide-by-two clock mode, clocks shut off 5 mA C i Input capacitance 15 pF C o Output capacitance 15 pF † Typical values are at VDD = 5 V, TA = 25°C, unless otherwise specified. NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over specified temperature range (unless otherwise noted) (’320LC5x only)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 3: All voltage values are with respect to VSS . recommended operating conditions (’320LC5x only) MIN NOM MAX UNIT VDD Supply voltage 3.13 3.3 3.47 V VSS Supply voltage 0 V X2/CLKIN, CLKIN2 2.5 VDD + 0.3 VIH High-level input voltage CLKX, CLKR, TCLKX, TCLKR 2.0 VDD + 0.3 V All other inputs 1.8 VDD + 0.3 VIL Low-level input voltage X2/CLKIN, CLKIN2, CLKX, CLKR, TCLKX, TCLKR –0.3 0.5 V IL o e e u o age All other inputs –0.3 0.6 V IOH High-level output current – 300‡ mA IOL Low-level output current 2 mA TC Operating case temperature 0 85 °C TA Operating ambient temperature –40 85 °C ‡ This IOH may be exceeded when using a 1-kW pulldown resistor on the TDM serial port TADD output; however, this output still meets VOH specifications under these conditions.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (’320LC5x only) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage IOH = 300 mA 2.0 VVOH gg (see Note 4) IOH = 20 mA VDD – 0.3‡ V VOL Low-level output voltage IOL = 2 mA 0.4 VVOL g (see Note 4) IOL = 20 mA 0.3‡ V I High-impedance output currentBR (with internal pullup) –500 20 AIOZ High im edance out ut current (VDD = 3.47 V) All other 3-state outputs –20 20 mA TRST (with internal pulldown) –10 800 TMS, TCK, TDI pins (with internal pullups)–500 10 II Input current (VI = VSS to VDD ) X2/CLKIN (oscillator enabled) –50 50 mAI ( IS S D D ) X2/CLKIN (oscillator disabled) –10 10 m All other inputs –10 10 fx = 40 MHz, V DD = 3.47 V 26 IDD(core) Supply current, core CPU fx = 50 MHz, V DD = 3.47 V 33 mA() fx = 80 MHz, V DD = 3.47 V 53 fx = 40 MHz, V DD = 3.47 V 18 IDD(pins) Supply current, pins fx = 50 MHz, V DD = 3.47 V 22 mA() fx = 80 MHz, V DD = 3.47 V 35 IDD(standby) Supply current, standby IDLE2, divide-by-two clock mode, clocks shut off 5 mA C i Input capacitance 15 pF C o Output capacitance 15 pF † All typical values are at VDD = 3.3 V, TA = 25°C. ‡ Values derived from characterization data and not tested NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels.

Figure 9. Test Load Circuit

2.4 V (2 V)

Figure 10. TTL-Level Outputs level at which the output is said to be low is 1 V (0.8 V). level at which the output is said to be high is 2 V (1.6 V). Figure 11 shows the TTL-level inputs. Figure 11. TTL-Level Inputs 2 V (1.8 V), and the level at which the input is said to be low is 0.8 V (0.6 V). 0.8 V (0.6 V), and the level at which the input is said to be high is 2 V (1.8 V).

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid dis disable time Z High impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) X Unknown, changing, or don’t care level

devices, X2/CLKIN functions as the external frequency input when using the PLL options. Table 9. Standard Clock Options Table 10. PLL Clock Option for ’LC56, ’C57S, and ’LC57

52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

it should be specified at a load capacitance of 20 pF. Overtone crystals require an additional tuned-LC circuit. Figure 12 shows an external crystal (fundamental frequency) connected to the on-chip oscillator. at frequencies approaching 0 Hz, but is tested at fclk = 6.7 MHz to meet device test time requirements. Figure 12. Internal Clock Option

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 53POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 external divide-by-two clock option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. Refer to Table 9 and Table 10 for appropriate configuration of the CLKMD1, CLKMD2 and CLKMD3 pins to generate the external divide-by-2 clock option. The external frequency injected must conform to the specifications listed in the timing requirements table. switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (’320C5x only) (see Figure 13) PARAMETER ’320C5x-40 ’320C5x-57 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 48.8 2tc(CI) † 35 2tc(CI) † ns td(CIH-COH/L) Delay time, X2/CLKIN high to CLKOUT1 high/low 3 11 20 3 11 20 ns tf(CO) Fall time, CLKOUT1 5 5 ns tr(CO) Rise time, CLKOUT1 5 5 ns tw(COL) Pulse duration, CLKOUT1 low H – 3 H H + 2 H – 3 H H + 2 ns tw(COH) Pulse duration, CLKOUT1 high H – 3 H H + 2 H – 3 H H + 2 ns PARAMETER ’320C5x-80 ’320C5x-100 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 25 2tc(CI) † 20 2tc(CI) † ns td(CIH-COH/L) Delay time, X2/CLKIN high to CLKOUT1 high/low 1 9 18 1 9 18 ns tf(CO) Fall time, CLKOUT1 4 4 ns tr(CO) Rise time, CLKOUT1 4 4 ns tw(COL) Pulse duration, CLKOUT1 low H – 3 H H + 2 H – 3 H H + 2 ns tw(COH) Pulse duration, CLKOUT1 high H – 3 H H + 2 H – 3 H H + 2 ns switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (’320LC5x only) (see Figure 13) PARAMETER ’320LC5x-40 ’320LC5x-50 ’320LC5x-80 UNIT PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 50 2tc(CI) † 40 2tc(CI) † 25 2tc(CI) † ns td(CIH-COH/L) Delay time, X2/CLKIN high to CLKOUT1 high/low 3 11 20 3 11 20 1 9 18 ns tf(CO) Fall time, CLKOUT1 5 5 4 ns tr(CO) Rise time, CLKOUT1 5 5 4 ns tw(COL) Pulse duration, CLKOUT1 low H – 3 H H + 2 H – 3 H H + 2 H – 3 H H + 2 ns tw(COH) Pulse duration, CLKOUT1 high H – 3 H H + 2 H – 3 H H + 2 H – 3 H H + 2 ns † This device utilizes a fully static design and, therefore, can operate with tc(Cl) approaching infinity. The device is characterized at frequencies approaching 0 Hz but is tested at tc(CO) = 300 ns to meet device test time requirements.

54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

approaching 0 Hz, but is tested at a minimum of tc(Cl) = 150 ns to meet device test time requirements. Figure 13. External Divide-by-Two Clock Timing

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 55POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PLL clock generator option An external frequency source can be used by injecting the frequency directly into CLKIN2‡ with X1 left unconnected and X2 connected to VDD . This external frequency is multiplied by the factors shown in Table 9 and Table 10 to generate the internal machine cycle. The multiply-by-one option is available on the ’C50, ’LC50, ’C51, ’LC51, ’C53, ’LC53, ’C53S and ’LC53S. The multiply-by-two option is available on the ’C52 and ’LC52. Multiplication factors of 1, 2, 3, 4, 5, and 9 are available on the ’LC56, ’LC57, ’C57S and ’LC57S. Refer to Table 9 and Table 10 for appropriate configuration of the CLKMD1, CLKMD2 and CLKMD3 pins to generate the desired PLL multiplication factor. The external frequency injected must conform to the specifications listed in the timing requirements table. switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (’320C5x only) (see Figure 14) PARAMETER ’320C5x-40 ’320C5x-57 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 48.8 75 35 75 ns tf(CO) Fall time, CLKOUT1 5 5 ns tr(CO) Rise time, CLKOUT1 5 5 ns tw(COL) Pulse duration, CLKOUT1 low H – 3† H H + 2† H – 3† H H + 2† ns tw(COH) Pulse duration, CLKOUT1 high H – 3† H H + 2† H – 3† H H + 2† ns td(C2H-COH) Delay time, CLKIN2 high to CLKOUT1 high 2 9 16 2 9 16 ns td(TP) Delay time, transitory phase—PLL synchronized after CLKIN2 supplied† 1000tc(C2)/C0277 1000tc(C2)/C0277ns PARAMETER ’320C5x-80 ’320C5x-100 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 25 55 20 45 ns tf(CO) Fall time, CLKOUT1 4 4 ns tr(CO) Rise time, CLKOUT1 4 4 ns tw(COL) Pulse duration, CLKOUT1 low H – 3† H H + 2† H – 3† H H + 2† ns tw(COH) Pulse duration, CLKOUT1 high H – 3† H H + 2† H – 3† H H + 2† ns td(C2H-COH) Delay time, CLKIN2 high to CLKOUT1 high 1 8 15 1 8 15 ns td(TP) Delay time, transitory phase—PLL synchronized after CLKIN2 supplied† 1000tc(C2)/C0277 1000tc(C2)/C0277ns † Values assured by design and not tested ‡ On the TMS320C57S devices, CLKIN2 functions as the PLL clock input.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (’320LC5x only) (see Figure 14) PARAMETER ’320LC5x-40 ’320LC5x-50 ’320LC5x-80 UNITPARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 50 75† 40 75† 25 55† ns td(C2H-COH) Delay time, CLKIN2 high to CLKOUT1 high 2 9 16 2 9 16 1 8 15 ns tf(CO) Fall time, CLKOUT1 5 5 4 ns tr(CO) Rise time, CLKOUT1 5 5 4 ns tw(COL) Pulse duration, CLKOUT1 low H–3 ‡ H H+2 ‡ H–3 ‡ H H+2 ‡ H–3 ‡ H H+2 ‡ ns tw(COH) Pulse duration, CLKOUT1 high H–3 ‡ H H+2 ‡ H–3 ‡ H H+2 ‡ H–3 ‡ H H+2 ‡ ns td(TP) Delay time, transitory phase—PLL synchronized after CLKIN2 supplied 1000tc(C2) 1000tc(C2) 1000tc(C2) ns † Clocks can only be stopped while executing IDLE2 when using the PLL clock generator option. ‡ Values assured by design and not tested § On the ’LC56, ’LC57, and ’LC57S devices, CLKIN2 functions as the PLL clock input.

restarting clock from IDLE2 in this mode. Figure 14. PLL Clock Generator Timing

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MEMORY AND PARALLEL I/O INTERFACE READ switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (’320C5x only) (see Figure 15) PARAMETER ’320C5x-40 ’320C5x-57 ’320C5x-80 ’320C5x-100 UNITPARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNIT tsu(AV-RDL) Setup time, address valid before th(RDH-AV) Hold time, address valid after RD tw(RDL) Pulse duration, RD low§¶# H – 2 H + 2 H – 2 H + 2 H – 2 H + 2 H – 2 H + 2 ns tw(RDH) Pulse duration, RD high§¶# H – 2 H – 2 H – 2 H – 2 ns td(CO-ST) Delay time, CLKOUT1 to STRB rising or falling edge§¶ – 1 3 – 2 2 – 2 2 – 2 2 ns td(CO-RD) Delay time, CLKOUT1 to RD rising or falling edge§¶ – 3 1 – 3 1 – 3 1 – 3 1 ns td(RDH-WEL) Delay time, RD high to WE low 2H – 5 2H – 5 2H – 4 2H – 4 ns switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (’320LC5x only) (see Figure 15) PARAMETER ’320LC5x-40 ’320LC5x-50 ’320LC5x-80 UNIT MIN MAX MIN MAX tsu(AV-RDL) Setup time, address valid before RD low† H–1 0 ‡ H – 7‡ ns th(RDH-AV) Hold time, address valid after RD high† 0‡ 0‡ ns tw(RDL) Pulse duration, RD low§¶# H–2 H+2 H–2 H+2 ns tw(RDH) Pulse duration, RD high§¶# H–2 H–2 ns td(RDH-WEL) Delay time, RD high to WE low 2H – 5 2H – 4 ns td(CO-RD) Delay time, CLKOUT1 to RD rising or falling edge§¶ –2 2 –3 1 ns td(CO-ST) Delay time, CLKOUT1 to STRB rising or falling edge§¶ 0 4 –2 2 ns † A0–A15, PS, DS, IS, R/W, and BR timings all are included in timings referenced as address. ‡ See Figure 16 for address bus timing variation with load capacitance. § These timings are for the cycles following the first cycle after reset, which is always seven wait states. ¶ Values are derived from characterization data and not tested. # Timings are valid for zero wait-state cycles only.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 59POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating ambient-air temperature [H = 0.5tc(CO)] (’320C5x only) (see Figure 15) ’320C5x-40 ’320C5x-57 ’320C5x-80 ’320C5x-100 UNIT MIN MAX MIN MAX MIN MAX MIN MAX UNIT ta(RDAV) Access time, read data from address valid 2H – 18† 2H – 15† 2H – 10† 2H – 10† ns ta(RDL-RD) Access time, read data after RD low H – 10 H – 10 H – 7 H – 6 ns tsu(RD-RDH) Setup time, read data before RD high 10 10 7 6 ns th(RDH-RD) Hold time, read data after RD high 0 0 0 0 ns timing requirements over recommended ranges of supply voltage and operating ambient-air temperature [H = 0.5tc(CO)] (’320LC5x only) (see Figure 15) ’320LC5x-40 ’320LC5x-50 ’320LC5x-80 UNIT MIN MAX MIN MAX ta(RDAV) Access time, read data from address valid 2H – 17† 2H – 10† ns tsu(RD-RDH) Setup time, read data before RD high 10 7 ns th(RDH-RD) Hold time, read data after RD high 0 0 ns ta(RDL-RD) Access time, read data after RD low H–1 0 H–7 ns † See Figure 16 for address bus timing variation with load capacitance.

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MEMORY AND PARALLEL I/O INTERFACE WRITE switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (’320C5x only) (see Figure 15) PARAMETER ’320C5x-40 ’320C5x-57 ’320C5x-80 ’320C5x-100 UNITPARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNIT tsu(AV-WEL) Setup time, address valid tsu(WDV-WEH) Setup time, write data valid before WE high 2H – 20 2H §¶ 2H – 20 2H §¶ 2H – 14 2H §¶ 2H – 14 2H §¶ ns th(WEH-AV) Hold time, address valid after WE high† H–1 0 ‡ H–1 0 ‡ H–7 ‡ H–7 ‡ ns th(WEH-WDV) Hold time, write data valid after WE high H–5 H+1 0 § H–5 H+1 0 § H–4 H+7 § H–4 H+7 § ns tw(WEL) Pulse duration, WE low§¶ 2H – 2 2H + 2§ 2H – 2 2H + 2§ 2H – 2 2H + 2 2H – 2 2H + 2 ns tw(WEH) Pulse duration, WE high§ 2H – 2 2H – 2 2H – 2 2H – 2 ns td(CO-ST) Delay time, CLKOUT1 to STRB rising or falling edge§ –1 3 –2 2 –2 2 –2 2 ns td(CO-WE) Delay time, CLKOUT1 to WE rising or falling edge§ 0 4 –1 3 –1 3 –1 3 ns td(WEH-RDL) Delay time, WE high to RD low 3H – 10 3H – 10 3H – 7 3H – 7 ns ten(WEL-BUd) Enable time, WE low to switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (’320LC5x only) (see Figure 15) PARAMETER ’320LC5x-40 ’320LC5x-50 ’320LC5x-80 UNIT MIN MAX MIN MAX tsu(AV-WEL) Setup time, address valid before WE low† H–7 ‡ H–4 ‡ ns tsu(WDV-WEH) Setup time, write data valid before WE high# 2H – 20 2H §¶ 2H – 14 2H §¶ ns th(WEH-AV) Hold time, address valid after WE high† H–1 0 ‡ H–7 ‡ ns th(WEH-WDV) Hold time, write data valid after WE high H–5 H+1 0 § H–4 H+7 § ns tw(WEL) Pulse duration, WE low¶§ 2H – 4 2H + 2 2H – 4 2H + 2 ns tw(WEH) Pulse duration, WE high¶ 2H – 2 2H – 2 ns td(WEH-RDL) Delay time, WE high to RD low 3H – 10 3H – 7 ns td(CO-ST) Delay time, CLKOUT1 to STRB rising or falling edge¶ 0 4 –2 2 ns td(CO-WE) Delay time, CLKOUT1 to WE rising or falling edge¶ 0 4 –1 3 ns ten(WE-BUd) Enable time, WE to data bus driven –5 § –4 § ns † A0–A15, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address. ‡ See Figure 16 for address bus timing variation with load capacitance. § Values derived from characterization data and not tested ¶ This value holds true for zero wait states or one software wait state only. # STRB and WE edges are 0–4 ns from CLKOUT1 edges on writes. Rising and falling edges of these signals track each other; tolerance of resulting pulsewidths is ± 2 ns, not ± 4 ns.

read or immediately followed by an external read require three machine cycles. B. Refer to Appendix B of TMS320C5x User’s Guide (literature number SPRU056) for logical timings of external interface. Figure 15. Memory and Parallel I/O Interface Read and Write Timing

62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 16. Address Bus Timing Variation With Load Capacitance

64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

require an extra half-cycle to ensure internal synchronization. § If in IDLE2, add 4H to these timings. Figure 19. Reset, Interrupt, and BIO Timings

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 65POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK), EXTERNAL FLAG (XF), AND TOUT (SEE NOTE 6) switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 20) PARAMETER ’320C5x-40 ’320C5x-57 ’320LC5x-40 ’320LC5x-50 ’320C5x-80 ’320C5x-100 ’320LC5x-80 UNIT MIN MAX MIN MAX tsu(AV-IQL) Setup time, address valid before IAQ low† H–1 2 ‡ H–9 ‡ ns th(IQL-AV) Hold time, address valid after IAQ low H–1 0 ‡ H–7 ‡ ns tw(IQL) Pulse duration, IAQ low H–1 0 ‡ H–7 ‡ ns td(CO-TU) Delay time, CLKOUT1 falling edge to TOUT –6 6 –6 6 ns tsu(AV-IKL) Setup time, address valid before IACK low§ H–1 2 ‡ H–9 ‡ ns th(IKL-AV) Hold time, address valid after IACK low H–1 0 ‡ H–7 ‡ ns tw(IKL) Pulse duration, IACK low H–1 0 ‡ H–7 ‡ ns tw(TUH) Pulse duration, TOUT high 2H – 12 2H – 9 ns td(CO-XFV) Delay time, XF valid after CLKOUT1 0 12 0 9 ns † IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being addressed resides in on-chip memory. ‡ Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS is on or code is executing off chip) § IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used. Address pins A1–A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must be set to zero for the address to be valid when the vectors reside in on-chip memory. NOTE 6: IAQ pin is not present on 100-pin packages. IACK pin is not present on 100-pin and 128-pin packages.

66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

† IAQ and IACK are not affected by wait states. Figure 20. IAQ, IACK, and XF Timings Example With Two External Wait States

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 67POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXTERNAL DMA switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Note 7) (see Figure 21) PARAMETER ’320C5x-40 ’320C5x-57 ’320LC5x-40 ’320LC5x-50 ’320C5x-80 ’320LC5x-80 ’320C5x-100 UNIT MIN MAX MIN MAX MIN MAX td(HOL-HAL) Delay time, HOLD low to HOLDA low 4H † 4H † 4H † ns td(HOH-HAH) Delay time, HOLD high before HOLDA high 2H 2H 2H ns th(AZ-HAL) Address high-impedance before HOLDA low‡ H–1 5 § H–1 0 § H–8 § ns ten(HAH-Ad) Enable time, HOLDA high to address driven H–5 § H–4 § H–3 § ns td(XBL-IQL) Delay time, XBR low to IAQ low 4H § 6H § 4H § 6H § 4H § 6H § ns td(XBH-IQH) Delay time, XBR high to IAQ high 2H § 4H § 2H § 4H § 2H § 4H § ns td(XSL-RDV) Delay time, read data valid after XSTRB low 40 29 25 ns th(XSH-RD) Hold time, read data valid after XSTRB high 0 0 0 ns ten(IQL-RDd) Enable time, IAQ low to read data driven¶ 0§ 2H § 0§ 2H § 0§ 2H § ns th(XRL-DZ) Hold time, XR/W low to data high impedance 0§ 15§ 0§ 10§ 0§ 8 ns th(IQH-DZ) Hold time, IAQ high to data high impedance H § H § H § ns ten(D-XRH) Enable time, data from XR/W going high 4§ 3§ 2§ ns † HOLD is not acknowledged until current external access request is complete. ‡ This parameter includes all memory control lines. § Values derived from characterization data and not tested ¶ This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the ’C5x data lines become valid. NOTE 7: X preceding a name refers to external drive of the signal. timing requirements over recommended ranges of supply voltage and operating ambient-air temperature (see Note 7) (see Figure 21) ’320C5x-40 ’320C5x-57 ’320LC5x-40 ’320LC5x-50 ’320C5x-80 ’320LC5x-80 ’320C5x-100 UNIT MIN MAX MIN MAX MIN MAX td(HAL-XBL) Delay time, HOLDA low to XBR low# 0§ 0§ 0§ ns td(IQL-XSL) Delay time, IAQ low to XSTRB low# 0§ 0§ 0§ ns tsu(AV-XSL) Setup time, Xaddress valid before XSTRB low 15 12 10 ns tsu(DV-XSL) Setup time, Xdata valid before XSTRB low 15 12 10 ns th(XSL-D) Hold time, Xdata hold after XSTRB low 15 12 10 ns th(XSL-WA) Hold time, write Xaddress hold after XSTRB low 15 12 10 ns tw(XSL) Pulse duration, XSTRB low 45 40 35 ns tw(XSH) Pulse duration, XSTRB high 45 40 35 ns tsu(RW-XSL) Setup time, R/W valid before XSTRB low 20 20 18 ns th(XSH-RA) Hold time, read Xaddress after XSTRB high 0 0 0 ns § Values derived from characterization data and not tested # XBR , XR/W, and XSTRB lines must be pulled up with a 10-kW resistor to be certain that they are in an inactive high state during the transition period between the ’C5x driving them and the external circuit driving them. NOTE 7: X preceding a name refers to external drive of the signal.

68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 21. External DMA Timing

of 0 Hz but tested at a much higher frequency to minimize test time. Figure 22. Serial-Port Receive Timing

70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

of 0 Hz but tested at a much higher frequency to minimize test time. independent of the source of CLKX. Figure 23. Serial-Port Transmit Timing of External Clocks and External Frames

independent of the source of CLKX. Figure 24. Serial-Port Transmit Timing of Internal Clocks and Internal Frames

72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

of 0 Hz but tested at a much higher frequency to minimize test time. illustrated in the transmit timing diagram in Figure 26. # These parameters apply only to the first bits in the serial bit string. Figure 25. Serial-Port Receive Timing in TDM Mode

illustrated in the receive timing diagram in Figure 27. of 0 Hz but tested as a much higher frequency to minimize test time. Figure 26. Serial-Port Transmit Timing in TDM Mode

74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

of 0 Hz but tested at a much higher frequency to minimize test time. § First bit is read when FSR is sampled low by CLKR clock. Figure 27. Buffered Serial-Port Receive Timing

of 0 Hz but tested at a much higher frequency to minimize test time. of CLKX). After falling edge of the FSX, data is shifted out on the DX pin. Serial-Port Transmit Timing of External Frames” section. Figure 28. Buffered Serial-Port Transmit Timing of External Clocks and External Frames

76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

in the “Buffered Serial-Port Transmit Timing of External Frames” section.

1. Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to 0.

Figure 29. Buffered Serial-Port Transmit Timing of Internal Clocks and Internal Frames

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 77POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (See Notes 11 and 12) (see Figure 30 through Figure 33) PARAMETER MIN MAX UNIT td(DSL-HDV) Delay time, DS low to HD valid 5 ns td(HEL-HDV1) Delay time, HDS falling to HD valid for first byte of a subsequent read: Case 1: Shared-access mode if tw(HDS )h < 7H † ‡ Case 2: Shared-access mode if tw(HDS )h > 7H Case 3: Host-only mode if tw(HDS )h < 7H Case 4: Host-only mode if tw(HDS )h > 7H 7H+20–tw(DSH) 40–tw(DSH) ns td(DSL-HDV2) Delay time, DS low to HD valid, second byte 20 ns td(DSH-HYH) Delay time, DS high to HRDY high ns tsu(HDV-HYH) Setup time, HD valid before HRDY rising edge 3H–10 ns th(DSH-HDV) Hold time, HD valid after DS rising edge 0 12§ ns td(COH-HYH) Delay time, CLKOUT rising edge to HRDY high 10 ns td(DSH-HYL) Delay time, HDS or HCS high to HRDY low 12 ns td(COH-HTX) Delay time, CLKOUT rising edge to HINT change 10 ns † Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access mode. HRDY does not go low for these accesses. ‡ Shared-access mode timings are met automatically if HRDY is used. § HD release NOTES: 11. SAM = shared-access mode, HOM = host-only mode HAD stands for HCNTRL0, HCNTRL1, and HR/W. HDS refers to either HDS1 or HDS2. DS refers to the logical OR of HCS and HDS. 12. On host-read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be specified here. timing requirements over recommended operating conditions [H = 0.5tc(CO)] (See Note 11) (see Figure 30 through Figure 33) MIN MAX UNIT tsu(HBV-DSL) Setup time, HAD/HBIL valid before HAS or DS falling edge# 10 ns th(DSL-HBV) Hold time, HAD/HBIL valid after HAS or DS falling edge# 10 ns tsu(HSL-DSL) Setup time, HAS low before DS falling edge 10 ns tw(DSL) Pulse duration, DS low 25 ns tw(DSH) Pulse duration, DS high 10 ns tc(DSH-DSH) Cycle time, DS rising edge to next DS rising edge: Case 1: When using HRDY (see Figure 32) Case 2a: SAM accesses and HOM active writes to DSPINT or HINT without using HRDY (see Figure 30 and Figure 31) Case 2b: When not using HRDY for other HOM accesses 10H ¶ ns tsu(HDV-DSH) Setup time, HD valid before DS rising edge 10 ns th(DSH-HDV) Hold time, HD valid after DS rising edge 0 ns ¶ A host not using HRDY must meet the 10 H requirement all the time unless a software handshake is used to change the access rate according to the HPI mode. # When HAS is tied to VDD , timing is referenced to DS. NOTE 11: SAM = shared-access mode, HOM = host-only mode HAD stands for HCNTRL0, HCNTRL1, and HR/W. HDS refers to either HDS1 or HDS2. DS refers to the logical OR of HCS and HDS.

78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 30. Read/Write Access Timings Without HRDY or HAS

Figure 31. Read/Write Access Timings Using HAS Without HRDY

80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Figure 32. Read/Write Access Timing With HRDY

Figure 33. HRDY Signal When HCS Is Always Low

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PQ (S-PQFP-G132) PLASTIC QUAD FLATPACK 116 0.012 (0,30) 0.008 (0,20) 0.025 (0,635) Seating Plane 0.966 (24,54) 0.934 (23,72) 1.112 (28,25) 1.088 (27,64) 0.800 (20,32) SQ 132117 8351 SQ SQ 0.180 (4,57) MAX 0.004 (0,10) M0.006 (0,15) 0.020 (0,51) MIN 0.130 (3,30) 0.150 (3,81) 0.006 (0,16) NOM Gage Plane 0.036 (0,91) 0.046 (1,17) 0°–8° 117 1.070 (27,18)SQ NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-069 Thermal Resistance Characteristics PARAMETER °C/W R Q JA 35 R Q JC 8.5

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 83POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA PBK (S-PQFP-G128) PLASTIC QUAD FLATPACK 4040279-3/B 10/94 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,23 11,60 TYP 0,13 128 SQ SQ 13,80 16,20 15,80 1,60 MAX 1,45 1,35 14,20 0°–7° 0,08 0,40 M0,07 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. Thermal Resistance Characteristics PARAMETER °C/W R Q JA 58 R Q JC 10

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PJ (R-PQFP-G100) PLASTIC QUAD FLATPACK 4040012/B 10/94 0,15 NOM 18,0014,20 17,2013,80 12,35 TYP 0,25 0,70 1,10 0,10 MIN Gage Plane 18,85 TYP 100 20,20 19,80 23,20 24,00 3,10 MAX 2,70 TYP 0,20 0,40 Seating Plane 0,15 0,65 M0,13 0°–10° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package. Thermal Resistance Characteristics PARAMETER °C/W R Q JA 78 R Q JC 13

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 85POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149/B 10/94 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 12,00 TYP 0,17 100 SQ SQ15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0°–7° Seating Plane 0,08 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136 Thermal Resistance Characteristics PARAMETER °C/W R Q JA 58 R Q JC 10

TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996

86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 4040147/B 10/94 0,27 0,17 0,13 NOM 0,25 0,75 0,45 0,05 MIN Seating Plane Gage Plane 108 109 144 SQ SQ22,20 21,80 19,80 17,50 TYP 20,20 1,35 1,45 1,60 MAX M0,08 0°–7° 0,08 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136 Thermal Resistance Characteristics PARAMETER °C/W R Q JA 40 R Q JC 9.9

www.ti.com 11-Jun-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMP320LBC57PBK80 OBSOLETE LQFP PBK 128 TBD Call TI Call TI TMS320BC51PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320BC51PQ100 NRND BQFP PQ 132 TBD Call TI Call TI 0 to 0 51PQ100 @1992 TI TMS320BC TMS320BC51PQ57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI @1992 TI TMS320BC51PQ57 TMS320BC51PQ80 OBSOLETE BQFP PQ 132 TBD Call TI Call TI @1992 TI TMS320BC51PQ80 TMS320BC51PQA OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 TMS320BC51PQA57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 51PQA57 @1992 TI TMS320BC TMS320BC51PQA80 OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 51PQA80 @1992 TI TMS320BC TMS320BC51PQA80G4 OBSOLETE BQFP PQ 132 TBD Call TI Call TI 51PQA80 @1992 TI TMS320BC TMS320BC51PZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320BC51PZ100 NRND LQFP PZ 100 TBD Call TI Call TI 0 to 0 @1992 TI 100 TMS320BC51PZ TMS320BC51PZ57 NRND LQFP PZ 100 TBD Call TI Call TI 0 to 0 @1992 TI TMS320BC51PZ TMS320BC51PZ80 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320BC51PZ TMS320BC51PZA OBSOLETE LQFP PZ 100 TBD Call TI Call TI -40 to 85 TMS320BC51PZA57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320BC51PZA TMS320BC52PJ OBSOLETE QFP PJ 100 TBD Call TI Call TI 0 to 0

www.ti.com 11-Jun-2016 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMS320BC52PJ100 OBSOLETE QFP PJ 100 TBD Call TI Call TI 100 @1992 TI TMS320BC52PJ TMS320BC52PJ57 OBSOLETE QFP PJ 100 TBD Call TI Call TI 57 @1992 TI TMS320BC52PJ TMS320BC52PJ80 OBSOLETE QFP PJ 100 TBD Call TI Call TI 80 @1992 TI TMS320BC52PJ TMS320BC52PJA OBSOLETE QFP PJ 100 TBD Call TI Call TI -40 to 85 TMS320BC52PJA57 OBSOLETE QFP PJ 100 TBD Call TI Call TI -40 to 85 57 @1992 TI TMS320BC52PJA TMS320BC52PZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI 0 to 0 TMS320BC52PZ100 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI 100 TMS320BC52PZ TMS320BC52PZ57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320BC52PZ TMS320BC52PZ80 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320BC52PZ TMS320BC52PZ80G4 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320BC52PZ TMS320BC52PZA OBSOLETE LQFP PZ 100 TBD Call TI Call TI -40 to 85 TMS320BC52PZA57 NRND LQFP PZ 100 TBD Call TI Call TI -40 to 85 @1992 TI TMS320BC52PZA TMS320BC53PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320BC53PQ57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI @1992 TI TMS320BC53PQ57 TMS320BC53PQ80 OBSOLETE BQFP PQ 132 TBD Call TI Call TI @1992 TI TMS320BC53PQ80 TMS320BC53PQA OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 TMS320BC53PQA57 NRND BQFP PQ 132 TBD Call TI Call TI TMS320BC53PQA

www.ti.com 11-Jun-2016 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples @1992 TI TMS320BC53SPZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320BC53SPZ80 NRND LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320BC53SPZ TMS320BC57SPGE57 OBSOLETE LQFP PGE 144 TBD Call TI Call TI TMS320BC57SPGE @1995 TI TMS320BC57SPGE80 OBSOLETE LQFP PGE 144 TBD Call TI Call TI 80 @1995 TI TMS320BC57SPGE TMS320C50PGE OBSOLETE LQFP PGE 144 TBD Call TI Call TI TMS320C50PGE57 NRND LQFP PGE 144 TBD Call TI Call TI 57 TMS320C50PGE TMS320C50PGE80 NRND LQFP PGE 144 TBD Call TI Call TI TMS320C50PGE TMS320C50PGEA57 OBSOLETE LQFP PGE 144 TBD Call TI Call TI 57 TMS320C50PGEA TMS320C50PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C50PQ57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C50PQ57 @1992 TI TMS320C50PQ80 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C50PQ80 @1992 TI TMS320C50PQA OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 TMS320C50PQA @1992 TI TMS320C50PQA57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 TMS320C50PQA57 @1992 TI TMS320C51PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C51PQ100 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C51PQ57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C51PQ80 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C51PQA OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 TMS320C51PQA57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 TMS320C51PQA80 OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85

www.ti.com 11-Jun-2016 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMS320C51PZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320C51PZ100 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320C51PZ57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320C51PZ80 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320C51PZA OBSOLETE LQFP PZ 100 TBD Call TI Call TI -40 to 85 TMS320C52PJ OBSOLETE QFP PJ 100 TBD Call TI Call TI TMS320C52PJ100 OBSOLETE QFP PJ 100 TBD Call TI Call TI TMS320C52PJ57 OBSOLETE QFP PJ 100 TBD Call TI Call TI TMS320C52PJ80 OBSOLETE QFP PJ 100 TBD Call TI Call TI 80 @1992 TI TMS320C52PJ TMS320C52PJA OBSOLETE QFP PJ 100 TBD Call TI Call TI -40 to 85 TMS320C52PJA57 OBSOLETE QFP PJ 100 TBD Call TI Call TI -40 to 85 TMS320C52PZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320C52PZ100 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320C52PZ57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320C52PZ80 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320C52PZA OBSOLETE LQFP PZ 100 TBD Call TI Call TI -40 to 85 TMS320C52PZA57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI -40 to 85 @1992 TI TMS320C52PZA TMS320C53PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C53PQ57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C53PQ80 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320C53PQA OBSOLETE BQFP PQ 132 TBD Call TI Call TI -40 to 85 TMS320C53SPZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LBC51PQ57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320LBC51PQA57 NRND BQFP PQ 132 TBD Call TI Call TI TMS320LBC51PQ @1992 TI A57 TMS320LBC51PZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LBC51PZ57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI

www.ti.com 11-Jun-2016 Addendum-Page 5 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMS320LBC51PZ TMS320LBC51PZA OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LBC51PZA57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320LBC51PZA TMS320LBC52PJ OBSOLETE QFP PJ 100 TBD Call TI Call TI TMS320LBC52PJ57 NRND QFP PJ 100 TBD Call TI Call TI 57 @1992 TI TMS320LBC52PJ TMS320LBC52PJA OBSOLETE QFP PJ 100 TBD Call TI Call TI TMS320LBC52PJA57 NRND QFP PJ 100 TBD Call TI Call TI 57 @1992 TI TMS320LBC52PJA TMS320LBC52PZ57 NRND LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320LBC52PZ TMS320LBC52PZA57 NRND LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320LBC52PZA TMS320LBC53PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320LBC53PQ57 NRND BQFP PQ 132 TBD Call TI Call TI 57 @1992 TI TMS320LBC53PQ TMS320LBC53SPZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LBC53SPZ57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LBC53SPZ80 OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320LBC53SPZ TMS320LBC53SPZA57 OBSOLETE LQFP PZ 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LBC53SPZA57 @1992 TI TMS320 TMS320LBC56PZ57 NRND LQFP PZ 100 TBD Call TI Call TI @1994 TI TMS320LBC56PZ TMS320LBC56PZ80 NRND LQFP PZ 100 TBD Call TI Call TI @1994 TI TMS320LBC56PZ

www.ti.com 11-Jun-2016 Addendum-Page 6 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMS320LBC57PBK57 NRND LQFP PBK 128 TBD Call TI Call TI TMS320LBC57PBK @1994 TI TMS320LBC57PBK80 NRND LQFP PBK 128 TBD Call TI Call TI TMS320LBC57PBK @1994 TI TMS320LBC57PGE57 NRND LQFP PGE 144 TBD Call TI Call TI TMS320LBC57 @1995 TI PGE57 TMS320LBC57PGE80 NRND LQFP PGE 144 TBD Call TI Call TI TMS320LBC57 @1995 TI PGE80 TMS320LC50PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320LC50PQ50 NRND BQFP PQ 132 TBD Call TI Call TI TMS320LC50PQ50 @1992 TI TMS320LC50PQ57 OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320LC50PQ57 @1992 TI TMS320LC50PQA OBSOLETE BQFP PQ 132 TBD Call TI Call TI TMS320LC50PQA @1992 TI TMS320LC51PZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LC51PZ57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LC52PZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI @1992 TI TMS320LC52PZ TMS320LC52PZ57 OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LC52PZA OBSOLETE LQFP PZ 100 TBD Call TI Call TI -40 to 85 @1992 TI TMS320LC52PZA TMS320LC53SPZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI TMS320LC53SPZ50 OBSOLETE LQFP PZ 100 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

www.ti.com 11-Jun-2016 Addendum-Page 7 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMS320C50 :

• Enhanced Product: SM320C50-EP
• Military: SMJ320C50 NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic”are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated