TMS320C25FNL50 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 70
Technical content
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristicdataandotherspecificationsaresubjectto changewithoutnotice. Copyright 1991, Texas Instruments Incorporated 80-ns Instruction Cycle Time 544 Words of On-Chip Data RAM 4K Words of On-Chip Secure Program EPROM (TMS320E25) 4K Words of On-Chip Program ROM (TMS320C25) 128K Words of Data/Program Space 32-Bit ALU/Accumulator 16 16-Bit Multiplier With a 32-Bit Product Block Moves for Data/Program Management Repeat Instructions for Efficient Use of Program Space Serial Port for Direct Codec Interface Synchronization Input for Synchronous Multiprocessor Configurations Wait States for Communication to Slow Off-Chip Memories/Peripherals On-Chip Timer for Control Operations Single 5-V Supply Packaging: 68-Pin PGA, PLCC, and CER-QUAD 68-to-28 Pin Conversion Adapter Socket for EPROM Programming Commercial and Military Versions Available NMOS Technology: CMOS Technology:
description
This data sheet provides complete design documentation for the second-generation devices of the TMS320 family. This facilitates the selection of the devices best suited for user applications by providing all specifications and special features for each TMS320 member. This data sheet is divided into four major sections: architecture, electrical specifications (NMOS and CMOS), timingdiagrams, and mechanical data. In each of these sections, generic information is presented first, followed by specific device information. An index is provided for quick reference to specific information about a device. 123456789 1 0 1 1 A B C D E F G H J K L 68-Pin GB Package† (Top View) IACK MSC CLKOUT1 CLKOUT2 XF HOLDA DX FSX X2 CLKIN BR D10 D11 D12 D13 D14 D15 READY CLKR CLKX STRB R/W PS IS DS V SS 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 987654321 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 VSS SYNC INT0 INT1 INT2 VCC DR FSR A10 A11 A12 A13 A14 A15 VSS VCC VCC VCC 68-Pin FN and FZ Packages† (Top View) ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN A0 K1/26 A12 K8/40 D2 E1/16 D14 A5/3 INT2 H1/22 VCC H2/23 A1 K2/28 A13 L9/41 D3 D2/15 D15 B6/2 IS J11/46 VCC L6/35 A2 L3/29 A14 K9/42 D4 D1/14 DR J1/24 MP/MC† A6/1 VSS B1/10 A3 K3/30 A15 L10/43 D5 C2/13 DS K10/45 MSC C10/59 VSS K11/44 A4 L4/31 BIO B7/68 D6 C1/12 DX E11/54 PS J10/47 VSS L2/27 A5 K4/32 BR G11/50 D7 B2/11 FSR J2/25 READY B8/66 XF D11/56 A6 L5/33 CLKOUT1 C11/58 D8 A2/9 FSX F10/53 RS A8/65 X1 G10/51 A7 K5/34 CLKOUT2 D10/57 D9 B3/8 HOLD A7/67 R/W H11/48 X2/CLKIN F11/52 A8 K6/36 CLKR B9/64 D10 A3/7 HOLDA E10/55 STRB H10/49 A9 L7/37 CLKX A9/63 D11 B4/6 IACK B11/60 SYNC F2/19 A10 K7/38 D0 F1/18 D12 A4/5 INT0 G1/20 VCC A10/61 A11 L8/39 D1 E2/17 D13 B5/4 INT1 G2/21 VCC B10/62 † On the TMS32020, MP/MCmust be connected to VCC. SIGNALS I/O/Z‡ DEFINITION VCC VSS X2/CLKIN CLKOUT1 CLKOUT2 D15-D0 A15-A0 PS ,D S,I S R/W STRB RS INT2-INT0 MP/MC MSC IACK READY BR XF HOLD HOLDA SYNC BIO DR CLKR FSR DX CLKX FSX I I O I O O I/O/Z O/Z O/Z O/Z O/Z I I I O O I O O I O I I I I I O/Z I I/O/Z 5-V supply pins Ground pins Output from internal oscillator for crystal Input to internal oscillator from crystal or external clock Master clock output (crystal or CLKIN frequency/4) A second clock output signal 16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/O spaces. 16-bit address bus A15 (MSB) through A0 (LSB) Program, data, and I/O space select signals Read/write signal Strobe signal Reset input External user interrupt inputs Microprocessor/microcomputer mode select pin Microstate complete signal Interrupt acknowledge signal Data ready input. Asserted by external logic when using slower devices to indicate thatthe current bus transaction is complete. Bus request signal. Asserted when the TMS320C2x requires access to an external global data memory space. External flag output (latched software-programmable signal) Hold input. When asserted, TMS320C2x goes into an idle mode and places the data, address, and control lines in the high impedance state. Hold acknowledge signal Synchronization input Branch control input. Polled by BIOZ instruction. Serial data receive input Clock for receive input for serial port Frame synchronization pulse for receive input Serial data transmit output Clock for transmit output for serial port Frame synchronization pulse for transmit. Configuration as either an input or an output. ‡ I/O/Z denotes input/output/high-impedance state.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and flexibility to produce a MOS microprocessor family thatis capable of executing more than 12.5 MIPS (million instructions per section). The TMS320 family optimizes speed by implementing functions in hardware that other processors implement through microcode or software. This hardware-intensive approach provides the design engineer with processing power previously unavailable on a single chip. The TMS320 family consists of three generations of digital signal processors. The first generation contains the TMS32010 and its spinoffs. The second generation includes the TMS32020, TMS320C25, and TMS320E25, which are described in this data sheet. The TMS320C30 isa floating-point DSP device designed for even higher performance. Many features are common among the TMS320 processors. Specific features are added in each processor to provide different cost/performance tradeoffs. Software compatibility is maintained throughout the family to protect the user’s investment in architecture. Each processor has software and hardware tools to facilitate rapid design. introduction The TMS32010, the first NMOS digital signal processor in the TMS320 family, was introduced in 1983. Its powerful instruction set, inherent flexibility, high- speed number-crunching capabilities, and innovative architecture have made this high-performance, cost-effective processor the ideal solution to many telecommunications, computer, commercial, industr ial, and military applications. Since that time, the TMS320C10, a low-power CMOS version of the industry-standard TMS32010, and other spinoff devices have been added to the first generation of the TMS320 family. The second generation of the TMS320 family (referred to as TMS320C2x) includes four members, the TMS32020, TMS320C25, TMS320C25-50, and TMS320E25. The architecture of these devices is based upon that of the TMS32010. The TMS32020, processed in NMOS technology, is source-code compatible with he TMS32010 and in many applications is capable of two times the throughput of the first-generation devices. Its enhanced instruction set (109 instructions), large on-chip data memory (544 words), large memory spaces, on-chip serial port, and hardware timer make the TMS32020 a powerful addition to the TMS320 family. The TMS320C25 is the second member of the TMS320 second generation. It is processed in CMOS technology, is capable of an instruction cycle time of 100 ns, and ispin-for-pin and object-code compatible with the TMS32020. The TMS320C25’s enhanced feature set greatlyincreases the functionality of the device over the TMS32020. Enhancements included 24 additional instructions (133 total), eight auxiliary registers, an eight-level hardware stack, 4K words of on-chip program ROM, a bit-reversed indexed-addressing mode, and the low-power dissipation inherent to the CMOS process. An extended-temperature range version (TMS320C25GBA) is also available. The TMS320C25-50 is a high-speed version of the TMS320C25. It is capable of an instruction cycle time of less than 80 ns. It is architecturally identical to the original 40-MHz version of the TMS320C25 and, thus, is pin-for-pin and object-code compatible with the TMS320C25. The TMS320E25 is identical to the TMS320C25, with the exception that the on-chip 4K-word program ROM is replaced with a 4K-word on-chip program EPROM. On-chip EPROM allows realtime code development and modification for immediate evaluation of system performance.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 Key Features: TMS32020 200-ns Instruction Cycle Time 544 Words of On-Chip Data RAM 128K Words of Total Data/Program Memory Space Wait States for Communication to Slower Off-Chip Memories Source Code Compatible With the TMS320C1x Single-Cycle Multiply/Accumulate Instructions Repeat Instructions Global Data Memory Interface Block Moves for Data/Program Management Five Auxiliary Registers With Dedicated Arithmetic Unit Serial Port for Multiprocessing or Interfacing to Codecs, Serial Analog-to-Digital Converters, etc. Key Features: TMS320C25, TMS320C25-50, TMS320E25 80-ns Instruction Cycle Time (TMS320C25-50) 100-ns Instruction Cycle Time (TMS320C25) 4K Words of On-Chip Secure Program EPROM (TMS320E25) 4K Words of On-Chip Program ROM (TMS320C25) 544 Words of On-Chip RAM 128K Words of Total Program/Data Memory Space Wait States for Communications to Slower Off-Chip Memories Object-Code Compatible With the TMS32020 Source-Code Compatible With TMS320C1x 24 Additional Instructions to Support Adaptive Filtering, FFTs, and Extended-Precision Arithmetic Block Moves for Data/Program Management Single-Cycle Multiply/Accumulate Instructions Eight Auxiliary Registers With Dedicated Arithmetic Unit Bit-Reversed Indexed-Addressing Mode for Radix-2 FFTS Double-Buffered Serial Port On-Chip Clock Generator Single 5-V Supply NMOS Technology 68-Pin Grid Array (PGA) Package On-Chip Clock Generator Single 5-V Supply Internal Security Mechanism (TMS320E25) 68-to-28 Pin Conversion Adapter Socket CMOS Technology 68-Pin Grid Array (PGA) Package (TMS320C25) 68-Lead Plastic Leaded Chip Carrier (PLCC) 68-Lead CER-QUAD Package (TMS320E25) Multiplier 32-BIT ALU/ACC Shifters Timer Interrupts Data (16) Address (16) +5 V GND 32-Bit ALU/ACC Shifters Timer MP/MC Data (16) Address (16) +5 V GND 4K-Words ROM/EPROM Multiplier 256-Word Data/Prog RAM 288-Word Data RAM Interrupts Serial Interface Multi- Processor Interface Serial Interface Multi- Processor Interface 256-Word Data/Prog RAM 288-Word Data RAM
Table 1. TMS320 Second-Generation Device Overview † SER = serial; PAR = parallel; DMA = directmemory access; CON = concurrent DMA. ‡ Military version available; contact nearest TI Field Sales Office for availability. § Military version planned; contact nearest TI Field Sales Office for details. available immediate instructions and subroutines based on computed values. dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing. transfers, communication to slower off-chip devices, and multiprocessing implementations. data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator. contents of the accumulator remain unchanged.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 functional block diagram (TMS320C2x) Data Bus Data Bus 16 16 16 Shifters (0-7)† ACCL(16) ACCH(16) ALU(32) Shifter(-6, 0, 1, 4) Shifter(0-16) 7L S B From IR 1616 TR(16) Multiplier PR(32) DATA/PROG RAM (25616) Block B0 16 16 Data RAM Block B1 (256 16) Block B2 (32 16) ARB(3) ARP(3) ARAU(16) AR4(16) AR3(16) AR2(16) AR1(16) AR0(16) DP(9) FSX CLKX DX FSR CLKR DRR(16) DXR(16) PRD(16) TIM(16) IMR(6) GREG(8) 16 16 IFR(6) RPTC(8) STO(16) ST1(16) IR(16) 16D15-D0 1616 A15-A0 INT(2-0) MP/MC Instruction (8 x 16) 16 16 16 Stack PC(16) IACK RS BIO MSC HOLDA HOLD XF BR STRB R/W Program Bus Program Bus Program ROM/ EPROM (4096 16) QIR(16) 16 16 X2/CLKIN CLKOUT1 CLKOUT2 Controller PFC(16) MCS(16) PS DS IS SYNC MUX MUX MUX MUX MUX MUX MUX DR MUXMUX C READY Address AR5(16) AR6(16) AR7(16) RSR(16) XSR(16) LEGEND: ACCH = Accumulator high IFR = Interrupt flag register PC = Program counter ACCL = Accumulator low IMR = Interrupt mask register PFC = Prefetch counter ALU = Arithmetic logic unit IR = Instruction register RPTC = Repeat instruction counter ARAU = Auxiliary register arithmetic unitMCS = Microcall stack GREG = Global memory allocation register ARB = Auxiliary register pointer buffer QIR = Queue instruction register RSR = Serial port receive shift register ARP = Auxiliary register pointer PR = Product register XSR = Serial port transmit shift register DP = Data memory page pointer PRD = Period register for timer AR 0-AR7 = Auxiliary registers DRR = Serial port data receive registerTIM = Timer ST0, ST1 = Status registers DXR = Serial port data transmit register TR = Temporary register C = Carry bit
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 scaling shifter The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1. 16 16-bit parallel multiplier The 16 16-bit hardware multiplier is capable of computing a signed or unsigned 32-bit product in a single machine cycle. The multiplier has the following two associated registers. A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and A 32-bit Product Register (PR) that holds the product. Incorporated into the instruction set are single-cycle multiply/accumulate instructions that allow both operands to be processed simultaneously. The data for these operations may reside anywhere in internal or external memory, and can be transferred to the multiplier each cycle via the program and data buses. Four product shift modes are available at the Product Register (PR) output that are useful when performing multiply/accumulate operations, fractional arithmetic, or justifying fractional products. timer The TMS320C2x provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM) register is a down counter that is continuously clocked by CLKOUT1 on the TMS320C25. The timer is clocked by CLKOUT1/4 on the TMS32020. A timer interrupt (TINT) is generated every time the timer decrements to zero. The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches zero so that interrupts may be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT 1 on the TMS320C25 or 4 PRD CLKOUT 1 cycles on the TMS32020. memory control The TMS320C2x provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks (B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words (block B0) are programmable as either data or program memory. A data memory size of 544 words allows the TMS320C2x to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed. When using on-chip program RAM, ROM, EPROM, or high-speed external program memory, the TMS320C2x runs at full speed without wait states. However, theREADY line can be used to interface the TMS320C2x to slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM speeds processing while cutting system costs. The TMS320C2x provides three separate address spaces for program memory, data memory, and I/O. The on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon the memory configuration (see Figure 1). The CNFD (configure block B0 as data memory) and CNFP (configure block B0 as program memory) instructions allow dynamic configuration of the memory maps through software. Regardless of the configuration, the user may still execute from external program memory. The TMS320C2x has six registers that are mapped into the data memory space: a serial port data receive register, serial port data transmit register, timer register, period register, interrupt mask register, and global memory allocation register.
Figure 1. Memory Maps
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 interrupts and subroutines The TMS320C2x has three external maskable user interrupts INT2-INT0, available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on two-word boundaries so that branch instructions can be accommodated in those locations if desired. A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle instruction, the interrupt is not processed until the instruction is completed. This mechanism applies to instructions that are repeated and to instructions that become multicycle due to the READY signal. external interface The TMS320C2x supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the processor’s external address and data buses in the same manner as memory-mapped devices. Interface to memory and I/O devices of varying speeds is accomplishedby using the READY line. When transactions are made with slower devices, the TMS320C2x processor waits until the other device completes its function and signals the processor via the READY line. Then, the TMS320C2x continues execution. A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and other serial systems. The interface signals are compatible with codecs and many other serial devices with a minimum of external hardware. The serial port may also be used for intercommunication between processors in multiprocessing applications. The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register (DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same manner as any other data memory location. Each registerhas an external clock, a framing synchronization pulse, and associated shift registers. One method of multiprocessing may be implemented by programming one device to transmit while the others are in the receivemode. The serial port on the TMS320C25 is double-buffered and fully static. multiprocessing The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements and can be used as follows: A standalone processor A multiprocessor with devices in parallel A slave/host multiprocessor with global memory space A peripheral processor interfaced via processor-controlled signals to another device. For multiprocessing applications, the TMS320C2x has the capability of allocating global data memory space and communicating with that space via the BR(bus request) and READY control signals. Global memory is data memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit memory-mapped GREG (global memory allocation register) specifies part of the TMS320C2x’s data memory as global external memory. The contents of the register determine the size of the global memory space. If the current instruction addresses an operand within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY line. The TMS320C2x supports DMA (direct memory access) toits external program/data memory using the HOLD and HOLDAsignals. Another processor can take complete control of the TMS320C2x’s external memory by asserting HOLD low. This causes the TMS320C2x to place its address data and control lines in a high-impedance state, and assert HOLDA. On the TMS320C2x, program execution from on-chip ROM may proceed concurrently when the device is in the hold mode.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 instruction set The TMS320C2x microprocessor implements a co mprehensive instruction set that supports both numeric-intensive signal processing operations as well as general-purpose applications, such as multiprocessing and high-speed control. The TMS32020source code is upward-compatible with TMS320C25 source code. TMS32020 object code runs directly on the TMS320C25. For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary depending upon whether the next data operand fetch is from internal or external memory. Highest throughput is achieved by maintaining data memory on-chip and using either internal or fast external program memory. addressing modes The TMS320C2x instruction set provides three memoryaddressing modes: direct, indirect, and immediate addressing. Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data memory address. Indirect addressing accesses data memory through the auxiliary registers. In immediate addressing, the data is based on a portion of the instruction word(s). In direct memory addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus, memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words. Up to eight auxiliary registers (AR0-AR7) provide flexible and powerful indirect addressing (five on the TMS32020, eight on the TMS320C25). To select a specific auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively. There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding or subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversal addressing (used in FFTs on the TMS320C25 only) with increment or decrement. All operations are performed on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary register and ARP may be modified. repeat feature A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded with either a data memory value (RPT instruction) or animmediate value (RPTK instruction). The value of this operand is one less than the number of times that the next instruction is executed. Those instructions that are normally multicycle are pipelined when using the r epeat feature, and effectively become single-cycle instructions.
instruction set. The symbol (‡) indicates instructions that are not included in the TMS32020 instruction set. Table 2. Instruction Symbols
S NO. WORDS D D D K D D S D S S D D S D S S X D DX S D D D D K D MNEMONIC K INSTRUCTION BIT CODE TMS320SECONDGENERATION DIGITALSIGNALPROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 Table 3. TMS320C25 Instruction Set Summary † These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
Table 3. TMS320C25 Instruction Set Summary (continued) † These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
† These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
† These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
Table 3. TMS320C25 Instruction Set Summary (concluded) † These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 TMS32020 PRODUCT NOTIFICATION Texas Instruments has identified an unusual set of circumstances that will cause the BIT (Test Bit) instruction on the TMS32020 to affect the contents of the accumulator; ideally, the BIT instruction should not affect the accumulator. This set of conditions is: 1. The overflow mode is set (the OVM status register bit is set to one.) 2. And, the two LSBs of the BIT instruction opcode word are zero. a. When direct memory addressing is used, every fourth data word is affected; all other locations are not affected. b. When indirect addressing is used, the two LSBs will be zero if a new ARP is not selected or if a new ARP is selected and that ARP is 0 or 4. 3. And, adding the contents of the accumulator with the contents of the addressed data memory location, shifted by 2(bit code), causes an overflow of the accumulator. If all of these conditions are met, the contents of the accumulator will be replaced by the positive or negative saturation value, depending on the polarity of the overflow. Various methods for avoiding this phenomenon are available: If the TMS32020 is not in the saturation mode when the BIT instruction is executed, the device operates properly and the accumulator is not affected. Execute the Reset Overflow Mode (ROVM) instruction immediately prior to the BIT instruction and the Set Overflow Mode (SOVM) instruction immediately following the BIT instruction. If direct memory addressing is being used during the BIT instructions, reorganize memory so that the page r e l a t i v el o c a t i o n s0 ,4 ,8 ,C ,1 0...a r en o tu s e d . If indirect addressing is being used during the Bit instruction, select a new ARP which is not AR0 or AR4. If necessary, follow the instruction with a LARP AR0 or LARP AR4 to restore the code. Use the Test Bit Specified by T Register (BITT) instruction instead of the BIT instruction. The BITT instruction operates correctly and will not affect the accumulator under any circumstances. Replace TMS32020 with TMS320C25 for ideal pin-to-pIn andobject-code compatibility. The BIT instruction on the TMS320C25 executes properly and will not affect the accumulator under any circumstances.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 development support Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development support products to assist the user in all aspec ts of TMS320 second-generation-based design and development. These products range from development and application software to complete hardware development and evaluation systems. Table 4 lists thedevelopment support products for the second-generation TMS320 devices. System development may begin with the use of the simulator, Software Development System (SWDS), or emulator (XDS) along with an assembler/linker. These tools give the TMS320 user various means of evaluation, from software simulation of the second-generation TMS320s (simulator) to full-speed in-circuit emulation with hardware and software breakpoint trace and timing capabilities (XDS). Software and hardware can be developed simultaneously by using the macro assembler/linker, C compiler, and simulator for software development, the XDS for hardware development, and the Software Development System for both software development and limited hardware development. Many third-party vendors offer additional developmentsupport for the second-generation TMS320s, including assembler/linkers, simulators, high-level languages, applications software, algorithm development tools, application boards, software development boards, and in-circuit emulators. Refer to theTMS320 Family Development Support Reference Guide(SPRU011A) for further information about TMS320 development support products offered by both Texas Instruments and its third-party suppliers. Additional support for the TMS320 products consists ofan extensive library or product and applications documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs). These workshops provide insight into the architecture and the instruction set of the second-generation TMS320s as well as hands-on training with the TMS320development tools. When technical questions arise regarding the TMS320 family, contact the Texas Instruments TMS320 Hotline at (713) 274-2320. Or, keep informed on the latest TI and third-party development support tools by accessing the DSP Bulletin Board Service (BBS) at (713) 274-2323. The BBS serves 2400-, 1200- and 300-bps modems. Also, TMS320 application source code may be downloaded from the BBS.
Table 4. TMS320 Second-Generation Software and Hardware Support Guide (SPRU011A) for the mailing address. IBM is a trademark of International Business Machines Corporation. PC-DOS is a trademark of International Business Machines Corporation. VAX and VMS are trademarks of Digital Equipment Corporation. XDS is a trademark of Texas Instruments Incorporated.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 documentation support Extensive documentation supports the second-generation TMS320 devices from product announcement through applications development. The types of documentation include data sheets with design specifications, complete user’s guides, and 750 pages of application reports published in the book,Digital Signal Processing TMS320C25 (SPRA014A), is available for that device. A series of DSP textbooks is being published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 newsletter,Details on Signal Processing, is published quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board service provides access to large amounts of information pertaining to the TMS320 family. Refer to theTMS320 Family Development Support Reference Guide(SPRU011A) for further information about TMS320 documentation. To receive copies of second-generation TMS320 literature, call the Customer Response Center at 1-800-232-3200. specification overview The electrical specifications for the TMS32020,TMS320C25, TMS320E25, and TMS320C25-50 are given in the following pages. Note that the electrical specifications for the TMS320E25 are identical to those for the TMS320C25, with the addition of EPROM-related spec ifications. A summary of differences between TMS320C25 and TMS320C25-50 specifications immediately follows the TMS320C25-50 specification.
Low-level input voltageVIL VIH TMS320SECONDGENERATION DIGITALSIGNALPROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 absolute maximum ratings over specified temperature range (unless otherwise noted)† † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or anyother conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.75 5 5.25 V VSS Supply voltage 0 V All inputs except CLKIN 2 VCC +0 . 3 V CLKIN 2.4 VCC +0 . 3 V All inputs except CLKIN -- 0 . 3 0.8 V CLKIN -- 0 . 3 0.8 V IOH High-level output current 300 A IOL Low-level output current 2 mA TA Operating free-air temperature (see Notes 1 and 2) 0 70 C NOTES: 1. Case temperature (TC) must be maintained below 90C. 2. RJA =3 6C/Watt, RJC =6 C/Watt. electrical characteristics over specified free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT VOH High-level output voltage VCC =M I N ,IOH =M A X 2.4 3 V VOL Low-level output voltage VCC =M I N ,IOL =M A X 0.3 0.6 V IZ Three-state current VCC =M A X -- 2 0 20 A II Input current VI =V SS to VCC -- 1 0 10 A TA =0 C, VCC = MAX, fx =M A X 360 mA ICC Supply current T A =2 5C, VCC = MAX, fx =M A X 250 mA TC =9 0C, VCC = MAX, fx =M A X 285 mA CI Input capacitance 15 pF CO Output capacitance 15 pF § All typical values for ICC are at VCC =5V ,T A =2 5C. This device contains circuits to protect itsinputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assembliesavailable from Texas Instruments. ADVANCE INFORMATION
The TMS32020 can use either its internal oscillator or an external frequency source for a clock. and be specified at a load capacitance of 20 pF. † Value derived from characterization data; minimum fsx at test = 825 kHz. Figure 2. Internal Clock Option unconnected. The external frequency injected must conform to the specifications listed in the following table.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(C1-S) STRB from CLKOUT1 (if STRBis present) Q- -1 5 Q Q+1 5 ns td(C2-S) CLKOUT2 to STRB(if STRBis present) -- 1 5 0 15 ns tsu(A) Address setup hold time before STRBl o w( s e eN o t e5 ) Q- -3 0 ns th(A) Address hold time after STRBhigh (see Note 5) Q- -1 5 ns tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q ns tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q ns tsu(D)W Data write setup time before STRBhigh (no wait states) 2Q - - 45 ns th(D)W D a t aw r i t eh o l dt i m ef r o mS T R Bhigh Q- -1 5 Q ns ten(D) Data bus starts being driven after STRBlow (write cycle) 0† ns tdis(D) Data bus three-state after STRBhigh (write cycle) Q Q+3 0† ns td(MSC) MSC valid from CLKOUT1 -- 2 5 0 25 ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 5. A15-A0, PS,D S,I S,R / W, and BRtimings are all included in timings referenced as “address”. 6. Delays between CLKOUT1/CLKOUT2 edges and STRBedges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states. timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT ta(A) Read data access time from address time (read cycle, see Notes 5 and 7) 3Q - - 70† ns tsu(D)R Data read setup time before STRBhigh 40 ns th(D)R Data read hold time from STRBhigh 0 ns td(SL-R) READY valid after STRBlow (no wait states) Q- -4 0 ns td(C2H-R) READY valid after CLKOUT2 high Q- -4 0 ns th(SL-R) R E A D Yh o l dt i m ea f t e rS T R Blow (no wait states) Q- -5 ns th(C2H-R) READY hold after CLKOUT2 high Q- -5 ns td(M-R) READY valid after MSCvalid 2Q - - 50 ns th(M-R) READY hold time after MSCvalid 0 ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 5. A15-A0, PS,D S,I S,R / W, and BRtimings are all included in timings referenced as “address”. 7. Read data access time is defined as ta(A) =t su(A) +t w(SL) -- tsu(D)R. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 RS,I N T,B I O, AND XF TIMING switching characteristics over recommended operating conditions (see Note 3 and 8) PARAMETER MIN TYP MAX UNIT td(RS) CLKOUT1 low to reset state entered 45 ns td(IACK) CLKOUT1 to IACKvalid -- 2 5 0 25 ns td(XF) XF valid before falling edge ofSTRB Q- -3 0 ns NOTES: 3. Q = 1/4tc(C). 8. RS,I N T, and BIOare asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur. timing requirements over recommended operating conditions (see Note 3 and 8) MIN NOM MAX UNIT tsu(IN) INT/BIO/RS setup before CLKOUT1 high 50 ns th(IN) INT/BIO/RS hold after CLKOUT1 high 0 ns tf(IN) INT/BIO fall time 15† ns tw(IN) INT/BIO low pulse duration tc(C) ns tw(RS) RS low pulse duration 3tc(C) ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 8. RS,I N T, and BIOare asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur. HOLD TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(C1L-AL) HOLDA low after CLKOUT1 low -- 2 5† 25 ns tdis(AL-A) HOLDA low to address three-state 15† ns tdis(C1L-A) Address three-state after CLKOUT1 low (HOLDmode, see Note 9) 30† ns td(HH-AH) HOLD high to HOLDAhigh 50 ns ten(A-C1L) Address driven before CLKOUT1 low (HOLDmode, see Note 9) 10† ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 9. A15-A0, PS,D S,I S,S T R B, and R/Wtimings are all included in timings referenced as “address.” timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT td(C2H-H) HOLD valid after CLKOUT2 high Q- -4 5 ns NOTE 3: Q = 1/4tc(C). ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(CH-DX) DX valid after CLKX rising edge (see Note 10) 100 ns td(FL-DX) DX valid after FSX falling edge (TXM = 0, see Note 10) 50 ns td(CH-FS) FSX valid after CLKX rising edge (TXM = 1) 60 ns NOTES: 3. Q = 1/4tc(C). 10. The last occurrence of FSX falling and CLKX rising. timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT tc(SCK) Serial port clock (CLKX/CLKR) cycle time 390 20 000† ns tf(SCK) Serial port clock (CLKX/CLKR) fall time 50‡ ns tr(SCK) Serial port clock (CLKX/CLKR) rise time 50‡ ns tw(SCK) Serial port clock (CLKX/CLKR) low pulse duration (see Note 11) 150 12 000 ns tw(SCK) Serial port clock (CLKX/CLKR) high pulse duration (see Note 11) 150 12 000 ns tsu(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) 20 ns th(FS) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) 20 ns tsu(DR) DR setup time before CLKR falling edge 20 ns th(DR) DR hold time after CLKR falling edge 20 ns † Value derived from characterization data; minimum fsx at test = 825 kHz. ‡ Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 11. The duty cycle of the serial port clock must be within 40-60%. ADVANCE INFORMATION
Operating free-air temperature ICC Low-level input voltage T A =0 C, VCC = MAX, fx =M A X mA TMS320SECONDGENERATION DIGITALSIGNALPROCESSORS SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 absolute maximum ratings over specified temperature range (unless otherwise noted)† † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or anyother conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.75 5 5.25 V VSS Supply voltage 0 V All inputs except CLKIN/CLKX/CLKR/INT(0-2) 2.35 VCC +0 . 3 V VIH High-level input voltage INT (0-2) 2.5 VCC +0 . 3 V CLKIN/CLKX/CLKR 3.5 VCC +0 . 3 V All inputs except MP/MC -- 0 . 3 0.8 V MP/MC -- 0 . 3 0.8 V IOH High-level output current 300 A IOL Low-level output current 2 mA TMS320C25, TMS320E25 0 70 C TMS320C25GBA -- 4 0 85 C electrical characteristics over specified free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT VOH High-level output voltage VCC =M I N ,IOH =M A X 2.4 3 V VOL Low-level output voltage VCC =M I N ,IOL =M A X 0.3 0.6 V IZ Three-state current VCC =M A X -- 2 0 20 A II Input current VI =V SS to VCC -- 1 0 10 A Normal 110 185 Idle/HOLD 50 100 CI Input capacitance 15 pF CO Output capacitance 15 pF § All typical values are at VCC =5V ,T A =2 5. Caution. This device contains circuits to protect its inputs and outputs against damage dueto high static voltages or electrostatic fields. These circuits have been qualified to protect this deviceagainst electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions to be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this typeare contained in the publication “Guidelines for Handling Electrostatic-Discharge Sensitive (ESDS) Devicesand Assemblies” available from Texas Instruments ADVANCE INFORMATION
The TMS32025 can use either its internal oscillator or an external frequency source for a clock. LC circuit; see the application report,Hardware Interfacing to the TMS320C25(SPRA014A). unconnected. The external frequency injected must conform to the specifications listed in the following table.
Figure 5. Voltage Reference Levels † Value derived from characterization data and not tested.
- A15-A0, PS,D S,I S,R / W, and BRtimings are all included in timings referenced as “address”.
- Delays between CLKOUT1/CLKOUT2 edges and STRBedges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait
- A15-A0, PS,D S,I S,R / W, and BRtimings are all included in timings referenced as “address”.
- Read data access time is defines as ta(A) =t su(A) +t w(SL) -- tsu(D)R.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 RS,I N T,B I O, AND XF TIMING switching characteristics over recommended operating conditions (see Note 3 and 8) PARAMETER MIN TYP MAX UNIT td(RS) CLKOUT1 low to reset state entered 22† ns td(IACK) CLKOUT1 to IACKvalid -- 6 0 12 ns td(XF) XF valid before falling edge ofSTRB Q- -1 5 ns NOTES: 3. Q = 1/4tc(C). 8. RS ,I N T, and BIOare asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur. timing requirements over recommended operating conditions (see Note 3 and 8) MIN NOM MAX UNIT tsu(IN) INT/BIO/RS setup before CLKOUT1 high 32 ns th(IN) INT/BIO/RS hold after CLKOUT1 high 0 ns tf(IN) INT/BIO fall time 8† ns tw(IN) INT/BIO low pulse duration tc(C) ns tw(RS) RS low pulse duration 3tc(C) ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 8. RS ,I N T, and BIOare asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur. HOLD TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(C1L-AL) HOLDA low after CLKOUT1 low 0 10 ns tdis(AL-A) HOLDA low to address three-state 0† ns tdis(C1L-A) Address three-state after CLKOUT1 low (HOLDmode, see Note 9) 20† ns td(HH-AH) HOLD high to HOLDAhigh 25 ns ten(A-C1L) Address driven before CLKOUT1 low (HOLDmode, see Note 9) 8† ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 9. A15-A0, PS,D S,I S,S T R B, and R/Wtimings are all included in timings referenced as “address.” timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT td(C2H-H) HOLD valid after CLKOUT2 high Q- -2 4 ns NOTE 3: Q = 1/4tc(C). ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(CH-DX) DX valid after CLKX rising edge (see Note 10) 75 ns td(FL-DX) DX valid after FSX falling edge (TXM = 0, see Note 10) 40 ns td(CH-FS) FSX valid after CLKX rising edge (TXM = 1) 40 ns NOTES: 3. Q = 1/4tc(C). 10. The last occurrence of FSX falling and CLKX rising. timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT tc(SCK) Serial port clock (CLKX/CLKR) cycle time† 200 ns tf(SCK) Serial port clock (CLKX/CLKR) fall time 25‡ ns tr(SCK) Serial port clock (CLKX/CLKR) rise time 25‡ ns tw(SCK) Serial port clock (CLKX/CLKR) low pulse duration (see Note 11) 80 ns tw(SCK) Serial port clock (CLKX/CLKR) high pulse duration (see Note 11) 80 ns tsu(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) 18 ns th(FS) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) 20 ns tsu(DR) DR setup time before CLKR falling edge 10 ns th(DR) DR hold time after CLKR falling edge 20 ns † The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to fsx =0H z . ‡ Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C). 11. The duty cycle of the serial port clock must be within 40-60%. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 EPROM PROGRAMMING absolute maximum ratings over specified temperature range (unless otherwise noted)† † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or anyother conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to GND. recommended operating conditions MIN NOM MAX UNIT VCC Programming mode supply voltage (see Note 13) 6 V VCC Read mode supply voltage 4.75 5 5.25 V VPP Programming mode supply voltage 12 12.5 13 V VPP Read mode supply voltage (see Note 12) VCC V NOTES: 12. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC +I PP.D u r i n g programming, VPP must be maintained at 12.5 V ( 0.25 V). 13. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. This device must not be inserted into or removed from the board when VPP or VCC is applied. electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT IPP1 VPP supply current VPP =V CC =5 . 2 5V 100 A IPP2 VPP supply current (during program pulse) VPP =1 3V 30 50 mA § All typical values for ICC are at VCC =5V ,T A =2 5C. recommended timing requirements for programming, TA =2 5C, VCC =6V ,V PP = 12.5 V (see Notes 14 and 15) MIN NOM MAX UNIT tw(IPGM) Initial program pulse duration 0.95 1 1.05 ms tw(FPGM) Final pulse duration 2.85 78.75 ms tsu(A) Address setup time 2 s tsu(E) E setup time 2 s tsu(G) G setup time 2 s tdis(G) Output disable time fromG 0 130¶ ns ten(G) Output enable time fromG 150¶ ns tsu(D) Data setup time 2 s tsu(VPP) VPP setup time 2 s tsu(VCC) VCC setup time 2 s th(A) Address hold time 0 s th(D) Data hold time 2 s ¶ Value derived from characterization data and not tested. programming. 15. Common test conditions apply for tdis(G) except during programming. ADVANCE INFORMATION
TA =0 C, VCC = MAX, fx =M A X mASupply current TMS320C2550 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 absolute maximum ratings over specified temperature range (unless otherwise noted)† † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or anyother conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.75 5 5.25 V VSS Supply voltage 0 V INT0-INT2 2.5 V VIH High-level input voltage CLKIN, CLKX, CLKR 3.5 V Other inputs 2.35 V MP/MC 0.8 V VIL Low-level input voltage CLKIN 0.8 V Other inputs 0.8 V IOH High-level output current 300 A IOL Low-level output current 2 mA TA Operating free-air temperature 0 70 C electrical characteristics over specified free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT VOH High-level output voltage VCC =M I N ,IOH =M A X 2.4 V VOL Low-level output voltage VCC =M I N ,IOL =M A X 0.6 V IZ High-impedance current VCC =M A X -- 2 0 20 A II Input current VI =V SS to VCC -- 1 0 10 A Normal 110 185 Idle, HOLD 50 100 CI Input capacitance 15 pF CO Output capacitance 15 pF § All typical values are at VCC =5V ,T A =2 5C. ADVANCE INFORMATION
The TMS320C25-50 can use either its internal oscillator or an external frequency source for a clock. at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned LC circuit. Figure 6. Internal Clock Option unconnected. The external frequency injected must conform to specifications listed in the following table.
Figure 7. External Clock Option † Value derived from characterization data and not tested.
- CLKIN duty cycle [tr(CI) +t w(CIH)]/tc(CI) must be within 40-60%.
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(C1-S) STRB from CLKOUT (if STRBis present) Q- -5 Q+3 ns td(C2-S) CLKOUT2 to STRB(if STRBis present) -- 2 5 ns tsu(A) Address setup time before STRBl o w( s e eN o t e5 ) Q -- 11 ns tn(A) Address hold time after STRBhigh (see Note 5) Q- -4 ns tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q - - 5 2Q + 2 ns tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q - - 2 2Q + 5† ns tsu(D)W Data write setup time before STRBhigh (no wait) 2Q - - 17 ns th(D)W D a t aw r i t eh o l dt i m ef r o mS T R Bhigh Q- -5 ns ten(D) Data bus starts being driven after STRBlow (write) 0† ns tdis(D) Data bus high-impedance state after STRBhigh, (write) Q Q+1 5† ns td(MSC) MSC valid from CLKOUT1 -- 1 9 ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 5. A15-A0, PS,D S,I S,R / W, and BRtimings are all included in timings referenced as “address”. 6. Delay between CLKOUT1, CLKOUT2, and STRBedges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states. timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT ta(A) Read data access time from address time (see Notes 5 and 7) 3Q - - 30 ns tsu(D)R Data read setup time before STRBhigh 19 ns th(D)R Data read hold time from STRBhigh 0 ns td(SL-R) READY valid after STRBlow (no wait states) Q- -2 1 ns td(C2H-R) READY valid after CLKOUT2 high Q- -2 1 ns th(SL-R) R E A D Yh o l dt i m ea f t e rS T R Blow (no wait states) Q- -1 ns th(C2H-R) READY valid after CLKOUT2 high Q- -1 ns td(M-R) READY valid after MSCvalid 2Q - - 24 ns th(M-R) READY hold time after MSCvalid 0 ns NOTES: 3. Q = 1/4 tc(C) 5. A15-A0, PS,D S,I S,R / W, and BRtimings are all included in timings referenced as “address”. 7. Read data access time is defined as ta(A) =t su(A) +t w(SL) -- tsu(D)R. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 RS,I N T,B I O, AND XF TIMING switching characteristics over recommended operating conditions (see Notes 3 and 16) PARAMETER MIN TYP MAX UNIT td(RS) CLKOUT1 low to reset state entered 22† ns td(IACK) CLKOUT1 to IACKvalid -- 5 7 ns td(XF) XF valid before falling edge ofSTRB Q- -8 ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 16. RS ,I N T,B I Oare asynchronous inputs and can occur at any time during a clock cycle. timing requirements over recommended operating conditions (see Notes 3 and 16) MIN NOM MAX UNIT tsu(IN) INT,B I O,R Ssetup before CLKOUT1 high 25 ns th(IN) INT,B I O,R Shold after CLKOUT1 high 0 ns tf(IN) INT,B I Ofall time 8† ns tw(IN) INT,B I Olow pulse duration tc(C) ns tw(RS) RS low pulse duration 3tc(C) ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 16. RS ,I N T,B I Oare asynchronous inputs and can occur at any time during a clock cycle. HOLD TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(CIL-AL) HOLDA low after CLKOUT1 low 1† 11 ns tdis(AL-A) HOLDA low to address high-impedance 0† ns tdis(CIL-A) Address high-impedance after CLKOUT1 low (HOLDmode, see Note 17) 20† ns td(HH-AH) HOLD high to HOLDAhigh 19 ns ten(A-CIL) Address driven before CLKOUT1 low (HOLDmode, see Note 17) 8† ns † Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 17. A15-A0, PS,D S,S T R B, and R/Wtimings are all included in timings referenced as “address”. timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT td(C2H-H) HOLD valid after CLKOUT2 high Q- -1 9 ns NOTE 3: Q = 1/4 tc(C) ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 3) PARAMETER MIN TYP MAX UNIT td(CH-DX) DX valid after CLKX rising edge (see Note 18) 75 ns td(FL-DX) DX valid after falling edge (TXM = 0, see Note 18) 40 ns td(CH-FS) FSX valid after CLKX raising edge (TXM = 1) 40 ns NOTES: 3. Q = 1/4 tc(C) 18. The last occurrence of FSX falling and CLKX rising. timing requirements over recommended operating conditions (see Note 3) MIN NOM MAX UNIT tc(SCK) Serial port clock (CLKX/CLKR) cycle time† 160 ns tf(SCK) Serial port clock (CLKX/CLKR) fall time 25‡ ns tr(SCK) Serial port clock (CLKX/CLKR) rise time 25‡ ns tw(SCK) Serial port clock (CLKX/CLKR) low or high pulse duration (see Note 19) 64 ns tsu(FS) FSX or FSR setup time before CLKX, CLKR falling edge (TXM = 0) 5 ns th(FS) FSX or FSR hold time before CLKX, CLKR falling edge (TXM = 0) 10 ns tsu(DR) DR setup time before CLKR falling edge 5 ns th(DR) DR hold time after CLKR falling edge 10 ns † The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to fsx =0H z . ‡ Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C) 19. The cycle of the serial port must be within 40%-60%. CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS The following table presents electrical parameters which differ between TMS320C25 (40 MHz, 100 ns) and TMS320C25-50 (50 MHz, 80 ns). clock characteristics and timing TMS320C25 TMS320C25-50 MIN TYP MAX MIN TYP MAX tc(SCK) 97.7 597 78.13 597 ns td(CIH-C) 5 30 12 27 ns tf(C) 5 4 ns tr(C) 5 4 ns tw(CL) 2Q - - 8 2Q 2Q + 8 2Q - - 7 2Q + 3 ns tw(CH) 2Q - - 8 2Q 2Q + 8 2Q - - 3 2Q + 7 ns td(C1-C2) Q- -5 Q Q+5 Q- -6 Q+2 ns tsu(S) 5 Q- -5 4 Q- -4 ns th(S) 8 4 ns ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 memory and peripheral interface timing TMS320C25 TMS320C25-50 MIN TYP MAX MIN TYP MAX td(C1-S) Q- -6 Q Q+6 Q- -5 Q+3 ns tsu(A) Q- -1 2 Q- -1 1 ns th(A) Q- -8 Q- -4 ns tw(SL) 2Q 2Q - - 5 2Q + 2 ns tw(SH) 2Q 2Q - - 2 2Q + 5 ns tsu(D)W 2Q - - 20 2Q - - 17 ns th(D)W Q- -1 0 Q Q- -5 ns td(MSC) -- 1 2 0 12 -- 1 9 ns ta(A) 3Q - - 35 3Q - - 30 ns tsu(D)R 23 19 ns th(D)R 0 0 ns td(SL-R) Q- -2 0 Q- -2 1 ns td(C2H-R) Q- -2 0 Q- -2 1 ns th(SL-R) Q+3 Q- -1 ns th(C2H-R) Q+3 Q- -1 ns td(M-R) 2Q - - 25 2Q - - 24 ns th(M-R) 0 0 ns RS,I N T,B I O, and XF timing TMS320C25 TMS320C25-50 MIN TYP MAX MIN TYP MAX td(IACK) -- 6 0 12 -- 5 7 ns td(XF) Q- -1 5 Q- -8 ns tsu(IN) 32 25 ns th(IN) 0 0 ns HOLD timing TMS320C25 TMS320C25-50 MIN TYP MAX MIN TYP MAX td(C1L-AL) 0 10 1 11 ns td(HH-AH) 25 19 ns td(C2H-H) Q- -2 4 Q- -1 9 ns serial port timing TMS320C25 TMS320C25-50 MIN TYP MAX MIN TYP MAX td(CH-DX) 75 70 ns td(FL-DX) 40 40 ns td(CH-FS) 40 40 ns tsu(FS) 18 5 ns th(FS) 20 10 ns tsu(DR) 10 5 ns th(DR) 20 10 ns ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 TIMING DIAGRAMS This section contains all the timing diagrams for the TMS320 second-generation devices. Refer to the top corner of page for the specific device. Timing measurements are referenced to and from a lowvoltage of 0.8 voltage and a high voltage of 2 volts, unless otherwise noted. clock timing X/2CLKIN SYNC CLKOUT1 STRB CLKOUT2 tc(CI) tf(CI) tr(CI) tw(CIH) tw(CIL) th(S) tsu(S) td(CIH-C) td(CIH-C) tw(CL) tc(C) tw(CH) tf(C)tr(C)td(CIH-C) tc(C) tw(CL) tr(C)tf(C) tw(CH) td(C1-C2) td(CIH-C) td(C1-C2) td(C1-C2) td(C1-C2) tsu(S) ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 memory read timing CLKOUT1 CLKOUT2 STRB A15-A0, BR,P S,D S or IS R/W READY D15-D0 td(C1-S) td(C1-S) td(C2-S)td(C2-S) tsu(A) tw(SL) th(A) tw(SH) td(SL-R) tsu(D)R th(SL-R) th(D)R Data In Valid ta(A) ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 memory write timing CLKOUT1 CLKOUT2 STRB A15-A0, BR,P S,D S or IS R/W READY D15-D0 Valid Data Out tsu(A) th(A) tsu(D)W tdis(D)ten(D) th(D)W ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 one wait-state memory access timing CLKOUT1 CLKOUT2 STRB A15-A0, BR, PS,D S,R / Wor IS MSC READY D15-D0 (For Read Operation) Data In Data Out th(C2H-R) Valid D15-D0 (For Write Operation) td(C2H-R) td(M-R) th(M-R)td(M-R) td(MSC) td(MSC) th(C2H-R) td(C2H-R) th(M-R) ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 reset timing CLKOUT1 RS A15-A0 D15-D0 PS STRB Control Signals† IACK Serial Port Control‡ Fetch Location 0 Begin Program Execution Valid Valid td(RS) tsu(IN) th(IN) tsu(IN) tw(RS) † Control signals are DS,I S,R / W, and XF. ‡ Serial port controls are DX and FSX. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 interrupt timing (TMS32020) CLKOUT1 STRB INT2-INT0 A15-A0 IACK FETCH N FETCH N + 1 FETCH I FETCH I + 1 tsu(IN) th(IN) tw(IN) td(IACK)tf(IN) td(IACK) interrupt timing (TMS320C25) CLKOUT1 STRB INT2-INT0 A15-A0 IACK FETCH N FETCH N + 1 FETCH N + 2 N + 3 tsu(IN) th(IN) tw(IN) td(IACK)tf(IN) td(IACK) FETCH I ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 serial port receive timing tc(SCK) tw(SCK) tw(SCK) tf(SCK) th(DR) th(FS) tsu(DR) tsu(FS) CLKR FSR DR tr(SCK) serial port transmit timing CLKX FSX (Input, TXM = 0) DX FSX (Output, TXM = 1) tc(SCK) tr(SCK)tw(SCK) tf(SCK) tw(SCK) td(CH-DX) th(FS) td(FL-DX) td(CH-DX)tsu(FS) td(CH-FS) td(CH-FS) N=1 N=8 , 1 6 ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 BIO timing CLKOUT1 STRB A15-A0 BIO FETCH BIOZ tsu(IN) th(IN) FETCH Branch Address FETCH Next Instruction P C=N P C=N+1 P C=N+2 P C=N+3 or Branch Address Valid external flag timing CLKOUT1 STRB A15-A0 XF td(XF) P C=N- -1 P C=N P C=N+1 P C=N+2 Valid FETCH SXF/RXF Valid Valid Valid ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 BIO timing CLKOUT1 STRB A15-A0 BIO FETCH BIOZ tsu(IN) th(IN) FETCH Next Instruction P C=N P C=N+1 P C=N+2 or Branch Address Valid FETCH Branch Address external flag timing CLKOUT1 STRB A15-A0 XF td(XF) P C=N P C=N+1 P C=N+2 P C=N+3 ValidFETCH SXF/RXF Valid Valid Valid ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 HOLD timing (part A) CLKOUT1 CLKOUT2 STRB HOLD A15-A0 PS,D S, or IS R/W D15-D0 HOLDA FETCH EXECUTE td(C2H-H)† tdis(C1L-A) tdis(AL-A) td(C1L-AL) In In NN + 1 N + 2 Valid Valid NN + 1N / AN / A N - - 1 N Dummy Dead † HOLD is an asynchronous input and can occur at any time during a clock cycle.If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 HOLD timing (part B) CLKOUT1 CLKOUT2 STRB HOLD A15-A0 PS,D S, or IS R/W D15-D0 HOLDA FETCH EXECUTE td(C2H-H)† In In N+2 N+3 Valid Valid N/A N /A N + 2 N + 3 Dead Dead N + 1 N + 2 ten(A-C1L) td(HH-AH) † HOLD is an asynchronous input and can occur at any time during a clock cycle.If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 HOLD timing (part A) CLKOUT1 CLKOUT2 STRB HOLD A15-A0 PS,D S, or IS R/W D15-D0 HOLDA FETCH EXECUTE td(C2H-H)† tdis(C1L-A) tdis(AL-A) td(C1L-AL) In In NN + 1 N + 2 Valid Valid N N + 1 -- -- N- -2 N - -1 N - - † HOLD is an asynchronous input and can occur at any time during a clock cycle.If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 HOLD timing (part B) CLKOUT1 CLKOUT2 STRB HOLD PS,D S, or IS R/W D15-D0 HOLDA A15-A0 FETCH EXECUTE td(C2H-H)† In N+2 N+2 Valid -- -- -- N + 2 -- -- -- N + 1 ten(A-C1L) td(HH-AH) † HOLD is an asynchronous input and can occur at any time during a clock cycle.If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25 170 160 150 140 130 120 110 100 4 8 12 16 20 24 28 32 36 40 44 48 52 TA =2 5C ICC vs f(CLKIN) and VCC Normal Operating Mode f(CLKIN),M H z VCC =5 . 5 0V VCC =5 . 2 5V VCC =5 . 0 0V VCC =4 . 7 5V VCC =4 . 5 0V Im ACC, 4 8 12 16 20 24 28 32 36 40 44 48 52 I CC vs f(CLKIN) and VCC Powerdown Mode f(CLKIN),M H z Im ACC, VCC =5 . 5 0V VCC =5 . 2 5V VCC =5 . 0 0V VCC =4 . 7 5V VCC =4 . 5 0V TMS320C25FNL (PLCC) reflow soldering precautions Recent tests have identified an industry-wide problem experienced by surface mounted devices exposed to reflow soldering temperatures. This problem involves a package cracking phenomenon sometimes experienced by large (e.g., 68-lead) plastic leaded chip carrier (PLCC) packages during surface mount manufacturing. This phenomenon occur if the TMS320C25FNL is exposed to uncontrolled levels of humidity prior to reflow solder. This moisture can flash to steamduring solder reflow, causing sufficient stress to crack the package and compromise device integrity. If the TMS320C25FNL is being socketed,no special handling precautions are required. In addition, once the device is soldered into the board,no special handling precautions are required. In order to minimize moisture absorption, TI ships the TMS320C25FNL in “dry pack” shipping bags with a RH indicator card and moisture-absorbing desiccant. These moisture-barrier shipping bags will adequately block moisture transmission to allow shelf storage for 12 months from date of seal when stored at less than 60% relative humidity (RH) and less than 30C. Devices may be stored outside the sealed bags indefinitely if stored at less than 25% RH and 30C. Once the bag seal is broken, the devices should be stored at less than 60% RH and 30Ca sw e l la sr e f l o w soldered within two days of removal. In the event that either of the above conditions is not met, TI recommends these devices be baked in a clean oven at 125C and 10% maximum RH for 24 hours. This restores the devices to their “dry packed” moisture level. NOTE Shipping tubes will not withstand the 125C baking process. Devices should be transferred to a metal tray or tube be- fore baking. Standard ESD precautions should be followed. In addition, TI recommends that the reflow process not exceed two solder cycles and the temperature not exceed 220C. If you have any additional questions or concerns, please contact your local TI representative. ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 28,448 (1.120) 27,432 (1.080) 4,953 (0.195) 2,032 (0.080) 3,302 (0.130) 2,794 (0.110) 0,508 (0.020) 0,406 (0.016) 1,575 (0.062) 1,473 (0.058) Dia 2,54 (0.100) T.P. 2,54 (0.100) T.P. 1,524 (0.060) Nom
4 Places
1,27 (0.050) Nom 1,397 (0.055) Max 17,02 (0.670) Nom 17,02 (0.670) Nom 28,448 (1.120) 27,432 (1.080) RJA Junction-to-free-air thermal resistance 36 C/W RJC Junction-to-case thermal resistance 6 C/W PARAMETER MAX UNIT Thermal Resistance Characteristics L K J H G F E D C B A 123456789 1 0 1 1 ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 25,27 (0.995) 25,02 (0.985) 24,33 (0.956) 24,13 (0.950) 0,81 (0.032) 0,66 (0.026) 0,51 (0.020) 0,36 (0.014) 1,52 (0.060) Min 0,64 (0.025) Min 4,50 (0.177) 4,24 (0.167) 2,79 (0.110) 2,41 (0.095) 1,27 (0.050) T.P. (see Note B)0,25 (0.010) R Max
3 Places
(see Note A) 25,27 (0.995) 25,02 (0.985) 24,33 (0.956) 24,13 (0.950) (see Note A) 23,62 (0.930) 23,11 (0.910) (At Seating Plane) 1,35 (0.053) 1,19 (0.047) RJA Junction-to-free-air thermal resistance 46 C/W RJC Junction-to-case thermal resistance 11 C/W PARAMETER MAX UNIT Thermal Resistance Characteristics Seating Plane Lead Detail 1,22 (0.048) 1,07 (0.042) 45 45 0,94 (0.037) 0,69 (0.027) R NOTES: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this dimension. B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side. WARNING When reflow soldering is required, refer to page 54 for special handling instructions. ADVANCE INFORMATION
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES RJA Junction-to-free-air thermal resistance 49 C/W RJC Junction-to-case thermal resistance 8 C/W PARAMETER MAX UNIT Thermal Resistance Characteristics (see Note 1) A (see Note 2) B BA (see Note 2) 1,02 (0.040) 45 0,64 (0.025) R Max 1,27 (0.050) Typ (see Note 3) C (At Seating Plane) 3,05 (0.120) 2,29 (0.090) 4,57 (0.180) 3,94 (0.155) 3,55 (0.140) 3,05 (0.120) 0,51 (0.020) 0,36 (0.014) 0,81 (0.032) 0,66 (0.026) 1,016 (0.040) Min Ref Seating Plane (see Note 4) JEDEC OUTLINE NO. OF TERMINALS TMS320E25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only) This hermetically-sealed chip carrier package consists of a ceramic base, ceramic cap, and a 68-lead frame. Hermetic sealing is accomplished with glass. The FZ package is intended for both socket- or surface- mounting. Having a Sn/Pb ratio of 60/40, the tin/lead-coated leads do not require special cleaning or processing when being surface-mounted. A B C MIN MAX MIN MAX MIN MAX MO-087AA 28 12,32 (0.485) 12,57 (0.465) 10,92 (0.430) 11,56 (0.455) 10,41 (0.410) 10,92 (0.430) MO-087AB 44 17,40 (0.685) 17,65 (0.695) 16,00 (0.630) 16,64 (0.655) 15,49 (0.610) 16,00 (0.630) -- -- -- 68 25,02 (0.985) 25,27 (0.995) 23,62 (0.930) 24,26 (0.955) 23,11 (0.910) 23,62 (0.930) NOTES: 1. Glass is optional, and the diameter is dependent on device application. 2. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by dimension B. 3. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side. 4. The lead contact points are within 0,15 (0.006) of being planar. ADVANCE INFORMATION
provide 68-pin to 28-pin conversion for programming the TMS320E25. Figure 8. EPROM Adapter Socket erasure, fast programming and verification, and EPROM protection and verification. at a time, the high byte first and the low byte second.
paragraphs following the table describe the function of each programming level. Table 5. TMS320E25 Programming Mode Levels † In accordance with TMS27C64. QOUT = byte stored at ADDR; RBIT = ROM protect bit. the TMS320E25, the window should be covered with an opaque label. After erasure (all memory bits in the cell are logic one), logic zeroes are programmed into the desired locations. can be programmed in any order. Programming uses two types of programming pulses: prime and final. The length of the prime pulse is 1 ms. programming routine is complete, all bits are verified with VCC =V PP =5V .
the timing for the program and verify operation. Figure 10. Fast Programming Flowchart
Figure 11. Fast Programming Timing Programming may be inhibited by maintaining a high level input on the Epin or PGMpin. of the EPROM location selected by the value on the address inputs appear on Q8-Q1. selected, Q8-Q1 are placed in the high-impedance state. copyright violations. Table 6 shows the programming levels required for protecting and verifying the EPROM. The paragraphs following the table describe the protect and verify functions.
Table 6. TMS320E25 Protect and Verify EPROM Mode Levels † In accordance with TMS27C64. PULSE = low-going TTL level pulse; RBIT = ROM protect bit. flowchart of Figure 12. The required setups in the figure are detailed in Table 6.
Figure 12. EPROM Protect Flowchart Protect verify is used following the EPROM protect to verify correct programming of the RBIT (see Figure 12). RBIT = 0, the EPROM is protected. The EPROM protect and verify timings are shown in Figure 13.
Figure 13. EPROM Protect Timing
INDEXTMS320SECONDGENERATION DEVICES SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 ADVANCE INFORMATION
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 clock flowcharts key features mechanical data memory microcomputer/microprocessor mode operation conditions overview pin nomenclature pinouts switching characteristics
www.ti.com 5-Oct-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TMS320C25FNA NRND PLCC FN 68 18 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMS320C25FNAR NRND PLCC FN 68 TBD Call TI Call TI TMS320C25FNL NRND PLCC FN 68 18 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMS320C25FNL33 OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS320C25FNLR NRND PLCC FN 68 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMS320C25FNLW OBSOLETE PLCC FN 68 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMS320C25GBA NRND CPGA GB 68 21 TBD AU N / A for Pkg Type TMS320C25GBL NRND CPGA GB 68 21 TBD AU N / A for Pkg Type TMS320C25PHL NRND QFP PH 80 66 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
www.ti.com 5-Oct-2011 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMS320C25 :
- Military: SMJ320C25 NOTE: Qualified Version Definitions:
- Military - QML certified for Military and Defense Applications
Texas InstrumentsIncorporatedand itssubsidiaries(TI)reservetherighttomake corrections,modifications,enhancements,improvements, and otherchanges toitsproductsand servicesatany timeand todiscontinueany productorservicewithoutnotice.Customersshould obtainthelatestrelevantinformationbeforeplacingordersand shouldverifythatsuch informationiscurrentand complete.Allproductsare soldsubjecttoTI’s termsand conditionsofsalesuppliedatthetimeoforderacknowledgment. TIwarrantsperformanceofitshardwareproductstothespecificationsapplicableatthetimeofsaleinaccordancewithTI’s standard warranty.Testingand otherqualitycontroltechniquesareused totheextentTIdeems necessarytosupportthiswarranty.Exceptwhere mandated by governmentrequirements,testingofallparametersofeach productisnotnecessarilyperformed. TIassumes no liabilityforapplicationsassistanceorcustomerproductdesign.Customersareresponsiblefortheirproductsand applicationsusingTIcomponents.To minimizetherisksassociatedwithcustomerproductsand applications,customersshouldprovide adequatedesignand operatingsafeguards. TIdoes notwarrantorrepresentthatany license,eitherexpressorimplied,isgrantedunderany TIpatentright,copyright,mask work right, orotherTIintellectualpropertyrightrelatingtoany combination,machine,orprocessinwhichTIproductsorservicesareused.Information publishedby TIregardingthird-partyproductsorservicesdoes notconstitutea licensefromTItouse such productsorservicesora warrantyorendorsementthereof.Use ofsuch informationmay requirea licensefroma thirdpartyunderthepatentsorotherintellectual propertyofthethirdparty,ora licensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofTIinformationinTIdatabooks ordatasheetsispermissibleonlyifreproductioniswithoutalterationand isaccompanied by allassociatedwarranties,conditions,limitations,and notices.Reproductionofthisinformationwithalterationisan unfairand deceptive businesspractice.TIisnotresponsibleorliableforsuch altereddocumentation.Informationofthirdpartiesmay be subjecttoadditional restrictions. ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyond theparametersstatedby TIforthatproductorservicevoidsall expressand any impliedwarrantiesfortheassociatedTIproductorserviceand isan unfairand deceptivebusinesspractice.TIisnot responsibleorliableforany such statements. TIproductsarenotauthorizedforuse insafety-criticalapplications(suchas lifesupport)where a failureoftheTIproductwouldreasonably be expectedtocause severepersonalinjuryordeath,unlessofficersofthepartieshave executedan agreementspecificallygoverning such use.Buyersrepresentthattheyhave allnecessaryexpertiseinthesafetyand regulatoryramificationsoftheirapplications,and acknowledgeand agreethattheyaresolelyresponsibleforalllegal,regulatoryand safety-relatedrequirementsconcerningtheirproducts and any use ofTIproductsinsuch safety-criticalapplications,notwithstandingany applications-relatedinformationorsupportthatmay be providedby TI.Further,Buyersmust fullyindemnifyTIand itsrepresentativesagainstany damages arisingoutoftheuse ofTIproductsin such safety-criticalapplications. TIproductsareneitherdesignednorintendedforuse inmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsare specificallydesignatedby TIas military-gradeor"enhanced plastic." Onlyproductsdesignatedby TIas military-grademeet military specifications.Buyersacknowledgeand agreethatany such use ofTIproductswhichTIhas notdesignatedas military-gradeissolelyat theBuyer's risk,and thattheyaresolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIproductsareneitherdesignednorintendedforuse inautomotiveapplicationsorenvironmentsunlessthespecificTIproductsare designatedby TIas compliantwithISO/TS 16949 requirements.Buyersacknowledgeand agreethat,iftheyuse any non-designated productsinautomotiveapplications,TIwillnotbe responsibleforany failuretomeet such requirements. FollowingareURLs where you can obtaininformationon otherTexas Instrumentsproductsand applicationsolutions: Products Applications Audio www.ti.com/audio Communicationsand Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP ® Products www.dlp.com Energyand Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocksand Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space,Avionicsand Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportationand Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Videoand Imaging www.ti.com/video RFID www.ti-rfid.com OMAP MobileProcessors www.ti.com/omap WirelessConnectivity www.ti.com/wirelessconnectivity TIE2E Community Home Page e2e.ti.com MailingAddress:Texas Instruments,PostOfficeBox 655303,Dallas,Texas 75265 Copyright© 2011,Texas InstrumentsIncorporated