TMS3000

TMS3000 TI | Alldatasheet

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Technical content

mos TMS 3000 LR-DUAL 25-BIT STATIC SHIFT REGISTER ts! TMS 3001 LR-DUAL 32-BIT STATIC SHIFT REGISTER

features

. Static logic Fy Fs © DC to 1 MHz operation € © Low power dissipation 2 © Push-pull output buffers $ © TTL compatible

description

The TMS 3000 LR and TMS 3001 LR are dual static shift registers. Each device contains two de-to-1-MHz shit regis- ters with independent input and output terminals and common clocks and power. MOS thick-oxide technology is used to fabricate cross-coupled flip-flops for each register bit so that data can be stored indefinitely. Transistors in the device are P-channel enhancement-mode type. All input leeds have zener network protection and all outputs contain low-output-impedance, non-inverting push-pull output buffers ‘Two power supply levels and two clocks are required for operation with a third clock generated internally. Data is tran sferred into the register when the @7 clock is pulsed to logic 1. Data is shifted when the $4 clock is returned to logic 0 and the #2 clock is pulsed to logic 1. Output data appears on the logic 0 to lagic ? transition of the $9 clock. For long term storage, the $1 clock must be held at logic 0 and the $2 clock at logic 1 mechanical data and pin configuration ‘The TMS 3000 LR and TMS 3001 LR are mounted in TO-100 packages. (See MOS/LSI packaging section.) Go) PIN NO. FUNCTION PIN NO. FUNCTION OM40) 1 Input 1 a Clock 2 ©) @ 2 Output 1 7 Vea @) @) 3 Yoo 3 Output 2

4 Clock $3 9 Input 2

CeO) 5 GND (Vss) 10 No connection BOTTOM VIEW logic definition Negative logic is assumed a) Logic 1 = most negative voltage b} Logic 0 = most positive voltage. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ‘Supply voltage Vp range (See Note 1) a . 8 . 8 30 V to 0.3V Phase orfe clock input voltage V1 range (See Note 1) fe : - 30 100.3 Phase two clock input voltage Vg2 range (See Note 1)... a oo -30V 100.3V Power dissipation oe . . tone oe oe ~ . 450 mw 14 Operating free-air temperature range to . oe a . . 55°C to 85°C Storage temperature range... . —55°C to 150°C NOTE 1: These voltage values are with rospect to network ground terminal, Vgg — SSeS PRELIMINARY DATA SHEET: Supplementary data wl be TEXAS INSTRUMENTS 14-29 Published at a later date. POST OFFICE BOX S012 + DALLAS. TEXAS 75222

TMS 3000 LR-DUAL 25-BIT STATIC SHIFT REGISTER TMS 3001 LR- DUAL 32-BIT STATIC SHIFT REGISTER recommended operating conditions “Giamactenisnes nox Tuts Supply wotwweVop a [3 | ‘Supply voltage VGG ee —28 | 29 | Vv Logie 1 data input voltage Vii1) (See Note 21 [ras [a [ev Width of data pulse, tp(gara) (See voltage waveforms) [ov] | Bate seiup Time, tgeiup See vortagewavetormsandNores)SSSC~‘~sCOS Data hold time, thoig (See voltage waveforms and Note 4) ns Logie O clock input voltage Va0iclock) (See Notes 2 and 8) - a 2 Logic T clock input voltage Va ictock) See Notes2and 5) a Fiise time of clock pulse, triciock) (See voltage waveforins) rr Fail time of clock pulse, Tyiciocx) See voltage waveforms) CS 5 Gp clock pulse width, tpig2) (See voltage waveforms) Oat =F Time interval from 99 clock to 91 Glock input pulse, 1921 See waveformsangNowes) | 001 | | 10 | as | Clock repetition rate ie 1 These values are at Vop = —14V. Vag = - 28. and Ta © 28°C. electrical characteristics over operating free-air temperature range (unless otherwise noted) __PARAMETER testconoitionst _| min _| tyet | max | units iho) E29 1 MPH erent nt eter lock Vie -28V, Vog=0¥, | [xj | ino re 2500 7 Von Logic 0 cutput voltage oem on — SS Tc SE i iowoswa tos fas | a Tv VoL Logic 1 output voltage lo = Oma. Vag = -12V. Veg 24, Vorvou"-24¥.) 3g fags | a2 |v Cue 206F, Vinity = -88V Vino * =? V i RoW Output resistance, togicO lon -20mA™ ~— TS | 25 kQ Fo Outpurrenstance,togich Tig = 05 mA a is [7 | ke as 000K, THCY] 14 | 20 mA |p Supply eurent from Vg teeinal* TS 2000 aa pg 2000 LT = 28 [2] 36 [ma gan Maximum diocktomency [ee ee + Uniess otherwise noted, vottages are as shown in the nominal column of the recommended operating conditions (nominal operating voltages). ¥ All typical values are at Ta ~ 25°C.

14.30 Texas INSTRUMENTS

TMS 3000 LR-DUAL 25-BIT STATIC SHIFT REGISTER TMS 3001 LR-DUAL 32-BIT STATIC SHIFT REGISTER ee switching characteristics, Vpp = —14V, Vgg = -28 V, Ry = 10 ma, C, = 20pF, Ty = 25°C min [rye [max | units Propagation delay Une To high Teel Propagation delay time to low level 7 ~ todt romero dam oun ‘See votage veers | = | 475 cm | Cin(pt) Capacitance of 9} clock input Vitg2) = OV, TMS 3001 LR f= 1 MHz a ae * Cin(ga) Includes the capacitance of the internal ¢2 clock. voltage waveforms ov tpldata) DATAINPUT oy a Vit idata) ry | 1 1 Vitidata) ‘setup hold Hletockd >] bk trletock) ov ie en ios whee Vintetock) e1 clock AY sox} _ | -wv_ gS ee VIL clock) so! (top! | lel a esc aS 10% = Ty 4 fT >E | Vittetock) ¢2 CLOCK | l ox Cee fe — wavy LD LI LE 1 | Vitictock) teat ! ‘edo ov sR DATA OUTPUT mu DAT DN rr a fn ~~ Vou Ss - LINE IS CONSIDERED SOLID WHEN RELATED TO DATA INPUT, AND BROKEN BY 25/32 BIT TIME INTERVAL WHEN RELATED TO DATA OUTPUT. SSS TEXAS INSTRUMENTS 1431

TMS 3000 LR-DUAL 25-BIT STATIC SHIFT REGISTER —_— typical characteristics LOGIC 0 OUTPUT VOLTAGE LOGIC 0 OUTPUT VOLTAGE « 4 z LOAD CURRENT < FREE AIR TEMPERATURE s Eo = rs 51 Tan +25°C 8 fs Vpp = -15V Vpp=-14V 5 &4| Voo"-29¥ Vgo--28V $ Vop--4V oT ‘Ss 3 | 2 E31 _ V@b+-12V 5 { 3 3 | Veo = -24V 3 a @ -10 g 2 : Fa lg=—4mA g z- _ 3, = r 1 l= -2 mA ; L — es 5! & = 1m So 1 ° 5 10 16 —75-55 o +85 «+125 Von - LOGIC 0 OUTPUT VOLTAGE - V Ta — FREE-AIR TEMPERATURE ~ °C LOGIC 1 OUTPUT VOLTAGE LOGIC 1 OUTPUT VOLTAGE « a LOAD CURRENT FREE AIR TEMPERATURE dss Tan 425°C s

4 Voo=-12¥ Vop=-14¥ Vop=-15V sg

Fe Voo"-24V Vog=-28V Vec=-29¥0 Fay) 5

5 SA NX 3-15

3 2 lo = Hi mA 5 +3 5 ee, 2 0 * 12 ma 2 3-0 em a? z | 2 Fa 3 3-5 z” 5 Vop=-14V ; T Vgc ~ -28V 2° 3 0 2 ° 5 -10 -15 > —75 -85 oO 485 (+125 Von — LOGIC 1 OUTPUT VOLTAGE — V Tq — FREE-AIR TEMPERATURE — °C typical application data 1) MOS/TTL interface With proper supply voltages, interfacing can be achieved with only three resistors. A typical MOS/TTL interface is shown below. An input pull-up resistor is required to provide the necessary input voltage swing. The value of this resistor (R) depends on the actual circuit requirements — values as low as 1 OQ can be used for high-speed operation, while values as high as 15 kQ can be used when low power consumption is important rather than high-speed.

14.32 TEXAS INSTRUMENTS

TMS 3000 LR-DUAL 25-BIT STATIC SHIFT REGISTER TMS 3001 LR-DUAL 32-BIT STATIC SHIFT REGISTER typical application data (continued) wy 4 (cLocK _— BV p—+——1 Sr priver + y ¥ -t- pata ! etock Stock “SS Re ie 1 INPUT Pp TMS 3000 LR OR DATA L 4 ‘TMS 3001 LR sour i P+— output = Yoo Vi [[ssvezs ata g¢__Voo ne — INPUT f LL pata fait L swr400 av 0 = ouTPUT > uy At the output interface, the 9.1-k®2 resistor sinks the 1.6 mA of TTL gate current when 0 volts is required on the TTL input. When 3 volts is required on the TTL input, the MOS output device supplies current from 14 volts, through the 3.9-kQ resistor and the 9.1-k& resistor to —14 volts. The 3.9-kQ resistor limits the voltage at the TTL gate input to 5 volts maximum. 2) Two-phase clock generator 3N7400 snare MASTER CLOCK IN o evoce |SN7473 (SEE NOTE A) 8N7400 ‘SN7416 @2 CLOCK @1 CLOCK Sf NOTE A: THE J. K, AND CLEAR INPUTS ARE TIED TO Vcc THROUGH A 2 k2 REBISTOR. TEXAS INSTRUMENTS 14-33

TMS 3000 LR-DUAL 25-BIT STATIC SHIFT REGISTER TMS 3001 LR-DUAL 32-BIT STATIC SHIFT REGISTER expansion to single 50- or 64-bit register CLOCK $1 CLOCK 92 CLOCK Ves DATA INPUT © 1 DATA INPUT 1 DATA OUTPUT 2 2 TMS 3000 LR OR TMS 3001 LR |

9 DATA INPUT 2 DATA OUTPUT 2 © DATA OUTPUT

i Yoo Yoo : schematic (each register) og FIRST SIT LAST BIT ures GENERATOR ae LF Vea Yoo 2 ° oe eee cock ee y of - cal ° ---+ cLOCK 3 z VW ay --5 08 ! z 1 S DATA in ae \\ 6 Vss V — Vss BUS a ene 14-34 TEXAS, INSTRUMENTS ar saree at te wre ee tiem pele! iingament rowr onmice aox seis « onuste, TEXAS 7228 vette to meno DSH 10" HPAL THE HST DEY PSS