TMS27C128-1JE

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Copyright  1993, Texas Instruments Incorporated This Data Sheet is Applicable to All TMS27C128s and TMS27PC128s Symbolized with Code “B” as Described on Page 12.

• Organization... 16K × 8
• Single 5-V Power Supply
• Pin Compatible With Existing 128K MOS ROMs, PROMs, and EPROMs
• All Inputs/Outputs Fully TTL Compatible
• Max Access/Min Cycle Times VCC ± 10% ’27C128-12 120 ns ’27C/PC128-15 150 ns ’27C/PC128-20 200 ns ’27C/PC128-25 250 ns
• Power Saving CMOS Technology
• Very High-Speed SNAP! Pulse Programming
• 3-State Output Buffers
• 400-mV Minimum DC Noise Immunity With Standard TTL Loads
• Latchup Immunity of 250 mA on All Input and Output Lines
• Low Power Dissipation (VCC = 5.25 V) – Active... 158 mW Worst Case – Standby... 1.4 mW Worst Case (CMOS Input Levels)
• PEP4 Version Available With 168-Hour Burn-In and Choices of Operating Temperature Ranges
• 128K EPROM Available With MIL-STD-883C Class B High-Reliability Processing (SMJ27C128)

description

The TMS27C128 series are 131 072-bit, ultraviolet-light erasable, electrically programmable read-only memories. The TMS27PC128 series are 131 072-bit, one time electrically programmable read-only memories. VPP A12 DQ0 DQ1 DQ2 GND V CC PGM A13 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 J AND N PACKAGES (TOP VIEW) 3213 2 3 1 A11 NC G A10 E DQ7 DQ6 NC DQ0 43 0 15 16 17 18 19DQ1 DQ2 V NU DQ3 DQ4 A12 V NU V PGM A13 FM PACKAGE (TOP VIEW) 20DQ5 CC SS PIN NOMENCLATURE PP A0–A13 Address Inputs E Chip Enable/Powerdown G Output Enable GND Ground NC No Connection NU Make No External Connection PGM Program DQ0–DQ7 Inputs (programming)/Outputs VCC 5-V Power Supply VPP 12-13 V Programming Power Supply PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external resistors. The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C128 and the TMS27PC128 are pin compatible with 28-pin 128K MOS ROMs, PROMs, and EPROMs. The TMS27C128 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C128 is offered with two operating temperature ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). The TMS27C128 is also offered with 168-hour burn-in temperature ranges (JL4 and JE4 suffixes). (See table below). The TMS27PC128 PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC128 is also supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). The TMS27PC128 is also offered with two operating temperature ranges of 0°C to 70°C (NL and FML suffixes) and –40°C to 85°C (NE and FME suffixes). The TMS27PC128 is also offered with 168 hour burn-in temperature ranges (NL4, FML4, NE4, and FME4 suffixes). (See table below). All package styles conform to JEDEC standards. SUFFIX FOR OPERATING TEMPERATURE RANGES WITHOUT PEP4 BURN-IN SUFFIX FOR OPERATING TEMPERATURE RANGES WITH PEP4 168 HR. BURN-IN 0°C TO 70°C –40 °C TO 85°C 0°C TO 70°C –40 °C TO 85°C TMS27C128-XXX JL JE JL4 JE4 TMS27PC128-XXX NL NE NL4 NE4 TMS27PC128-XXX FML FME FML4 FME4 These EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in microprocessor-based systems. One other 12-13-V supply is needed for programming . All programming signals are TTL level. These devices are programmable by using the SNAP! Pulse programming algorithm.The SNAP! Pulse programming algorithm uses a VPP of 13.0 V and a VCC of 6.5 V for a nominal programming time of two seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random.

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 operation The seven modes of operation are listed in the following table. Read mode requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode. MODE READ OUTPUT DISABLE STANDBY PROGRAMMING VERIFY PROGRAM INHIBIT SIGNATURE MODE E VIL VIL VIH VIL VIL VIH VIL G VIL VIH X† VIH VIL X VIL PGM VIH VIH X VIL VIH X VIH VPP VCC VCC VCC VPP VPP VPP VCC VCC VCC VCC VCC VCC VCC VCC VCC A9 X X X X X X VH VH ‡ A0 X X X X X X VIL VIH CODE DQ0–DQ7 Data Out HI-Z HI-Z Data In Data Out HI-Z MFG DEVICE 97 83 † X can be VIL or VIH. VH = 12 V± 0.5 V.

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 read/output disable When the outputs of two or more TMS27C128s or TMS27PC128s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7. latchup immunity Latchup immunity on the TMS27C128 and TMS27PC128 is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup without compromising performance or packing density. power down Active I CC supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level inputs) by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance state. erasure (TMS27C128) Before programming, the TMS27C128 EPROM is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to assure that all bits are at the logic high level. Logic lows are programmed into the desired locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum ultraviolet light exposure dose (UV intensity × exposure time) is 15-W⋅s/cm 2. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C128, the window should be covered with an opaque label. initializing (TMS27PC128) The one-time programmable TMS27PC128 PROM is provided with all bits at the logic high level. The logic lows are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased. SNAP! Pulse programming The 128K EPROM and PROM are programmed using the TI SNAP! Pulse programming algorithm, illustrated by the flowchart in Figure 1, which programs in a nominal time of two seconds. Actual programming time will vary as a function of the programmer used. Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, PGM is pulsed. The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs pulses per byte are provided before a failure is recognized. The programming mode is achieved when VPP = 13 V, VCC = 6.5 V, G = VIH, and E = VIL. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with VCC = VPP = 5 V. program inhibit Programming may be inhibited by maintaining a high level input on the E or PGM pin.

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 program verify Programmed bits may be verified with VPP = 13 V when G = VIL, E = VIL, and PGM = VIH. signature mode The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by A0; i.e., A0 = VIL accesses the manufacturer code, which is output on DQ0–DQ7; A0 = VIH accesses the device code, which is output on DQ0–DQ7. All other addresses must be held at VIL. The manufacturer code for these devices is 97, and the device code is 83.

Figure 1. SNAP! Pulse Programming Flowchart

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 logic symbol† A0 10 G 22 DQ011 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 EPROM 16 384 × 8 A ∇ A ∇ A ∇ A ∇ A ∇ A ∇ A ∇ [PWR DWN] EN A 16 383 DQ719A ∇ A10 A11 A12 16 383 A0 10 G 22 DQ011 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 PROM 16 384 × 8 A ∇ A ∇ A ∇ A ∇ A ∇ A ∇ A ∇ [PWR DWN] EN A DQ719A ∇ A10 A11 A12 26A13 26A13 20E E 20 PGM 27 PGM 27 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are J and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Operating free-air temperature range (’27C128-_ _JL and JL4, ’27PC128-_ _NL, and NL4 Operating free-air temperature range (’27C128-_ _JE and JE4, ’27PC128-_ _NE, NE4, ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage Read mode (see Note 2) 4.5 5 5.5 VVCC Supply voltage SNAP! Pulse programming algorithm 6.25 6.5 6.75 V VPP Supply voltage Read mode VCC – 0.6 VCC + 0.6 VVPP Supply voltage SNAP! Pulse programming algorithm 12.75 13 13.25 V VIH High level dc input voltage TTL 2 VCC +1 VVIH High-level dc input voltage CMOS VCC –0.2 VCC +1 V VIL Low level dc input voltage TTL –0.5 0.8 V VIL Low-level dc input voltage CMOS –0.5 0.2 V TA Operating free-air temperature ’27C128-_ _JL,JL4 ’27PC128_ _NL,NL4 FML, FML4 0 70 °C TA Operating free-air temperature ’27C128-_ _JE,JE4 ’27PC128_ _NE,NE4 FME, FME4 –40 70 °C NOTES: 2. V CC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied. electrical characteristics over full ranges of operating conditions PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High level dc output voltage IOH = –2.5 mA 3.5 V VOH High-level dc output voltage IOH = –20 µA VCC –0.1 V VOL Low level dc output voltage IOL = 2.1 mA 0.4 V VOL Low-level dc output voltage IOL = 20 µA 0.1 V II Input current (leakage) VI = 0 to 5.5 V ±1 µA IO Output current (leakage) VO = 0 to VCC ±1 µA IPP1 VPP supply current VPP = VCC = 5.5 V 1 10 µA IPP2 VPP supply current (during program pulse) VPP = 13 V 35 50 mA ICC1 VCC supply current (standby) TTL-input level VCC = 5.5 V, E = VIH 250 500 µA ICC1 VCC supply current (standby) CMOS-input level VCC = 5.5 V, E = VCC 100 250 µA VCC = 5.5 V, E = VIL, ICC2 VCC supply current (active) t cycle = minimum cycle time, 15 30 mA outputs open † Typical values are at TA = 25°C and nominal voltages. capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz‡ PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT C i Input capacitance VI = 0, f = 1 MHz 6 10 pF C O Output capacitance VO = 0, f = 1 MHz 10 14 pF † Typical values are at TA = 25°C and nominal voltages. Capacitance measurements are made on sample basis only.

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics over full ranges of recommended operating conditions (see Notes 3 and 4) PARAMETER TEST CONDITIONS ’27C128-12 ’27C/PC128-15 UNITPARAMETER TEST CONDITIONS (SEE NOTES 3 AND 4) MIN MAX MIN MAX UNIT ta(A) Access time from address 120 150 ns ta(E) Access time from chip enable C L = 100pF 120 150 ns ten(G) Output enable time from G C L = 100 F,

1 Series 74 TTL Load, 55 75 ns

tdis Output disable time from G or E, whichever occurs first† Input tr ≤ 20 ns, Input tf≤ 20 ns 0 45 0 60 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first† In ut tf ≤ 20 ns 0 0 ns TEST CONDITIONS ’27C/PC128-20 ′27C/PC128-25 UNIT(SEE NOTES 3 AND 4) MIN MAX MIN MAX UNIT ta(A) Access time from address 200 250 ns ta(E) Access time from chip enable C L = 100pF 200 250 ns ten(G) Output enable time from G C L = 100 F,

1 Series 74 TTL Load, 75 100 ns

tdis Output disable time from Go r E, whichever occurs first† Input tr ≤ 20 ns, Input tf≤ 20 ns 0 60 0 60 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first† In ut tf ≤ 20 ns 0 0 ns † Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested. switching characteristics for programming:VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 3) PARAMETER MIN NOM MAX UNIT tdis(G) Output disable time from G 0 130 ns ten(G) Output enable time from G 150 ns recommended timing requirements for programming: VCC = 6.5 V and V PP =13 V (SNAP! Pulse), TA = 25°C (see Note 3) MIN NOM MAX UNIT tw(IPGM) Initial program pulse durationSNAP! Pulse programming algorithm 95 100 105 µs tsu(A) Address setup time 2 µs tsu(E) E setup time 2 µs tsu(G) G setup time 2 µs tsu(D) Data setup time 2 µs tsu(VPP) VPP setup time 2 µs tsu(VCC) VCC setup time 2 µs th(A) Address hold time 0 µs th(D) Data hold time 2 µs NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (reference page 10). 4. Common test conditions apply for tdis except during programming.

† tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer. 13-V VPP and 6.5-V VCC for SNAP! Pulse programming. Figure 4. Program Cycle Timing

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 device symbolization This data sheet is applicable to all TI TMS27C128 CMOS EPROMs and TMS27PC128 PROMs with the data sheet revision code “B” as shown below. B L X P YY WW TMS 27C128 TI FML TMS27PC128 B L X P YY WW Data Sheet Revision Code Wafer Fab Code Die Revision Code Assembly Site Code Year of Manufacture Month of Manufacture

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS128E–OCTOBER 1984–REVISED JANUARY 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TYPICAL TMS27C/PC128 CHARACTERISTICS —Standby Supply CurrentI (Normalized) CC1 1.50 1.25 1.00 0.75 0.50 STANDBY SUPPLY CURRENT vs SUPPLY VOLTAGE VCC — Supply Voltage — V —Standby Supply CurrentI (Normalized) CC1 1.50 1.25 1.00 0.75 0.50 STANDBY SUPPLY CURRENT vs FREE-AIR TEMPERATURE T A — Free-Air Temperature — °C –75 –50 –25 0 25 50 75 100 125 VCC = 5 V TA = 25 °C — Active Supply CurrentI (Normalized) CC2 — Active Supply CurrentI (Normalized) CC2 1.50 1.25 1.00 0.75 0.50 ACTIVE SUPPLY CURRENT vs SUPPLY VOLTAGE V CC — Supply Voltage — V TA = 25 °C f = Max 1.50 1.25 1.00 0.75 0.50 ACTIVE SUPPLY CURRENT vs FREE-AIR TEMPERATURE T A — Free-Air Temperature — °C –75 –50 –25 0 25 50 75 100 125 VCC = 5 V — Access TimeT (Normalized) A — Acctss TimeT (Normalized) A 1.50 1.25 1.00 0.75 0.50 ACCESS TIME vs SUPPLY VOLTAGE V CC — Supply Voltage — V TA = 25 °C 1.50 1.25 1.00 0.75 0.50 ACCESS TIME vs FREE-AIR TEMPERATURE T A — Free-Air Temperature — °C –75 –50 –25 0 25 50 75 100 125 VCC = 5 V

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