TMS27C040_08 TI1 | Alldatasheet
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/C0084/C0077/C0083/C0050/C0055/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0089 SMLS040F − NOVEMBER 1990 − REVISED SEPTEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization. . . 524288 by 8 Bits /C0068Single 5-V Power Supply /C0068Industry Standard 32-Pin Dual In-Line Package and 32-Lead Plastic Leaded Chip Carrier /C0068All Inputs/Outputs Fully TTL Compatible /C0068Static Operation (No Clocks, No Refresh) /C0068Max Access/Min Cycle Time VCC ± 10% ’27C/PC040-10 100 ns ’27C/PC040-12 120 ns ’27C/PC040-15 150 ns /C00688-Bit Output For Use in Microprocessor-Based Systems /C0068Power-Saving CMOS Technology /C00683-State Output Buffers /C0068400-mV Assured DC Noise Immunity With Standard TTL Loads /C0068Latchup Immunity of 250 mA on All Input and Output Pins /C0068No Pullup Resistors Required /C0068Low Power Dissipation (VCC = 5.5 V) − Active. . . 275 mW Worst Case − Standby. . . 0.55 mW Worst Cas E (CMOS-Input Levels) /C0068Temperature Range Options
description
The TMS27C040 devices are 524288 by 8-bit (4194304-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs). The TMS27PC040 devices are 524288 by 8-bit (4194304-bit), one-time programmable (OTP) electrically programmable read-only memories (PROMs). These devices are fabricated using CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by the Series 74 TTL circuits. Each output can drive one Series 74 TTL circuit without external resistors. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 321 3 2 3 1 43 0 15 16 17 18 1920 TMS27C040 J PACKAGE (TOP VIEW) PIN NOMENCLATURE A0−A18 Address Inputs DQ0−DQ7 Inputs (programming)/Outputs E Chip Enable G Output Enable GND Ground VCC 5-V Supply VPP 13-V Power Supply† † Only in program mode. VPP A16 A15 A12 DQ0 DQ1 DQ2 GND V CC A18 A17 A14 A13 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A14 A13 A11 G A10 E DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 A12 A15 A16 V A18 A17 TMS27PC040 FM PACKAGE (TOP VIEW) DQ6 PP GND VCC Copyright 1997, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
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is offered with two choices of temperature ranges of 0°C to 70°C (JL suffix) and −40°C to 85°C (JE suffix). Table 1. Temperature Range Suffixes signals are TTL level. For programming outside the system, existing EPROM programmers can be used. TTL level except for VPP during programming (13 V), and VH (12 V) on A9 for the signature mode. Table 2. Operation Modes devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins. Latchup immunity on the TMS27C040 and TMS27PC040 is a minimum of 250 mA on all inputs and outputs. without compromising performance or packing density.
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state. lamp must be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. programmed into the desired locations. A programmed low can be erased only by UV light. the desired locations. Logic lows programmed into an OTP PROM cannot be erased. programming sequence is shown in the SNAP! Pulse programming flow chart shown in Figure 1. programmed only once before going to interactive mode. all bytes are verified with VCC = VPP = 5 V ± 10%. Programming can be inhibited by maintaining high level inputs on the E and G pins. Programmed bits can be verified with VPP = 13 V when G = VIL, and E = VIH. code 97 (Hex), and A0 high selects the device code 50 (Hex), as shown in Table 3. Table 3. Signature Mode
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Figure 1. SNAP! Pulse Programming Flow Chart
/C0084/C0077/C0083/C0050/C0055/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0089 SMLS040F − NOVEMBER 1990 − REVISED SEPTEMBER 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 logic symbol† [PWR DWN] EN A A A A A A A A A10 A11 A12 A13 A14 A15 A16 E G EPROM 524 288 × 8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A 0 524 287 A17 A18 31 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers are for the J package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND.
/C0084/C0077/C0083/C0050/C0055/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0089 SMLS040F − NOVEMBER 1990 − REVISED SEPTEMBER 1997
6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage Read mode (see Note 2) 4.5 5 5.5 V VCC Supply voltage SNAP! Pulse programming algorithm 6.25 6.5 6.75 V VPP Supply voltage Read mode VCC − 0.6 VCC + 0.6 V VPP Supply voltage SNAP! Pulse programming algorithm 12.75 13 13.25 V VIH High-level dc input voltage TTL 2 VCC + 0.5 V VIH High-level dc input voltage CMOS VCC − 0.2 VCC + 0.5 V VIL Low-level dc input voltage TTL − 0.5 0.8 V VIL Low-level dc input voltage CMOS − 0.5 0.2 V TA Operating free-air temperature ’27C040-_ _JL ’27PC040-_ _FML 0 70 °C TA Operating free-air temperature ’27C040-_ _JE −4 0 85 °C NOTE 2: V CC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level dc output voltage IOH = − 400 µA 2.4 VVOH High-level dc output voltage IOH = − 20 µA VCC − 0.1 V VOL Low-level dc output voltage IOL = 2.1 mA 0.4 VVOL Low-level dc output voltage IOL = 20 µA 0.1 V II Input current (leakage) VI = 0 V to 5.5 V ±1 µA IO Output current (leakage) VO = 0 V to VCC ±1 µA IPP1 VPP supply current VPP = VCC = 5.5 V 10 µA IPP2 VPP supply current (during program pulse) VPP = 12.75 V 50 mA ICC1 VCC supply current (standby) TTL-Input level VCC = 5.5 V, E = VIH 1 mA ICC1 VCC supply current (standby)CMOS-Input level VCC = 5.5 V, E = VCC 100 µA ICC2 VCC supply current (active) E = VIL,V CC = 5.5 V tcycle = minimum cycle time, outputs open† 50 mA † Minimum cycle time = maximum access time. capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz‡ PARAMETER TEST CONDITIONS MIN TYP § MAX UNIT C i Input capacitance VI = 0 V 4 8 pF C o Output capacitance VO = 0 V 8 12 pF ‡ All typical values are at TA = 25°C and nominal voltages. § Capacitance measurements are made on sample basis only.
/C0084/C0077/C0083/C0050/C0055/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0089 SMLS040F − NOVEMBER 1990 − REVISED SEPTEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 switching characteristics over recommended ranges of operating conditions (see Notes 3 and 4) PARAMETER TEST CONDITIONS ’27C040-10 ’27PC040-10 ’27C040-12 ’27PC040-12 ’27C040-15 ’27PC040-15 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT ta(A) Access time from address 100 120 150 ns ta(E) Access time from chip enable C L = 100 pF, 100 120 150 ns ten(G) Output enable time from G C L = 100 pF,
1 Series 74
TTL load, 50 50 50 ns tdis Output disable time from G or E, whichever occurs first TTL load, Input tr ≤ 20 ns, Input tf ≤ 20 ns 0 50 0 50 0 50 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first† Input tf ≤ 20 ns 0 0 0 ns † Value calculated from 0.5-V delta to measured output level. NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low. (See Figure 2) 4. Common test conditions apply for tdis except during programming. switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 3) PARAMETER MIN MAX UNIT tdis(G) Output disable time from G 0 100 ns ten(G) Output enable time from G 150 ns NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low. (See Figure 2) timing requirements for programming MIN NOM MAX UNIT tw(PGM) Pulse duration, program SNAP! Pulse programming algorithm 95 100 105 µs tsu(A) Setup time, address 2 µs tsu(E) Setup time, E 2 µs tsu(G) Setup time, G 2 µs tsu(D) Setup time, data 2 µs tsu(VPP) Setup time, VPP 2 µs tsu(VCC) Setup time, VCC 2 µs th(A) Hold time, address 0 µs th(D) Hold time, data 2 µs
8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
NOTES: A. C L includes probe and fixture capacitance. 0.8 V for logic low for both inputs and outputs. Figure 2. AC Testing Output Load Circuit and Waveform Figure 3. Read-Cycle Timing
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
/C0084/C0077/C0083/C0050/C0055/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0089 SMLS040F − NOVEMBER 1990 − REVISED SEPTEMBER 1997
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER 4040201-4/B 03/95 0.020 (0,51) 0.015 (0,38) Seating Plane 0.140 (3,56) 0.132 (3,35) 0.123 (3,12) 0.129 (3,28) 0.043 (1,09) 0.049 (1,24) 0.008 (0,20) NOM 0.595 (15,11) 0.553 (14,05) 0.585 (14,86) TYP 0.030 (0,76) 0.547 (13,89) 301 0.495 (12,57) 0.453 (11,51) 0.485 (12,32) 0.447 (11,35) 0.050 (1,27) 0.004 (0,10) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-016
/C0084/C0077/C0083/C0050/C0055/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0048/C0052/C0048 /C0053/C0050/C0052/C0050/C0056/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0089 SMLS040F − NOVEMBER 1990 − REVISED SEPTEMBER 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 J (R-CDIP-T) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 4040084/B 04/95 B C 0.018 (0,46) MIN 0.125 (3,18) MIN 0.022 (0,56) 0.008 (0,20) Seating Plane A WIDE A PINS DIM MAX MIN NARR MIN MAX B C MAX MIN NARR WIDE NARR WIDE WIDE NARR
24 PIN SHOWN
0.045 (1,14) 0.065 (1,65) 0.090 (2,29) 0.060 (1,53) Lens Protrusion 0.010 (0,25) MAX 0.175 (4,45) 0.140 (3,56) 0.100 (2,54) 0°−/C0257 10° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
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