TMS27C020-15JE

TMS27C020 TI | Alldatasheet

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TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization...2 6 2 1 4 4 b y 8 Bits /C0068Single 5-V Power Supply /C0068Operationally Compatible With Existing Megabit EPROMs /C0068Industry Standard 32-Pin Dual-In-line Package and 32-Lead Plastic Leaded Chip Carrier /C0068All Inputs/Outputs Fully TTL Compatible /C0068±10% V CC Tolerance /C0068Max Access/Min Cycle Time VCC ± 10% ’27C/PC020-10 100 ns ’27C/PC020-12 120 ns ’27C/PC020-15 150 ns ’27C/PC020-20 200 ns ’27C/PC020-25 250 ns /C00688-Bit Output For Use in Microprocessor-Based Systems /C0068Very High-Speed SNAP! Pulse Programming /C0068Power Saving CMOS Technology /C00683-State Output Buffers /C0068400 mV Minimum DC Noise Immunity With Standard TTL Loads /C0068Latchup Immunity of 250 mA on All Input and Output Pins /C0068No Pullup Resistors Required /C0068Low Power Dissipation (VCC = 5.5 V) – Active... 165 mW Worst Case – Standby... 0.55 mW Worst Case (CMOS-Input Levels) /C0068Temperature Range Options

description

The TMS27C020 series are 262144 by 8-bit (2097152-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs). The TMS27PC020 series are one-time program- mable (OTP) electrically programmable read-only memories (PROMs). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 321 3 2 3 1 43 0 15 16 17 18 19 20 J PACKAGE (TOP VIEW) PIN NOMENCLATURE A0–A17 Address Inputs DQ0–DQ7 Inputs (programming)/Outputs E Chip Enable G Output Enable GND Ground PGM Program VCC 5-V Power Supply VPP 13-V Power Supply† †O n l y in program mode VPP A16 A15 A12 DQ0 DQ1 DQ2 GND V CC PGM A17 A14 A13 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A14 A13 A11 G A10 E DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 A12 A15 A16 V PGM A17 TMS27PC020 FM PACKAGE (TOP VIEW) DQ6 CC VPP GND Copyright  1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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temperature ranges of 0° to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). See Table 1. and – 40°C to 85°C (FME suffix). See Table 1. Table 1. Temperature Range Suffixes are TTL level. For programming outside the system, existing EPROM programmers can be used. Table 2. Operation Modes

TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 read/output disable When the outputs of two or more TMS27C020s or TMS27PC020s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from competing outputs of the other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins. latchup immunity Latchup immunity on the TMS27C020 and TMS72PC020 is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup without compromising performance or packing density. power down Active I CC supply current can be reduced from 30 mA to 500 µA by applying a high TTL input on E and to 100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state. erasure Before programming, the TMS27C020 is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity × exposure time) is 15-W⋅s/cm 2. A typical 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C020, the window should be covered with an opaque label. After erasure (all bits in logic high state), logic lows are programmed into the desired locations. A programmed low can be erased only by ultraviolet light. SNAP! Pulse programming The TMS27C020 and TMS27PC020 are programmed using the TI SNAP! Pulse programming algorithm, illustrated by the flowchart in Figure 1, which programs in a nominal time of twenty-six seconds. Actual programming time varies as a function of the programmer used. The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to ten 100-µs pulses per byte are provided before a failure is recognized. The programming mode is achieved when V PP equals 13 V, VCC = 6.5 V, E = VIL, G = VIH. Data is presented in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, PGM is pulsed low. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with V CC = VPP = 5 V ± 10%. program inhibit Programming can be inhibited by maintaining a high level input on the E or PGM pins. program verify Programmed bits can be verified with VPP equals 13 V when G = VIL, E = VIL, and PGM = VIH. signature mode The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must be held low. The signature code for the TMS27C020 is 9732. A0 low selects the manufacturer’s code 97 (Hex), and A0 high selects the device code 32 (Hex), as shown in Table 3.

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Table 3. Signature Mode

Figure 1. SNAP! Pulse Programming Flowchart

TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997

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logic symbol† A0 12 A10 A11 A12 A13 A14 A15 A16 E G DQ013 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 EPROM 262 144 × 8 A ∇ A ∇ A ∇ A ∇ A ∇ A ∇ A ∇ A ∇ DQ721 [PWR DOWN] EN A17 30 17 A 0 262 143 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers are for the J package.

TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage Read mode (see Note 2) 4.5 5 5.5 V VCC Supply voltage SNAP! Pulse programming algorithm 6.25 6.5 6.75 V VPP Supply voltage Read mode VCC –0.6 VCC VCC +0.6 V VPP Supply voltage SNAP! Pulse programming algorithm 12.75 13 13.25 V VIH High level dc input voltage TTL 2 VCC +0.5 VVIH High-level dc input voltage CMOS VCC –0.2 VCC +0.5 V VIL Low level dc input voltage TTL –0.5 0.8 VVIL Low-level dc input voltage CMOS –0.5 GND+0.2 V TA Operating free-air temperature ’27C020-_ _JL, ’27PC020-_ _FML 0 70 °C TA Operating free-air temperature ’27C020-_ _JE, ’27PC020-_ _FME – 40 85 °C NOTE 2: V CC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied. electrical characteristics over full ranges of operating conditions PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High level dc output voltage IOH = –20 µA VCC – 0.2 VVOH High-level dc output voltage IOH = – 2 mA 2.4 V VOL Low level dc output voltage IOL = 2.1 mA 0.4 VVOL Low-level dc output voltage IOL = 20 µA 0.1 V II Input current (leakage) VI = 0 V to 5.5 V ±1 µA IO Output current (leakage) VO = 0 V to VCC ±1 µA IPP1 VPP supply current VPP = VCC = 5.5 V 10 µA IPP2 VPP supply current (during program pulse) VPP = 13 V 50 mA ICC1 VCC supply current (standby) TTL-input level VCC = 5.5 V, E = VIH. . . 500 µAICC1 VCC supply current (standby) CMOS-input level VCC = 5.5 V, E = VCC ± 0.2 V 100 µA ICC2 VCC supply current (active) VCC = 5.5 V, E = VIL tcycle = minimum cycle time, outputs open† 30 mA † Minimum cycle time = maximum access time.

TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997

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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz† PARAMETER TEST CONDITIONS MIN NOM ‡ MAX UNIT C I Input capacitance VI = 0 V, f = 1 MHz 4 8 pF C O Output capacitance VO = 0 V, f = 1 MHz 6 10 pF † Capacitance measurements are made on sample basis only. ‡ All typical values are at TA = 25°C and nominal voltages. switching characteristics over full ranges of recommended operating conditions (see Notes 3 and 4) TEST ’27C020-10 ’27C020-12 ’27C020-15 27C020-20 ’27C020-25 PARAMETER TEST CONDITIONS ’27PC020-10 ’27PC020-12 ’27PC020-15 27PC020-20 ’27PC020-25 UNITCONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX ta(A) Access time from address 100 120 150 200 250 ns ta(E) Access time from chip en- able 100 120 150 200 250 ns ten(G) Output enable time from G CL = 100 pF,

1 Series 74

E, whichever occurs first† TTL load, Input tr ≤ 20 ns, Input tf ≤ 20 ns 0 50 0 50 0 60 0 60 0 80 ns tv(A) Output data valid time after change of ad- dress, E, or G, whichever oc- curs first§ 0 0 0 0 0 ns § Value calculated from 0.5-V delta to measured output level. This parameter is sampled and not 100% tested. NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low. (See Figure 2). 4. Common test conditions apply for tdis except during programming.

TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 3) PARAMETER MIN MAX UNIT tdis(G) Output disable time from G 0 100 ns ten(G) Output enable time from G 150 ns NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (See Figure 2). timing requirements for programming MIN TYP MAX UNIT tw(PGM) Pulse duration, program SNAP! Pulse programming algorithm 95 100 105 µs tsu(A) Setup time, address 2 µs tsu(E) Setup time, E 2 µs tsu(G) Setup time, G 2 µs tsu(D) Setup time, data 2 µs tsu(VPP) Setup time, VPP 2 µs tsu(VCC) Setup time, VCC 2 µs th(A) Hold time, address 0 µs th(D) Hold time, data 2 µs

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NOTES: A. C L includes probe and fixture capacitance. Figure 2. The ac Testing Output Load Circuit and Waveform Figure 3. Read-Cycle Timing

† tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer. ‡ 13-V VPP and 6.5-V VCC for SNAP! Pulse programming. Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)

TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997

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FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER 4040201-4/B 03/95 0.020 (0,51) 0.015 (0,38) Seating Plane 0.140 (3,56) 0.132 (3,35) 0.123 (3,12) 0.129 (3,28) 0.043 (1,09) 0.049 (1,24) 0.008 (0,20) NOM 0.595 (15,11) 0.553 (14,05) 0.585 (14,86) TYP 0.030 (0,76) 0.547 (13,89) 301 0.495 (12,57) 0.453 (11,51) 0.485 (12,32) 0.447 (11,35) 0.050 (1,27) 0.004 (0,10) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-016

TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 J (R-CDIP-T) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 4040084/B 04/95 B C 0.018 (0,46) MIN 0.125 (3,18) MIN 0.022 (0,56) 0.008 (0,20) Seating Plane A WIDE A PINS DIM MAX MIN NARR MIN MAX B C MAX MIN NARR WIDE NARR WIDE WIDE NARR

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0.045 (1,14) 0.065 (1,65) 0.090 (2,29) 0.060 (1,53) Lens Protrusion 0.010 (0,25) MAX 0.175 (4,45) 0.140 (3,56) 0.100 (2,54) 0°–10° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

TMS27C020 262144 BY 8-BIT UV ERASABLE TMS27PC020 262144 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997

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