TMS2532 TI | Alldatasheet
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Mos TMS 2532-30 JL, TMS 2532-35 JL, LsI TMS 2532-45 JL, TMS 25L32-45 JL 32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES DECEMBER 1979-REVISED MAY 1982 © Organization... 4096 X 8 24PIN CERAMIC © Single +5 V Power Supply DUAL.IN-LINE PACKAGE (ToP view) © Pin Compatible with Existing ROMs and EPROMs (8K, 16K, 32K, and 64K) ar 1 bs veo @ =JEDEC Standard Pinout Ae 2 O23 as © All Inputs/Outputs Fully TTL Compatible as 3 Qe p22 ao © Static Operation (No Clocks, No Refresh) a4 4 Oe 2! ver © Max A /Min Cycle Ti A3 5) Sammi 420 PO/PGM lax Access/Min Cycle Time: He a TMS 2532-30 300 ns a ot & B ip'e Ar TMS 2532-35 350 ns AL 7a 5 RR pe An TMS 2532-45 450 ns ao 8C] Mmmm [O17 os TMS 25132-45 450 ns Q1 9 Cbmvemenercemeced[] 16 07 © 8-Bit Output for Use in Microprocessor- Q2 10 fis a6 Based Systems 03 11 Ge 14 os © N-Channel Silicon-Gate Technology Vss_ 12 Cp ee 13 04 © 3-State Output Buffers © 40% Lower Power IND ‘Address inpute TMS 25132 . . . 500 mW Max Active Porm Power Down/Program TMS 2532 . . . 840 mW Max Active an) Input/Output © Guaranteed DC Noise Immunity with Yee +5 'V Power Supply Standard TTL Loads vep +25 V Power Supply Vss 0V Ground © No Pull-Up Resistors Required
description
The TMS 2532 series (TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL, and TMS 25L32-45 JL) are 32,768-bit, ultraviolet-light-erasable, electrically programmable read-only memories. These devices are fabricated us- ing N-channel silicon-gate technology for high speed and simple interface with MOS and bipolar circuits. All inputs (in- cluding program data inputs) can be driven by Series 74 TTL circuits without the use of external pull-up resistors, and each output can drive one Series 74 TTL circuit without external resistors. The data outputs are three-state for con- necting multiple devices to a common bus. The TMS 2532 series are plug-in compatible with the TMS 4732 32K ROM. The devices are offered in a dual-in-line ceramic package (JL suffix) rated for operation from 0°C to 70°C. ‘Since these EPROMs operate from a single + 5 V supply (in the read mode), they are ideal for use in microprocessor ‘systems. One other (+ 25 V) supply is needed for programming but all programming signals are TTL level, requiring a ‘single 50 ms pulse. For programming outside of the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. Total programming time for all bits is 200 seconds. a TEXAS INSTRUMENTS 145 INCORPORATED POST OFFICE BOX 225012 © DALLAS, TEXAS 75265
TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL, TMS 25132-45 JL 32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES operation ree = ee Tako J Disable Programming POTPEM vic Vin Vin Paised Vin Vi (20) to Vy Vee +5V +8 +5 +25V +25 Vee WV BV wv BV Vv (20 a (9 to 11, 131017) read/output disable ‘When the outputs of two or more TMS 2532's are connected on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. The device whose output is to be read should have a low-level TTL signal applied to the PD/PGM Pin. Alll other devices in the circuit should have their outputs disabled by applying a high-level signal to this pin. Output data is accessed at pins Q1 through Q8. Data can be accessed in 450 ns = ta(a)- power down Active power dissipation can be cut by over 70% by applying a high TTL signal to the PD/PGM pin. In this mode all out- puts are in a high-impedance state. erasure Before programming, the TMS 2532 is erased by exposing the chip through the transparent lid to high-intensity ultraviolet light having @ wavelength of 253.7 nm (2537 angstroms). The recommended minimum exposure dose (UV intensity times exposure time) is fifteen watt-seconds per square centimeter. Thus, a typical 12 milliwatt per square centimeter, filterless UV lamp will erase the device in a minimum of 21 minutes. The lamp should be located about 2.5 centimeters above the chip during erasure. After erasure, all bits are in the ‘1"" state (assuming high-level output cor- responds to logic “1’’). start programming After erasure (all bits in logic "1" state), logic ‘0's’ are programmed into the desired locations. A ‘O"’ can be erased only by ultraviolet light. The programming mode is achieved when Vpp is 25 V. Data is presented in parallel (8 bits) on pins Q1 through QB. Once addresses and data are stable, a 50-millisecond TTL low-level pulse should be applied to the PGM pin at each address location to be programmed. Maximum pulse width is 55-milliseconds. Locations can be pro- grammed in any order. Several TMS 2532's can be programmed simultaneously when the devices are connected in parallel. inhibit programming When two or more devices are connected in parallel, data can be Programmed into all devices or only chosen devices. Any TMS 2532's not intended to be programmed should have a high level applied to PD/PGM. Program verification The TMS 2532 program verification is simply the read operation, which can be performed as soon as Vpp returns to +5 V ending the program cycle.
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TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL, TMS 25132-45 JL 32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES ——— logic symbolt EPROM A096x8 ‘A0- 3) 0 At it) (6) ” (5) 9) a1 a3. Aton (4) Av a2 aa Oo as: ar ape **L om gy ac 4095 AY ay a Ay] ‘5 ar (15) (23) ay 06 As: (16) 7 at al une, “e 7 pe All. (18) 11, aay _(20) PoPa— he _Jiowe pwn} Laden * This symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and IEC, See ‘explanation on page 289. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)* Supply voltage, Vcc (see Note 1) tee . oe eeeee -0.3t06V Allinput voltages (see Note 1) nae . Pan . aoe vee. =O.3t06V Output voltage (operating with respect to Vgs) nee . wae ee . -0.3t06V Operating free-air temperature range . 0°C to 70°C ‘Storage temperature range aoe . . . - 55°C to 125°C. NOTE 1: Under absolute maximum ratings, voltge values are with respect to the most negative supply voltage, Veg (substrate) "Stresses beyond those listed under Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional not implied. Exposure to absoite-maximum-rated conditions for extended periods may affect device vehabaty TEXAS INSTRUMENTS 147 INCORPORATED POST OFFICE BOX 225012 # DALLAS, TEXAS 75205
recommended operating conditions TMS 2532.30 TMS 2532.35 TMS 25132.45 Supply voltage, Vcc (see Note 2) 4755 525 [475 6 5.25 Suppiy vorage, Vpp (see Note 3) Supply voltage, Ves a High-level input voltage, Vin 22 Veo+i| 2 Veet Low-level input voltage, Vit [Foy 0.68 [0.1 08 Read cycle time, tered a Operating free-air temperature, Ta NOTES 2. Voc must be applied betore or tthe sme time as Vpp nd removed alter ora the same time as Vpp. The device must not be inserted int or removed from the board when Vpp is apotied 3. Vpp.canbe connected to Voc directly except inthe rogram mode). Voc Supp eUrent in thi case would be Ic + pp. During programming, Vpp must be maintanes a 28 V1 Vi electrical characteristics over full ranges of recommended operating conditions TMS 2532-30 TEST CONDITIONS TMS 2532-35 Tws 28132-45 | UNIT TMS 2532.45 MIN Tye! Max | MIN TyP? MAX Von High-level output vottage* | Ion= — 400 4A foe fea Vou — tew-level output votage* | lop =2.1 mA [ oas [oas Tv 1|___Input current (eakege! Vi=0 Vor 6.28V [to [10 ae] ig Output current leakage? | Vo=0.4 Vor 525 [to [10 a] ipp1_Vep supply curent Vpp=8.25V, POPOM=Vi | St | SSS | ma Vep supply current — \\ PO/PGM =v Voc supply current — \\ POrPGM= ma ICC1 (standby) " Voc supply curent — Iec2 Cc Supply currer PD/PGM = Vi. 80 160 (active) *AC ond OC measurements are made at 10% ond 90% points using a 50% pater, capacitance over recommended supply voltage and operating free-air temperature ranges, f= 1 MHzt [____ranameren TEST CONDITIONS tet wax | unr | Vi=0V, 11 MHz { 4 6 | oF | Vo=0V. f= 1 Mie [os 2 TF | ‘Typical values are Ta = 25°C and nominal voltages. * Capacitance measurements are made on a sample basis only. sa
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TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL, TMS 25132-45 JL 32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES switching characteristics over full ranges of recommended operating conditions (see note 4) TEST TMs 25132-45 PARAMETER CONDITIONS ims 2532-35 _| TMs 2532.45 | UNIT (See Notes 4 & 5) ‘Access time 'etA) from address CL=100 pF, ‘Access time 1 Series 74 Output data valid tr <20 ns, ‘IA) after address change t<20 ns, Output disable time See Figure 1 a a TAll typical values are at Ta = 25°C and nominal voltages. * Value calculated from 0.5 volt delta to measured output level, recommended timing requirements for programming Ta = 25°C (see note 4) [eanameren dara | on] | twer) Pulse width prowram pulse *d;a 8 | om | | Supa) Rise te, program pulse Te] | Rupr) Fal time, program pute ae] [sway —Adorons setup tine | tsuioy Date setup tine a ie | tsuiver) Setup time trom Vp oe [ tna) Aaess Rot tme [ tnioy Date ote ime ae [ thier) Program pulse hold ime 0 Lnwep) Vee hold time fo oe] ‘Typical values are at nominal voltages. NOTES: 4, For atawitching characteristics and timing measurements, input pulse levels are 0.65 V 102.2 Vand Vpp=25V + 1 V during programming. All AC and DC measurements are mage at 10% and 90% points with « 50% pattern 5. Common test conditions apply for tyig except during programming. For taia nd tai, PO/PGM = Vi. See PARAMETER MEASUREMENT INFORMATION v-2.09 v Ay-780 0 ourur UNDER TEST F CL=100 pF FIGURE 1 — TYPICAL OUTPUT LoaD CIRCUIT -—-eere eo ie TEXAS INSTRUMENTS 149 INCORPORATED POST OFFICE 80x 225012 # DALLAS. TEXAS 75705
TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL, TMS 25132-45 JL 32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES OE read cycle timing Pi 4 Vin ADDRESSES vin | way Vin PomPGM l\\ L/\\ | Mn | | j beeen | bese v eee " f+ tains —o standby mode t Vin ADDRESSES ADDRESS N , ADDRESS N+ m vi ' \\ \\ — I PO/PGM vin 1 STANDBY ACTIVE etic — fi tarnyt | Vou 01.08 VALI +. — vaLiD Vou "taipn referenced to PO/PGM or the address, whichever occurs last. All timing reference points in this data sheet (inputs and outputs) are 90% Points. se
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TMS 2532-30 JL, TMS 2532-35 JL, TMS 2532-45 JL, TMS 25132-45 JL 32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES ——— | Program cycle timing neeieuen! oT erie vi avoress " (aoness vin | Nem 14) —4} pa $4 | PoiPam i frisene| fl i I vn | 1 | 4s Hewed bol LE | y, EY RRR ‘PRI | Ni Ln ‘ectweny | fs . vv SRY iI | | Vow/in word pe ord a | | 1-8 DATA IN mz “Program verity equivalent to raed mode TEXAS INSTRUMENTS 151 INCORPORATED POST OFFICE BOX 225012 © DALLAS, TEXAS 75265