TMS2516 TI | Alldatasheet
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MOS TMS 2516-25 JL, TMS 2516-35 JL AND TMS 2516-45 JL LSI 16,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES DECEMBER 1979-REVISED MAY 1982 © Organization... 2048 X 8 ° 24-IN CERPAK Single +5 V Power Supply DUAL-IN-LINE PACKAGE © Pin Compatible with Existing ROMs and (TOP VIEW) EPROMs (16K, 32K, and 64K) eapaanaoas © emma: © JEDEC Standard Pi Al 1 Ee 24 Veo tandard Pinout AG 20 23 as © All Inputs/Outputs Fully TTL Compatible as 3 Qe 22 ao © Static Operation (No Clocks, No Refresh) Aa 4 Chernin 21 Vep @ Max Access/Min Cycle Time a3 5 gem }f20 cs a2 6H & Bm fD19 A10 — TMS 2516-25... 250 ns He] = pD/PGM — TMS 2516-35... 350 ns a. 7h § A ip’? — TMS 2516-45... 450 ns ao 8} MRNNNMR j}17 08 © 8-Bit Output for Use in Microprocessor-Based O19 Cptrterreemmmerrery) 16 07 5 Systems 2 10 Gee 18 6 Ce Ba 8 © N-Channel Silicon-Gate Technology oN See Vsg 12 F304 © 3-State Output Buffers SE © Low Power - Active . . . 285 mW Typical AN) ‘Address inputs - Standby . . . 50 mW Typical S Chip Select PO/PGM Power Down/Program © Guaranteed DC Noise Immunity with Standard ain) Input/Output TTL Loads Vec 45.V Power Supply © No Pull-Up Resistors Required Vee 428 V Power Supply Vss 0 V Ground
description
The TMS 2516 series are 16,384-bit, ultraviolet light erasable, electrically programmable read-only memories. These devices are fabricated using N-channel silicon-gate technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the use of ex- ternal pull-up resistors, and each output can drive one Series 74 TTL circuit without external resistors. The data out- puts are three-state for connecting multiple devices to a common bus. The TMS 2516 is plug-in compatible with the TMS 4016 16K static RAM. It is offered in a dual-in-line cerpak package (JL suffix) rated for operation from 0°C to 70°C. ‘Since these EPROMs operate from a single +5 V supply (in the read mode), they are ideal for use in microprocessor systems. One other ( +25 V) supply is needed for programming but all programming signals are TTL level, requiring a single 50-ms pulse. For programming outside of the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. Total programming time for all bits is 100 seconds. TEXAS INSTRUMENTS 137 INCORPORATED POST OFFICE BOX 225012 © DALLAS, TEXAS 75265
16,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES operation Disable ° PO/PGM Vit Vin Pulsed Vip Vit Vit 18) Vin A Ver 5V BV 75 25V BV +25 (21) (or +8) Vee 78V +5 +5V +5 1V 48 (24) a (81011, 131017) read/output disable When the outputs of two or more TMS 2516's are connected to the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. The device whose output is to be read should have a low-level TTL signal applied to the CS and PD/PGM pins. All other devices in the circuit should have their outputs disabled by applying high-level signals to these same pins. PD/PGM can be left low, but it ‘may be advantageous to power down the device during output disable. Output data is accessed at pins Q1 through Q8. On the TMS 2516-45 data can be accessed in 450 ns and access time from CS is 150 ns, On the TMS 2516-35 and TMS 2516-26 data can be accessed in 350 and 250 (respectively) and access time from CS is 120 ns. These ac- cess times assume that the addresses are stable. power down Active power dissipation can be cut by 80% by applying a high TTL signal to the PD/PGM pin. In this mode all outputs are in a high-impedance state. erasure Before programming, the TMS 2516 is erased by exposing the chip through the transparent lid to high-intensity ultraviolet light having a wavelength of 253.7 nm (2537 angstroms). The recommended minimum exposure dose (UV intensity times exposure time) is fifteen watt-seconds per square centimeter. Thus, a typical 1 2-milliwatt per-square- centimeter, filterless UV lamp will erase the device in a minimum of 21 minutes. The lamp should be located about 2.5 Centimeters above the chip during erasure. After erasure, all bits are in the ‘'1"’ state (assuming a high-level output cor- responds to logic “"1"). start programming After erasure (all bits in logic "1 state), logic '"0's"’ are programmed into the desired locations. A ““O'" can be erased only by ultraviolet light. The programming mode is achieved when Vp is 25 V and CS is at Vi. Data is presented in Parallel (8 bits) on pins Q1 through Q8. Once addresses and data are stable, a 50-millisecond TTL high-level pulse should be applied to the PGM pin at each address location to be programmed. Maximum pulse width is 55 milliseconds. Locations can be programmed in any order. Several TMS 2516's can be programmed simultaneously when the devices are connected in parallel. cr
138 TEXAS INSTRUMENTS
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TMS 2516-25 JL, TMS 2516-35 JL AND TMS 2516-45 JL 16,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES ee inhibit programming When two or more devices are connected in parallel, data can be programmed into all devices or only chosen devices. TMS 2516's not intended to be programmed (i.e., inhibited) should have a low level applied to the PD/PGM pin and a high-level applied to the CS pin program verification A verification is done to see if the device was programmed correctly. A verification can be done at any time. It can be done on each location immediately after that location is programmed. To do a verification, Vpp may be kept at +25 V. logic symbolt EPROM 20005 a0 ° a a2 (9) (5) av 1 a3. (10) @ av 2 Aa m (3) AT a3 as ano 3) 2 a7 AY o4 as. (14) im ay 05 ar 415) (23 ay 08 a8 6) no 2 ay 7 a7) 9 ag 8 A10" (19) 10, ‘PD/PGM- 18) (PWR DWN] 1 This eymbol isin accordance with IEEE Std 91/ANSI ¥22.14 and recent dacisions by IEEE and IEC. See explanation on page 289, absolute maximum ratings over operating free-air temperature range (unless otherwise noted) * Supply voltage, Vcc (see Note 1) -0.3t06V Supply voltage, Vpp (see Note 1) eee bees . . -0.3t028V Allinput voltages (see Note 1) . . -0.3to6V Output voltage (operating with respect to Vs) vos. -0,.3t06V Operating free-air temperature range 0°C to 70°C Storage temperature range . cee veces ee . . -55°C to 125°C * Stresses beyond those listed under ‘Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional ee TEXAS INSTRUMENTS 139 INCORPORATED POST OFFICE BOX 228012 # DALLAS, TEKAS 75265
TMS 2516-25 JL, TMS 2516-35 JL AND TMS 2516-45 JL 16,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES recommended operating conditions TMS 2516-25 TMS 2516-35 TMS 2516-45 UNIT min NOM Max | MIN NOM MAX | MIN” NOM. MAX Supply votage, Voc wee Note 2) | 4.75 8 8.25 | 475 6 528] 478 5 525 SE Sa tase. a High-evel input voltage, Vig | _2vegs |? vecrt | 2 Veert Low-level input voltage, Vit =o4 oe [=ot oe [=o1 O68 NOTES: 2. Voc must be applied before or atthe same tine as Vpp and removed after or at the ame ine a Vpp. The device must not be merad nto or tamoved trom the board when Vpp or Vcc aplog 2. Vpp-canbe connected to Vcc rectly except inthe program mode). Voc suppl curentin this case would be leg + lp. During programming Vpp must be maintained at 25 V(1V1 electrical characteristics over full ranges of recommended operating conditions [PanamereR | TEST CONDITIONS Min _Tyet_max]unr | Von Hishievel output voliage™ TON = 400 nA [2s sv | [Vou tower otine® [toy = 1 wa or [pet caren Weakage) [vy = 09 88 aor 19 Output current (leakage) [Vo = O.4Vt0526V Cd SSCS | nn] 'ppy___Vpp supply current Ver = 5.25V, PD/PGM = V, Pg | ma] VPP supply current
1 PorPGM = Vv;
\\ PorPGM - Vv) ct (standby) i tH toca VEOsupety erent 3 = PDIPGM = Vip 57 100 [- | * Typical values are at Ta = 25°C and nominal voltage. "All AC and DC measurements are made at 10% and 90% Points with a 50% pattern. capacitance over recommended supply voltage and operating free-air temperature ranges, f= 1 MHz* [| __Panameren Tes CONDITIONS tyet max] unit | [_So_Ouroutcapasitonee TT vosoviisimme Cd | | All typical values are Tq = 25°C and nominal voltage eee se
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switching characteristics over full ranges of recommended operating conditions (see Note 4) PARAMETER TEST CONDITIONS | TMS 251626 | TMS 251636 | TMS ISTE | (SEE NOTES 4 AND 5) | MIN TYP’ MAX | MIN TYP’ MAX | MIN TYP? MAX tala) Access time from address [230 250] 250 350] 280 450 | ns _| taics)_Access time from chip select 150 |’ os | TaypR) Access time From POIPGM | 230250 [280350 [780480 [as | CL = 100 pF, Output data valid after WIA) ee 1 Series 74 TTL load, address change ‘Output disable time from chip 20 ns, ° 100 Output disable time from chip * taisics) select during program 120 120 and program verity? Output disable time 'distPR) from PD/PGM* recommended timing requirements for programming Ta = 25°C (see Note 4) PARAMETER Min tyet_max[unit | twiPR) Pulse width, program pulse [4550 55] ms | tePR) Rise time, program pulse [os ids | [wer Failte, prowempuie [teuiay Adress serum time ‘su(ver) Setup time trom Vep fos] [tniay Adress oe time a nics) Chip-select hold time es wo) Gerald tne a programming. All AC and OC measurements are made at 10% and 90% points with @ 50% pattern —— eee PARAMETER MEASUREMENT INFORMATION v-209v Ry 780.8 oureut UNDER TEST 7 €.=100 pF FIGURE 1 — TYPICAL OUTPUT LOAD CIRCUIT TEXAS INSTRUMENTS 141 INCORPORATED
TMS 2516-25 JL, TMS 2516-35 JL AND TMS 2516-45 JL 16,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES read cycle timing 1 f vin OOOO AXXXKERLAKY an BRO RR ! ' ofa vin oy — 1 \\! | 4 cs 1 If “ i | ry v roam 1 \\ 1 | ' ! ™ = —>uics) ‘dis ( vou has rte ° standby mode Vin ADDRESSES ADDRESS N . ADDRESS N+ m vie { 1 Vin i Povecm x STANDBY \\ Active vin be +! ‘tdis(PR) | tart | Vou 1.08 vauo + z —{ VALID Vou ‘taipRy referenced to PD/PGM or the address, whichever occurs last, All timing reference points in this data sheet (inputs and outputs) are 90% Points. eee 582
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TMS 2516-25 JL, TMS 2516-35 JL AND TMS 2516-45 JL 16,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES program cycle timing f+ rroonen ———olu— "gent a v vi ; antes a | reso ke +4 be ‘disics) ae roto vin | vin | Hewienr> | x y ; twioyt | Lewes) 2! | \\ Po/PGM 4 \\ yA | siesie) | vi - Twente le | T 1 | petatvenrel aol Le luiens Le i i ! | sav wy | } 1 \\ 1 | | \\ 1 | 1 Vou!Vin Vou/Vit Texas INSTRUMENTS 143 INCORPORATED POST OFFICE BOX 728012 © DALLAS, TEXAS 75265
TMS 2516-25 JL, TMS 2516-35 JL AND TMS 2516-45 JL 16,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES EES typical device characteristics (read mode) TMs 251645 TMS 2516-35 TMs 2516-25 gg CURRENT TewrenaTune “COT ot | Pee | || lec2 ACTIVE CURRENT im C1 HER ope | LT TTT 0 10 20 30 40 50 60 70 TEMPERATURE (°C) Ts 2516-45 TMs 2516-35 TMs 2516.25 ACCESS TIME TewpenaTune 700 wo TTT TTT wo | | | ttt DLT PCC wrt | | | | of | TT TTT | LTT Tt t | 0 10 2 3% 4 50 60 70 TEMPERATURE (°C) sn