TMPP320C6202BGLW167

TMS320C6211B TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 83

Technical content

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x (TMS320C6211 and TMS320C6211B) − Eight 32-Bit Instructions/Cycle − C6211, C6211B, C6711, and C6711B are Pin-Compatible − 150-, 167-MHz Clock Rates − 6.7-, 6-ns Instruction Cycle Time − 1200, 1333 MIPS − Extended Temperature Device (C6211B) /C0068VelociTI Advanced Very Long Instruction Word (VLIW) C62x DSP Core (C6211/11B) − Eight Highly Independent Functional Units: − Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Results) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional /C0068Instruction Set Features − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization /C0068L1/L2 Memory Architecture − 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) − 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) − 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) /C0068Device Configuration − Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot − Endianness: Little Endian, Big Endian /C006832-Bit External Memory Interface (EMIF) − Glueless Interface to Asynchronous Memories: SRAM and EPROM − Glueless Interface to Synchronous Memories: SDRAM and SBSRAM − 512M-Byte Total Addressable External Memory Space /C0068Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) /C006816-Bit Host-Port Interface (HPI) − Access to Entire Memory Map /C0068Two Multichannel Buffered Serial Ports (McBSPs) − Direct Interface to T1/E1, MVIP, SCSA Framers − ST-Bus-Switching Compatible − Up to 256 Channels Each − AC97-Compatible − Serial-Peripheral-Interface (SPI) Compatible (Motorola) /C0068Two 32-Bit General-Purpose Timers /C0068Flexible Phase-Locked-Loop (PLL) Clock Generator /C0068IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible /C0068256-Pin Ball Grid Array (BGA) Package (GFN Suffix) /C00680.18-µm/5-Level Metal Process − CMOS Technology /C00683.3-V I/Os, 1.8-V Internal Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

absolute maximum ratings over operating case electrical characteristics over recommended ranges of supply voltage and operating case temperature 40. GFN BGA package (bottom view) 1915 1713119 Y V T U P N R W L J K H F G D B C A E M 2468 2 0 1816141210 GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

description

The TMS320C62x DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000  DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI  very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals. The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TMS320C6000 is a trademark of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation.

4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C6000 DSP device part numbers and part numbering, see Table 17 and Figure 4. Table 1. Characteristics of the C6211/C6211B Processors C6000 is a trademark of Texas Instruments.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device compatibility The TMS320C6211/C6211B and C6711/C6711B devices are pin-compatible and have the same peripheral set; thus, making new system designs easier and providing faster time to market. The following list summarizes the device characteristic differences among the C6211, C6211B, C6711, and C6711B devices: /C0068The C6211 and C6211B devices have a fixed-point C62x CPU, while the C6711 and C6711B devices have a floating-point C67x CPU. /C0068The C6211/C6211B device runs at -167 and -150 MHz clock speeds (with a C6211BGFNA extended temperature device that also runs at -150 MHz), while the C6711/C6711B device runs at -150 and -100 MHz (with a C6711BGFNA extended temperature device that also runs at -100 MHz). For a more detailed discussion on the similarities/differences between the C6211 and C6711 devices, see the How to Begin Development Today with the TMS320C6211 DSP and How to Begin Development with the TMS320C6711 DSP application reports (literature number SPRA474 and SPRA522, respectively).

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

functional block and CPU (DSP core) diagram ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Test C6000 CPU (DSP Core) Data Path B B Register File Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File Power-Down Logic SDRAM ROM/FLASH SBSRAM I/O Devices L1P Cache Direct Mapped 4K Bytes Total Control Registers Control Logic L1D Cache 2-Way Set Associative 4K Bytes Total In-Circuit Emulation Interrupt Control Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs C6211/C6211B Digital Signal Processors Enhanced DMA Controller (16 channel) Memory

4 Banks

(x1, x4) Timer 0 External Memory Interface (EMIF) Multichannel Buffered Serial Port 1 (McBSP1) Multichannel Buffered Serial Port 0 (McBSP0) Host Port Interface (HPI) SRAM Timer 1 Boot ConfigurationInterrupt Selector

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 CPU (DSP core) description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI  VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 1. TMS320C62x CPU (DSP Core) Data Paths

address ranges in the C6211/C6211B devices begin at the address location 0x8000 0000. Table 2. TMS320C6211/C6211B Memory Map Summary addressable memory, additional general-purpose output pin or external logic is required.

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 3. EMIF Registers Table 4. L2 Cache Registers

Table 5. EDMA Registers Table 6. EDMA Parameter RAM† † The C6211/C6211B device has sixty-nine parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.

12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 7. Quick DMA (QDMA) and Pseudo Registers† Table 8. Interrupt Selector Registers

Table 9. McBSP 0 Registers Table 10. McBSP 1 Registers

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 11. Timer 0 Registers Table 12. Timer 1 Registers Table 13. HPI Registers

TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Table 14. PWRD field bits in the CPU CSR Register controls the device power-down modes. Accessible by writing a value to the CSR register.

16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 15. TMS320C6211/C6211B EDMA Channel Synchronization Events

0 DSP_INT Host-port interface (HPI)-to-DSP interrupt

1 TINT0 Timer 0 interrupt

2 TINT1 Timer 1 interrupt

3 SD_INT EMIF SDRAM timer interrupt

4 EXT_INT4 External interrupt pin 4

5 EXT_INT5 External interrupt pin 5

6 EXT_INT6 External interrupt pin 6

7 EXT_INT7 External interrupt pin 7

12 XEVT0 McBSP0 transmit event

13 REVT0 McBSP0 receive event

14 XEVT1 McBSP1 transmit event

15 REVT1 McBSP1 receive event

TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).

registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004). Table 16. C6211/C6211B DSP Interrupts INT_02† − − Reserved Reserved. Do not use. INT_03† − − Reserved Reserved. Do not use. − − 10000 − 11111 Reserved Reserved. Do not use. † Interrupts INT_00 through INT_03 are non-maskable and fixed.

18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 2. CPU (DSP Core) and Peripheral Signals

Figure 3. Peripheral Signals

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TYPE† IPD/ DESCRIPTIONNAME NO. TYPE† IPD/ IPU‡ DESCRIPTION CLOCK/PLL CLKIN A3 I IPD Clock Input CLKOUT1 D7 O IPD Clock output at device speed The CLK1EN bit in the EMIF GBLCTL register controls the CLKOUT1 pin. CLK1EN = 0: CLKOUT1 is disabled CLK1EN = 1: CLKOUT1 enabled to clock [default] CLKOUT2 Y12 O IPD Clock output at half of device speed When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control register (GBLCTL) controls the CLKOUT2 pin. CLK2EN = 0: CLKOUT2 is disabled CLK2EN = 1: CLKOUT1 enabled to clock [default] CLKMODE0 C4 I IPU Clock mode select

• Selects whether the CPU clock frequency = input clock frequency x4 or x1 PLLV§ A4 A¶ PLL analog VCC connection for the low-pass filter PLLG§ C6 A¶ PLL analog GND connection for the low-pass filter PLLF B5 A¶ PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS B7 I IPU JTAG test-port mode select TDO A8 O/Z IPU JTAG test-port data out TDI A7 I IPU JTAG test-port data in TCK A6 I IPU JTAG test-port clock TRST B6 I IPD JTAG test-port reset EMU5 B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 D10 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 B9 I/O/Z IPU Emulation pin 1# EMU0 D9 I/O/Z IPU Emulation pin 0# RESETS AND INTERRUPTS RESET A13 I IPU Device reset NMI C13 I IPD Nonmaskable interrupt
• Edge-driven (rising edge) Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. EXT_INT7 E3 External interrupts EXT_INT6 D2 I IPU External interrupts
• Edge-driven EXT_INT5 C1 I IPU • Edge-driven
• Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL [3 0])EXT_INT4 C2 yp y p y g (EXTPOL.[3:0]) HOST-PORT INTERFACE (HPI) HINT J20 O IPU Host interrupt (from DSP to host) HCNTL1 G19 I IPU Host control − selects between control, address, or data registers HCNTL0 G18 I IPU Host control − selects between control, address, or data registers HHWIL H20 I IPU Host half-word select − first or second half-word (not necessarily high or low order) HR/W G20 I IPU Host read or write select † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 § PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these pins. ¶ A = Analog signal (PLL Filter) # The EMU0 and EMU1 pins are internally pulled up with 30-k Ω resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicate d 1-kΩ resistor. Terminal Functions (Continued) SIGNAL TYPE† IPD/ DESCRIPTIONNAME NO. TYPE† IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) HD15 B14 IPU HD14 C14 IPU HD13 A15 IPU HD12 C15 IPU HD11 A16 IPU Host-port data U d f t f f d t dd d t lHD10 B16 IPU • Used for transfer of data, address, and control

• Also controls initialization of DSP modes at reset via pullup/pulldown resistors HD9 C16 IPU
• Also controls initialization of DSP modes at reset via pullup/pulldown resistors − Device Endian mode HD8 B17 I/O/Z IPU Device Endian mode HD8: 0 – Big Endian

1 Little EndianHD7 A18 I/O/Z IPU 1 − Little Endian

− Boot mode HD6 C17 IPU − Boot mode HD[4:3]: 00 – HPI boot HD5 B18 IPU HD[4:3]: 00 HPI boot 01 − 8-bit ROM boot with default timings 10 16 bit ROM boot with default timings HD4 C19 IPD 10 − 16-bit ROM boot with default timings 11 − 32-bit ROM boot with default timings HD3 C20 IPU 11 − 32-bit ROM boot with default timings HD2 D18 IPU HD1 D20 IPU HD0 E20 IPU HAS E18 I IPU Host address strobe HCS F20 I IPU Host chip select HDS1 E19 I IPU Host data strobe 1 HDS2 F18 I IPU Host data strobe 2 HRDY H19 O IPD Host ready (from DSP to host) EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 V6 O/Z IPU CE2 W6 O/Z IPU Memory space enables

• Enabled by bits 28 through 31 of the word addressCE1 W18 O/Z IPU
• Enabled by bits 28 through 31 of the word address
• Only one asserted during any external data access CE0 V17 O/Z IPU
• Only one asserted during any external data access BE3 V5 O/Z IPU Byte-enable control BE2 Y4 O/Z IPU Byte-enable control
• Decoded from the two lowest bits of the internal address BE1 U19 O/Z IPU
• Decoded from the two lowest bits of the internal address
• Byte-write enables for most types of memory C b di tl t d t SDRAM d d it k i l (SDQM)BE0 V20 O/Z IPU yy p y
• Can be directly connected to SDRAM read and write mask signal (SDQM) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued) SIGNAL TYPE† IPD/ DESCRIPTIONNAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIF − BUS ARBITRATION HOLDA J18 O IPU Hold-request-acknowledge to the host HOLD J17 I IPU Hold request from the host BUSREQ J19 O IPU Bus request output EMIF − ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL ECLKIN Y11 I IPD EMIF input clock ECLKOUT Y10 O IPD EMIF output clock (based on ECLKIN) ARE/SDCAS/ SSADS V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe AOE/SDRAS/ SSOE W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable AWE/SDWE/ SSWE V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable ARDY Y5 I IPU Asynchronous memory ready input EMIF − ADDRESS EA21 U18 EA20 Y18 EA19 W17 EA18 Y16 EA17 V16 EA16 Y15 EA15 W15 EA14 Y14 EA13 W14 EA12 V14 O/Z IPU EMIF external address EA11 W13 O/Z IPU EMIF external address EA10 V10 EA9 Y9 EA8 V9 EA7 Y8 EA6 W8 EA5 V8 EA4 W7 EA3 V7 EA2 Y6 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 23POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE† IPD/ DESCRIPTIONNAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIF − DATA ED31 N3 ED30 P3 ED29 P2 ED28 P1 ED27 R2 ED26 R3 ED25 T2 ED24 T1 ED23 U3 ED22 U1 ED21 U2 ED20 V1 ED19 V2 ED18 Y3 ED17 W4 ED16 V4 I/O/Z IPU External dataED15 T19 I/O/Z IPU External data ED14 T20 ED13 T18 ED12 R20 ED11 R19 ED10 P20 ED9 P18 ED8 N20 ED7 N19 ED6 N18 ED5 M20 ED4 M19 ED3 L19 ED2 L18 ED1 K19 ED0 K18 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued) SIGNAL TYPE† IPD/ DESCRIPTIONNAME NO. TYPE† IPD/ IPU‡ DESCRIPTION TIMER 1 TOUT1 F1 O IPD Timer 1 or general-purpose output TINP1 F2 I IPD Timer 1 or general-purpose input TIMER 0 TOUT0 G1 O IPD Timer 0 or general-purpose output TINP0 G2 I IPD Timer 0 or general-purpose input MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 E1 I IPD External clock source (as opposed to internal) CLKR1 M1 I/O/Z IPD Receive clock CLKX1 L3 I/O/Z IPD Transmit clock DR1 M2 I IPU Receive data DX1 L2 O/Z IPU Transmit data FSR1 M3 I/O/Z IPD Receive frame sync FSX1 L1 I/O/Z IPD Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 K3 I IPD External clock source (as opposed to internal) CLKR0 H3 I/O/Z IPD Receive clock CLKX0 G3 I/O/Z IPD Transmit clock DR0 J1 I IPU Receive data DX0 H2 O/Z IPU Transmit data FSR0 J3 I/O/Z IPD Receive frame sync FSX0 H1 I/O/Z IPD Transmit frame sync RESERVED FOR TEST RSV0 C12 O IPU Reserved (leave unconnected, do not connect to power or ground) RSV1 D12 O IPU Reserved (leave unconnected, do not connect to power or ground) RSV2 A5 O IPU Reserved (leave unconnected, do not connect to power or ground) RSV3 D3 O Reserved (leave unconnected, do not connect to power or ground) RSV4 N2 O Reserved (leave unconnected, do not connect to power or ground) RSV5 Y20 O Reserved (leave unconnected, do not connect to power or ground) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 25POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE† DESCRIPTIONNAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS A17 B13 C10 D16 D19 H18 M18 DVDD R1 S 3.3-V supply voltageDVDD R18 S 3.3 V supply voltage U12 U16 V13 V15 V19 W12 Y17 A10 A12 B19 CV S 1 8 V supply voltageCVDD C7 S 1.8-V supply voltage C18 D11 D14 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued) SIGNAL TYPE† DESCRIPTIONNAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) D15 F17 K17 L17 L20 CV S 1 8 V supply voltageCVDD R17 S 1.8-V supply voltage U10 U11 U14 U15 V18 W19 GROUND PINS A11 A14 A19 A20 V B11 GND Ground pinsVSS B15 GND Ground pins B20 D13 D17 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 27POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE† DESCRIPTIONNAME NO. TYPE† DESCRIPTION GROUND PINS (CONTINUED) E17 F19 G17 H17 K20 M17 N17 P17 V P19 GND Ground pinsVSS T4 GND Ground pins T17 U13 U17 U20 W11 W16 W20 Y13 Y19 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TI offers an extensive line of development tools for the TMS320C6000  DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS ), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000  DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select “Find Development Tools”. For device-specific tools, under “Semiconductor Products”, select “Digital Signal Processors”, choose a product family, and select the particular DSP device. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a final product and Texas Instruments reserves the right to change or discontinue these products without notice. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example,GFN), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -167 is 167 MHz). Figure 4 provides a legend for reading the complete device name for any TMS3206000 DSP family member. TMS320 is a trademark of Texas Instruments.

30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 17. TMS320C6211/C6211B Device Part Numbers (P/Ns) and Ordering Information

100 MHz

120 MHz

150 MHz

167 MHz

200 MHz

233 MHz

250 MHz

300 MHz

Figure 4. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6211 MicroStar BGA is a trademark of Texas Instruments.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 documentation support Extensive documentation supports all TMS320  DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: For device-specific datasheets and related documentation, visit the TI web site at: http://www.ti.com. The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an overview and briefly describes the functionality of the peripherals available on the C6000  DSP platform of devices. This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x/TMS320C67x devices, associated development tools, and third-party support. The TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646) describes the interrupt selector, interrupt selector registers, and the available interrupts in the TMS320C6000 DSPs. The TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234) describes the operation of the enhanced direct memory access (EDMA) controller in the TMS320C6000 DSPs. The TMS320C62x/C67x Power Consumption Summary application report (literature number SPRA486) discusses the power consumption for user applications with the TMS320C6211 and TMS320C6211B DSP devices. The TMS320C6211/TMS320C6211B Digital Signal Processors Silicon Errata (literature number SPRZ154) describes the known exceptions to the functional specifications for the TMS320C6211 and TMS320C6211B DSP devices. The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio  Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for the application reports How To Begin Development Today with the TMS320C6211 DSP (literature number SPRA474) and How To Begin Development with the TMS320C6711 DSP (literature number SPRA522), which describe in more detail the similarities/differences between the C6211 and C6711 C6000 DSP devices. TMS320C67x is a trademark of Texas Instruments.

32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

bypasses the PLL to become the internal CPU clock. external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. section). Table 18 lists some examples of compatible CLKIN external clock sources. Table 18. Compatible CLKIN External Clock Sources

342 Corning Frequency Control

components other than the ones shown. C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV DD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U. Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode

NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV DD. Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only Table 19. C6211/C6211B PLL Component Selection typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 7 shows the power-down mode logic on the C6211/C6211B. † External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic. Figure 7. Power-Down Mode Logic† of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 20. and Instruction Set Reference Guide (literature number SPRU189).

bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 8. PWRD Field of the CSR Register upon PD1 mode termination by an enabled interrupt. PD2 and PD3 modes can only be aborted by device reset. Table 20 summarizes all the power-down modes.

36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 20. Characteristics of the Power-Down Modes

000000 No power-down — —

001001 PD1 Wake by an enabled interrupt CPU halted (except for the interrupt logic)

010001 PD1 Wake by an enabled or

between peripherals and internal memory.

011010 PD2† Wake by a device reset

011100 PD3† Wake by a device reset

PLL needs time to re-lock, just as it does following power-up. the PLL needs to be re-locked, just as it does following power-up. peripherals will not operate according to specifications.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 37POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 power-supply sequencing TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw. A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP. Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

IEEE 1149.1 JTAG compatibility statement The TMS320C6211/C6211B DSP requires that both TRST and RESET resets be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. For maximum reliability, the TMS320C6211/C6211B DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. EMIF device speed TI recommends utilizing the input/output buffer information specification (IBIS) models to analyze all AC timings. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839).

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 39POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 bootmode The C62x device resets using the active-low signal RESET signal (for the C6211/C6211B device, the RESET signal is the same as the internal reset signal). While RESET is low, the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of the internal reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts the processor running with the prescribed device configuration and boot mode. The C6211/C6211B has three types of boot modes: /C0068Host boot If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of the device is released. During this period, an external host can initialize the CPU’s memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received. /C0068Emulation boot Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution, the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development. /C0068EMIF boot (using default ROM timings) Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored in the endian format that the system is using. The boot process also lets you choose the width of the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the “stalled” state and start running from address 0.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

absolute maximum ratings over operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to V SS. recommended operating conditions MIN NOM MAX UNIT CVDD Supply voltage, Core 1.71 1.8 1.89 V DVDD Supply voltage, I/O 3.14 3.3 3.46 V VSS Supply ground 0 0 0 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V I High level output current All signals except CLKOUT1, CLKOUT2, and ECLKOUT −4 mA IOH High-level output current CLKOUT1, CLKOUT2, and ECLKOUT −8 mA I Low level output current All signals except CLKOUT1, CLKOUT2, and ECLKOUT 4 mA IOL Low-level output current CLKOUT1, CLKOUT2, and ECLKOUT 8 mA T Operating case temperature Default 0 90 /C0095C TC Operating case temperature A version (C6211BGFNA only) −40 105 /C0095C electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS‡ MIN TYP MAX UNIT VOH High-level output voltage DVDD = MIN, I OH = MAX 2.4 V VOL Low-level output voltage DVDD = MIN, I OL = MAX 0.4 V II Input current VI = VSS to DVDD ±150 uA IOZ Off-state output current VO = DVDD or 0 V ±10 uA I Supply current, CPU + CPU memory C6211, CVDD = NOM, CPU clock = 150 MHz 270 mA IDD2V Supply current, CPU + CPU memory access§ C6211B, CVDD = NOM, CPU clock = 150 MHz 270 mA I Supply current peripherals§ C6211, CVDD = NOM, CPU clock = 150 MHz 220 mA IDD2V Supply current, peripherals§ C6211B, CVDD = NOM, CPU clock = 150 MHz 220 mA I Supply current I/O pins§ C6211, DVDD = NOM, CPU clock = 150 MHz 60 mA IDD3V Supply current, I/O pins§ C6211B, DVDD = NOM, CPU clock = 150 MHz 60 mA Ci Input capacitance 7 pF Co Output capacitance 7 pF ‡ For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. § Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, refer to the TMS320C62x/C67x Power Consumption Summary application report (literature number SPRA486).

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences. For example: /C0068In typical boards with the C6211B commercial temperature device, the routing delay improves the external memory’s ability to meet the DSP’s EMIF data input hold time requirement [t h(EKOH-EDV)]. /C0068In some boards with the C6211BGFNA extended temperature device, the routing delay improves the external memory’s ability to meet the DSP’s EMIF data input hold time requirement [t h(EKOH-EDV)]. In addition, it may be necessary to add an extra delay to the input clock of the external memory to robustly meet the DSP’s data input hold time requirement. If the extra delay approach is used, memory bus frequency adjustments may be needed to ensure the DPS’s input setup time requirement [t su(EDV-EKOH)] is still maintained. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 21 and Figure 12). Figure 12 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device.

Table 21. IBIS Timing Parameters Example (see Figure 12)

1 Clock route delay

2 Minimum DSP hold time

3 Minimum DSP setup time

4 External device hold time requirement

5 External device setup time requirement

6 Control signal route delay

7 External device hold time

8 External device access time

9 DSP hold time requirement

10 DSP setup time requirement

11 Data route delay

† Control signals include data for Writes. ‡ Data signals are generated during Reads from an external device. Figure 12. IBIS Input/Output Timings

44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

NO. CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 UNITNO. † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 40 MHz, use C = 25 ns. Figure 13. CLKIN Timings

46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. Figure 16. ECLKIN Timings ‡ The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ¶ EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns. Figure 17. ECLKOUT Timings

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles†‡§ (see Figure 18−Figure 19) NO. C6211−150 C6211−167 C6211B−150 C6211B−167 C6211BGFNA−150 UNIT MIN MAX MIN MAX 3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 9 9 ns 4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 2 ns 6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 3 3 ns 7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 1 2 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § E = ECLKOUT period in ns switching characteristics over recommended operating conditions for asynchronous memory cycles for C6211 and C6211B‡§¶ (see Figure 18−Figure 19) NO. PARAMETER C6211−150 C6211−167 C6211B−150 C6211B−167 UNITNO. PARAMETER MIN MAX MIN MAX UNIT 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * E − 3 RS * E − 3 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * E − 3 RH * E − 3 ns 5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE vaild 1.5 8 1.5 8 ns 8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * E − 3 WS * E − 3 ns 9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * E − 3 WH * E − 3 ns 10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE vaild 1.5 8 1.2 8 ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § E = ECLKOUT period in ns ¶ Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0]. switching characteristics over recommended operating conditions for asynchronous memory cycles for C6211BGFNA‡§¶ (see Figure 18−Figure 19) NO PARAMETER C6211BGFNA−150 UNITNO. PARAMETER MIN MAX UNIT 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * E − 3 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * E − 3 ns 5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE vaild 1.5 8 ns 8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * E − 3 ns 9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * E − 3 ns 10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE vaild 1 8 ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § E = ECLKOUT period in ns ¶ Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].

48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

respectively, during asynchronous memory accesses. Figure 18. Asynchronous Memory Read Timing

respectively, during asynchronous memory accesses. Figure 19. Asynchronous Memory Write Timing

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles† (see Figure 20) NO. C6211−150 C6211−167 C6211BGFNA−150 C6211B−150 C6211B−167 UNITNO. MIN MAX MIN MAX MIN MAX UNIT 6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 2.5 2.5 2.5 ns 7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 1 2.5 2 ns † The C6211/C6211B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ (see Figure 20 and Figure 21) NO. PARAMETER C6211−150 C6211−167 C6211BGFNA−150 C6211B−150 C6211B−167 UNITNO. PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx 2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 6.5 6.5 6.5 ns 3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.5 1 1.2 ns 4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 6.5 6.5 6.5 ns 5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.5 1 1.2 ns 8 td(EKOH-ADSV) Delay time, ECLKOUT high to ARE 9 td(EKOH-OEV) Delay time, ECLKOUT high to AOE 10 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 7 7 ns 11 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.5 1 1.2 ns 12 td(EKOH-WEV) Delay time, ECLKOUT high to AWE † The C6211/C6211B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ‡ ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS , SSOE, and SSWE, respectively, during SBSRAM accesses.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

timing requirements for synchronous DRAM cycles† (see Figure 22) NO. C6211−150 C6211−167 C6211BGFNA−150 C6211B−150 C6211B−167 UNITNO. MIN MAX MIN MAX MIN MAX UNIT 6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 2.5 2.5 2.5 ns 7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 1 2.5 2 ns † The C6211/C6211B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ (see Figure 22−Figure 28) NO. PARAMETER C6211−150 C6211−167 C6211BGFNA−150 C6211B−150 C6211B−167 UNITNO. PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx 2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 6.5 6.5 6.5 ns 3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.5 1 1.2 ns 4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 6.5 6.5 6.5 ns 5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.5 1 1.2 ns 8 td(EKOH-CASV) Delay time, ECLKOUT high to ARE 9 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 7 7 ns 10 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.5 1 1.2 ns 11 td(EKOH-WEV) Delay time, ECLKOUT high to AWE 12 td(EKOH-RAS) Delay time, ECLKOUT high to AOE † The C6211/C6211B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ‡ ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS , SDWE, and SDRAS, respectively, during SDRAM accesses.

Figure 22. SDRAM Read Command (CAS Latency 3)

54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 23. SDRAM Write Command

56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 26. SDRAM DEAC Command Figure 27. SDRAM REFR Command

Figure 28. SDRAM MRS Command

58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. Figure 29. HOLD/HOLDA Timing

Figure 30. BUSREQ Timing

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

timing requirements for reset† (see Figure 31) NO. −150 −167 UNITNO. MIN MAX UNIT 1 t Width of the RESET pulse (PLL stable)‡ 10P ns 1 tw(RST) Width of the RESET pulse (PLL needs to sync up)§ 250 µs 14 tsu(HD) Setup time, HD boot configuration bits valid before RESET high¶ 2P ns 15 th(HD) Hold time, HD boot configuration bits valid after RESET high¶ 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable. § This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. ¶ HD[4:3] are the boot configuration pins during device reset. switching characteristics over recommended operating conditions during reset†#|| (see Figure 31) NO. PARAMETER −150 −167 UNITNO. PARAMETER MIN MAX UNIT 2 td(RSTL-ECKI) Delay time, RESET low to ECLKIN synchronized internally 2P + 3E 3P + 4E ns 3 td(RSTH-ECKI) Delay time, RESET high to ECLKIN synchronized internally 2P + 3E 3P + 4E ns 4 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance 2P + 3E ns 5 td(RSTH-EMIFZV) Delay time, RESET high to EMIF Z group valid 3P + 4E ns 6 td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid 2P + 3E ns 7 td(RSTH-EMIFHV) Delay time, RESET high to EMIF high group valid 3P + 4E ns 8 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group invalid 2P + 3E ns 9 td(RSTH-EMIFLV) Delay time, RESET high to EMIF low group valid 3P + 4E ns 10 td(RSTL-HIGHIV) Delay time, RESET low to high group invalid 2P ns 11 td(RSTH-HIGHV) Delay time, RESET high to high group valid 4P ns 12 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance 2P ns 13 td(RSTH-ZV) Delay time, RESET high to Z group valid 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. # E = ECLKIN period in ns || EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0] , BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE EMIF high group consists of: HOLDA EMIF low group consists of: BUSREQ High group consists of: HRDY and HINT Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.

Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1. ‡ HD[8, 4:3] are the endianness and boot configuration pins during device reset. Figure 31. Reset Timing

62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

† P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. Figure 32. External/NMI Interrupt Timing

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 63POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles [C6211]†‡ (see Figure 33, Figure 34, Figure 35, and Figure 36) NO. C6211−150 C6211−167 UNITNO. MIN MAX UNIT 1 tsu(SELV-HSTBL) Setup time, select signals§ valid before HSTROBE low 5 ns 2 th(HSTBL-SELV) Hold time, select signals§ valid after HSTROBE low 4 ns 3 tw(HSTBL) Pulse duration, HSTROBE low 4P ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P ns 10 tsu(SELV-HASL) Setup time, select signals§ valid before HAS low 5 ns 11 th(HASL-SELV) Hold time, select signals§ valid after HAS low 3 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § Select signals include: HCNTL[1:0], HR/W, and HHWIL. switching characteristics over recommended operating conditions during host-port interface cycles [C6211]†‡ (see Figure 33, Figure 34, Figure 35, and Figure 36) NO. PARAMETER C6211−150 C6211−167 UNITNO. PARAMETER MIN MAX UNIT 5 td(HCS-HRDY) Delay time, HCS to HRDY¶ 1 15 ns 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 3 15 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P − 4 2P ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 15 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 15 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 15 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 15 ns 20 td(HASL-HRDYH) Delay time, HAS low to HRDY high 3 15 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

HOST-PORT INTERFACE TIMING (CONTINUED) timing requirements for host-port interface cycles [C6211BGFNA/C6211B] †‡ (see Figure 33, Figure 34, Figure 35, and Figure 36) NO. C6211B−150 C6211B−167 C6211BGFNA−150 UNIT MIN MAX 1 tsu(SELV-HSTBL) Setup time, select signals§ valid before HSTROBE low 5 ns 2 th(HSTBL-SELV) Hold time, select signals§ valid after HSTROBE low 4 ns 3 tw(HSTBL) Pulse duration, HSTROBE low 4P ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P ns 10 tsu(SELV-HASL) Setup time, select signals§ valid before HAS low 5 ns 11 th(HASL-SELV) Hold time, select signals§ valid after HAS low 3 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § Select signals include: HCNTL[1:0], HR/W, and HHWIL. switching characteristics over recommended operating conditions during host-port interface cycles [C6211BGFNA/C6211B]†‡ (see Figure 33, Figure 34, Figure 35, and Figure 36) NO. PARAMETER C6211BGFNA−150 C6211B−150 C6211B−167 UNITNO. PARAMETER MIN MAX MIN MAX UNIT 5 td(HCS-HRDY) Delay time, HCS to HRDY¶ 1 13 1 12 ns 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 3 13 3 12 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 2 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P − 4 2P 2P − 4 2P ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 13 3 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 13 3 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 13 3 12 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 13 3 12 ns 20 td(HASL-HRDYH) Delay time, HAS low to HRDY high 3 13 3 12 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 35. HPI Write Timing (HAS Not Used, Tied High) † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 36. HPI Write Timing (HAS Used)

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 67POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 37) NO. −150 −167 UNITNO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5tc(CKRX) − 1 ns 5 t Setup time external FSR high before CLKR low CLKR int 20 ns5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 1 ns 6 t Hold time external FSR high after CLKR low CLKR int 6 ns6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3 ns 7 t Setup time DR valid before CLKR low CLKR int 22 ns7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 3 ns 8 t Hold time DR valid after CLKR low CLKR int 3 ns8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4 ns 10 t Setup time external FSX high before CLKX low CLKX int 23 ns10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 1 ns 11 t Hold time external FSX high after CLKX low CLKX int 6 ns11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP and other device is 83 Mbps for 167 MHz CPU clock or 75 Mbps for 150 MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 30 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 37) NO. PARAMETER −150 −167 UNITNO. PARAMETER MIN MAX UNIT 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 4 26 ns 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1# C + 1# ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −11 3 ns 9 t Delay time CLKX high to internal FSX valid CLKX int −11 3 ns9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 9 ns 12 t Disable time, DX high impedance following last data bit CLKX int −9 4 ns12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX ext 3 9 ns 13 t Delay time CLKX high to DX valid CLKX int −9+ D1|| 4 + D2|| ns13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 3 + D1|| 19 + D2|| ns 14 t Delay time, FSX high to DX valid FSX int −1 3 ns14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP and other device is 83 Mbps for 167 MHz CPU clock or 75 Mbps for 150 MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 30 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above). || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. If DXENA = 0, then D1 = D2 = 0 If DXENA = 1, then D1 = 2P, D2 = 4P

Figure 37. McBSP Timings

70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 38. FSR Timing When GSYNC = 1

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 71POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 39) NO −150 −167 UNITNO. MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 26 2 − 6P ns 5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4 6 + 12P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 39) NO PARAMETER −150 −167 UNITNO. PARAMETER MASTER§ SLAVE UNIT MIN MAX MIN MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ T − 9 T + 9 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# L − 9 L + 9 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −9 9 6P + 4 10P + 20 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low L − 9 L + 9 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 2P + 3 6P + 20 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 20 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 39. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

† P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 40. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 41) NO −150 −167 UNITNO. MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 26 2 − 6P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 6 + 12P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 41) NO PARAMETER −150 −167 UNITNO. PARAMETER MASTER§ SLAVE UNIT MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ T − 9 T + 9 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# H − 9 H + 9 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid −9 9 6P + 4 10P + 20 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high H − 9 H + 9 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 2P + 3 6P + 20 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 20 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Figure 41. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 42) NO −150 −167 UNITNO. MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 26 2 − 6P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 6 + 12P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 42) NO PARAMETER −150 −167 UNITNO. PARAMETER MASTER§ SLAVE UNIT MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ H − 9 H + 9 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# T − 9 T + 9 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −9 9 6P + 4 10P + 20 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high −9 9 6P + 3 10P + 20 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L − 9 L + 9 4P + 2 8P + 20 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Figure 42. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

† P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. Figure 43. Timer Timing

Figure 44. JTAG Test-Port Timing

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004

80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

GFN (S-PBGA-N256) PLASTIC BALL GRID ARRAY 0,635 1915 1713119 Y V T U P N R W L J K H F G D B C A E M 24,13 TYP Seating Plane 4040185-2/D 02/02 10 12 14 16 18 208642 27,20 23,80 24,70 SQ SQ26,80 0,90 0,60 0,50 0,70 0,635 1,27 0,15 1,27 M0,15 2,32 MAX 0,40 0,30 1,17 NOM A1 Corner Bottom View NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151 thermal resistance characteristics (S-PBGA package) NO °C/W Air Flow (m/s)† 1 RΘJC Junction-to-case 6.4 N/A 2 RΘJA Junction-to-free air 25.5 0.0 3 RΘJA Junction-to-free air 23.1 0.5 4 RΘJA Junction-to-free air 22.3 1.0 5 RΘJA Junction-to-free air 21.2 2.0 † m/s = meters per second

TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 81POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS073J device-specific data sheet to make it an SPRS073K revision. Scope: Applicable updates to the C62x device family, specifically relating to the C6211 and C6211B devices, have been incorporated. PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS

35 Power-down mode logic section:

Updated the text found under Figure 8.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TMS320C6211BGFN150 ACTIVE BGA GFN 256 40 None SNPB Level-4-220C-72HR TMS320C6211BGFN167 ACTIVE BGA GFN 256 40 None SNPB Level-4-220C-72HR TMS320C6211GFN150 NRND BGA GFN 256 None Call TI Call TI TMS320C6211GFN167 NRND BGA GFN 256 None Call TI Call TI TMS32C6211BGFNA150 ACTIVE BGA GFN 256 40 None SNPB Level-4-220C-72HR TMX320C6211GFN OBSOLETE BGA GFN 256 None Call TI Call TI TMX320C6211GFN21 OBSOLETE BGA GFN 256 None Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 17-Dec-2004 Addendum-Page 1

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2004, Texas Instruments Incorporated