TMP82C79P-2

TMP82C79 TOSHIBA | Alldatasheet

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PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE . TMP82C79P-2/TMP82C79M-2 1. GENERAL DESCRIPTION The TMP82C79P-2/M-2 (hereinafter referred to as TMP82C79) is a programmable keyboard/display interface. The keyboard portion can provide a scanned interface up to 64-contact key matrix. Also, the keyboard portion can interface to an array of sensors or a strobed interface keyboard. Key depressions can be 2-key lockout or N-key rollover. The display portion has 16 X8 bits display RAM which can be treated as dual 16 x 4 bits. Both right entry and left entry display formats are possible. 2. FEATURES e Simultaneous Keyboard Display operation. e Scanned Keyboard mode. . Scanned Sensor matrix mode. e Strobed Input Entry mode. e =: Built-in 8-Character FIFO or 64 bit Sensor RAM. e Programmable 2-key Lockout or N-key Rollover with contact debounce. e Built-in 16 X 8bit Display RAM e Programmable scan timing. e Extend operating temperature range — 40°C to +85 °C. MPU85-272

1. PIN NAMES AND PIN DESCRIPTION e VSS (Power Supply) Gound e VCC (Power Supply) +5V during operation e DBog-DB7 (Input/Output) Bidirectional data bus. All data and commands are transferred via this data bus. e CLK (Input) System Clock used to generate the TMP82C79 internal timing. e RESET (Input) A high level signal on this pin resets the TMP82C79. After being reset the TMP82C79 is placed in the following state. (1)16 X8 bit character display, left entry. (2)Encode scan keyboard, 2 key lockout, clock pre-scale value is set to 31. e CS (Input) A low level input on this pin enables RD and WR communication between the MPU and the TMP82C79. e Ag (Input) This input acts in conjunction with the CS, WR and RD pins. A high level on this pin indicates the signals on data bus are interpreted as command or status. A low level indicates they are data in the RAMs. e = =WR (Input) A low level input on this pin when CS is low enables the TMP82C79 to accept command or data from the MPU. e = RD (Input) A low level input on this pin when CS is low enables the TMP82C79 to output data or status onto the data bus. MPU85-274

e TRQ (Output) Interrupt request output. In keyboard mode, the interrupt line is high when the FIFO/Sensor RAM has effective data. The interrupt line goes low when each FLFO/Sensor RAM is read and returns high if the RAM still has effective data. In sensor matrix mode, the interrupt line goes high whenever any change in the sensor matrix is detected. e SLo-SL3 (Output) Scan lines which are used to scan the key switch or sensor matrix and the display digits. These lines can be either encoded (1 of 16) or decoded (1 of 4). e RLg-RL7 (Input) Return lines which are connected to the scan lines through the key or sensor switches. Each line has an internal pullup to keep it high until a switch closure pulls it low. They also serve as an 8-bit input in Strobed Input mode. e SHIFT (Input) This input status is stored in the FIFO RAM in addition to the information of the key position on key closure in Scanned key board modes. It has an internal pullup to keep it high until a switch closure pulls it low. e CNTL/STB (Input) For Keyboard modes this line is used as a control input and stored like status on akey closure. This can be also programmed as the strobe line that enters the data into FIFO in Strobed Input mode (Rising Edge). It has an internal pullup to keep it high until a switch closure pulls it low. OUTAp-OUTA3 (Output) OUTBo-OUTB3 (Output) These two ports are the outputs for the 16X4 display refresh registers. The data from these outputs is updated synchronized with the scan lines (SLo-SLg) for multiplexed digit displays. The two 4 bit ports may be blanked independently. These two ports may also be treated as one 8-bit port. e BD (Output) This output is used to blank the display during digit switching or by a display blanking command. MPU85-275

1. FUNCTIONAL DESCRIPTION

6.1 I/O CONTROL AND DATA BUS BUFFER

The I/O control section uses the CS, Ag, RD and WR lines and controls the flow of data to and from the various internal registers and buffers in the TMP82C79. CS input enables the all data flow to and from the TMP82C79. The character of the information given by the MPU, is identified by Ag. RD and WR decide the direction of data flow through the data bus buffer. The data bus buffer is bidirectional buffer which is used for connecting the internal bus and a system bus. When CS is high, the buffer is in a high impedance state.

6.2 CONTROL REGISTER, TIMING REGISTER AND TIMING CONTROL CIRCUIT

Keyboard and display modes and the other operating conditions are programmed by the MPU. These modes are latched at the rising edge of WR when Ag is high. The timing control contains the basic counter chains. The first counter is the 1/N prescaler that can be programmed to yield an basic internal frequncy. In case of 100kHz basic internal frequency, it gives a 5.1 ms keyboard scan time and a 10.3 ms debounce time. The other counters divide down the basic internal frequency to provide the proper key scan, row scan, keyboard matrix scan and display scan timings. 6.3. SCAN COUNTER Two modes are available for the scan counter. In the encode mode, the counter provides a binary count that must be externally decoded to provide the scan lines for the key board and display. In the decode mode, the scan counter decodes the least significant 2 bits internally and provides a decoded 1 of 4 scan. Note that the only first 4 characters in the Display RAM are outputted from OUTAg_3 and OUTBo_3 in the decode mode.

6.4 RETURN BUFFER AND KEYBOARD DEVOUNCE CONTROL CIRCUIT

The 8 return lines are latched onto the return line buffer. In the Keyboard mode, these lines are scanned to look for key closures in a row. If the debounce circuit detects a closed switch, it waits about *10 ms, and checks if the switch remains closed. If it does so, the address of the switch and the status of SHIFT and CNTL lines is transferred to the FIFO. In the scanned Sensor Matrix Modes, the contents of the return lines are directly transferred to the corresponding row of the sensor RAM (FIFO) each scan time. In the Strobed Input Mode, the contents of the return lines are transferred to the FIFO on the rising edge of the CNTL/STB line pulse. MPU85-276

6.5 FIFO/SENSOR RAM AND FIFO/SENSER RAM STATUS

The FIFO/Sensor RAM is a dual function RAM. In the keyboard mode or In the Strobe Input mode, this RAM serves as a FIFO. The FIFO status shows whether the FIFO is empty or full and keeps the number of characters in the FIFO. In addition, there is a flag to show an error in the case where too many reads or writes is recognized. The FIFO status can be read at CS=RD=0, Ag=1. The FIFO status logic provides an IRQ signal when the FIFO is not empty. In the scanned sensor matrix mode, the RAM serves as a sensor RAM. IRQ becomes high when a change in the sensor is detected.

6.6 DISPLAY ADDRESS REGISTERS AND DISPLAY RAM

The display address registers hold the address of the word currently being written or read by the MPU and the two 4 bit nibbles being displayed. The Display RAM stores data for display outputs. The read/write addresses are programmed by the MPU command. They also can be programmed to autoincrement after read or write. The Display RAM can be directry read out by the MPU after mode and address is set. The A and B nibbles of the Display RAM are outputted to the Display Output A and B synchronously with scan signals (SLo-SL3). The A and B nibbles can be entered independently or as one word by the MPU command. * Incase of 100kHz basic internal frequency MPU85-277

1. COMMAND DESCRIPTION 7.1. KEYBOARD/DISPLAY MODE SET DB7 DBg DBs OBg DB3 DB: DB; DBo [otofTofotot«i«]«] DisplayMode r [oo 8x8 bit character display-Left entry ‘o]o]o| Encoded Scan Keyboard-2-Key Lockout * fo] 16 x8 bit character display-Left entry jojo || Decoded Scan Keyboard-2-Key Lockout | Jo | 8x8 bit character display-Right entry 10/1 [0] Encoded Scan Keyboard-N-Key Rollover oo 16 x8 bit character display-Right entry P| Recoded Scan Keyboard-N-Key [ojo| Encoded Scan Sensor Matrix + Default after Reset [ols] Decoded Scan Sensor Matrix [fo] Strobed Input, Encoded Display Scan noe Strobed Input, Decoded Display Scan | 050489

7.2 PROGRAM CLOCK

DB7 DBg DBs DB, DB3 DB2 DB; DBo The TMP82C79 generates all timing and multiplexing signals by means of the internal prescaler. The prescaler generates internal reference clocks by dividing an external supply clock by a programmable value PPPPP. Any number from 2 to 31 can be set as a prescaler value. When this value is set to 0 or 1, it is interpreted to be 2. If the internal reference clock is set to 100kHz, it is possible to obtain 5.1ms keyboard scan time and 10.3ms debounce time. The value PPPPP is set to 31 after reset, but cannot be changed by the Clear command. MPU85-278

7.3. READ FIFO/SENSOR RAM DB7 DBs DBs DBa DB3 DB2 DB; DBo If this command is written, the subsequent data reads are set up for the FIFO/Sensor RAM. Auto-increment flag (AI) and the RAM address bits AAA are valid only in Senser Matrix Mode. The address bits AAA select one of the 8 rows of the Sensor RAM. If AI=1, the RAM address is incremented after each successive read. The Auto-increment flag does not affect the auto-increment of the Display RAM.

7.4 READ DISPLAY RAM

DB7 DBs DBs DBy DB3 DB) DB; OB If this command is written, the subsequent data reads are set up for the Display RAM. The address bits AAAA select one of the 16 rows of the Display RAM. If AI=1, the address is incremented after each read or write to the Display RAM. Since the same counter is used for both reading and writing, this command sets the next read or wirte address and the sense of the Auto-increment for both operation.

7.5 WRITE DISPLAY RAM

DB7 DBs DBs DBq DB3 D82_ DB; _DBo If this command is written, the subsequent data writes are set up for the Display RAM. Note that writing this command does not switch the source of the subsequent data reads. The address register of the Display RAM is same for read/write operations. The addressing and Auto-increment function are identical to those for the Read Display RAM.

7.6 DISPLAY WRITE INHIBIT/BLANKING

D87 DBs DBs DBq DB3 DB2 DB; DB . The IWA or IWB bit can be used to mask A nibble or B nibble for entering the Display data independently. The BLA of BLB flag is available for the nibble A or B to blank the display. In the case where the Display Outputs are used as separate 4-bit display ports, the IWA or IWB bit is useful so as not to affect the other display port when the MPU writes a word to the display RAM. The BLA or BLB bit is used for blanking the display independently without giving any affect to the other 4-bit display port. The blank code is determined by the last Clear command that has been programmed after reset. If the Display Output is used as an 8-bit port, it is necessary to set both BLA and BLB bits for blnaking the display. Then BD signal becomes low. MPU85-279

DB7 DBs DBs DBg DB3 DBz DB; DBo A Pt tt tt tt AR A2 A Ao B3 Bo By Bo Correspondence between Display Output and Data Bus soe

7.7 CLEAR

DB7 DBs DBs DBq DB3 DB2 DB; DB The CD bits are used to clear all rows of the Display RAM to the following code shown below. (DBg) (DB3) (DB2) cD cD cD 1 0 x +++ All Zeros (X = Don't Care) 1 1 0 +++ All Hex 20H (0010 0000) 1 1 1 ++++ AltOnes it} x x +++: notclear display if CA=0 4 ____ Enable clear display when CD = 1 (or by CA=1) osoae9 While the Display RAM is being cleared, it may not write to the Display RAM. The MSB bit of the FIFO status word is set during this time. If the CF bit is set to "1", the FIFO status is cleared and the interrupt request output (IRQ) is reset. Also, the Senser RAM pointer is set to the row 0. The CA bit has the combined effect of the CD bit and CF bit. It enables clear display code to the Display RAM and also clears the FIFO status. Furthermore, it re- synchronizes the internal timing chains.

7.8 END INTERRUPT/ERROR MODE SET

DB7 DBs DBs DB, DB3 DB2 DB; Bo don" In the Sensor Matrix mode, this command loweres the IRQ line and enables writing to the sensor RAM. This means that a write to the Sensor RAM is inhibited when IRQ line is high. Ifthe E bit is set to"1", the S/E bit of the FIFO status becomes "1" when any one of the sensor switches is closed. If E=0, the S/E bit is always "0". In the N-Key Rollover mode, if the E bit is programmed to "1", the Special Error mode will be resulted. MPUB5-280

7.9 FIFOSTATUS

DB7 DBs DBs DBg DB3 DB2 DB; DBo X: don't care [oulse fo lul*[w[n[n] ee | Number of characters in FIFO Error-Underrun Error-Overrun Multiple Closures Display unavailable 050489 Du : Indicates that the Display RAM was unavailable because a Clear Display or Clear All command has not completed its clearing operation. SIE : In a Sensor Matrix mode, if the E bit of End Interrupt/error mode set is programmed to "0", this S/E bit is set to indicate that at least one sensor closure indication is contained in the Sensor RAM. In Special Error Mode, this S/E bit is showing the error flag and serves as an indication to whether a simultaneous multiple closure error has occurred. ie) : indicates that the entry of another character into a full FIFO was attempted. U : indicates that the MPU tried to read an empty FIFO. F : indicates that the FIFO is full of the eight characters. NNN _ : indicates number of characters in the FIFO when in the Keyboard Mode or in | the Strobe Input Mode. Table 7.1 ADDRESSING Te[a [elm [smn pee pe [a [eon Pete [ae [icon Pea [os [reasoe Pe Te wt conan | DTT ishinpadacse | 050489 MPU85-281

1. INTERFACE WITH KEYBOARD

8.1 SCANNED KEYBOARD, 2-KEY LOCKOUT

In this mode, if one key only is kept depressed during one debounce cycle (2 times of the key scan cycle), the key is recognized. When a key is depressed, the debounce logic is set and the other depressed keys are checked during the next two scan cycle. If none are encountered, it is a single key depression and the key position is entered into the FIFO along with the status of CNTL and SHIFT lines. If another depressed key are encountered, operates as follows. KEY1 4 t t Ay DEBOUNCE CYCLE KEY2 Eo |r t t ene 0 es 0 es 0 4 ‘ 4 os0489 Figure 8.1 Example of a Case Where a First Depressed Key is Continuously Kept to the Last es Oe 0 es ee 2 ee 2 4 t t t KEY2 es 0 es 0 t t rs ee es t t t 4 +++ Debounce logic is set { +++ Entered to FIFO 50489 Figure 8.2 Example of a Case Where all Depressed Keys are Ignored As shown in Figure 8.1 if all the other keys are released before the first depressed key, the first depressed key is recognized. As shown in Figure 8.2 if the first depressed key is released within one debounce cycle after the other keys was released, then all keys are ignored. MPU85-282

8.2 SCANNED KEYBOARD, N-KEY ROLLOVER

In this mode, each key depression is independently treated from all others. In the 2- key lockout mode, if a key is depressed, the debounce logic is set. If the other keys are depressed within one debounce cycle after it, the debounce logic is set again. The first depressed key is ignored. In the N-key Rollover mode, if a key is depressed waits one debounce cycle and then checks of the key is still down. If it is, the key is entered into the FIFO even of other keys are depressed. KeY1 3 t 1 DEBOUNCE CYCLE acres 0 eee 0 es 8 ee 2 t KEY3 4. 1DEBOUNCE CYCLE osoae Figure 8.3 Example of 3 Keys Being Pushed Simultaneously In the example as shown in Figure 8.3 the debounce circuit starts by Key 1, and checks if the key is still down after one debounce cycle. If it is, Key 1 is recognized and Key 2 is ignored not to be depressed for one debounce cycle. 8.3. SPECIAL ERROR MODE (N-KEY ROLLOVER) This mode is set if the E bit of the End interrupt/error mode set command is programmed to "1". In the normal N-Key Rollover Mode, the key information is entered to the FIFO according to the key scan timing even if a simultaneous multiple depression occures during one debounce cycle. In the Special Error Mode, if a simultaneous multiple depression occurs during one debounce cycle, sets the error falg (the S/E bit of the FIFO status word) to "1". This flag prevents any further writing into the FIFO and will set interrupt request (IRQ). The S/E bit is cleared if the normal Clear command is written with CF=1.

8.4 SENSOR MATRIX MODE

In Sensor Matrix Mode, the debounce circuit does not operate. The status of the sensor switch is inputted directly to the Sensor RAM. The MPU can only know a validated closure in the keyboard mode, however this mode has such advantage that the CPU knows how long the sensor was closed and when it was released. If there is any change in the sensor value at the end of the sensor matrix scan, the IRQ line goes high. The IRQ line is cleared by the first data read if the Auto-increment flag is "0" or by the End Interrupt/error mode set command if AI=1. MPU85-283

8.5 STROBE INPUT MODE

Tn Strobe Input Mode, the debounce circuit does not operate. The data is inputted into the FIFO from the return lines at the rising edge of CNTL/STB Signal. When the data is entered into the FIFO, the IRQ line goes high. The functions of the FIFO and the FIFO status in this mode are same as those in the keyboard mode. 9. DATA FORMAT

9.1 KEYBOARD MODE

DB7 DBe DBs DB4a DB3 DBz DB; DBo In this mode, the Data Format of the character entered into the FIFO is as follows. The MSB is the status of CNTL/STB line and the next MSB shows the status of SHIFT line. The next three bits are from the scan counter and indicate the row the key was found in. The last three bits are from the column counter and indicate to which return line the key was connected.

9.2 SENSOR MATRIX MODE

DB7 DBs DBs DBa 0B; DB2 DB; DBo [m[ne]ne[ae]m [em 7 In this mode, the data on return lines is inputted in the row of the Sensor RAM in order according to the scan. The data is entered even if there is no change in the status of the sensor matrix switches. Each switch position maps to a Sensor RAM position. CNTL and SHIFT signals are ignored. 9.3. STROBE INPUT MODE DB7 DBs DBs DB4 DB3 DBz DB; DBo . In this mode, the data on return lines is entered into FIFO at the rising edge of CNTLASTB signal. MPU85-284

1. INTERFACE WITH DISPLAY

10.1 LEFT ENTRY

In Left Entry mode, address 0 of the Display RAM is the left-most side of the display and address 15 (address 7 in the case of 8-character display) is the right-most side. when characters are inputted onto the display RAM with the auto increment mode from address 0 of the display RAM, Characters are filled from the left-most position of the display. The 17th (or 9th) character is placed in the left-most position again. Address of the display RAM corresponds directly to each display positon of the display, and so its position does not change every entry. < Dispiay RAM Address > 0 1 Woe 1415 i) 1 2 3.4 ~ 5 6 7 0 1 Woe 1415 0 1 2 3.4 5 6 7 andentry [7 [2 TT) andentry 0 ae 1415 Command _2 1 2 3 4 5 6 7 vethentry [4 [2 T3516} enryyL1 ]2] | JT ToT 7) (10010101) Entry from Address 5 with Auto increment mode. Oot 14 15 o 1 2 3 4 5 6 7 rrheney Ga as [6] aenty CTT TT st a O14 15 o 1 2 3 4 5 6 7 iethentry (77 [ie [as 16] athentry (4 T2T TT 3 T4T osoasa MPU85-285

10.2 RIGHT ENTRY

In Right Entry, the first entry is from the right-most position. Address of the Display RAM does not correspond to the display position. © Display RAM Address > 12a 5 0 o 1 2 3 4 5 6 7 rstenyy CD ET] stemty Go 203 15 8 2,93 4 5 6 7 O 1 andenty [To Pte] andenty GD OT] 304 0 tt 2) command 2 3 4 5 6 7 OO 1 ardentry FD eT te CD (10010101) Right entry from Address 5 with Auto- increment mode i) 1 a 13, 14 (15 3 4 5 6 7 O 1 2 tethentry [7 [2 TO ardentry [J [3t fT [if2t | 1214 15 0 4 5 6 7 O0 1 2 3 whenty (QTE se 7] thenty (TS Te Tre 2 3 a 15 0 1 5 6 7 0 1 2.3 4 18th entry [1647 [78] Sthentry [3 Tats Taif2y TT] 1 6 7 O 1 2 3 4 5 siheny [aps pele). 1 13] 2 3 4 5 6 7 0 1 rohentry [Ee] SOPs ATS 1617] 3. 4 5 6 7 0 1 2 iithenty [9 [wT 4] s] 6178] os0ag9 MPU85-286

1. ELECTRIC CHARACTERISTICS

11.1 ABSOLUTE MAXIMUM RATINGS

Vee VCC Supply Voltage (with respect to VSS(GND)) | -0.5to +7.0 VIN Input Voltage (with respect to VSS (GND) ) -O0.5toVCC+0.5 } Vv Vout {| Output Voltage (with respect to VSS (GND) ) Pp Power Dissipation 250 Tsot Soldering Temperature (soldering time 10 sec) 260 5089 11.2. D.C. ELECTRICAL CHARACTERISTICS (Ta = - 40 to +85 °C, Vcc = 5V + 10%, Vss (GND) = OV) PARAMETER CONDITION =| MIN. UNIT Input Low Voltage _ 14 Input Low Voltage | Input High Voltage Vint euaRL vec +0.5| Vv Input High Voltage Vine (Others) Vec+ 0.5) V Hai awige [tezaee P= Ss fiwsvee ==] | Input 1LEAK Current | -30 | hua (SHIFT, CNTL, Rug-RL7) LVIN=2.4V | -10 [ -30 | - | ws | Input Leak Current | ovevin< + In (hers) OVS VINS Vcc +10 | pa ort Output Leak Current | 0.45VS VouTS vec [| - [| = [+0 J aa | , VIH =VCC-0.2V lec Operating Supply ViL=0.2V, 5 mA fe=5MHz os0ees MPU85-287

11.3 INPUT CAPACITY

symBoL | PARAMETER CONDITION typ. | max 50089 11.4 A.C. ELECTRICAL CHARACTERISTICS Ta= -40 to +85°C, VCC =5.0V + 10%, VSS (GND) = 0V tar ‘Address Set up Time (RD) | w | - | - | ns | *tap | Address to Valid Data | - | - | 185 | ns tor | Data Floating (RD) | w | - | 85 ns Fiver wiveyietne a | CLK Pulse Width of Low Level 50 Clock Period 200 50008 *TEST CONDITION CL = 150pF 11.4.1. AC TEST CONDITION but }— sb cle 150pF L ososss

14.4.2 AC TESTINPUT WAVEFORM

72, Gest 2 > pont < 0.45 0.8 0.8 osoaes MPU85-288

1. EXAMPLE OF APPLICATION CIRCUIT SHIFT KEYBOARD MATRIX

8 COLUMNS

SHIFT CNTL Rlg~7 8 = IRQ a 3-98 DECODER }

2 DATA BUS A OBo~7 ot LU —__}

a — 8 ISCAN LINE 4 (LSB 3 BIT) CONTROL WR Wa 2 sto~3 4 3 / RESET Cc Sl 2 — eSeT RESET = 7 xt a 2 appress{ n ° ° & Ag Ao 4-316 DECODER

3 ED)

. cLock CLK _.} cuk OUTB9~3 OUTA9~3 16 BLANKING ADDRESS (DECODER)

4 DISPLAY DATA

Figure 13.1 EXAMPLE OF APPLICATION CIRCUIT MPU85-291

1. EXTERNAL DIMENSION 14.1 40PIN DIP EXTERNAL DIMENSION DIP40-P-600 Unit: mm 49 2 ae} in D) = E \\ | 3 2 | ei 7 20 3 50.7+02 i $f Ni} IT ilaitarairatnaitt : < ” ——s—-th 1.22TYP rates foster array 2 osoaes Note: Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoritical positions with respect to No.1 and No.40 leads. MPU85-292

14.2 40PIN SOP EXTERNAL DIMENSION SSOP40-P-450 Unit: mm 4 21 HOnMONgggnoqoRneg HHEHEHEHHSSHAHRRERY ntl ~ a Fo val] os “WS eo =e Y HOHE AH AAHARABHARARG 7 GOOCEUOAUSRROECER EEG 1 20] 1.ASTYP 0.35401 d.ustyP 08 fr { _ 17.5+0.2 w / eS | ——F | ae oy Aw ' / a1) . . 3 ° 08202 050489 | Note : Package Width and Length do not include Mold Protrusions. Allowable Mold Protrusion is 0.15mm. MPU85-293

PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE TMP8279P-5 1. GENERAL DESCRIPTION The TMP8279P-5 (hereinafter referred to as TMP8279) is a programmable keyboard/display interface designed for use as the TLCS-85A microcomputer peripheral. The keyboard portion can provide a scanned interface to a 64-contact key matrix. Also, the keyboard portion can interface to an array of sensors or a strobed interface keyboard. Key depressions can be 2-key lockout or N-key rollover. The display portion has 16x8 bits display RAM which can be treated as dual 16X4 bits. Both right entry and left entry display formats are possible. 2. FEATURES . Simulataneous Keyboard/Display operation is possible . Scanned Keyboard mode. . Scanned Sensor Matrix mode. e Strobed Input Entry mode. ° Buil in 8-character FIFO or 64 bit Sensor RAM e Programmable 2 Key Lockout or N-key Rollover with contact Debounce. ° Built in 16 <8 bit display RAM. e Programmable scan timing e Compatible with INTEL 8279-5. MPU85-294

1. PINNAME AND PIN DESCRIPTION e VSS (Power Supply) Ground e VCC (Power Supply) +5V during operaiton . DBo~DB7 (Input/Output) Bidirecitonal Data Bus. All data and commands are transfered via this data bus. e CLK (Input) System clock used to generate the TMP8279 internal timing. e RESET (Input) A high level signal on this pin resets the TMP8279. After being reset the TMP8279 is placed in the following state. (1) 16X8 bit character display, left entry. (2) Encode scan keyboard, 2 key lockout, clock pre-scale value is set to 31. e =CS (Input) A low level input on this pin enables RD and WR communication between the MPU and the TMP8279. e Ag (Input) This inputs acts in conjunction with the CS, WR and RD pins. A high level input on this pin indicates the signals on data bus are interpreted as command or status. A low level input indicates they are data in the RAMs, e = WR(Input) A low level input on this pin when CS is low enables the TMP8279 to accept command or data from the MPU. e RD (Input) A low level input on this pin when CS is low enables the TMP8279 to output data or status onto the bus. MPU85-296

° IRQ (Output) Interrupt request output. In a keyboard mode, the interrupt line is high when the FIFO/Sensor RAM has effective data. The interrupt line goes low when each FIFO/Sensor RAM read and returns high if the RAM still has effective data. In sensor matrix mode, the interrupt line goes high whenever any change in the sensor matrix is detected. @ ~~ SLo~SL3 (Output) Scan lines which are used to scan the key switch or the sensor matrix and the display digits. These lines can be either encoded (1 of 16) of decode (1 of 4). ° RLo~RL7 (Input) Return lines which are connected to the scan lines through the keys or sensor switches. Each line has an internal pullup to kery “' high until a switch closure pulls it low. They also serve as an 8-bit input in Strobed Input mode. © SHIFT (Input) This input status is stored in the FIFO RAM in addition to information of the key position on key closure in Scannned key board modes. It has an internal pullup to keep it high until a switch closure puils it low. e = CNTL/STB (Input) For Keyboard modes this line is used as a control input and stored like status on a key closure. This can be programmed as the strobe line that enters the data into FIFO in Strobed Input mode (Rising Edge). It has an internal pullup to keep it high until a switch closure pulls it low. . OUTA9~OUTA3 (Output) © OUTBo~OUTB3 (Output) These two ports are the outputs for the 16 4 display refresh registers. The data from these outputs is updated synchronized with the scan lines (SLg~SLg) for multiplexed digit displays. The two 4 bit ports may be blanked independently. These two ports may also be treated as one 8-bit port. e =BD (Output) This output is used to blank the display during digit switching or by a display blanking command. MPU85-297

1. FUNCTIONAL DESCRIPTION

6.1 WO CONTROL AND DATA BUS BUFFER

The I/O control section uses the CS, Ag, RD and WR lines and controls the flow of data to and from the various internal registers and buffers in the TMP8279. CS input enables the all data flow to and from the TMP8279. The character of the information given by the MPU, is identified by Ag. RD and WR decide the direction of data flow through the data bus buffer. The data bus buffer is bidirectional buffer which is used for connecting the internal bus and a system bus. When CS is high, the buffer is in a high impedance state.

6.2 CONTORL REGISTER, TIMING REGISTER AND TIMING CONTROL CIRCUIT

The keyboard and display modes or the other operating conditions are programmed by the MPU. These modes are latched at the rising edge of WR when Ag is high. The timing control contains the basic counter chains. The first counter is the 1/N prescaler that can be programmed to yield an basic internal frequency which gives a 5.1ms keyboard scan time and a 10.3ms debounce time. The other counters divide down the basic internal frequency to provide the proper keyboard matrix scan and display scan timings.

6.3 SCAN COUNTER

Two modes are available for the scan counter. In the encode mode, the counter provides a binary count that must be externally decoded to provide the scan lines for the key board and display. In the decode mode, the scan counter decodes the least significant 2 bits internally and provides a decoded 1 of 4 scan. Note that the only first 4 characters in the Display RAM are outputted from OUTAg.3 and OUTBg.3 in the decode mode.

6.4 RETURN BUFFER AND KEYBOARD DEVOUNCE CONTROL CIRCUITS

The 8 return lines are latched onto the return line buffer. In the Keyboard mode, these lines are scanned to look for key closures in a row. If the debounce circuit detects a closed switch, it waits about 10ms*, and checks if the switch remains closed. If it does so, the address of the switch and the status of SHIFT and CNTL lines is transferred to the FIFO. MPU85-298

6.5 FIFO/SENSOR RAM AND FIFO/SENSOR RAM STATUS

The FIFO/Sensor RAM is a dual funciton RAM. In the keyboard mode or in the Strobe Input mode, this RAM serves as a FIFO. The FIFO status shows whether the FIFO is empty or full and keeps the number of characters in the FIFO. In addiiton, there is a flag to show an error in the case where too many reads or writes is recognized. The FIFO status can be read at CO=RD=0, Ag=1. The FIFO status logic provides an IRQ signal when the FIFO is not empty. In the scanned sensor matrix mode, the RAM serves as a Sensor RAM. IRQ becomes high when a change in the sensor is detected. The display address registers hold the address of the word currently being written or read by the MPU and the two 4 bit nibbles being displayed. The Display RAM stores data for display outputs. The read/write addresses are programmed by the MPU command. They also can be programmed to auto-increment after read or wirte. The Display RAM can be directy read out by the MPU after mode and address is set. The A and B nibbles of the Display RAM are outputted to the Display Outputs A and B syncronously with scan signals (SLg~SL3). The A and B nibbles can be entered independently or as one word by the MPU command. * Jn case of LOOKHz basic internal frequency. MPU85-299

1. COMMAND DESCRIPTION 7.1. KEYBOARD/DISPLAY MODE SET DB7 DBs DBs DBg DB3 DB2 DB; DB» Leofofolotoyt« ~ ij Display Mode i Keyboard Mode 8x8 bit character display - { Encoded Scan Keyboard — lo o | Left entry ia *|0 [elo 2-Key Lockout 1 16 x8 bit character display — g | 1 | Decoded Scan Keyboard - * Left entry _ 2-Key Lockout : 8x8 bit character display — 1 | 9 | Encoded Scan Keyboard ~ | Right entry N-Key Rollover 16 x 8 bit character display — ila Decoded Scan Keyboard - 1] TRight entry J N-Key Rollover [fo 0 | Encoded Scan Sensor Matrix * Default after reset ”

1 Decoded Scan Sensor Matrix

ito] Strobed Input, Encoded Display Scan 1 1 | Strobed input, Decoded Display Scan 050489 7.2. PROGRAM CLOCK DB7 DBs DBs DBa DB3 DB2 DB: _DBy The TMP8279 generates all timing and multiplexing signals by means of the internal prescaler. The prescaler generates internal reference clocks by dividing an external supply clock by a programmable value PPPPP. Any number from 2 to 31 can be set asa prescaler value. When this value is set to 0 or 1, it is interpreted to be 2. If the internal reference clock is set to 100kHz, it is possible to obtain 5.1ms keyboard scan time and 10.3ms debounce time. The value PPPPP is set to 31 after reset, but cannot be changed by the Clear command. MPU85-300

7.3. READ FIFO/SENSOR RAM OB; DBs DBs DBa DB3 DB2 DBi DBo [oT To Tal x [ala [a | X=sonteare esos If this command is writen, the subsequent data reads are set up for the FIFO/Sensor RAM. Auto-increment flag (AI) and the RAM address bits AAA are valid only in Sensor Matrix Mode. The address bits AAA select one of the 8 rows of the Sensor RAM. If Al=1, the RAM address is incremented after each successive read. The Auto- incremented flag does not affect the auto-increment of the Display RAM. 7.4. READ DISPLAY RAM DB7 DBe DBs DBqg DB3 DB2 DB; DBo If this command is written, the subsequent data reads are set up for the Display RAM. The address bits AAAA select one of the 16 rows of the Display RAM. If AI=1, the address is incremented after each read or write to the Display RAM. This command sets the next read or write address and the sense of the Auto-increment. DB7 DBg DBs OBa DB3 DBz DB1 DBo Lato totajatatala esos if this command is written, the subsequent data writes are set up for the Display | RAM. Note that writing this command does not switch the source of the subsequent data reads. The address register of the Display RAM is same for read/write operations. The addressing and Auto-increment funciton are identical to those for the Read Display RAM. MPU85-301

DB7 DBe DBs DBg D83 DB2 DB; DBo The IWA or IWB bit can be used to mask A nibble or B nibble for entering the Display data independently. The BLA or BLB flag is available for the nibble A or B to blank the display. In the case where the Display Outputs are used as separate 4-bit display ports, the IWA or IWB bit is useful so as not to affect the other display port when the MPU writes a word to the display RAM. The BLA or BLB bit is used for blanking the display independently without giving any affect to the other 4-bit display port. The blank code is determined by the last Clear command that has been programmed after reset. If the Display Output is used as an 8-bit port, it is necessary to set both BLA and BLB bits for blanking the display. The BD signal becomes low. DB7 DBg DBs DB, D83 DBz DB; DBo Az Az Ar Ago 83 B2 By Bo Correspondence between Display Output and Data Bus osoaes MPU85-302

DBy DBs DBs DBg DB3 DB: DB; DBo The Cp bits are used to clear all rows of the Dislay RAM to the following code shown below. (DB4) {DB3) (DB2) Co Cp Cp 1 0 x «+++ All Zeros (X = Don't Care) i 1 0 +++ All Hex 20H (0010 0000) i 1 1 sees All Ones 0 x x «+++ notcear display ifCa=0 to Enable clear display when Cp = 1 (or by Ca = 1) 050489 While the Display RAM is being cleared, it may not write to the Display RAM. The MSB bit of the FIFO status word is set during this time. If the Cr bit is set to “1”, the FIFO status is cleared and the interrupt request output (IRQ) is reset. Also, the Sensor RAM pointer is set to the row 0. The Ca bit has the combined effect of the Cp bit and Cy bit. It enables clear display code to the Display RAM and also clears the FIFO status. Furthermore, it re- synchronizeds the inernal timing chains. DB7 DBg DBs DB4 DB3 DB2 DB; D8 Pata tr fet x | «x |x [x] % don'tere esate In the Sensor Matrix mode, this command loweres the IRQ line and enables writing to the Sensor RAM. This means that a write to the Sensor RAM is inhibited when IRQ line is high. Ifthe E bit is set to “1”, the S/E bit of the FIFO status becomes “1” when any one of the sensor switches is closed. If E=0, the S/E bit is always “O”. In the N-Key Rollover, if the E bit is progrmamed to “1”, the Special Error mode will be resulted. MPU85-303

DB7 DBs DBs DBa DB3 D82 DB, DBo FIFO Full Error-Overrun Sensor Closure/Error Flag for Multiple Closures Du: indicates that the Display RAM is unavailable because a Clear Display or Clear All command has not completed its clearing operation. S/E : in a Sensor Matrix mode, if the E bit of End Interrupt/Error Mode Set is programmed to “1”, this S/E bit is set to indicate that at least one sensor closure indication is contained in the Sensor RAM. In Special Error Mode, this S/E bit is showing the error flag and serves as an indication to whether a simulataneous multiple closure error has occured. O : indicates that the entry of another character into a full FIFO was attempted. U : indicates that the MPU tried to read an empty FIFO. F : indicates that the FIFO is full of the eight characters. NNN : indicate number of characters in the FIFO when in the Keyboard Mode or in the Strobe Input Mode. Table 7.1 Addressing fe[=[e [mT mon | 0 0 0 1 Read Data o | Oo 1 0 Write Data 0 1 0 1 Read Status word 0 1 1 0 Write Command word 1 x x x High-impedance state 050489 MPU85-304

1. INTERFACE WITH KEYBOARD

In this mode, if one key only is kept depressed during one debounce cycle (2 times of the key scan cycle), the key is recognized. When a key is depressed, the debounce logic is set and the other depressed keys are checked during the next two scan cycle. If none are encountered, it is a single key depressing and the key position is entered into the FIFO along with the status of CNTL and SHIFT lines. If another depressed key are encountered, operates as follows. KEY 1 { f 4 t t 1DEBOUNCE CYCLE KEY 2 ee Os Se t t 69 a A 4 t 0s0489 Figure 8.1 Example of a case where a first (lepressed key is continuously kept to the las ee Oe ees 2 ees 2 ee 2 t f 4 4 KEY 2 es 0 ees 0 t t es es 0 es 0 t t t 4 -+++ Debounce logics set $ “+++ Entered to FIFO osoea9 Figure 8.2 Example of a case where all depressed keys are ignored As shown in Figure 8.1, if all the other keys are released before the first depressed key, the first depressed key is recognized. As shown in Figure 8.2, if the first depressed key is released within one debounce cycle after the other keys was released, than all keys are ignored. In this mode, each key depression is independently treated from all others. In the 2- Key lockout mode, if a key is depressed, the debounce logic is set. If the other keys are depressed within one debounce cycle after it, the debounce logic is set again. The first MPU85-305

depressed key is ignored. In the N-key Rollover mode, if a key is depressed waits one debounce cycle and then checks if the key is still down. If it is, the key is entered into the FIFO even if other keys are depressed. Eto t 1DEBOUNCE CYCLE | a eee ee es 2 t KEY3 f 4 1oEBOUNCE CYCLE ‘os0609 Figure 8.3 Example of 3 keys being pushed simultaneously In the example as shown in Figure 8.3, the debounce circuit starts by Key 1, and checks if the key is still down after one debounce cycle. If it is, Key 1 is recognized and Key 2 is ignored not to be depressed for one debounce cycle.

8.3 SPECIAL ERROR MODE (N-KEY ROLLOVER)

This mode is set if the E bit of the End Interrupt/error Mode Set command is programmed to “1”. In the normal N-Key Rollover Mode, the key information is entered to the FIFO according to the key scan timing even if a simulataneous multiple depression occures during one debounce cycle. In the Special Error Mode, if a simulataneous multiple depression occurs during one debounce cycle, sets the error flag (the S/E bit of the FIFO status word) to “1”. This flag prevents any further writing into the FIFO and will set interrupt request (IRQ). The S/E bit is cleared if the normal Clear command is written with Cr=1. In Sensor Matrix Mode, the debounce circuit does not operate. The status of the sensor switch is inputted directly to the Sensor RAM. The MPU can know a validated closure in the keyboard, however this mode has such advantage that the MPU knows how long the sensor was closed and when it was released. If there is any change in the sensor value at the end of the sensor matrix scan, the IRQ line goes high. The IRQ line is cleared by the first data read if the Auto-increment flag is “O” or by the End Interrupt/Error Mode Set command if AI=1. In Strobe Input Mode, the debounce circuit does not operate. The data is inputted into the FIFO from the return lines at the rising edge of CNTL/STB Signal. When the data is entered into the FIFO, the IRQ line goes high The functions of the FIFO and the FIFO status in this mode are same as those in the keyboard mode. MPU85-306

1. DATA FORMAT

DB7 DBs DBs DBq DB3 DB2 DB, DB Cr 7 In this mode, the Data Format of the character entered into the FIFO is as follows. The MSB is the status of CNTL/STB line and the next MSB shows the status of SHIFT line. The next three bits are from the scan counter and indicate the row the key was found in. The last three bits are from the column counter and indicate to which return line the key was connected. DB; DBe DBs DBq DB3 DB2 DB; DBo [nae] me] [om] [ms [a] v In this mode, the data on return lines is inputted in the row of the Sensor RAM in order according to the scan. The data is entered even if there is no change in the status of the sensor matrix switches. Each switch position maps to a Sensor RAM position. CNTL and SHIFT signals are ignored.

9.3 STROBE INPUT MODE

DB7_ DBs DBs DBg_ _DB3_ DB DB; _DBo_ | fen] ee] no] mr] 7 in this mode, the data on the return line is entered into the FIFO at the rising edge of CNTL/STB signal. MPU85-307

1. INTERFACE WITH DISPLAY

In Left Entry mode, address 0 of the Display RAM is the left-most side of the display and address 15 (address 7 in the case of 8-character display) is the right-most side. When characters are inputted onto the Display RAM with the auto-increment mode from address 0 of the display RAM, Characters are filled from the left-most position of the display. The 17th (or 9th) character is placed in the left-most position again. Address of the display RAM corresponds directly to each display position of the display, and so its position does not change every entry. < Display RAM Address > i) 1 1415 0 1 2 3 4 5 6 7 rstentry CTT TT] wey GET TT PT o.4 1415 o 1 2 3 4 5 6 7 and entry TL andenty (XT 2P 1 TT 1 Td o 1 1415 command 9 1 2 3 4 5 6 7 tethenty [7 T2 TO entry [112] [ [J [| T 1 3 (10010101) Entry from Address 5 with Auto increment mode. ie) 1 . 1415 ie) 1 2 3 4 5 6 7 ‘th entry , ardentry [a [27 TT [3st Tt] 0 i . a 1415 0 1 2 3.4 ~=6S 6 7 18th entry athenty (4727 T JT [3 t4T | osoa89 MPU85-308

In Right Entry, the first entry if from the right-most position. Address of the Display RAM does not correspond to the display position. © Display RAM Address > 1 2 . 14 15 O 0 i 2 3 4 § 6 7 2.3 i501 203 4 5 6 7 oO 1 2nd entry andenty [1 [2], | [ | 1 [2 34 0 1 2 + command 2.3 4 5 6 7 0 1 ardentry ( .T write] [1 1. | [+12] (10010101) Right Entry from Address 5 with Auto-increment mode 0 1 13, (14 «(15 3.4 5 6 7 O 1 2 16th entry 7 ardenty [ [Tsp 1 7+? 1 1 2 14 15 0 4 5 6 7 0 1 2 3 ithentry [273] 16 [17] 4thenty [_T3 [74] Til2y Ty 2 3 15 0 1 5 6 7 O 1 2 3.4 rethentry (3 Ta sthenry (3 ]#@]>5]>1[?]7 1 1 6 7 0 1 2 3 4 5 6thentry [a [5 [6 [2 L J 3 203 4 5 6 7 O 1 rothenty [es] 9TWl3 14] 5] 617] 3 4 5 6 7 0 1 2 iithenty [spoT aT4 Tsp é6]7 1a] osoaea MPU85-309

1. ELECTRIC CHARACTERISTICS

Vee Supply Voltage (with respect to GND (Vas) Input Voltage (with respect to GND (ss) Output Voltage (with respect to GND (Vss)) | -o5to +70 Pp Power Dissipation i 1 w Toot Soldering Temperature (soldering time 10 sec) | 260 °C Storage Temperature | 65to +150 Operating Temperature | Oto 70 050289 11.2 D.C. ELECTRICAL CHARACTERISTICS (Ta =0 to 70°C, Vcc = 5V t 10%, Vss5 = OV) SYMBOL PARAMETER CONDITIONS UNIT Mina BA 050269

11.4 A.C. ELECTRICAL CHARACTERISTICS (Ta =0 to 70°C, Vec = 5.0V + 10%, Vss = OV) Pet] Address Set up Time (RD 1) ——ae tao Valid Data (RD 7) C= 150pF | | 150 | ns aie ‘Address Set up Time (WR |) ft ‘Address Hold Time (WR 7) — 2b ns tww__ | WR Pulse Width ee ee Data Set up Time (WR?) | wo) =| | ns Ke Hold Time (WRT) aor as tow | CiK Pulse Width | ss | (| _ns | pores MPU85-311

1. EXTERNAL DIMENSION 13.1 40 PIN DIP EXTERNAL DIMENSION DIP40-P-600 Unit : mm 40 21 _ " mnooooannonenoenanst 3 E S| fg Ss) ia 8 1 20 5 50.7202 $f [ee WEL WL WO Oy oye} m H z a —_ stis Som 1.22TYP 14201 llossor arom S os0a89 Note: Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoritical positions with respect to No.1 and No.40 leads. MPU85-314

1. EXAMPLE OF APPLICATION CIRCUIT SHIET KEYBOARD hoot a MATRIX LINE 8 __ 8 COLUMNS

8 ROWS

8-BiT SHIFT CNTL RLo~7 8 MICROPROCESSOR| SYSTEM IRQ Cl

38 DECODER

DATA BUS DBo~7 _ T RD RD M SCAN LINE TPs Wa RO P 4 (LSB 3 BIT) CONTROL wee |e g sto-al 4 U S RESET (| cS a 7 f la ADDRESS 4 Ao fo i 4 16 DECODER clock ss cLK OQUTBo~3_OUTAg~3 16 BLANKING ADDRESS (DECODER) a DISPLAY DATA DISPLAY 050089 Figure 14.1 Example of Application Circuit MPU85-315