TMP75C TI | Alldatasheet
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/cb13 /cb12 /cb11 /cb175 /cb150 /cb125 0 25 50 75 100 125 150 Temperature Error (/c83C) Temperature (/c83C) Mean Mean - 6/c31 Mean + 6/c31 C005 TMP75C SDA SCL GND ALERT VS 0.01 /c50F Two-Wire Host Controller 1.4 V to 3.6 V Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community TMP75C SBOS707B –APRIL 2014–REVISED AUGUST 2014 TMP75C1.8-VDigitalTemperatureSensorwithTwo-WireInterfaceandAlert
1 Features 3 Description
The TMP75C is an integrated digital temperature 1• Low-Voltage Alternative to NCT75 and ADT75 sensor with a 12-bit analog-to-digital converter (ADC)• Digital Output with Two-Wire Serial Interface that can operate at a 1.8-V supply, and is pin and
- Up to 8 Pin-Programmable Bus Addresses register compatible with the NCT75 and ADT75. This device is available in SOIC-8 and VSSOP-8• Overtemperature ALERT Pin with Programmable packages and requires no external components toTrip Values sense the temperature. The TMP75C is capable of• Shutdown Mode for Battery Power Saving reading temperatures with a resolution of 0.0625°C
- One-Shot Conversion Mode and is specified over a temperature range of –55°C to +125°C.• Operating Temperature Range: –55°C to +125°C
- Operating Supply Range: 1.4 V to 3.6 V The TMP75C features SMBus and two-wire interface compatibility, and allows up to eight devices on the• Quiescent Current: same bus with the SMBus overtemperature alert– 15 μA Active (typ) function. The programmable temperature limits and – 0.3 μA Shutdown (typ) the ALERT pin allow the sensor to operate as a stand-alone thermostat, or an overtemperature alarm• Accuracy: for power throttling or system shutdown.– ±0.25°C (typ) from 0°C to +70°C The factory-calibrated temperature accuracy and the– ±0.5°C (typ) from –20°C to +85°C noise-immune digital interface make the TMP75C the– ±1°C (typ) from –55°C to +125°C preferred solution for temperature compensation of
- Resolution: 12 Bits (0.0625°C) other sensors and electronic components, without the need for additional system-level calibration or• Packages: SOIC-8 and VSSOP-8 elaborate board layout for distributed temperature sensing.2 Applications The TMP75C is ideal for thermal management and• Server and Computer Thermal Management protection of a variety of consumer, computer,• Telecommunication Equipment communication, industrial, and environmental• Office Machines applications.
- Video Game Consoles Device Information(1)
- Set-Top Boxes DEVICE NAME PACKAGE BODY SIZE (NOM)• Power Supply and Battery Thermal Protection SOIC (8) 4.90 mm × 3.90 mm• Thermostat Control TMP75C VSSOP (8) 3.00 mm × 3.00 mm
- Environmental Monitoring and HVAC (1) For all available packages, see the package option addendum• Electrical Motor Driver Thermal Protection at the end of the datasheet. Temperature Accuracy (Error) vs Ambient Simplified Schematic Temperature An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SBOS707B –APRIL 2014–REVISED AUGUST 2014 www.ti.com Table of Contents
4 Revision History
Changes from Revision A (April 2014) to Revision B Page Changes from Original (April 2014) to Revision A Page
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5 Pin Configuration and Functions
(Top View) Pin Functions PIN I/O DESCRIPTION NAME NO. A0 7 I Address select. Connect to GND or VS. A1 6 I Address select. Connect to GND or VS. A2 5 I Address select. Connect to GND or VS. ALERT 3 O Overtemperature alert. Open-drain output; requires a pull-up resistor. GND 4 — Ground. SCL 2 I Serial clock. SDA 1 I/O Serial data. Open-drain output; requires a pull-up resistor. VS 8 I Supply voltage, 1.4 V to 3.6 V. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TMP75C
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, VS 4 V SDA, SCL, ALERT, A2, A1 -0.3 4 V Input voltage Sink current SDA, ALERT 10 mA Operating junction temperature -55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
Tstg Storage temperature range -60 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2000 2000ElectrostaticV(ESD) Vdischarge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –1000 1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage 1.4 1.8 3.6 V Operating free-air temperature, TA -55 125 °C
6.4 Thermal Information
THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 125.4 188.1 RθJC(top) Junction-to-case (top) thermal resistance 71.5 79.1 RθJB Junction-to-board thermal resistance 65.8 109.6 °C/W ψJT Junction-to-top characterization parameter 21.1 15.3 ψJB Junction-to-board characterization parameter 65.3 108 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE INPUT Temperature range –55 +125 °C Temperature resolution 0.0625 °C Temperature accuracy –20°C to +85°C ±0.5 ±2 °C(error) DIGITAL INPUT/OUTPUT VIH High-level input voltage 0.7(VS) VS V VIL Low-level input voltage -0.3 0.3(VS) V IIN Input current 0 V < VIN < (VS) + 0.3 V 1 μA VS ≥ 2 V, IOUT = 3 mA 0.4 VLow-level outputVOL voltage VS < 2 V, IOUT = 3 mA 0.2(VS) V ADC resolution 12 Bit Conversion time One-shot mode 20 27 35 ms Update Rate 80 ms Bus timeout time 16 22 29 ms POWER SUPPLY Operating supply range 1.4 3.6 V Serial bus inactive 15 37 μA IQ Quiescent current Serial bus active, SCL frequency = 400 kHz 25 μA Serial bus active, SCL frequency = 3.4 MHz 95 μA Serial bus inactive 0.3 8 μA ISD Shutdown current Serial bus active, SCL frequency = 400 kHz 10 μA Serial bus active, SCL frequency = 3.4 MHz 80 μA Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TMP75C
6.6 Typical Characteristics
At TA = 25°C and VS = +1.8 V (unless otherwise noted). Figure 1. Quiescent Current vs Temperature Figure 2. Shutdown Current vs Temperature Figure 3. Conversion Time vs Temperature Figure 4. Quiescent Current vs Bus Frequency Figure 6. Temperature Error at 25°CFigure 5. Temperature Error vs Temperature
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OscillatorVoltage Regulator TMP75C www.ti.com SBOS707B –APRIL 2014–REVISED AUGUST 2014
7 Detailed Description
7.1 Overview
The TMP75C is a digital temperature sensor optimal for thermal management and thermal protection applications. The TMP75C is two-wire and SMBus interface compatible, and is specified over a temperature range of –55°C to +125°C. The temperature sensing device for the TMP75C is the chip itself. A bipolar junction transistor (BJT) inside the chip is used in a band-gap configuration to produce a voltage proportional to the chip temperature. The voltage is digitized and converted to a 12-bit temperature result in degrees Celsius, with resolution of 0.0625°C. The package leads provide the primary thermal path because of the lower thermal resistance of the metal. Thus, the temperature result is equivalent to the local temperature of the printed circuit board (PCB) where the sensor is mounted.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Digital Temperature Output
below 1°C is not required. Table 1 summarizes the temperature data format. One LSB equals 0.0625°C. Negative numbers are represented in binary twos complement format. Table 1. Temperature Data Format(1) (1) The temperature sensor resolution is 0.0625°C/LSB. a given temperature, and vice versa. format, and MSB = 0 to denote a positive sign. decimal number. Then, multiply the decimal number by the resolution to obtain the positive temperature. number and adding one. Denote a negative number with MSB = 1.
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7.3.2 Temperature Limits and Alert
an interrupt, and is set by the TM bit in the Configuration register (Table 6). counter prevents false alerts as a result of environmental noise. shutdown mode description). This action also clears the fault counter memory. various modes is illustrated in Figure 7. Figure 7. ALERT Pin Modes of Operation
7.3.3 Serial Interface
7.3.3.1 Bus Overview
generates the start and stop conditions. generating an acknowledge bit and pulling SDA low.
7.3.3.2 Serial Bus Address
addressed on a single bus. The TMP75C latches the status of the address pins at the start of a communication. Table 2 describes the pin logic levels and the corresponding address values. Table 2. Address Pin Connections and Slave Addresses
1001000 GND GND GND
1001001 GND GND VS
1001010 GND VS GND
1001011 GND VS VS
1001100 VS GND GND
1001101 VS GND VS
1001110 VS VS GND
1001111 VS VS VS
7.3.3.3 Writing and Reading Operation
bit low. Every write operation to the TMP75C requires a value for the pointer register (see Figure 9). changed by the next write operation. Note that register bytes are sent with the most significant byte first, followed by the least significant byte.
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7.3.3.4 Slave Mode Operations
The TMP75C can operate as a slave receiver or slave transmitter.
7.3.3.4.1 Slave Receiver Mode:
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP75C then acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The TMP75C then acknowledges reception of the pointer register byte. The next byte or bytes are written to the register addressed by the pointer register. The TMP75C acknowledges reception of each data byte. The master can terminate data transfer by generating a start or stop condition.
7.3.3.4.2 Slave Transmitter Mode:
The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master can terminate data transfer by generating a not-acknowledge bit on reception of any data byte, or by generating a start or stop condition.
7.3.3.5 High-Speed (Hs) Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an SMBus Hs-mode master code (00001xxx) as the first byte after a start condition to switch the bus to high-speed operation. The TMP75C does not acknowledge this byte, but does switch its input filters on SDA and SCL and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3 MHz. After the Hs-mode master code has been issued, the master transmits a two-wire slave address to initiate a data-transfer operation. The bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop condition, the TMP75C switches the input and output filters back to fast-mode operation.
7.3.3.6 Timeout Function
The TMP75C resets the serial interface if SCL or SDA are held low for 22 ms (typ) between a start and stop condition. If the TMP75C is pulled low, it releases the bus and then waits for a start condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1 kHz for the SCL operating frequency. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TMP75C
7.3.3.7 Two-Wire Timing
Bus Idle Both SDA and SCL lines remain high. start condition. Each data transfer is initiated with a start condition. stop condition. Each data transfer is terminated with a repeated start or stop condition. determined by the master device. or stop condition on the bus. Acknowledge Each receiving device, when addressed, must generate an acknowledge bit. (1) on the last byte transmitted by the slave. Table 3. Timing Diagram Requirements Hold time after repeated start condition.t(HDSTA) 600 160 nsAfter this period, the first clock is generated.
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7.3.3.8 Two-Wire Timing Diagrams
Figure 8. Two-Wire Timing Diagram (1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins. Figure 9. Two-Wire Timing Diagram for Write Word Format
(1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins. (2) Master should leave SDA high to terminate a single-byte read operation. (3) Master should leave SDA high to terminate a two-byte read operation. Figure 10. Two-Wire Timing Diagram for Read Word Format
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7.4 Device Functional Modes
7.4.1 Continuous-Conversion Mode
makes a conversion, and then powers down and waits for a delay 53 ms. current during delay is 1 μA (typical at +25°C). (1) Delay is set to 53 ms (typ). Figure 11. Conversion Start
7.4.2 Shutdown Mode
clear until the SD bit is set.
7.4.3 One-Shot Mode
OS bit, and a write to the one-shot register has no effect.
7.5 Programming
write command. Figure 13 identifies the bits of the pointer register byte. Figure 12. Internal Register Structure
7.6 Register Map
of the bits in each register. Table 4. Register Map and Pointer Addresses Figure 13. Pointer Register (pointer = N/A) [reset = 00h]
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Figure 16. TLOW - Temperature Low Limit Register (pointer = 2h) reset = 4B00h Table 7. TLOW Register Description Figure 17. THIGH - Temperature High Limit Register (pointer = 3h) reset = 5000h Table 8. THIGH Register Description
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8 Application and Implementation
8.1 Application Information
watchdog operation of all devices, interrupting the host controller only if the temperature exceeds the limits.
8.2 Typical Application
Figure 18. Temperature Monitoring of Multiple Locations on a PCB
8.2.1 Design Requirements
resistors. To configure one of eight different addresses on the bus, connect A0, A1, and A2 to either VS or GND.
8.2.2 Detailed Design Procedure
8.2.3 Application Curves
temperature (27°C). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 seconds. Figure 19. Temperature Step Response
9 Power Supply Recommendations
supply but can measure temperature accurately in the full supply range. or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
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10 Layout
10.1 Layout Guidelines
noisy or high-impedance power supplies. through 10-kΩ pull-up resistors.
10.2 Layout Example
Figure 20. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
SBOU141 — TMP75xEVM User's Guide
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TMP75C
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TMP75CID Obsolete Production SOIC (D) | 8 - - Call TI Call TI -55 to 125 TMP75C TMP75CIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG | SN Level-2-260C-1 YEAR -55 to 125 T75C TMP75CIDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -55 to 125 T75C TMP75CIDGKT Obsolete Production VSSOP (DGK) | 8 - - Call TI Call TI -55 to 125 T75C TMP75CIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 TMP75C TMP75CIDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 TMP75C (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 23-May-2025 OTHER QUALIFIED VERSIONS OF TMP75C :
- Automotive : TMP75C-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP75CIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 TMP75CIDR SOIC D 8 2500 356.0 356.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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