1.8-V Digital Temperature Sensor with Two-Wire Interface and Alert
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SBOS721,*]
- PDF pages: 31
Technical content
/cb13 /cb12 /cb11 /cb175 /cb150 /cb125 0 25 50 75 100 125 150 Temperature Error (/c83C) Temperature (/c83C) Mean Mean - 6/c31 Mean + 6/c31 C005 SDA SCL GND ALERT VS 0.01 /c50F Two-Wire Host Controller TMP75B-Q1 1.4 V to 3.6 V Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community TMP75B-Q1 SBOS721 –OCTOBER 2014 TMP75B-Q11.8-VDigitalTemperatureSensorwithTwo-WireInterfaceandAlert
1 Features 3 Description
The TMP75B-Q1 is an integrated digital temperature 1• Qualified for Automotive Applications sensor with a 12-bit analog-to-digital converter (ADC)• AEC-Q100 Qualified with the Following Results: that can operate at a 1.8-V supply, and is pin and – Temperature Grade 1: –40°C to 125°C register compatible with the industry-standard LM75 and TMP75. This device is available in SOIC-8 and– HBM ESD Classification 2 VSSOP-8 packages, and requires no external– CDM ESD Classification C4B components to sense the temperature. The TMP75B-
- Digital Output with Two-Wire Serial Interface Q1 is capable of reading temperatures with a resolution of 0.0625°C and is specified over a• Up to 8 Pin-Programmable Bus Addresses temperature range of –40°C to 125°C.• Programmable Overtemperature ALERT The TMP75B-Q1 features SMBus and two-wire• Shutdown Mode for Power Saving interface compatibility, and allows up to eight devices• One-Shot Conversion Mode on the same bus with the SMBus overtemperature• Operating Temperature Range: –40°C to 125°C alert function. The programmable temperature limits
- Operating Supply Range: 1.4 V to 3.6 V and the ALERT pin allow the sensor to operate as a stand-alone thermostat, or an overtemperature alarm• Quiescent Current: for power throttling or system shutdown.– 45 μA Active (typ) The factory-calibrated temperature accuracy and the– 0.3 μA Shutdown (typ) noise-immune digital interface make the TMP75B-Q1• Accuracy: the preferred solution for temperature compensation – ±0.5°C (typ) from –20°C to 85°C of other sensors and electronic components, without the need for additional system-level calibration or– ±1°C (typ) from –40°C to 125°C elaborate board layout for distributed temperature• Resolution: 12 Bits (0.0625°C) sensing.
- Packages: SOIC-8 and VSSOP-8 The TMP75B-Q1 is ideal for thermal management and protection of a variety of automotive applications,2 Applications and is a high-performance alternative to a PCB-
- Automotive Embedded Systems mounted NTC thermistor.
- ECU Processor Temperature Monitoring Device Information(1)
- TCM Processor Temperature Monitoring DEVICE NAME PACKAGE BODY SIZE (NOM)
- BCM Processor Temperature Monitoring SOIC (8) 4.90 mm × 3.90 mm TMP75B-Q1• LED Headlight Thermal Control VSSOP (8) 3.00 mm × 3.00 mm
- Battery Thermal Protection (1) For all available packages, see the package option addendum
- Electrical Motor Driver Thermal Protection at the end of the datasheet. Temperature Accuracy (Error) vs Ambient Simplified Schematic Temperature An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SBOS721 –OCTOBER 2014 www.ti.com Table of Contents
4 Revision History
October 2014 * Initial release.
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5 Pin Configuration and Functions
(Top View) Pin Functions PIN I/O DESCRIPTION NAME NO. A0 7 I Address select. Connect to GND or VS. A1 6 I Address select. Connect to GND or VS. A2 5 I Address select. Connect to GND or VS. ALERT 3 O Overtemperature alert. Open-drain output; requires a pull-up resistor. GND 4 — Ground SCL 2 I Serial clock SDA 1 I/O Serial data. Open-drain output; requires a pull-up resistor. VS 8 I Supply voltage, 1.4 V to 3.6 V Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TMP75B-Q1
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VS 4 V SDA, SCL, ALERT, A2, A1 –0.3 4 V Input voltage Sink current SDA, ALERT 10 mA Operating junction temperature –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
Tstg Storage temperature range –60 150 °C Human body model (HBM), per AEC Q100-002(1) –2000 2000 Corner pins (1, 4, 5,V(ESD) Electrostatic discharge –1000 1000 VCharged device model (CDM), per and 8) AEC Q100-011 Other pins –1000 1000 (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage 1.4 1.8 3.6 V Operating free-air temperature, TA –40 125 °C
6.4 Thermal Information
THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 125.4 188.1 RθJC(top) Junction-to-case (top) thermal resistance 71.5 79.1 RθJB Junction-to-board thermal resistance 65.8 109.6 °C/W ψJT Junction-to-top characterization parameter 21.1 15.3 ψJB Junction-to-board characterization parameter 65.3 108 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE INPUT Temperature range –40 125 °C Temperature resolution 0.0625 °C –20°C to 85°C ±0.5 ±2 °CTemperature accuracy (error) –40°C to 125°C ±1 ±3 °C DIGITAL INPUT/OUTPUT VIH High-level input voltage 0.7(VS) VS V VIL Low-level input voltage –0.3 0.3(VS) V IIN Input current 0 V < VIN < (VS) + 0.3 V 1 μA VS ≥ 2 V, IOUT = 3 mA 0.4 VLow-level outputVOL voltage VS < 2 V, IOUT = 3 mA 0.2(VS) V ADC resolution 12 Bit Conversion time One-shot mode 20 27 35 ms CR1 = 0, CR0 = 0 (default) 37 Conv/s CR1 = 0, CR0 = 1 18 Conv/s Conversion modes CR1 = 1, CR0 = 0 9 Conv/s CR1 = 1, CR0 = 1 4 Conv/s Timeout time 38 54 70 ms POWER SUPPLY Operating supply range 1.4 3.6 V Serial bus inactive, CR1 = 0, CR0 = 0 (default) 45 89 μA Serial bus inactive, CR1 = 0, CR0 = 1 22 48 μA IQ Quiescent current Serial bus inactive, CR1 = 1, CR0 = 0 12 30 μA Serial bus inactive, CR1 = 1, CR0 = 1 6.5 21 μA Serial bus inactive 0.3 8 μA ISD Shutdown current Serial bus active, SCL frequency = 400 kHz 10 μA Serial bus active, SCL frequency = 3.4 MHz 80 μA Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TMP75B-Q1
6.6 Typical Characteristics
At TA = 25°C and VS = 1.8 V (unless otherwise noted). Figure 1. Quiescent Current vs Temperature Figure 2. Shutdown Current vs Temperature Figure 3. Conversion Time vs Temperature Figure 4. Quiescent Current vs Bus Frequency Figure 6. Temperature Error at 25°CFigure 5. Temperature Error vs Temperature
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OscillatorVoltage Regulator TMP75B-Q1 www.ti.com SBOS721 –OCTOBER 2014
7 Detailed Description
7.1 Overview
The TMP75B-Q1 is a digital temperature sensor optimal for thermal management and thermal protection applications. The TMP75B-Q1 is two-wire and SMBus interface compatible, and is specified over a temperature range of –40°C to 125°C. The temperature sensing device for the TMP75B-Q1 is the chip itself. A bipolar junction transistor (BJT) inside the chip is used in a band-gap configuration to produce a voltage proportional to the chip temperature. The voltage is digitized and converted to a 12-bit temperature result in degrees Celsius, with a resolution of 0.0625°C. The package leads provide the primary thermal path because of the lower thermal resistance of the metal. Thus, the temperature result is equivalent to the local temperature of the printed circuit board (PCB) where the sensor is mounted.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Digital Temperature Output
represented in binary twos complement format. Table 1. Temperature Data Format(1) (1) The temperature sensor resolution is 0.0625°C/LSB. a given temperature, and vice versa. format, and MSB = 0 to denote a positive sign. decimal number. Then, multiply the decimal number by the resolution to obtain the positive temperature. number and adding one. Denote a negative number with MSB = 1. multiply by the resolution to get the absolute temperature, then multiply by –1 for the negative sign.
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7.3.2 Temperature Limits and Alert
an interrupt, and is set by the TM bit in the configuration register (Table 7). counter prevents false alerts as a result of environmental noise. cycle repeats with the ALERT pin becoming active when the temperature equals or exceeds THIGH, and so on. various modes is shown in Figure 7. Figure 7. ALERT Pin Modes of Operation
7.3.3 Serial Interface
7.3.3.1 Bus Overview
generates the start and stop conditions. generating an acknowledge bit and pulling SDA low.
7.3.3.2 Serial Bus Address
communication. Table 2 describes the pin logic levels and the corresponding address values. Table 2. Address Pin Connections and Slave Addresses
1001000 GND GND GND
1001001 GND GND VS
1001010 GND VS GND
1001011 GND VS VS
1001100 VS GND GND
1001101 VS GND VS
1001110 VS VS GND
1001111 VS VS VS
7.3.3.3 Writing and Reading Operation
bit low. Every write operation to the TMP75B-Q1 requires a value for the pointer register (see Figure 9). changed by the next write operation. Note that register bytes are sent with the most significant byte first, followed by the least significant byte.
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7.3.3.4 Slave-Mode Operations
The TMP75B-Q1 can operate as a slave receiver or slave transmitter.
7.3.3.4.1 Slave Receiver Mode:
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP75B-Q1 then acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The TMP75B-Q1 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the register addressed by the pointer register. The TMP75B-Q1 acknowledges reception of each data byte. The master can terminate data transfer by generating a start or stop condition.
7.3.3.4.2 Slave Transmitter Mode:
The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master can terminate data transfer by generating a not-acknowledge bit on reception of any data byte, or by generating a start or stop condition.
7.3.3.5 SMBus Alert Function
The TMP75B-Q1 supports the SMBus alert function. When the TMP75B-Q1 operates in interrupt mode (TM = 1), the ALERT pin may be connected as an SMBus alert signal. When a master senses that an alert condition is present on the ALERT line, the master sends an SMBus alert command (00011001) to the bus. If the ALERT pin is active, the device acknowledges the SMBus alert command and responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates whether the alert condition is caused by the temperature exceeding THIGH or falling below TLOW. The LSB is high if the temperature is greater than THIGH, or low if the temperature is less than TLOW. See Figure 11 for details of this sequence. If multiple devices on the bus respond to the SMBus alert command, arbitration during the slave address portion of the SMBus alert command determines which device clears its alert status first. If the TMP75B-Q1 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus alert command. If the TMP75B-Q1 loses the arbitration, its ALERT pin remains active.
7.3.3.6 General Call
The TMP75B-Q1 responds to a two-wire general call address (0000000) if the eighth bit is 0. The device acknowledges the general call address and responds to commands in the second byte. If the second byte is 00000100, the TMP75B-Q1 latches the status of the address pin, but does not reset. If the second byte is 00000110, the TMP75B-Q1 internal registers are reset to power-up values.
7.3.3.7 High-Speed (Hs) Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an SMBus Hs-mode master code (00001xxx) as the first byte after a start condition to switch the bus to high-speed operation. The TMP75B-Q1 does not acknowledge this byte, but does switch its input filters on SDA and SCL and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3 MHz. After the Hs-mode master code has been issued, the master transmits a two-wire slave address to initiate a data-transfer operation. The bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop condition, the TMP75B-Q1 switches the input and output filters back to fast-mode operation.
7.3.3.8 Timeout Function
The TMP75B-Q1 resets the serial interface if SCL or SDA are held low for 54 ms (typ) between a start and stop condition. If the TMP75B-Q1 is pulled low, it releases the bus and then waits for a start condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1 kHz for the SCL operating frequency. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TMP75B-Q1
7.3.3.9 Two-Wire Timing
Bus Idle Both SDA and SCL lines remain high. start condition. Each data transfer is initiated with a start condition. stop condition. Each data transfer is terminated with a repeated start or stop condition. determined by the master device. or stop condition on the bus. Acknowledge Each receiving device, when addressed, must generate an acknowledge bit. (1) on the last byte transmitted by the slave. Table 3. Timing Diagram Requirements Hold time after repeated start condition.t(HDSTA) 600 160 nsAfter this period, the first clock is generated.
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7.3.3.10 Two-Wire Timing Diagrams
Figure 8. Two-Wire Timing Diagram (1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins. Figure 9. Two-Wire Timing Diagram for Write Word Format
(1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins. (2) Master should leave SDA high to terminate a single-byte read operation. (3) Master should leave SDA high to terminate a two-byte read operation. Figure 10. Two-Wire Timing Diagram for Read Word Format (1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins. Figure 11. Timing Diagram for SMBus Alert
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7.4 Device Functional Modes
7.4.1 Continuous-Conversion Mode
shows the settings for CR1 and CR0. Table 4. Conversion Rate Settings After power-up or a general-call reset, the TMP75B-Q1 immediately starts a conversion, as shown in Figure 12. at 25°C). The quiescent current during delay is 1 μA (typical at 25°C). (1) Delay is set by the CR bits in the configuration register. Figure 12. Conversion Start
7.4.2 Shutdown Mode
and the fault counter until a rising edge is generated on the shutdown signal.
7.4.3 One-Shot Mode
temperature monitoring is not required. When the configuration register is read, the OS bit always reads zero.
7.5 Programming
read or write command. Figure 14 identifies the bits of the pointer register byte. Figure 13. Internal Register Structure
7.6 Register Map
description of the bits in each register. Table 5. Register Map and Pointer Addresses Figure 14. Pointer Register (pointer = N/A) [reset = 00h]
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Figure 17. TLOW: Temperature Low Limit Register (pointer = 2h) reset = 4B00h Table 8. TLOW Register Description Figure 18. THIGH: Temperature High Limit Register (pointer = 3h) reset = 5000h Table 9. THIGH Register Description
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
watchdog operation of all devices, interrupting the host controller only if the temperature exceeds the limits.
8.2 Typical Application
Figure 19. Temperature Monitoring of Multiple Locations on a PCB
8.2.1 Design Requirements
present on the SCL as well. A 0.01-μF bypass capacitor on the supply is recommended, as shown in Figure 19.
8.2.2 Detailed Design Procedure
8.2.3 Application Curve
temperature (27°C). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 seconds. Figure 20. Temperature Step Response
9 Power-Supply Recommendations
supply but can measure temperature accurately in the full supply range. high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
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10 Layout
10.1 Layout Guidelines
Place the power-supply bypass capacitor as close as possible to the supply and ground pins.
10.2 Layout Example
Figure 21. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
SBOU141 — TMP75xEVM User's Guide
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 11-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMP75BQDGKRQ1 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T75BQ TMP75BQDGKTQ1 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T75BQ TMP75BQDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-2-260C-1 YEAR -40 to 125 T75BQ TMP75BQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-2-260C-1 YEAR -40 to 125 T75BQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
www.ti.com 11-Apr-2015 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMP75B-Q1 :
- Catalog: TMP75B NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Dec-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP75BQDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0 TMP75BQDGKTQ1 VSSOP DGK 8 250 366.0 364.0 50.0 TMP75BQDRQ1 SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Dec-2015 Pack Materials-Page 2
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