TMP75-Q1 TI | Alldatasheet
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ΔΣ ADC OSC Control Logic Serial Interface Config. and T e mp. Reg ister T emperature ALERT SDA 1 5GND SCL 2 7 A0 T emp. SCL ALERT GND Two-Wire Host Controller TMP175-Q1, TMP75-Q1 SDA 5-k Pullup Resistors 0.01-µF Supply Bypass Capacitor 2.7-V to 5.5-V Supply Voltage Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community TMP175-Q1,TMP75-Q1 SBOS759 –NOVEMBER 2015 TMPx75-Q1AutomotiveGradeTemperatureSensorWithI2CandSMBusInterfacein Industry-StandardLM75FormFactorandPinout
1 Features 3 Description
The TMP75-Q1 and TMP175-Q1 devices are digital 1• AEC-Q100 Qualified with: temperature sensors ideal for negative temperature– Temperature Grade 1: –40°C to +125°C coefficient (NTC) and positive temperature coefficientAmbient Operation Temperature Range (PTC) thermistor replacement. The devices offer a – HBM ESD Classification Level 2 typical accuracy of ±1°C without requiring calibration or external component signal conditioning. Device– CDM ESD Classification Level C6 temperature sensors are highly linear and do not• TMP175-Q1 Accuracy: require complex calculations or look-up tables to – ±1°C (Typical) from –40°C to +125°C derive the temperature. The on-chip, 12-bit, analog- to-digital converter (ADC) offers resolutions down to– ±2°C (Maximum) from –40°C to +125°C 0.0625°C. The devices are available in the industry-• TMP75-Q1 Accuracy: standard, LM75, 8-pin SOIC and VSSOP footprint. – ±1°C (Typical) from –40°C to +125°C The TMP175-Q1 and TMP75-Q1 feature SMBus,– ±3°C (Maximum) from –40°C to +125°C two-wire, and I2C interface compatibility. The
- TMP175-Q1: 27 Addresses TMP175-Q1 device allows up to 27 devices on one bus. The TMP75-Q1 allows up to eight devices on• TMP75-Q1: 8 Addresses, NIST Traceable one bus. The TMP175-Q1 and TMP75-Q1 both• Digital Output: SMBus™ , Two-Wire, and I2C feature an SMBus alert function.Interface Compatibility The TMP175-Q1 and TMP75-Q1 devices are ideal for• Resolution: 9 to 12 Bits, User-Selectable extended temperature measurement in a variety of• Low Quiescent Current: 50-μA, 0.1-μA Standby communication, computer, consumer, environmental,
- Wide Supply Range: 2.7 V to 5.5 V industrial, and instrumentation applications. The TMP75-Q1 production units are 100% tested against• Small 8-Pin VSSOP and 8-Pin SOIC Packages sensors that are NIST-traceable and are verified with equipment that are NIST-traceable through ISO/IEC2 Applications 17025 accredited calibrations.
- Climate Controls The TMP175-Q1 and TMP75-Q1 devices are• Infotainment Processor Management specified for operation over the temperature range of
- Airflow Sensors –40°C to +125°C.
- Battery Control Units Device Information(1)
- Engine Control Units PART NUMBER PACKAGE BODY SIZE (NOM)• UREA Sensors SOIC (8) 4.90 mm × 3.91 mm TMPx75-Q1• Water Pumps VSSOP (8) 3.00 mm × 3.00 mm
- HID Lamps (1) For all available packages, see the orderable addendum at
- Airbag Control Units the end of the data sheet. Simplified Schematic TMP175-Q1 and TMP75-Q1 Internal Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP175-Q1,TMP75-Q1 SBOS759 –NOVEMBER 2015 www.ti.com Table of Contents
4 Revision History
November 2015 * Initial release.
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Product Folder Links: TMP175-Q1 TMP75-Q1
TMP175-Q1,TMP75-Q1 www.ti.com SBOS759 –NOVEMBER 2015
5 Pin Configuration and Functions
DGK, D Packages 8-Pin VSSOP, SOIC Top View NOTE: Pin 1 is determined by orienting the package marking as indicated in the diagram. Pin Functions PIN I/O DESCRIPTION NO. NAME 1 SDA I/O Serial data. Open-drain output; requires a pullup resistor. 2 SCL I Serial clock. Open-drain output; requires a pullup resistor. 3 ALERT O Overtemperature alert. Open-drain output; requires a pullup resistor.
4 GND — Ground
6 A1 I Address select. Connect to GND, V+, or (for the TMP175-Q1 device only) leave these pins floating. 7 A0 8 V+ I Supply voltage, 2.7 V to 5.5 V Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TMP175-Q1 TMP75-Q1
TMP175-Q1,TMP75-Q1 SBOS759 –NOVEMBER 2015 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Power supply, V+ 7 V Input voltage(2) –0.5 7 V Input current 10 mA Operating temperature –55 127 °C Junction temperature, TJ 150 °C Storage temperature, Tstg –60 130 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input voltage rating applies to all TMP175-Q1 and TMP75-Q1 input voltages.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage 2.7 5.5 V Operating free-air temperature, TA –40 125 °C
6.4 Thermal Information
TMP175-Q1, TMP75-Q1 THERMAL METRIC(1) DGK (SOIC), D (VSSOP) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 185 °C/W RθJC(top) Junction-to-case (top) thermal resistance 76.1 °C/W RθJB Junction-to-board thermal resistance 106.4 °C/W ψJT Junction-to-top characterization parameter 14.1 °C/W ψJB Junction-to-board characterization parameter 104.8 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: TMP175-Q1 TMP75-Q1
TMP175-Q1,TMP75-Q1 www.ti.com SBOS759 –NOVEMBER 2015
6.5 Electrical Characteristics
at TA = –40°C to +125°C and V+ = 2.7 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE INPUT Range –40 125 °C –25°C to +85°C TMP75-Q1 ±0.5 ±2 Accuracy (temperature error) °C TMP175-Q1 ±1 ±2 –40°C to +125°C TMP75-Q1 ±1 ±3 Accuracy (temperature error) vs supply 0.2 ±0.5 °C/V Resolution(1) Selectable 0.0625 °C DIGITAL INPUT/OUTPUT Input capacitance 3 pF VIH High-level input logic 0.7 (V+) 6 V VIL Low-level input logic –0.5 0.3 (V+) V IIN Leakage input current 0 V ≤ VIN ≤ 6 V 1 µA Input voltage hysteresis SCL and SDA pins 500 mV SDA IOL = 3 mA 0 0.15 0.4 VOL Low-level output logic V ALERT IOL = 4 mA 0 0.15 0.4 Resolution Selectable 9 to 12 Bits 9 bits 27.5 37.5 10 bits 55 75 Conversion time ms 11 bits 110 150 12 bits 220 300 Timeout time 25 54 74 ms POWER SUPPLY Operating range 2.7 5.5 V Serial bus inactive 50 85 IQ Quiescent current Serial bus active, SCL frequency = 400 kHz 100 µA Serial bus active, SCL frequency = 3.4 MHz 410 Serial bus inactive 0.1 3 ISD Shutdown current Serial bus active, SCL frequency = 400 kHz 60 µA Serial bus active, SCL frequency = 3.4 MHz 380 TEMPERATURE RANGE Specified range –40 125 °C Operating range –55 127 °C (1) Specified for 12-bit resolution. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TMP175-Q1 TMP75-Q1
TMP175-Q1,TMP75-Q1 SBOS759 –NOVEMBER 2015 www.ti.com
6.6 Timing Requirements
see the Timing Diagrams and Two-Wire Timing Diagrams sections for additional information(1) HIGH-SPEEDFAST MODE MODE UNIT MIN MAX MIN MAX ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.38 MHz Bus-free time between STOP and STARTt(BUF) 1300 160 nscondition Hold time after repeated START condition.t(HDSTA) 600 160 nsAfter this period, the first clock is generated. See the Timing Diagrams sectiont(SUSTA) Repeated START condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time 4 900 4 120 ns t(SUDAT) Data setup time 100 10 ns t(LOW) SCL clock low period V+ , see the Timing Diagrams section 1300 280 ns t(HIGH) SCL clock high period See the Timing Diagrams section 600 60 ns tFD Data fall time See the Timing Diagrams section 300 150 ns See the Two-Wire Timing Diagrams section 300 40 ns tRC Clock rise time SCLK ≤ 100 kHz, see the Timing Diagrams 1000 nssection tFC Clock fall time See the Two-Wire Timing Diagrams section 300 40 ns (1) Values are based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and are not production tested.
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Product Folder Links: TMP175-Q1 TMP75-Q1
6.7 Typical Characteristics
Figure 1. Quiescent Current vs Temperature Figure 2. Shutdown Current vs Temperature Figure 4. Temperature Error vs TemperatureFigure 3. Conversion Time vs Temperature Figure 5. Quiescent Current With Bus Activity vs Temperature
ΔΣ ADC OSC Control Logic Serial Interface Config. and T e mp. Reg ister T emperature ALERT SDA 1 5GND SCL 2 7 A0 T emp. TMP175-Q1,TMP75-Q1 SBOS759 –NOVEMBER 2015 www.ti.com
7 Detailed Description
7.1 Overview
The TMP175-Q1 and TMP75-Q1 devices are digital temperature sensors that are optimal for thermal management and thermal protection applications. The TMP175-Q1 and TMP75-Q1 are two-wire, SMBus, and I2C interface compatible. The devices are specified over a temperature range of –40°C to +125°C. The Functional Block Diagram section shows the internal block diagram of the TMP175-Q1 and TMP75-Q1 devices. The temperature sensor in the TMP175-Q1 and TMP75-Q1 devices is the chip itself. Thermal paths run through the package leads as well as the plastic package. The package leads provide the primary thermal path because of the lower thermal resistance of the metal.
7.2 Functional Block Diagram
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Product Folder Links: TMP175-Q1 TMP75-Q1
7.3 Feature Description
7.3.1 Digital Temperature Output
Table 7. The first 12 bits are used to indicate temperature with all remaining bits equal to zero. The data format for temperature is listed in Table 1. Negative numbers are represented in binary twos complement format. Following power-up or reset, the Temperature register reads 0°C until the first conversion is complete. register are used with the unused least significant bits (LSBs) set to zero. Table 1. Temperature Data Format
7.3.2 Serial Interface
high-speed (up to 2.38-MHz) modes. All data bytes are transmitted MSB first.
7.3.2.1 Bus Overview
generates the START and STOP conditions. responds to the master by generating an Acknowledge bit and pulling SDA low.
7.3.2.2 Serial Bus Address
of executing a read or write operation. The TMP175-Q1 features three address pins to allow up to 27 devices to be addressed on a single bus interface. prior to any activity on the interface. Table 2. Address Pins and Slave Addresses for the TMP175-Q1
0 Float 0 0101000
0 Float 1 0101001
1 Float 0 0101010
1 Float 1 0101011
0 Float Float 0110101
1 Float Float 0110110
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address is latched to minimize power dissipation associated with detection. Table 3. Address Pins and Slave Addresses for the TMP75-Q1
7.3.2.3 Writing and Reading to the TMP175-Q1 and TMP75-Q1
value for the Pointer register (see Figure 7). slave address byte with the R/W bit low, followed by the Pointer register byte. No additional data are required. remember the Pointer register value until it is changed by the next write operation. Register bytes are sent MSB first, followed by the LSB.
7.3.2.4 Slave Mode Operations
The TMP175-Q1 and TMP75-Q1 can operate as a slave receiver or slave transmitter.
7.3.2.4.1 Slave Receiver Mode
7.3.2.4.2 Slave Transmitter Mode
data byte, or by generating a START or STOP condition.
TMP175-Q1,TMP75-Q1 SBOS759 –NOVEMBER 2015 www.ti.com
7.3.2.5 SMBus Alert Function
The TMP175-Q1 and TMP75-Q1 support the SMBus alert function. When the TMP75-Q1 and TMP175-Q1 are operating in interrupt mode (TM = 1), the ALERT pin of the TMP75-Q1 or TMP175-Q1 can be connected as an SMBus alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP75-Q1 or TMP175-Q1 is active, the devices acknowledge the SMBus Alert command and respond by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below TLOW caused the ALERT condition. This bit is high if the temperature is greater than or equal to THIGH. This bit is low if the temperature is less than TLOW; see Figure 10 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command determines which device clears its ALERT status. If the TMP75-Q1 or TMP175-Q1 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP75-Q1 or TMP175-Q1 loses the arbitration, its ALERT pin remains active.
7.3.2.6 General Call
The TMP175-Q1 and TMP75-Q1 respond to a two-wire, general-call address (0000000) if the eighth bit is 0. The device acknowledges the general call address and responds to commands in the second byte. If the second byte is 00000100, the TMP175-Q1 and TMP75-Q1 latches the status of their address pins, but do not reset. If the second byte is 00000110, the TMP175-Q1 and TMP75-Q1 latches the status of their address pins and resets their internal registers to their power-up values.
7.3.2.7 High-Speed Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP175-Q1 and TMP75-Q1 devices do not acknowledge this byte, but do switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 2.38 MHz. After the Hs-mode master code is issued, the master transmits a two-wire slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP175-Q1 and TMP75-Q1 switch the input and output filter back to fast-mode operation.
7.3.2.8 Time-out Function
The TMP175-Q1 resets the serial interface if either SCL or SDA is held low for 54 ms (typical) between a START and STOP condition. The TMP175-Q1 releases the bus if it is pulled low and waits for a START condition. To avoid activating the time-out function, a communication speed of at least 1 kHz must be maintained for the SCL operating frequency.
7.3.3 Timing Diagrams
The TMP175-Q1 and TMP75-Q1 devices are two-wire, SMBus, and I2C interface compatible. Figure 6 to Figure 10 describe the various operations on the TMP175-Q1. The following list provides bus definitions. Parameters for Figure 6 are defined in the Timing Requirements table. Bus Idle: Both the SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge bit on the last byte that is transmitted by the slave.
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Product Folder Links: TMP175-Q1 TMP75-Q1
7.3.3.1 Two-Wire Timing Diagrams
Figure 6. Two-Wire Timing Diagram Figure 7. Two-Wire Timing Diagram for the TMP75-Q1 Write Word Format Figure 8. Two-Wire Timing Diagram for the TMP175-Q1 Write Word Format
NOTE: Address pins A0, A1, and A2 = 0. Figure 9. Two-Wire Timing Diagram for Read Word Format NOTE: Address pins A0, A1, and A2 = 0. Figure 10. Timing Diagram for SMBus ALERT
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TMP175-Q1,TMP75-Q1 www.ti.com SBOS759 –NOVEMBER 2015
7.4 Device Functional Modes
7.4.1 Shutdown Mode (SD)
The shutdown mode of the TMP175-Q1 and TMP75-Q1 devices lets the user save maximum power by shutting down all device circuitry other than the serial interface, thus reducing current consumption to typically less than 0.1 μA. Shutdown mode is enabled when the SD bit is 1; the device shuts down when the current conversion is completed. When SD is equal to 0, the device maintains a continuous conversion state.
7.4.2 One-Shot (OS)
The TMP175-Q1 and TMP75-Q1 feature a one-shot temperature measurement mode. When the device is in shutdown mode, writing 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the completion of the single conversion. This feature is useful to reduce power consumption in the TMP175-Q1 and TMP75-Q1 when continuous temperature monitoring is not required. When the configuration register is read, OS always reads zero.
7.4.3 Thermostat Mode (TM)
The thermostat mode bit of the TMP175-Q1 and TMP75-Q1 indicates to the device whether to operate in comparator mode (TM = 0) or interrupt mode (TM = 1). For more information on comparator and interrupt modes, see the High- and Low-Limit Registers section.
7.4.3.1 Comparator Mode (TM = 0)
In comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in the T(HIGH) register and remains active until the temperature falls below the value in the T(LOW) register. For more information on the comparator mode, see the High- and Low-Limit Registers section.
7.4.3.2 Interrupt Mode (TM = 1)
In interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds T(HIGH) or goes below the T(LOW) registers. The ALERT pin is cleared when the host controller reads the Temperature register. For more information on the interrupt mode, see the High- and Low-Limit Registers section. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: TMP175-Q1 TMP75-Q1
7.5 Programming
7.5.1 Pointer Register
power-up reset value of P1/P0 is 00. Figure 11. Internal Register Structure of the TMP175-Q1 and TMP75-Q1 Table 4. Pointer Register Byte (pointer = N/A) [reset = 00h] Table 5. Pointer Addresses of the TMP175-Q1 and TMP75-Q1
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7.5.2 Temperature Register
the most recent conversion. Two bytes must be read to obtain data and are described in Table 6 and Table 7. the first conversion is complete. Table 6. Byte 1 of the Temperature Register Table 7. Byte 2 of the Temperature Register
7.5.3 Configuration Register
register for the TMP175-Q1 and TMP75-Q1 is shown in Table 8, followed by a breakdown of the register bits. The power-up or reset value of the Configuration register are all bits equal to 0. Table 8. Configuration Register Format
1 OS R1 R0 F1 F0 POL TM SD
7.5.3.1 Polarity (POL)
Figure 12. Output Transfer Function Diagrams
7.5.3.2 Fault Queue (F1/F0)
TLOW register format and byte order, see the High- and Low-Limit Registers section. Table 9. Fault Settings of the TMP175-Q1 and TMP75-Q1
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7.5.3.3 Converter Resolution (R1/R0)
identifies the resolution bits and the relationship between resolution and conversion time. Table 10. Resolution of the TMP175-Q1 and TMP75-Q1
7.5.4 High- and Low-Limit Registers
device, returning the device to comparator mode (TM = 0).
The format of the data for THIGH and TLOW is the same as for the Temperature register. Table 11. Byte 1 of the THIGH Register Table 12. Byte 2 of the THIGH Register Table 13. Byte 1 of the TLOW Register
1 L11 L10 L9 L8 L7 L6 L5 L4
Table 14. Byte 2 of the TLOW Register configured for 9-bit resolution.
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
although a 0.1-μF bypass capacitor is recommended. provide the primary thermal path.
8.2 Typical Application
Figure 13. Typical Connections of the TMP175-Q1 and TMP75-Q1
8.2.1 Design Requirements
eight different addresses on the bus, connect A0, A1, and A2 to either the GND or V+ pin.
8.2.2 Detailed Design Procedure
adhesive is helpful in achieving accurate surface temperature measurement.
8.2.3 Application Curve
Figure 14. Temperature Step Response
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9 Power Supply Recommendations
high-impedance power supplies can require additional decoupling capacitors to reject power-supply noise.
10 Layout
10.1 Layout Guidelines
10.2 Layout Example
Figure 15. Layout Example
11 Device and Documentation Support
11.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 15. Related Links
11.2 Community Resources
solve problems with fellow engineers. contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments. SMBus is a trademark of Intel Corporation. All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TMP175AQDGKRQ1 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 175Q TMP175AQDGKRQ1.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 175Q TMP175AQDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T175Q1 TMP175AQDRQ1.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T175Q1 TMP75AQDGKRQ1 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 75Q1 TMP75AQDGKRQ1.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 75Q1 TMP75AQDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T75Q1 TMP75AQDRQ1.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T75Q1 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMP175-Q1, TMP75-Q1 :
- Catalog : TMP175 , TMP75 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product Addendum-Page 2
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM
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