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ADVANCE□INFORMATION Temperature (qC) Resistance (k:) -40 -20 0 20 40 60 80 100 120 140 64_F RBias VBias VTempRTMP64 VTempRTMP64 IBias Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TMP64-Q1 SNIS220 –MARCH 2020 TMP64-Q1±1%47-kΩLinearThermistorWith0402Package

1 Features

1• AEC-Q100 qualified with the following results: – Temperature Grade 1: –40 °C ≤ TA ≤ 125 °C – HBM ESD classification level H2 – CDM ESD classification level C6

Silicon-based thermistor with a positive temperature coefficient (PTC)
Linear resistance change across temperature
47-kΩ nominal resistance at 25 °C (R25) – ±1% maximum (0 °C to 70 °C)
Consistent sensitivity across temperature – 6400 ppm/°C TCR (25 °C) – 0.2% typical TCR tolerance across temperature range
Fast thermal response time of 0.6 s (DEC)
Long lifetime and robust performance – Built-in fail-safe in case of short-circuit failures – 0.5% typical long term sensor drift

2 Applications

Thermal compensation – Display backlight – Battery management systems
Thermal threshold detection – Motor control – On-board chargers & DC-DC converters

3 Description

Get started today with the Thermistor Design Tool, offering complete resistance vs temperature table (R- T table) computation, other helpful methods to derive temperature and example C-code. Linear thermistors offer linearity and consistent sensitivity across temperature to enable simple and accurate methods for temperature conversion. Low power consumption and a small thermal mass minimize the impact of self-heating. With built-in failsafe behavior at high temperatures and powerful immunity to environmental variation, these devices are designed for a long lifetime of high performance. The small size of the TMP6 series also allows for close placement to heat sources and quick response times. Take advantage of benefits over NTC thermistors such as no extra linearization circuitry, minimized calibration, less resistance tolerance variation, larger sensitivity at high temperatures, and simplified conversion methods to save time and memory in the processor. The TMP64-Q1 is currently available in a 0402 footprint-compatible X1SON package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMP64-Q1 X1SON 0.60 mm × 1.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Implementation Circuits Typical Resistances vs Ambient Temperature

11.1 Receiving Notification of Documentation Updates 16

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES March 2020 * Initial release.

5 Pin Configuration and Functions

Top View (Angled) Pin Functions PIN TYPE DESCRIPTION NAME NO. – 1 — Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the + terminal is at a higher voltage potential than the – terminal.+ 2

ADVANCE□INFORMATION TMP64-Q1 SNIS220 –MARCH 2020 www.ti.com Product Folder Links: TMP64-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage across pins 2 (+) and 1 (–) +6 V Current through the device +450 µA Junction temperature (TJ) –65 +150 °C Storage temperature (Tstg) –65 +150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

VESD Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM classification level 2 ±2000 V Charged-device model (CDM), per AEC Q100-011 CDM classification level C6 ±1000 V

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VSns Voltage across pins 2 (+) and 1 (–) 0 5.5 V ISns Current passing through the device 0 400 µA TA Operating free-air temperature (specified performance) (X1SON/DEC Package) –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are included in the PCB, per JESD 51-5. (3) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

6.4 Thermal Information

THERMAL METRIC (1) TMP64-Q1 UnitsDEC (X1SON)

2 PINS

RθJA Junction-to-ambient thermal resistance(2)(3) 443.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 195.7 °C/W RθJB Junction-to-board thermal resistance 254.6 °C/W ΨJT Junction-to-top characterization parameter 19.9 °C/W ΨJB Junction-to-board characterization parameter 254.5 °C/W RθJC(bot) Junction-to-case (bot) thermal resistance – °C/W

6.5 Electrical Characteristics

TA = -40 °C - 125 °C, ISns = 42.553 μA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R25 Thermistor Resistance at 25 °C TA = 25 °C 46.53 47 47.47 kΩ RTOL Resistance Tolerance TA = 25 °C –1 1 TCR-35 Temperature Coefficient of Resistance ppm/°CTCR25 T1 = 20 °C, T2 = 30 °C +6400 TCR85 T1 = 80 °C, T2 = 90 °C +5910 TCR-35 % Temperature Coefficient of Resistance Tolerance %TCR25 % T1 = 20 °C, T2 = 30 °C ±0.2 TCR85 % T1 = 80 °C, T2 = 90 °C ±0.3 ΔR Sensor Long Term Drift (Reliability) 96 hours continuous operation at RH = 85% and TA = 130 °C VBias = 5.5 V -1 ±0.1 1 600 hours continuous operation at TA = 150 °C VBias = 5.5V -1 0.5 1.8 tRES (stirred liquid) Thermal response to 63% T1 = 25 °C in Still Air to T2 = 125 °C in Stirred Liquid 0.6 s tRES (still air) Thermal response to 63% T1 = 25 °C to T2 = 70 °C in Still Air 3.2 s

6.6 Typical Characteristics

Figure 1. Resistance vs. Ambient Temperature Using Figure 2. Resistance vs. Ambient Temperature Using Figure 3. TCR as a Function of Sense Current, ISNS Figure 4. TCR as a Function of Sense Voltage, VSNS Figure 5. Supply Dependence Resistance vs. Bias Current Figure 6. Supply Dependence R vs. VBias

7 Detailed Description

7.1 Overview

potential. Connect the negative terminal to the lowest voltage potential. the Design Requirements section. Consult the TMP64-Q1 R-T table section for more information.

ISNS: Current flowing through the TMP64-Q1.
VSNS: Voltage across the two TMP64-Q1 terminals.
IBias: Current supplied by the biasing circuit.
VBias: Voltage supplied by the biasing circuit.
VTemp: Output voltage that corresponds to the measured temperature. Note that this is different from VSns. In the use case of a voltage divider circuit with the TMP64-Q1 in the high side, VTemp is taken across RBias.

7.2 Functional Block Diagram

Figure 10. Typical Implementation Circuits

7.3 TMP64-Q1 R-T table

The TMP64-Q1 R-T table must be re-calculated for any change in the bias voltage, bias resistor, or bias current. TI provides a Thermistor Design Tool to calculate the R-T table. The system designer should always validate the calculations provided.

7.4 Feature Description

7.4.1 Linear resistance curve

The TMP64-Q1 has good linear behavior across the whole temperature range as shown in Figure 1. This range allows a simpler resistance-to-temperature conversion method that reduces look-up table memory requirements. The linearization circuitry or midpoint calibration associated with traditional NTCs is not necessary with the device. The linear resistance across the entire temperature range allows the device to maintain sensitivity at higher operating temperatures.

7.4.2 Positive Temperature Coefficient (PTC)

The TMP64-Q1 has a positive temperature coefficient. As temperature increases the device resistance increases leading to a reduction in power consumption of the bias circuit. In comparison, a negative coefficient system increases power consumption with temperature as the resistance decreases. The TMP64-Q1 benefits from the reduced power consumption of the bias circuit with less self-heating than a typical NTC system.

7.5 Device Functional Modes

The device has one mode of operation that applies when operated within the Recommended Operating Conditions.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.2 Typical Application

8.2.1 Thermistor Biasing Circuits

Figure 11. Biasing Circuit Implementations With Linear Thermistor (Left) vs. Non-Linear Thermistor

8.2.1.1 Design Requirements

divider circuit can be used to generate the temperature voltage. input for an active feedback control circuit. filter to reject system level noise, and the user should place the filter as close to the ADC input as possible.

8.2.1.2 Detailed Design Procedure

range, and ADC resolution is given in Equation 3. Figure 12. TMP64-Q1 Voltage Divider With an ADC

FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF)
n is the resolution of the ADC (3) Equation 4 shows whenever VREF = VBIAS, VBIAS cancels out. (4)

8.2.1.2.1 Thermal Protection With Comparator

The engineer can use the TMP64-Q1, a voltage reference, and a comparator to program the thermal protection. comparator with built-in hysteresis or feedback resistors may be used. Figure 15. Temperature Switch Using TMP64-Q1 Voltage Divider and a Comparator

8.2.1.2.2 Thermal Foldback

One application that uses the output voltage of the TMP64-Q1 in an active control circuit is thermal foldback. divider with RTMP64-Q1 and the input to the op amp to prevent loading and variations in VTEMP.

9 Power Supply Recommendations

through the device is 400 µA (ISns).

10 Layout

10.1 Layout Guidelines

10.2 Layout Example

Figure 18. Recommended Layout: DEC Package

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 6-May-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTMP6431QDECTQ1 ACTIVE X1SON DEC 2 250 TBD Call TI Call TI -40 to 125 TMP6431QDECRQ1 PREVIEW X1SON DEC 2 10000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 HJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 6-May-2020 Addendum-Page 2 OTHER QUALIFIED VERSIONS OF TMP64-Q1 :

Catalog: TMP64 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

www.ti.com PACKAGE OUTLINE C 0.50 0.41 0.05 0.00 0.65

0.1 C A B

2X 0.55 0.45 2X 0.3 0.2 A 1.05 0.95 B 0.65 0.55 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.03 C 1 2 X0.125)(45 PIN 1 ID NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M 2. This drawing is subject to change without notice. SCALE 11.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND0.07 MAX ALL AROUND (R0.05) TYP (0.65) 2X (0.5) 2X (0.25) 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:60X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP (0.7) 2X (0.5) 2X (0.3) (0.05) 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:60X SYMM 1 2 SYMM PCB PAD METAL UNDER SOLDER PASTE

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Product Information

TMP6431QDECRQ1 specifications and overview.

Summary

TMP64-Q1 짹1% 47-k廓 Linear Thermistor With 0402 Package

Description

TMP64-Q1 짹1% 47-k廓 Linear Thermistor With 0402 Package

Source title TMP6431QDECRQ1 Datasheet(PDF) - Texas Instruments

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