TMP6131DECR

TMP61 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 29

Technical content

VTemp = VBias X RTMP61 RBias + RTMP61 VTemp = IBias X RTMP61 VBias RBias RTMP61 VTEMP IBias VTEMP RTMP61 Temperature (qC) Resistance (k:) -40 -20 0 20 40 60 80 100 120 140 160 d001 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. TMP61 SBOS921 –DECEMBER 2018 TMP61Silicon-BasedLinearThermistorforTemperatureSensing

1 Features

1• Silicon-Based Thermistor With a Positive Temperature Coefficient (PTC)

• Linear Resistance Change With Temperature – Simplifies Resistance-to-Temperature Conversion – Decrease Accuracy Spread Compared to Non- Linear Negative Temperature Coefficient (NTC) Thermistor-Based Circuits Across a Wide Temperature Range
• 10-kΩ Nominal Resistance at 25°C (R25) – ±1% Maximum (0°C to 70°C)
• Consistent Sensitivity Across Temperature – 6400 ppm/°C TCR (25°C) – 0.2% Typical TCR Tolerance Across Temperature (-40°C to 125°C)
• Wide Operating Temperature: – –65 to +150°C
• Fast Thermal Response Time: – 0.6s (DEC package)
• Long Lifetime and Robust Performance – Ultra low power consumption compared to traditional NTCs that lower errors due to self heating – Built-in fail-safe in case of short circuit failures – <1% Maximum Drift after high temperature and high humidity stress tests
• Available Package Options: – X1SON (DEC/0402 Footprint) – TO-92S (LPG) (Contact Representative for Availability)

2 Applications

• Temperature Measurement And Monitoring
• Thermal Compensation
• Thermal Protection (With Comparator)

3 Description

The TMP61xx series of Silicon Linear Thermistors has a linear positive temperature coefficient (PTC) that results in a uniform, consistent temperature coefficient resistance (TCR) across a wide operating temperature range. These devices are designed for temperature measurement, protection, compensation, and control systems. Compared to traditional NTC thermistors, the TMP61xx series of devices offers enhanced linearity and consistent sensitivity across the full temperature range. They also have robust performance due to their immunity to environmental variation and their built-in fail-safe behavior at high temperatures. These devices are currently available in a 2-pin, surface-mount, 0402 footprint-compatible X1SON package and a 2-pin, through-hole, mini- sized transistor-outline TO-92S package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMP61 X1SON 0.60 mm × 1.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) This package is in preview SPACER Typical Implementation Circuits Typical Resistances vs Ambient Temperature

SBOS921 –DECEMBER 2018 www.ti.com Product Folder Links: TMP61 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents

12.1 Receiving Notification of Documentation Updates 19

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES December 2018 * Initial release.

www.ti.com SBOS921 –DECEMBER 2018 Product Folder Links: TMP61 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

5 Device Comparison Table

PART NUMBER RATING R25 TYP R25 %TOL PACKAGE TA TMP61DEC Catalog 10k 1% X1SON / DEC (0402) –65°C to 150°C TMP61LPG TO92s / LPG –65°C to 150°C

6 Pin Configuration and Functions

Top View (Angled) 2-Pin TO-92S Top View (Angled) (1) The package is in preview Pin Functions PIN TYPE DESCRIPTION NAME X1SON (DEC) TO-92S (LPG) – 1 1 — Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the + terminal is at a higher voltage potential than the – terminal.+ 2 2

SBOS921 –DECEMBER 2018 www.ti.com Product Folder Links: TMP61 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage across the device +6 V Current through the device +450 µA Junction temperature (TJ) –65 +150 °C Storage temperature (Tstg) –65 +150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM) per JESD22-A114 (1) ±1500 VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VSns Voltage Across Pins 2 (+) and 1 (–) 0 5.5 V ISns Current passing through the device 0 400 µA TA Operating free-air temperature (specified performance) (X1SON/DEC Package) –40 125 °C TA Operating free-air temperature (functional, unspecified performance) (X1SON/DEC Package) –65 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) For information on self-heating and thermal response time see Layout Guidelines section. (3) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are included in the PCB, per JESD 51-5. (4) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

7.4 Thermal Information

THERMAL METRIC (1) (2) TMP6131 UnitsDEC (X1SON)

2 PINS

RθJA Junction-to-ambient thermal resistance(3) (4) 443.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 195.7 °C/W RθJB Junction-to-board thermal resistance 254.6 °C/W ΨJT Junction-to-top characterization parameter 19.9 °C/W ΨJB Junction-to-board characterization parameter 254.5 °C/W

www.ti.com SBOS921 –DECEMBER 2018 Product Folder Links: TMP61 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

7.5 Electrical Characteristics

TA = -40°C - 125°C, ISns = 200 μA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R25 Thermistor Resistance at 25°C TA = 25°C 9.9 10 10.1 kΩ RTOL Resistance Tolerance TA = 25°C –1 +1 TCR-35 Temperature Coefficient of Resistance ppm/°CTCR25 T1 = 20°C, T2 = 30°C +6400 TCR85 T1 = 80°C, T2 = 90°C +5910 TCR-35 % Temperature Coefficient of Resistance Tolerance TCR85 % T1 = 80°C, T2 = 90°C ±0.3 ΔR Sensor Long Term Drift (Reliability) 96 hours continuous operation,RH=85%, TA 600 hours continuous operation, TA = 150°C, VBias = 5.5V 0.1 +1 tRES (stirred liquid) Thermal response to 63% T1=25°C in Still Air to T2=125°C in Stirred Liquid 0.6 s tRES (still air) Thermal response to 63% T1=25°C to T2=70°C in Still Air 3.2 s

7.6 Typical Characteristics

Figure 1. Resistance vs. Ambient Temperature Using Figure 2. Resistance vs. Ambient Temperature Using Figure 3. TCR as a Function of Sense Currents ISns Figure 4. TCR as a Function of Sense Voltages, VSns Figure 5. Supply Dependence R vs. IBias Figure 6. Supply Dependence R vs. VBias

8 Detailed Description

8.1 Overview

range. They are suitable for use for temperature measurement, protection, compensation, and control systems. sized transistor-outline TO-92S packages.

8.2 Functional Block Diagram

Figure 10. Typical Implementation Circuits

8.3 Feature Description

range, but a small non-linearity can observed as well as supply dependence as shown in Figure 3 and Figure 4. region area. Also, the TMP61xx has an active area and a substrate due to the polarized terminals of the device.

• T is the temperature of interest (1) TCR (ppm/°C) = (RT2 – RT1) / ((T2 – T1) × R(T2+T1)/2) (2) Below are the definitions of the key terms used throughout this document:
• ISns: Current flowing through TMP61
• VSns: Voltage across the two terminals of TMP61
• IBias: Current supplied by the biasing circuit
• VBias: Voltage supplied by the biasing circuit
• VTemp: Output voltage corresponding to the measured temperature. Note that this is different than VSns in case of a voltage divider circuit with TMP61 in the high side and VTemp is taken across RBias.

Table 1. TMP61 Transfer Table Using an Ideal IBias of 200 µA Table 2. TMP61 Transfer Table Using a Voltage Divider With an Ideal VBias of 2.5 V and RBias of 10 kΩ

Table 2. TMP61 Transfer Table Using a Voltage Divider With an Ideal VBias of 2.5 V and RBias of 10 kΩ With

8.4 Device Functional Modes

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application

9.2.1 Thermistor Biasing Circuits

Figure 11. Biasing Circuit Implementations With Linear Thermistor (Left) vs. Non-Linear Thermistor

9.2.1.1 Design Requirements

resistor can be biased directly using a precision current source (yielding the highest accuracy and voltage gain).

active feedback control circuit.

9.2.1.2 Detailed Design Procedure

range, and ADC resolution is given in Equation 4. Figure 12. TMP61 Voltage Divider with an ADC.

• FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF)
• n is the resolution of the ADC (4) Equation 5 shows whenever VREF = VBIAS, VBIAS will cancel out. (5)

Figure 15. TMP61 vs. NTC With Linearization Resistor (RP) Voltage Divider Circuits Figure 16. NTC With and Without a Linearization Resistor vs. TMP61 Temperature Voltages

9.2.1.2.1 Thermal Compensation

• R(T0) is the resistance
• the temperature coefficient, α, is specified (25°C)
• the change in temperature, ΔT, is the temperature of interest, T, minus T0 (25°C) (6) This circuit is shown in Figure 17.

Figure 17. TMP61 Thermal Compensation Circuit

9.2.1.2.2 Thermal Protection With Comparator

feedback resistors may be used. Figure 18. Temperature Switch Using TMP61 Voltage Divider and a Comparator

9.2.1.2.3 Thermal Foldback

and the input to the op amp to prevent loading and variations in VTEMP. Figure 19. Thermal Foldback Using TMP61 Voltage Divider and a Rail-to-Rail Op Amp dependent on the feedback network, RFB and R1, which varies the gain of the op amp, G, given by Equation 9.

Figure 20. Thermal Foldback Voltage Output Curve

9.2.1.3 Application Curve

The TMP61 accuracy varies depending on the selected biasing circuit. This variation can be seen in Figure 21. sources used are assumed to be ideal. The best accuracy is achieved using a direct current bias method. Figure 21. TMP61 Voltage Output and Temperature Error Based on the Bias Method

10 Power Supply Recommendations

the device is 400 µA (ISns).

11 Layout

11.1 Layout Guidelines

layout is as shown in Figure 22.

11.2 Layout Examples

Figure 22. Recommended Layout: DEC Package

www.ti.com SBOS921 –DECEMBER 2018 Product Folder Links: TMP61 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 13-Dec-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMP6131DECR ACTIVE X1SON DEC 2 10000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -65 to 150 EL TMP6131DECT ACTIVE X1SON DEC 2 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -65 to 150 EL TMP6131LPG PREVIEW TO-92 LPG 2 1000 TBD Call TI Call TI -65 to 150 TMP6131LPGM PREVIEW TO-92 LPG 2 3000 TBD Call TI Call TI -65 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 13-Dec-2018 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Dec-2018 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP6131DECR X1SON DEC 2 10000 205.0 200.0 33.0 TMP6131DECT X1SON DEC 2 250 205.0 200.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Dec-2018 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.50 0.41 0.05 0.00 0.65

0.1 C A B

2X 0.55 0.45 2X 0.3 0.2 A 1.05 0.95 B 0.65 0.55 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.03 C 1 2 X0.125)(45 PIN 1 ID NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M 2. This drawing is subject to change without notice. SCALE 11.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND0.07 MAX ALL AROUND (R0.05) TYP (0.65) 2X (0.5) 2X (0.25) 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:60X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP (0.7) 2X (0.5) 2X (0.3) (0.05) 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:60X SYMM 1 2 SYMM PCB PAD METAL UNDER SOLDER PASTE

www.ti.com PACKAGE OUTLINE 4.1 3.9 15.5 15.1 3X 0.48 0.33 2X 1.27 0.05 3.25 3.05 3X 0.51 0.33 3X 0.51 0.40 2X ( )45° 0.86 0.66 1.62 1.42 2.64 2.44 2.68 2.28 5.05 MAX 6X 0.076 MAX 2.3 2.0

2 MAX

(0.55) 4221971/A 03/2015 TO-92 - 5.05 mm max heightLPG0002A TO-92 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 2 1 2 SCALE 1.300

www.ti.com EXAMPLE BOARD LAYOUT TYP ALL AROUND 0.05 MAX (1.07) (1.7) (1.27) (2.54) (1.7) 3X ( ) VIA0.75 4221971/A 03/2015 TO-92 - 5.05 mm max heightLPG0002A TO-92 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE:20X METAL TYP TYP OPENING SOLDER MASK 1 2

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated