TMP411ADR.A

TMP411_V01 TI | Alldatasheet

Document overview

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Technical content

TMP411 ±1°C and TMP411D ±0.8°C Remote and Local Temperature Sensor With N-Factor and Series Resistance Correction

1 Features

• TMP411: – ±1°C Local channel accuracy – ±1°C Remote channel accuracy – Supply range: 2.7V to 5.5V – Available in VSSOP and SOIC 8-pin packages
• TMP411D: – ±0.8°C Local channel accuracy – ±0.8°C Remote channel accuracy – Supply range: 1.62V to 5.5V – Available in SOT-23 8-pin package
• Wide operating range: –40°C to 125°C
• Support I2C and SMBus interface
• Programmable Resolution: 9 to 12 Bits
• Programmable Non-Ideality Factor
• Series Resistance Cancellation
• Offset Registers for System Calibration
• Programmable Threshold Limits
• Diode Fault Detection
• Alert Function – ALERT and THERM2 Pin Configuration
• Multiple Interface Addresses
• Pin and Registers Compatible With ADT7461 and ADM1032

2 Applications

• Enterprise systems – Rack server motherboard – Smart network interface card (NIC)
• Standard notebook PC
• Wireless infrastructure – Small cell base station – Baseband unit (BBU)
• Software defined radio
• Processor and FPGA Temperature Monitoring

3 Description

The TMP411 and TMP411D devices are remote temperature sensors with a built-in local temperature sensor. The remote temperature sensor, diode- connected transistors are typically low-cost, NPN- or PNP-type transistors or diodes that are an integral part of microcontrollers, microprocessors, or FPGAs. Remote temperature accuracy is ±1°C (TMP411) or ±0.8°C (TMP411D) for multiple device manufacturers, with no calibration needed. The two-wire serial interface accepts SMBus write byte, read byte, send byte and receive byte commands to program the alarm thresholds and to read temperature data. Features that are included in the TMP411 and TMP411D devices are: series resistance cancellation, programmable non-ideality factor, programmable resolution, programmable threshold limits, user- defined offset register for maximum accuracy, minimum and maximum temperature monitors, wide remote temperature measurement range (up to 150°C), diode fault detection, and temperature alert function. The TMP411 device is available in VSSOP-8 and SOIC-8 packages and TMP411D is available in SOT23-8 package.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TMP411 VSSOP (8) 3.0mm × 4.9mm SOIC (8) 4.9mm × 6.0mm TMP411D SOT23 (8) 2.9mm × 2.8mm (1) For more information, see Section 12. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TMP411 TMP411D SCL SDA GND Processor or ASIC SMBus Controller 4 5 2.7V to 5.5V 2.7V to 5.5V Fixed VIH/VIL Built-In Thermal Transistor, Diode Overtemperature Shutdown THERM THERM2ALERT / Simplified Block Diagram TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10.2 Receiving Notification of Documentation Updates..46

12 Mechanical, Packaging, and Orderable

TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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4 Device Comparison

Table 4-1. Device Comparison Feature TMP411 TMP411D (2) , (4) TMP421 TMP451 (1) , (4) TMP461 (2) , (4) TMP4718 (2) , (5) Local Temperature Accuracy (°C) Remote Temperature Accuracy (°C) Digital Input/Output Resolution (Bit) (Local & Remote) L = 9 to 12 R = 12 L = 9 to 12 R = 12 L = 12 R = 12 L = 12 R = 12 L = 12 R = 12 L = 8 R = 11 70%/30% VDD Current Consumption and Conversion Time (Typ: VDD=3.3V and 25°C) TConv (ms) (per channel) 115÷2 17.7 115 31÷2 15 17.7 IAVG at 0.0625Hz (μA) 28 1.5 32 27 16 1.5 ISB (μA) 7.5 1 - - 15 1 ISD (μA) 3 0.6 3 3 3 0.5 Features: RSeriesCancellation, N-Factor Correction, Diode Fault Detection, Digital Filter I2C Addresses 4 orderables 4 orderables 4 (A1/A0 pins) 2 orderables 9 (A1/A0 pins) 2 orderables Packaging Dimension Dimensions [mm × mm × mm] VSSOP (8-pin) 3 × 4.9 × 1.1 SOIC (8-pin) 4.9 × 6 × 1.75 SOT-23 (8-pin) 2.9 × 2.8 × 1.1 SOT-23 (8-pin) 2.9 × 2.8 × 1.1 DSBGA (8-pin) 2.2 × 1 × 0.625 WSON (8-pin) 2 × 2 × 0.8 WQFN (10-pin) 2 × 2 × 0.8 VSSOP (8-pin) 3 × 4.9 × 1.1 1. Temperature accuracy is specified over VDD= 3.3V. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TMP411 TMP411D

1. Temperature accuracy is specified over whole power supply. 3. Remote temperature accuracy is specified over TDIODE = -40°C to 150°C. 4. Remote temperature accuracy is specified over TDIODE = -55°C to 150°C. 5. Remote temperature accuracy is specified over TDIODE = -55°C to 125°C. TMP 411D x Q yyy R Q1 Device Name (TMP411 or TMP411D) I2C Address (A, B, C, D or E) Optional: Only Automotive Qualified T&R Packing size Optional: Only Grade-1 Automotive Qualified Sensor Family Figure 4-1. TMP411/TMP411D Device Nomenclature Table 4-2. TMP411/TMP411D Device Nomenclature Description Field Description Field Detail Sensor Family TMP: Temperature Sensors Device Name 411 or 411D I2C Address

• TMP411A/ TMP411DA - 4Ch/ 1001100'b
• TMP411B/ TMP411DB - 4Dh/ 1001101'b
• TMP411C/ TMP411DC - 4Eh/ 1001110'b
• TMP411E/ TMP411DE - 4Ch/ 1001100'b - Offset register Automotive qualified Optional: applies to only automotive qualified devices TMP411:
• D, SOIC package, 1.75mm (max) height
• DGK, VSSOP package, 1.1mm (max) height TMP411D:
• DDF, SOT23 package, 1.1mm (max) height T&R Packing Size Large T&R, SPQ (TMP411) = 2,500 units & SPQ (TMP411D) = 3,000 units Automotive grade-1 qualified Optional: AEC-Q100 Qualified for automotive applications Table 4-3. TMP411/TMP411D Device Nomenclature Detail PRODUCT OUT TMP411x yyyR x indicates that the device has A, B, C or E variant. These devices can ship with the legacy chip (CSO: WFM or DM5) or the new chip (CSO: RFB). The reel packaging label provides date code information to distinguish which chip is being used. Device performance for new and legacy chips is denoted throughout the document. yyy indicates that the package type of the device which can be D (SOIC 8-pin) or DGK (VSSOP 8-pin). TMP411Dx yyyR x indicates that the device has A, B, C or E variant. TMP411D has only CSO: RFB. yyy indicates that the package type of the device which is DDF (SOT23 8-pin). TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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5 Pin Configuration and Functions

3D– 6 ALERT/THERM2 4THERM 5 GND Not to scale Figure 5-1. DGK, D and DDF Packages 8-Pin VSSOP, SOIC and SOT23 Top View Table 5-1. Pin Functions PIN Type DESCRIPTION NAME NO. V+ 1 Power supply Positive supply (2.7V to 5.5V for TMP411) and (1.62V to 5.5V for TMP411D) D+ 2 Analog input Positive connection to remote temperature sensor D– 3 Analog input Negative connection to remote temperature sensor THERM 4 Digital output Thermal flag, active low, open-drain; requires pullup resistor to V+ GND 5 Ground Ground ALERT/THERM2 6 Digital output Alert (reconfigurable as second thermal flag), active low, open-drain; requires pullup resistor to V+ SDA 7 Bidirectional digital input-output Serial data line for SMBus, open-drain; requires pull-up resistor to V+ SCL 8 Digital input Serial clock line for SMBus, open-drain; requires pullup resistor to V+ www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TMP411 TMP411D

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage Pins 2, 3, 4 only TMP411 (Legacy chip) –0.5 (V+) + 0.5 V Pins 6, 7, 8 only –0.5 7 Pins 2, 3 only TMP411 (New chip) TMP411D –0.5 2 V Pins 4, 6, 7, 8 only –0.5 6 Input current 10 mA Power supply, V+ TMP411 (Legacy chip) 7 VTMP411 (New chip) TMP411D 6 Operating temperature range –55 127 °C Junction temperature, TJ(max) 150 °C Storage temperature, Tstg –60 130 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage, TMP411 2.7 3.3 5.5 V Supply voltage, TMP411D 1.62 3.3 5.5 TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TMP411/TMP411D UNITD (SOIC) Legacy chip D (SOIC) New chip DGK (VSSOP) Legacy chip DGK (VSSOP) New chip DDF (SOT-23)

8 PINS 8 PINS 8 PINS 8 PINS 8 PINS

Rθ JC(top) TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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THERMAL METRIC(1) TMP411/TMP411D UNITD (SOIC) Legacy chip D (SOIC) New chip DGK (VSSOP) Legacy chip DGK (VSSOP) New chip DDF (SOT-23) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics (TMP411)

At TA = -40°C to +125°C and V+ = 2.7V to 5.5V, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE ERROR TERROR(L OCAL) Local temperature sensor TA = 15°C to 85°C TERROR(R EMOTE) Remote temperature sensor(1) TA = 15°C to 75°C TDIODE = -40°C to 150°C V+ = 3.3V –1 ±0.0625 1 TA = -40°C to 100°C TDIODE = -40°C to 150°C V+ = 3.3V –3 ±1 3 TA = -40°C to 125°C TDIODE = -40°C to 150°C V+ = 3.3V –5 ±3 5 TERROR_P S Temperature error power supply sensitivity (local and remote) V+ = 2.7V to 5.5V TDIODE = -40°C to 150°C –0.5 ±0.2 0.5 °C/V TEMPERATURE MEASUREMENT tCONV Conversion time One-Shot mode Legacy chip 105 115 125 ms New chip 30 35 40 TRES Resolution Local temperature sensor (programmable) 9 12 Bits Remote temperature sensor 12 RSERIES Remote sensor source current High Series resistance: 3kΩ maximum 120 µA Medium high 60 Medium low Legacy chip only 12 Low 6 η Remote transistor ideality factor Optimized ideality factor 1.008 SMBus INTERFACE VIH Logic input high voltage (SCL, SDA) 2.1 V VIL Logic input low voltage (SCL, SDA) 0.8 V VHYST Hysteresis 170 mV SMBus output low sink current 6 mA ILI and ILO Logic input current Legacy chip -1 1 µA New chip -0.2 0.2 CIN SMBus input capacitance (SCL, SDA) 3 pF SMBus clock frequency 3.4 MHz www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TMP411 TMP411D

At TA = -40°C to +125°C and V+ = 2.7V to 5.5V, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SMBus timeout 25 30 35 ms SCL falling edge to SDA valid time 1 µs DIGITAL OUTPUTS VOL Output low voltage IOUT = 6mA Legacy chip 0.15 0.4 V New chip 0.3 0.4 IOH High-level output leakage current VOUT = V+ Legacy chip 0.1 1 µA New chip 0.05 0.2 ALERT or THERM2 output low sink current ALERT/THERM2 forced to 0.4V 6 mA THERM output low sink current THERM forced to 0.4V 6 mA POWER SUPPLY V+ Specific voltage range 2.7 5.5 V IDD_AVG Average current consumption 0.0625Hz conversion V+ = 3.3V Legacy chip 28 30 µA New chip 1.5 8.2 8Hz conversion V+ = 3.3V Legacy chip 400 475 New chip 45 85 IDD_SD Shutdown current Serial bus inactive Legacy chip 3 10 µA New chip 0.6 7 Serial bus active, fs = 400kHz Legacy chip 90 New chip 7 Serial bus active, fs = 3.4MHz Legacy chip 350 New chip 55 Undervoltage lockout Legacy chip 2.3 2.4 2.6 V This behavior is combined with Power-on-reset (POR). For more information, please see section 7.3.6 and footnote(2) New chip POR Power-on-reset threshold Legacy chip 1.6 2.3 V New chip 1.23 1.4 Brownout detect New chip 1 1.14 V (1) Tested with less than 5Ω effective series resistance and 100pF differential input capacitance. TA is the ambient temperature of the TMP411. TDIODE is the temperature at the remote diode sensor. (2) When there is no remote diode connected, the first remote conversion must be ignored with the power supply ramp rate less than 240V/s. TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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6.6 Electrical Characteristics (TMP411D)

At TA = -40°C to +125°C and V+ = 1.62V to 5.5V, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE ERROR TERROR(LO CAL) Local temperature sensor TA = -40°C to 125°C –1 1 TERROR(RE MOTE) Remote temperature sensor(1) TA = -25°C to 85°C TDIODE = -55°C to 150°C –0.8 ±0.25 0.8 °CTA = -40°C to 105°C TDIODE = -55°C to 150°C –1 1 TA = -40°C to 125°C TDIODE = -55°C to 150°C –1.25 1.25 TERROR_PS Temperature error power supply sensitivity (local and remote) V+ = 1.62V to 5.5V TDIODE = -55°C to 150°C –0.2 ±0.1 0.2 °C/V TEMPERATURE MEASUREMENT TRES Resolution Local temperature sensor (programmable) 9 12 Bits Remote temperature sensor 12 TREPEAT Repeatability Local sensor V+ = 3.3V, 1Hz conversion cycle ±1 LSB RSERIES Remote sensor source current High Series resistance: 3kΩ maximum 120 µAMedium 60 Low 6 tCONV Conversion time Local conversion only one-shot mode 17.7 ms Remote conversion + local conversion 30 35 40 tVAR Timing variation Conversion period -15 ±5 15 % η Remote transistor ideality factor Optimized ideality factor 1.008 SMBus INTERFACE CIN SMBus input capacitance (SCL, SDA) 3 pF VIH Logic input high voltage (SCL, SDA) V+ ≥ 2.7V 2.1 V V+ < 2.7V 0.7×V+ VIL Logic input low voltage (SCL, SDA) V+ ≥ 2.7V 0.8 V V+ < 2.7V 0.3×V+ ILI and ILO Logic input/output current –0.2 0.2 µA VHYST Hysteresis 170 mV SMBus clock frequency V+ ≥ 2.7V 3.4 MHz SMBus timeout 25 30 35 ms SCL falling edge to SDA valid time 1 µs DIGITAL OUTPUTS VOL Output low voltage IOUT = 6mA V+ ≥ 2.7V 0.3 0.4 V IOUT = 3mA V+ < 2.7V 0.17 0.4 IOH High-level output leakage current VOUT = V+ 0.05 0.2 µA POWER SUPPLY www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMP411 TMP411D

At TA = -40°C to +125°C and V+ = 1.62V to 5.5V, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V+ Specific voltage range 1.62 5.5 V IDD_ACTIVE Active conversion current Local sensor 100 150 µA Remote sensor 220 320 IDD_SB Standby current Serial bus inactive 1 7.5 µA IDD_AVG Average current consumption 0.0625Hz conversion V+ = 3.3V 1.5 8.2 µA 8Hz conversion V+ = 3.3V 45 85 IDD_SD Shutdown current Serial bus inactive 0.6 7 µASerial bus active, fs = 400kHz 7 Serial bus active, fs = 3.4MHz 55 POR Power-on-reset threshold 1.23 1.4 V Brownout detect 1 1.14 (1) Tested with less than 5Ω effective series resistance and 100pF differential input capacitance. TA is the ambient temperature of the TMP411D. TDIODE is the temperature at the remote diode sensor. TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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6.7 Timing Characteristics

f(SCL) SCL operating frequency 0.001 0.4 0.001 3.4 MHz t(BUF) Bus free time between STOP and START condition 600 160 ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 100 100 ns t(SUSTA) Repeated START condition setup time 100 100 ns t(SUSTO) STOP condition setup time 100 100 ns t(HDDAT) Data hold time 0(1) 0(2) ns t(SUDAT) Data setup time TMP411 (Legacy chip) 100 10 nsTMP411 (New chip) TMP411D 100 20 t(LOW) SCL clock LOW period 1300 160 ns t(HIGH) SCL clock HIGH period 600 60 ns tF Clock and data fall time 300 160 ns tR Clock and data rise time 300 160 ns SCLK ≤ 100kHz 1000 ns (1) For cases with an SCL fall time of less than 20ns, or an SDA rise or fall time of less than 20ns, the hold time must be greater than 20ns. (2) For cases with an SCL fall time of less than 10ns, or an SDA rise or fall time of less than 10ns, the hold time must be greater than 10ns.

6.8 Two-Wire Timing Diagram

t(BUF) SDA SCL P S S t(HDSTA) t(HDDAT) t(HIGH) t(SUSTA) t(SUDAT) t(LOW) t(HDSTA) t(SUSTO) tR tF P Figure 6-1. Two-Wire Timing Diagram www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TMP411 TMP411D

6.9 Typical Characteristics (TMP411)

At TA = 25°C and V+ = VS = 5V (unless otherwise noted) Local T emperature Error ( °C) Ambient Temperature,TA ( °C) 3.0 2.0 1.0 í1.0 í2.0 í3.0 í50 125í25 0 25 50 75 100 50 Units ShownVS = 3.3V Figure 6-2. Local Temperature Error vs TMP411 Ambient Temperature (Legacy Chip) A m b i e n t T e m p e r a t u r e , T A ( C ) Local Temperature Error ( - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 3 - 2 - 1 V S = 3 . 3 V ( 5 0 U n i t s S h o w n ) Figure 6-3. Local Temperature Error vs TMP411 Ambient Temperature (New Chip) TA í50 í25 1251007550250 Remote Temperature Error (°C) VS = 3.3V TDIODE = +25 °C (temperature at remote diode)

30 Typical Units Shown

= 1.008 Ambient Temperature, (°C) Figure 6-4. Remote Temperature Error vs TMP411 Ambient Temperature (Legacy Chip) A m b i e n t T e m p e r a t u r e , T A ( C ) Remote Temperature Error ( - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 3 - 2 - 1 V S = 3 . 3 V T D I O D E = + 2 5 ° C ( t e m p e r a t u r e a t r e m o t e d i o d e ) 3 0 T y p i c a l U n i t s S h o w n  = 1 . 0 0 8 Figure 6-5. Remote Temperature Error vs TMP411 Ambient Temperature (New Chip) í20 í40 í60 Leakage Resistance (MŸ) 0 5 10 15 20 25 30 Remote Temperature Error ( °C) R íGND R íVS Figure 6-6. Remote Temperature Error vs Leakage Resistance (Legacy Chip) L e a k a g e R e s i s t a n c e ( M  ) Remote Temperature Error ( 0 5 1 0 1 5 2 0 2 5 3 0 - 6 0 - 4 0 - 2 0 2 0 4 0 6 0 N e w c h i p L e g a c y c h i p Figure 6-7. Remote Temperature Error vs Leakage Resistance (Comparison of Legacy Chip and New Chip) TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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6.9 Typical Characteristics (TMP411) (continued)

At TA = 25°C and V+ = VS = 5V (unless otherwise noted) Remote T emperature Error ( °C) R S(Ÿ) 2.0 1.5 1.0 0.5 í0.5 í1.0 í1.5 í2.0 0 3500500 1000 1500 2000 2500 3000 VS = 2.7V VS = 5.5V Figure 6-8. Remote Temperature Error vs Series Resistance (Diode-Connected Transistor, 2N3906 PNP) (Legacy Chip) R S (  ) Remote Temperature Error ( 0 5 0 0 1 , 0 0 0 1 , 5 0 0 2 , 0 0 0 2 , 5 0 0 3 , 0 0 0 3 , 5 0 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 V S = 2 . 7 V a n d 5 . 5 V Figure 6-9. Remote Temperature Error vs Series Resistance (Diode-Connected Transistor, 2N3906 PNP) (New Chip) Remote T emperature Error ( °C) RS(Ÿ) 2.0 1.5 1.0 0.5 í0.5 í1.0 í1.5 í2.0 0 3500500 1000 1500 2000 2500 3000 VS= 2.7V VS= 5.5V Figure 6-10. Remote Temperature Error vs Series Resistance (GND Collector-Connected Transistor, 2N3906 PNP) (Legacy Chip) R S (  ) Remote Temperature Error ( 0 5 0 0 1 , 0 0 0 1 , 5 0 0 2 , 0 0 0 2 , 5 0 0 3 , 0 0 0 3 , 5 0 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 V S = 2 . 7 V a n d 5 . 5 V Figure 6-11. Remote Temperature Error vs Series Resistance (GND Collector-Connected Transistor, 2N3906 PNP) (New Chip) Capacitance (nF) Remote Temperature Error ( °C) Figure 6-12. Remote Temperature Error vs Differential Capacitance (Legacy Chip) C a p a c i t a n c e ( n F ) Remote Temperature Error ( 0 0 . 5 1 1 . 5 2 2 . 5 3 - 3 - 2 - 1 3 Figure 6-13. Remote Temperature Error vs Differential Capacitance (New Chip) www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TMP411 TMP411D

At TA = 25°C and V+ = VS = 5V (unless otherwise noted) í10 í15 í20 í25 Frequency (MHz) 0 5 10 15 Temperature Error ( °C) Local 100mVPP Noise Remote 100mVPP Noise Local 250mVPP Noise Remote 250mVPP Noise Figure 6-14. Temperature Error vs Power-Supply Noise Frequency (Legacy Chip) F r e q u e n c y ( H z ) Temperature Error ( 0 x 1 0 5 x 1 0 1 0 x 1 0 1 5 x 1 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 1 0 1 5 2 0 2 5 1 0 0 m V P P N o i s e ( N e w c h i p ) 2 5 0 m V P P N o i s e ( N e w c h i p ) 1 0 0 m V P P N o i s e ( L e g a c y c h i p ) 2 5 0 m V P P N o i s e ( L e g a c y c h i p ) Figure 6-15. Remote Temperature Error vs Power-Supply Noise Frequency (Comparison of Legacy Chip and New Chip) 500 450 400 350 300 250 200 150 100 Conversion Rate (conversions/sec) 0.0625 0.125 0.25 0.5 1 2 4 8 IQ(µA) VS = 2.7V VS = 5.5V Figure 6-16. Quiescent Current vs Conversion Rate (Legacy Chip) C o n v e r s i o n R a t e ( c o n v e r s i o n s / s e c ) IQ(A) 1 0 2 0 3 0 4 0 5 0 0 . 1 2 5 0 . 2 5 V S = 2 . 7 V V S = 5 . 5 V Figure 6-17. Quiescent Current vs Conversion Rate (New Chip) 500 450 400 350 300 250 200 150 100 SCL CLock Frequency (Hz) 1k 10k 100k 1M 10M IQ (µA) VS = 3.3V VS = 5.5V Figure 6-18. Shutdown Quiescent Current vs SCL Clock Frequency (Legacy Chip) S C L C L o c k F r e q u e n c y ( H z ) IQ(A) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 V S = 3 . 3 V V S = 5 . 5 V Figure 6-19. Shutdown Quiescent Current vs SCL Clock Frequency (New Chip) TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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At TA = 25°C and V+ = VS = 5V (unless otherwise noted) IQ(µA) VS (V) Figure 6-20. Shutdown Quiescent Current vs Supply Voltage (Legacy Chip) V S ( V ) IQ(A) 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 8 Figure 6-21. Shutdown Quiescent Current vs Supply Voltage (New Chip) www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TMP411 TMP411D

6.10 Typical Characteristics (TMP411D)

At TA = 25°C and V+ = 3.3V (unless otherwise noted) A m b i e n t T e m p e r a t u r e T A ( C ) Local Temperature Error ( - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 1 . 2 - 0 . 8 - 0 . 4 0 . 4 0 . 8 1 . 2 T M P 4 1 1 D ( M a x ) T M P 4 1 1 D ( m i n ) V + = 3 . 3 V ( 3 0 U n i t s S h o w n ) Figure 6-22. Local Temperature Error vs TMP411D Ambient Temperature A m b i e n t T e m p e r a t u r e , T A ( C ) Remote Temperature Error ( - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 T M P 4 1 1 D M a x T M P 4 1 1 D m i n V + = 3 . 3 V ( 3 0 U n i t s S h o w n ) &  = 1 . 0 0 8 Figure 6-23. Remote Temperature Error vs TMP411D Ambient Temperature L e a k a g e R e s i s t a n c e ( M  ) Remote Temperature Error ( 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 2 0 D + t o G N D D + t o V + Figure 6-24. Remote Temperature Error vs Leakage Resistance R S (  ) Remote Temperature Error ( 0 5 0 0 1 , 0 0 0 1 , 5 0 0 2 , 0 0 0 2 , 5 0 0 3 , 0 0 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 V + = 1 . 6 2 V V + = 2 . 7 V V + = 5 . 5 V Figure 6-25. Remote Temperature Error vs Series Resistance (Diode-Connected Transistor, 2N3906 PNP) R S (  ) Remote Temperature Error ( 0 5 0 0 1 , 0 0 0 1 , 5 0 0 2 , 0 0 0 2 , 5 0 0 3 , 0 0 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 V + = 1 . 6 2 V t o 5 . 5 V Figure 6-26. Remote Temperature Error vs Series Resistance (GND Collector-Connected Transistor, 2N3906 PNP) D i f f e r e n t i a l C a p a c i t a n c e ( n F ) Remote Temperature Error ( 0 0 . 5 1 1 . 5 2 2 . 5 3 - 3 - 2 - 1 3 Figure 6-27. Remote Temperature Error vs Differential Capacitance TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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6.10 Typical Characteristics (TMP411D) (continued)

At TA = 25°C and V+ = 3.3V (unless otherwise noted) F r e q u e n c y ( H z ) Temperature Error ( 0 x 1 0 5 x 1 0 1 0 x 1 0 1 5 x 1 0 - 1 - 0 . 5 0 . 5 1 0 0 m V P P N o i s e 2 5 0 m V P P N o i s e Figure 6-28. Temperature Error vs Power-Supply Noise Frequency C o n v e r s i o n R a t e ( H z ) Average Current (A) 1 0 2 0 3 0 4 0 5 0 0 . 1 2 5 0 . 2 5 V + = 1 . 6 2 V V + = 2 . 7 V V + = 5 . 5 V Figure 6-29. Average Current vs Conversion Rate S C L C L o c k F r e q u e n c y ( H z ) Shutdown Current (A) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 V + = 1 . 6 2 V V + = 2 . 7 V V + = 5 . 5 V Figure 6-30. Shutdown Current vs SCL Clock Frequency A m b i e n t T e m p e r a t u r e ( C ) Standby Current (A) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 0 . 5 1 . 5 2 . 5 3 . 5 V + = 1 . 6 2 V V + = 2 . 7 V V + = 5 . 5 V Figure 6-31. Standby Current vs Temperature Figure 6-32. Shutdown Current vs Temperature T e m p e r a t u r e ( C ) Active Conversion Current (A) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 L o c a l R e m o t e Figure 6-33. Active Current vs Temperature (Local and Remote) www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TMP411 TMP411D

At TA = 25°C and V+ = 3.3V (unless otherwise noted) A m b i e n t T e m p e r a t u r e ( C ) Conversion Time (ms) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 0 1 5 2 0 2 5 3 0 3 5 4 0 L o c a l L o c a l + R e m o t e Figure 6-34. Conversion Time vs Temperature (Local and Local + Remote) S u p p l y V o l t a g e ( V ) Current (A) 0 . 3 0 . 5 1 0 2 0 3 0 5 0 1 0 0 2 0 0 3 0 03 0 0 S h u t d o w n S t a n d b y A c t i v e ( L o c a l ) A c t i v e ( R e m o t e ) Figure 6-35. Shutdown, Standby, Active (Local) and Active (Remote) Currents vs Supply Voltage (Temperature at 25°C) D a t a D i s t r i b u t i o n ( L S B ) Population 5 0 1 0 0 1 5 0 2 0 0 2 5 0 - 2 - 1 0 1 2 Figure 6-36. Remote Temperature Noise Data Distribution (300 Samples) T i m e ( s ) Temperature ( - 4 - 2 0 2 4 6 8 1 0 1 2 1 4 2 0 3 0 4 0 5 0 6 0 7 0 8 0 L o c a l R e m o t e Figure 6-37. Temperature Response Time (Stirred Liquid, soldered device on 62mil 2-layer FR4 PCB) TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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7 Detailed Description

7.1 Overview

The TMP411/TMP411D is a dual-channel digital temperature sensor that combines a local die-temperature measurement channel in a single VSSOP-8, SOIC-8 or SOT23-8 package. The TMP411/TMP411D is two-wire and SMBus interface-compatible and is specified over a temperature range of –40°C to 125°C. The TMP411/ TMP411D device contains multiple registers for holding configuration information, temperature measurement results, temperature comparator maximum and minimum limits, and status information. User-programmed high and low temperature limits stored in the TMP411/TMP411D triggers an overtemperature alarm ( ALERT) on local and remote temperatures. Additional thermal limits can be programmed into the TMP411/TMP411D and can trigger another flag ( THERM) that initiates a system response to rising temperatures. The TMP411/TMP411D requires only a transistor connected between D+ and D– for proper remote temperature sensing operation. The SCL and SDA interface pins require pullup resistors as part of the communication bus, while ALERT and THERM pins are open-drain outputs that require pullup resistors. ALERT and THERM pins can be shared with other devices for a wired-OR implementation, if desired. TI recommends using a 0.1µF power-supply bypass capacitor for good local bypassing. Figure 7-1 shows a typical configuration for the TMP411/TMP411D. 0.1µF D RS RS CDIFF CDIFF GND SCL SDA ALERT/THERM2 THERM +5V SMBus Controller Fan Controller Series Resistance RS RS (B) (B) (C) (C) (B) (B) 10k (typ) 10k (typ) 10k (typ) 10k (typ) TMP411 TMP411D CDIFF RS RS (C) (B) (B) PNP Diode-connected configuration(A): Transistor-connected configuration(A): NPN Diode-connected configuration(A): A. Diode-connected configuration provides better settling time. Transistor-connected configuration provides better series resistance cancellation. NPN transistors must be diode-connected. PNP transistors can either be transistor or diode-connected. TI recommends this layout for the MMBT3906LP and MMBT3904LP devices. B. Rs (optional) must be < 1.5kΩ in most applications. Selections of Rs depends on specific applications; see the Filtering section. C. CDIFF (optional) must be < 1000pF in most applications. Selection of CDIFF depends on specific application; see the Filtering section and Figure 6-12 (Figure 6-13 for new chip) and Figure 6-27. Figure 7-1. Basic Connections www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TMP411 TMP411D

7.2 Functional Block Diagram

n2×ID n1×ID ALERT / THERM2

7.3 Feature Description

7.3.1 Series Resistance Cancellation

Figure 7-1 shows series resistance in an application circuit that results from printed circuit board (PCB) trace resistance and remote line length. The TMP411/TMP411D automatically cancels the resistance, which prevents a temperature offset. The TMP411/TMP411D device cancels up to 3kΩ of series line resistance that eliminates the need for additional characterization and temperature offset correction. See Figure 6-8 (Figure 6-9 for new chip), Figure 6-10 (Figure 6-11 for new chip), Figure 6-25 and Figure 6-26 for details on the effect of series resistance and power-supply voltage on sensed remote temperature error.

7.3.2 Differential Input Capacitance

The TMP411/TMP411D tolerates differential input capacitance of up to 1000pF with minimal change in temperature error. The effect of capacitance on sensed remote temperature error is shown in Figure 6-12 (Figure 6-13 for new chip) and Figure 6-27.

7.3.3 Temperature Measurement Data

Temperature measurement data is taken over a default range of 0°C to 127°C for local and remote locations. Measurements from –55°C to 150°C can be made locally and remotely by reconfiguring the TMP411/TMP411D device for the extended temperature range. To change the TMP411/TMP411D configuration from the standard to the extended temperature range, switch bit 2 (RANGE) of the Configuration Register from low to high. TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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Temperature data resulting from conversions within the default measurement range are represented in binary form, as listed in the standard binary column of Table 7-1. Note that any temperature below 0°C results in a data value of zero (00h). Likewise, temperatures above 127°C results in a value of 127 (7Fh). The device can be set to measure over an extended temperature range by changing bit 2 of the Configuration Register from low to high. The change in measurement range and data format from standard binary to extended binary occurs at the next temperature conversion. For data captured in the extended temperature range configuration, an offset of 64 (40h) is added to the standard binary value, as listed in the extended binary column in Table 7-1. This configuration allows measurement of temperatures below 0°C. Having binary values in the range of –64°C to 191°C is possible, but most temperature-sensing diodes measure in the range of –55°C to 150°C. The TMP411/ TMP411D device is rated only for ambient local temperatures ranging from –40°C to 125°C. Parameters in the Absolute Maximum Ratings table must be observed. Table 7-1. Temperature Data Format (Local and Remote Temperature High Bytes) TEMP (°C) LOCAL AND REMOTE TEMPERATURE REGISTER HIGH BYTE VALUE (1°C RESOLUTION) STANDARD BINARY EXTENDED BINARY BINARY HEX BINARY HEX –64 0000 0000 00 0000 0000 00 –50 0000 0000 00 0000 1110 0E –25 0000 0000 00 0010 0111 27 0 0000 0000 00 0100 0000 40 1 0000 0001 01 0100 0001 41 5 0000 0101 05 0100 0101 45 10 0000 1010 0A 0100 1010 4A 25 0001 1001 19 0101 1001 59 50 0011 0010 32 0111 0010 72 75 0100 1011 4B 1000 1011 8B 100 0110 0100 64 1010 0100 A4 125 0111 1101 7D 1011 1101 BD 127 0111 1101 7F 1011 1111 BF 150 0111 1111 7F 1101 0110 D6 175 0111 1111 7F 1110 1111 EF 191 0111 1111 7F 1111 1111 FF TMP411/TMP411D temperature sensor does not utilize 2's complement format to read in temperature values. For this reason, the decode does not cast them into a signed type. The way that TMP411/TMP411D device expresses a negative temperature is by enabling a RANGE bit which adds 64°C to the result. When RANGE is enabled, the decode must subtract 64, causing a raw value of 0 to become -64°C output. Table 7-2. 12-Bit Q4 Parameters PARAMETER VALUE Bits 12 Q 4 Resolution 0.0625 Range (+) 127.9375 Range (–) 0 First Byte Integer C Yes 25˚C 0x1900 www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TMP411 TMP411D

Table 7-3. 12-Bit Q4 Bit Values in °C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - 64 32 16 8 4 2 1 0.5 0.25 0.125 0.0625 - - - - - 64 32 16 8 4 2 1 1/2 1/4 1/8 1/16 - - - - - 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 - - - - /* 12-bit format will have 4 bits discarded by right shift q4 is 0.062500 resolution the following bytes represent 24.5C there is no cast into signed type */ uint8_t byte1 = 0x18; uint8_t byte2 = 0x80; float f = ((byte1 << 8 | byte2) >> 4) * 0.0625f; int mC = ((byte1 << 8 | byte2) >> 4) * 1000 >> 4; int C = byte1; Note Whenever changing between standard and extended temperature ranges, be aware that the temperatures stored in the temperature limit registers are NOT automatically reformatted to correspond to the new temperature range format. These temperature limit values must be reprogrammed in the appropriate binary or extended binary format. Local and remote temperature data uses two bytes for data storage. The high byte stores the temperature with a resolution of 1°C. The second or low byte stores the decimal fraction value of the temperature and allows a higher measurement resolution, as listed in Table 7-4. The measurement resolution for the remote channel is 0.0625°C, and is not adjustable. The measurement resolution for the local channel is adjustable, and can be set Table 7-4. Decimal Fraction Temperature Data Format (Local and Remote Temperature Low Bytes) TEMP (°C) REMOTE TEMPERATURE REGISTER LOW BYTE VALUE LOCAL TEMPERATURE REGISTER LOW BYTE VALUE STANDARD AND EXTENDED BINARY HEX STANDARD AND EXTENDED BINARY HEX STANDARD AND EXTENDED BINARY HEX STANDARD AND EXTENDED BINARY HEX STANDARD AND EXTENDED BINARY HEX 0.0000 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0.0625 0001 0000 10 0000 0000 00 0000 0000 00 0000 0000 00 0001 0000 10 0.1250 0010 0000 20 0000 0000 00 0000 0000 00 0010 0000 20 0010 0000 20 0.1875 0011 0000 30 0000 0000 00 0000 0000 00 0010 0000 20 0011 0000 30 0.2500 0100 0000 40 0000 0000 00 0100 0000 40 0100 0000 40 0100 0000 40 0.3125 0101 0000 50 0000 0000 00 0100 0000 40 0100 0000 40 0101 0000 50 0.3750 0110 0000 60 0000 0000 00 0100 0000 40 0110 0000 60 0110 0000 60 0.4375 0111 0000 70 0000 0000 00 0100 0000 40 0110 0000 60 0111 0000 70 0.5000 1000 0000 80 1000 0000 80 1000 0000 80 1000 0000 80 1000 0000 80 0.5625 1001 0000 90 1000 0000 80 1000 0000 80 1000 0000 80 1001 0000 90 0.6250 1010 0000 A0 1000 0000 80 1000 0000 80 1010 0000 A0 1010 0000 A0 0.6875 1011 0000 B0 1000 0000 80 1000 0000 80 1010 0000 A0 1011 0000 B0 0.7500 1100 0000 C0 1000 0000 80 1100 0000 C0 1100 0000 C0 1100 0000 C0 0.8125 1101 0000 D0 1000 0000 80 1100 0000 C0 1100 0000 C0 1101 0000 D0 0.8750 1110 0000 E0 1000 0000 80 1100 0000 C0 1110 0000 E0 1110 0000 E0 0.9375 1111 0000 F0 1000 0000 80 1100 0000 C0 1110 0000 E0 1111 0000 F0 TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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7.3.4 THERM (Pin 4) and ALERT/THERM2 (Pin 6)

The THERM and ALERT/THERM2 pins on the TMP411/TMP411D device are dedicated to alarm functions. The pins are open-drain outputs that each require a pullup resistor to V+. These pins can be wire-ORed together with other alarm pins for system monitoring of multiple sensors. The THERM pin provides a thermal interrupt that cannot be software disabled. The ALERT pin is an earlier warning interrupt, and can be software disabled or masked. The ALERT/THERM2 pin can be configured as a THERM2 pin, which is a second THERM pin (Configuration Register: AL or TH bit = 1). The default setting configures pin 6 to function as an ALERT pin (AL or TH = 0). The THERM pin asserts low when the measured local or remote temperature is outside of the temperature range programmed in the corresponding Local and Remote THERM Limit Register. The THERM temperature limit range can be programmed with a wider range than that of the limit registers, which allows the ALERT pin to provide an earlier warning than the THERM pin. The THERM alarm resets automatically when the measured temperature falls within the THERM temperature limit range minus the hysteresis value stored in the THERM Hysteresis Register. The permitted hysteresis values are listed in Table 8-8. The default hysteresis is 10°C. When the ALERT/THERM2 pin is configured as a second thermal alarm (Configuration Register: bit 7 = 0, bit 5 = 1), the pin functions the same as the THERM pin, but uses the temperatures stored in the Local and Remote Temperature High and Low Limit Registers to set the comparison range. When ALERT/THERM2 (pin 6) is configured as an ALERT pin, (Configuration Register: bit 7 = 0, bit 5 = 0), the pin asserts low when the measured local or remote temperature violates the range limit set by the corresponding Local and Remote Temperature High and Low Limit Registers. The alert function configures to assert only if the range is violated a specified number of consecutive times (either one, two, three or four times). The consecutive violation limit is set in the Consecutive Alert Register. Required consecutive faults prevent false alerts that are caused by environmental noise. The ALERT pin asserts low if the remote temperature sensor is open-circuit. When the MASK function is enabled (Configuration Register: bit 7 = 1), the ALERT pin is disabled (that is, masked). The ALERT pin resets when the controller reads the device address, as long as the condition that caused the alert no longer persists, and the Status Register is reset.

7.3.5 Sensor Fault

The TMP411/TMP411D senses a fault at the D+ input resulting from an incorrect diode connection or an open circuit. The detection circuitry consists of a voltage comparator that trips when the voltage at D+ exceeds (V+) − 0.6V (typical). The comparator output is checked during a conversion. If a fault is detected, the last valid measured temperature is the temperature measurement result, the OPEN bit (Status Register, bit 2) is set high, and the ALERT pin asserts low if the alert function is enabled. The D+ and D − inputs must be connected together to prevent meaningless fault warnings when the TMP411/ TMP411D remote sensor is not in use.

7.3.6 Undervoltage Lockout (TMP411 Only)

Legacy Chip : The TMP411 senses when the power-supply voltage reaches a minimum voltage level for the ADC converter to function as shown in Figure 7-2 . The detection circuitry consists of a voltage comparator that enables the ADC converter after the power supply (V+) exceeds 2.45V (typical). The comparator output is checked during a conversion. The TMP411 does not perform a temperature conversion if the power supply is not valid. The last valid measured temperature is remained as the temperature measurement result. Note that the device can still communicate with the Host when the power supply value is between Power-on-reset (POR) and Undervoltage Lockout voltages. New Chip: This behavior is combined with Power-on-reset (POR) and the user must consider POR instead of Undervoltage lockout. The new chip can both communicate with the Host and do temperature conversion when the power supply value is above POR voltage as shown in Figure 7-3. In addition, when there is no remote diode connected, the first remote conversion must be ignored with the power supply ramp rate less than 240V/s. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TMP411 TMP411D

2.4V t (sec) VS (V) 2.7V To 5.5V t (sec) Vout_ADC (V) Undervoltage lockout TMP411 Supply Voltage range 1.6V POR Figure 7-2. Undervoltage Lockout Behavior (Legacy Chip) 2.45V t (sec) VS (V) 2.7V To 5.5V Vout_ADC (V) Undervoltage lockout TMP411 Supply Voltage range 1.23V POR t (sec) Figure 7-3. Undervoltage Lockout Behavior (New Chip)

7.3.7 Filtering

Remote junction temperature sensors are typically implemented in a noisy environment. Noise is often created by fast digital signals that corrupt measurements. The TMP411/TMP411D has a built-in 65kHz filter on the D+ and D− inputs to minimize the effects of noise. TI recommends placing a bypass capacitor differentially across the sensor inputs to protect the application against unwanted coupled signals. The value of the capacitor must be between 100pF and 1nF. Some applications have better overall accuracy with additional series resistance, however, this increased accuracy is specific to the setup. When series resistance is added, the value must not be greater than 3kΩ. If filtering is needed, TI recommends component values of 100pF and 50 Ω on each input. Exact values are specific to the application.

7.4 Device Functional Modes

7.4.1 Shutdown Mode (SD)

The TMP411/TMP411D shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface, which reduces current consumption to typically less than 3 μA (0.6μA for TMP411 new chip and TMP411D); see Figure 6-20 (Figure 6-21 for new chip). Shutdown mode is enabled when the shutdown bit (SD) of the Configuration Register is configured 1’b. Once programmed, the device enters the shutdown mode immediately and stops any current temperature conversion. If the shutdown mode is entered during local temperature conversion, no update to local/remote temperature result occurs. If the shutdown mode is entered during remote temperature conversion, no update to the remote temperature result occurs, but the local temperature result is updated since the local temperature conversion is already completed. When the shutdown bit (SD) is configured to 0’b, the device remains in continuous conversion state.

7.4.2 One-Shot Conversion

When the TMP411/TMP411D is in shutdown mode (SD = 1 in the Configuration Register), a single conversion on both channels starts by writing any value to the One-Shot Start Register (pointer address 0Fh). This write operation starts one conversion, and the TMP411/TMP411D device returns to shutdown mode when the conversion is complete. The value of the data sent in the write command is irrelevant, and is not stored by the TMP411/TMP411D. When the TMP411/TMP411D is in shutdown mode, an initial 200 μs is required before a one-shot command is given. TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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When a shutdown command is issued, the TMP411/TMP411D device completes the current conversion before shutting down. The wait time only applies to the 200 μs immediately following shutdown. One-shot commands can be issued without delay thereafter.

7.5 Programming

7.5.1 Serial Interface

The TMP411/TMP411D operates only as a target device on either the two-wire bus or the SMBus. Connections to either bus are made through the SDA and SCL open-drain I/O lines. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers that minimize the effects of input spikes and bus noise. The TMP411/TMP411D supports the transmission protocol for fast (1kHz to 400kHz) and high-speed (1kHz to 3.4MHz) modes. All data bytes are transmitted with the MSB first.

7.5.2 Bus Overview

The TMP411/TMP411D is SMBus interface-compatible. In SMBus protocol, the device that initiates the transfer is a controller, and the controller controls devices known as targets. The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated. START is indicated by pulling the data line (SDA) from a high to low logic level while the SCL line is high. All targets on the bus shift are in the target address byte, with the last bit indicating if a read or write operation is needed. During the ninth clock pulse, the target that is addressed responds to the controller by generating an acknowledge bit and pulling the SDA line low. Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data transfer, the SDA line must remain stable while the SCL is high. A change in the SDA while the SCL is high is interpreted as a control signal. Once all data transfers, the controller generates a STOP condition. STOP is indicated by pulling the SDA line from low to high, while the SCL line is high.

7.5.3 Timing Diagrams

The TMP411/TMP411D is two-wire and SMBus-compatible. Figure 7-4 to Figure 7-7 describe the various operations on the TMP411/TMP411D. Bus definitions are given below: Bus Idle: Both SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line, from high to low (while the SCL line is high) defines a START condition. A START condition initiates each data transfer. Stop Data Transfer: A change in the state of the SDA line from low to high (while the SCL line is high) defines a STOP condition. A STOP or repeated START condition terminates each data transfer. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the controller device. The receiver acknowledges the data transfer. Acknowledge: Each receiving device (when addressed) is required to generate an acknowledge bit. A device that acknowledges must pull the SDA line down during the acknowledge clock pulse so the SDA line is stable and low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account. On a controller receive, the controller signals data transfer termination by generating a not-acknowledge bit transmitted by the controller. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TMP411 TMP411D

Frame 1 Two Wire Device Address Byte Frame 2 Pointer Register Byte Frame 4 Data Byte 2 Host Device Device ACK By Device Stop By Host D7 D6 D5 D4 D3 D2 D1 D0 Frame 3 Data Byte 1 ACK By Device D7SDA (Continued) SCL (Continued) D6 D5 D4 D3 D2 D1 D0 SCL … 1 9 1 Start By ACK By ACK By SDA 0 0 1 1 0 0 P6 P7 P5 P4 P3 P2 P1 P0 … (1) W / R A. Target address 1001100 (TMP411A/TMP411DA) shown. Target address changes for TMP411B/TMP411DB and TMP411C/TMP411DC. See Ordering Information table for more details. Figure 7-4. Two-Wire Timing Diagram for Write Word Format Frame 1 Two Wire Device Address Byte Frame 2 Pointer Register Byte Host Device Device SCL 1 9 1 Start By ACK By ACK By SDA 0 0 1 1 0 0 P6 P7 P5 P4 P3 P2 P1 P0 (1) W / R Frame 3 Two Wire Device Address Byte Frame 4 Data Byte 1 Read Register Host Device Host SCL 1 9 1 Start By ACK By NACK By SDA 0 0 1 1 0 0 D6 D7 D5 D4 D3 D2 D1 D0 (1) W / R (Continued) (Continued) (2) From Device A. Target address 1001100 (TMP411A/TMP411DA) shown. Target address changes for TMP411B/TMP411DB and TMP411C/TMP411DC. See Ordering Information table for more details. B. Host must leave the SDA high to terminate a single−byte read operation. Figure 7-5. Two-Wire Timing Diagram for Single-Byte Read Format TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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THERM Limit and ALERT High Limit ALERT Low Limit and THERM Limit Hysteresis THERM ALERT SMBus ALERT Read Read Time Read Figure 7-8. SMBus Alert Timing Diagram

7.5.4 Serial Bus Address

To communicate with the TMP411/TMP411D, the controller must first address target devices through a target address byte. The target address byte consists of seven address bits and a direction bit that indicates whether the operation is read or write. The address of the TMP411 A/TMP411DA is 4Ch (1001100b). The address of the TMP411B/TMP411DB is 4Dh (1001101b). The address of the TMP411E/TMP411DE is 4Ch (1001100b). Table 7-5. TMP411/TMP411D Device Address Options DEVICE NAME PART NUMBER I2C BINARY ADDRESS I2C HEX ADDRESS OFFSET REGISTERS TMP411 (DGK and D packages) TMP411ADGKR TMP411ADR 100 1100b 4Ch No TMP411BDGKR TMP411BDR 100 1101b 4Dh No TMP411CDGKR TMP411CDR 100 1110b 4Eh No TMP411EDGKR 100 1100b 4Ch Yes TMP411D (DDF package) TMP411DADDFR 100 1100b 4Ch No TMP411DBDDFR 100 1101b 4Dh No TMP411DCDDFR 100 1110b 4Eh No TMP411DEDDFR 100 1100b 4Ch Yes

7.5.5 Read and Write Operations

To access a particular register on the TMP411/TMP411D, the appropriate value must be written to the Pointer Register. With the read and write bit low, the value for the Pointer Register is the first byte transferred after the target address byte. Every write operation to the TMP411/TMP411D requires a value for the Pointer Register, as shown in Figure 7-4. When reading from the TMP411/TMP411D, the last value stored in the Pointer Register by a write operation determines which register is read by a read operation. A new value must be written to the Pointer Register to change the register pointer for a read operation. This transaction is accomplished by issuing a target address byte with the read and write bit low, followed by the Pointer Register byte. No additional data is required. The controller then generates a START condition and sends the target address byte with the read and write bit high to initiate the read command. See Figure 7-5 for details of this sequence. Continually sending the Pointer Register bytes is not necessary if repeated reads from the same register are desired, because the TMP411/ TMP411D device retains the Pointer Register value until the next write operation changes the value. Note that the MSB sends the register bytes first, followed by the LSB. TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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7.5.6 Timeout Function

When bit 7 of the Consecutive Alert Register is set high, the TMP411/TMP411D timeout function is enabled. The TMP411/TMP411D device resets the serial interface if the SCL or SDA lines are held low for 30ms (typical) between a START and STOP condition. If the TMP411/TMP411D device is holding the bus low, the device releases the bus and waits for a START condition. Maintaining a communication speed of at least 1kHz for the SCL operating frequency is necessary to avoid activating the timeout function. The default state of the timeout function is enabled (bit 7 = high).

7.5.7 High-Speed Mode

For the two-wire bus to operate at frequencies above 400kHz, the controller device must issue a high-speed mode (Hs-mode) controller code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP411/TMP411D device does not acknowledge this byte, but switches the input filters on the SDA and SCL lines, switches the output filter on SDA to operate in Hs-mode, which allows transfers at up to 3.4MHz. After the Hs-mode controller code is issued, the controller transmits a two-wire target address to initiate a data transfer operation. The bus operates in high-speed mode until a STOP condition occurs on the bus. The TMP411/TMP411D switches the input and output filter after receiving the STOP condition.

7.5.8 General Call Reset

The TMP411/TMP411D device supports reset through the two-wire general call address 00h (0000 0000b). The TMP411/TMP411D device reads the general call address and responds to the second byte. If the second byte is 06h (0000 0110b), the TMP411/TMP411D executes a software reset. The software reset restores the power-on-reset state to all TMP411/TMP411D registers, aborts any conversion in progress, and clears the ALERT and THERM pins. The TMP411/TMP411D does not respond to other values in the second byte.

7.5.9 Software Reset

The TMP411/TMP411D resets by writing any value to Pointer Register FCh. This restores the power-on-reset state to all of the TMP411/TMP411D registers, aborts any conversion in process, and clears the ALERT and THERM pins.

7.5.10 SMBus Alert Function

The TMP411/TMP411D device supports the SMBus alert function. When pin 6 is configured as an alert output, the ALERT pin of the TMP411/TMP411D can connect as an SMBus alert signal. When a controller detects an alert condition on the ALERT line, the controller sends an SMBus alert command (00011001) on the bus. If the ALERT pin of the TMP411/TMP411D is active, the device acknowledges the SMBus alert command and returns the target address on the SDA line. The eighth bit of the target address byte indicates if the high limit or low limit temperature settings caused the alert condition. The bit is high if the temperature is greater than one of the temperature high limit settings; the bit is low if the temperature is less than or equal to one of the temperature low limit settings. See Figure 7-8 for details of this sequence. If multiple devices on the bus respond to the SMBus alert command, arbitration during the target address portion of the SMBus alert command determines which device clears the alert status. If the TMP411/TMP411D wins the arbitration, the ALERT pin inactivates when the SMBus alert command is complete. If the TMP411/TMP411D device loses the arbitration, the ALERT pin remains active. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TMP411 TMP411D

8 Register Map

Table 8-1. Register Map Summary POINTER ADDRESS (HEX) POWER-ON- RESET (HEX) BIT DESCRIPTION REGISTER DESCRIPTIONS READ WRITE D7 D6 D5 D4 D3 D2 D1 D0

00 NA (1) 00 LT11 LT10 LT9 LT8 LT7 LT6 LT5 LT4 Local Temperature (High Byte)

01 NA 00 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 Remote Temperature (High Byte)

02 NA XX BUSY LHIGH LLOW RHIGH RLOW OPEN RTHRM LTHRM Status Register

03 09 00 MASK1 SD AL/TH 0 0 RANGE 0 0 Configuration Register 04 0A 08 0 0 0 0 R3 R2 R1 R0 Conversion Rate Register 05 0B 55 LTH11 LTH10 LTH9 LTH8 LTH7 LTH6 LTH5 LTH4 Local Temperature High Limit (High Byte) 06 0C 00 LTL11 LTL10 LTL9 LTL8 LTL7 LTL6 LTL5 LTL4 Local Temperature Low Limit (High Byte) 07 0D 55 RTH11 RTH10 RTH9 RTH8 RTH7 RTH6 RTH5 RTH4 Remote Temperature High Limit (High Byte) 08 0E 00 RTL11 RTL10 RTL9 RTL8 RTL7 RTL6 RTL5 RTL4 Remote Temperature :Low Limit (High Byte) NA 0F XX X (2) X X X X X X X One-Shot Start

10 NA 00 RT3 RT2 RT1 RT0 0 0 0 0 Remote Temperature (Low Byte)

11 11 00 RTOS11 RTOS10 RTOS9 RTOS8 RTOS7 RTOS6 RTOS5 RTOS4 Remote Temperature Offset Register (High Byte) (3) 12 12 00 RTOS3 RTOS2 RTOS1 RTOS0 0 0 0 0 Remote Temperature Offset Register (Low Byte)(3) 13 13 00 RTH3 RTH2 RTH1 RTH0 0 0 0 0 Remote Temperature High Limit (Low Byte) 14 14 00 RTL3 RTL2 RTL1 RTL0 0 0 0 0 Remote Temperature Low Limit (Low Byte)

15 NA 00 LT3 LT2 LT1 LT0 0 0 0 0 Local Temperature (Low Byte)

16 16 00 LTH3 LTH2 LTH1 LTH0 0 0 0 0 Local Temperature High Limit (Low Byte) 17 17 00 LTL3 LTL2 LTL1 LTL0 0 0 0 0 Local Temperature Low Limit (Low Byte) 18 18 00 NC7 NC6 NC5 NC4 NC3 NC2 NC1 NC0 N-factor correction 19 19 55 RTHL11 RTHL10 RTHL9 RTHL8 RTHL7 RTHL6 RTHL5 RTHL4 Remote THERM Limit 1A 1A 1C 0 0 0 1 1 1 RES1 RES0 Resolution Register 20 20 55 LTHL11 LTHL10 LTHL9 LTHL8 LTHL7 LTHL6 LTHL5 LTHL4 Local THERM Limit 21 21 0A TH11 TH10 TH9 TH8 TH7 TH6 TH5 TH4 THERM Hysteresis 22 22 81 TO_EN 0 0 0 C2 C1 C0 1 Consecutive Alert Register 30 30 FF LMT11 LMT10 LMT9 LMT8 LMT7 LMT6 LMT5 LMT4 Local Temperature Minimum (High Byte) 31 31 F0 LMT3 LMT2 LMT1 LMT0 0 0 0 0 Local Temperature Minimum (Low Byte) 32 32 00 LXT11 LXT10 LXT9 LXT8 LXT7 LXT6 LXT5 LXT4 Local Temperature Maximum (High Byte) TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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Table 8-1. Register Map Summary (continued) POINTER ADDRESS (HEX) POWER-ON- RESET (HEX) BIT DESCRIPTION REGISTER DESCRIPTIONS READ WRITE D7 D6 D5 D4 D3 D2 D1 D0 33 33 00 LXT3 LXT2 LXT1 LXT0 0 0 0 0 Local Temperature Maximum (Low Byte) 34 34 FF RMT11 RMT10 RMT9 RMT8 RMT7 RMT6 RMT5 RMT4 Remote Temperature Minimum (High Byte) 35 35 F0 RTM3 RTM2 RTM1 RTM0 0 0 0 0 Remote Temperature Minimum (Low Byte) 36 36 00 RXT11 RXT10 RXT9 RXT8 RXT7 RXT6 RXT5 RXT4 Remote Temperature Maximum (High Byte) 37 37 00 RXT3 RXT2 RXT1 RXT0 0 0 0 0 Remote Temperature Maximum (Low Byte) NA FC XX X (2) X X X X X X X Software Reset FE NA 55 0 1 0 1 0 1 0 1 Manufacturer ID FF NA 12 0 0 0 1 0 0 1 0 Device ID for TMP411A/TMP411DA FF NA 13 0 0 0 1 0 0 1 1 Device ID for TMP411B/TMP411DB FF NA 10 0 0 0 1 0 0 0 0 Device ID for TMP411C/TMP411DC FF NA 12 0 0 0 1 0 0 1 0 Device ID for TMP411E/TMP411DE (1) NA = not applicable; register is write- or read-only. (2) X = indeterminable state. (3) Offset registers 11 and 12 are only available for the TMP411E/TMP411DE device. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TMP411 TMP411D

8.1 Register Information

The TMP411/TMP411D contains multiple registers for holding configuration information, temperature measurement results, maximum and minimum temperature comparator limits, and status information. These registers are described in Figure 8-1 and Table 8-1.

8.2 Pointer Register

Figure 8-1 shows the internal register structure of the TMP411/TMP411D. The 8-bit pointer register addresses a given data register. The Pointer Register identifies which of the data registers must respond to a read or write command on the two-wire bus. This register is set with every write command. A write command must be issued to set the proper value in the pointer register before executing a read command. Table 8-1 lists the pointer address of the registers available in the TMP411/TMP411D. Offset registers 11 and 12 are only available for the TMP411E/TMP411DE device . The power-on-reset (POR) value of the Pointer Register is 00h (0000 0000b). Local and Remote Temperature Registers I/O Control Interface Pointer Register Configuration Register Status Register Local and Remote Temperature Limit Registers Conversion Rate Register Remote Temperature Offset Registers One-Shot Start Register Local and Remote THERM Limit Registers THERM Hysteresis Register N-factor Correction Register Consecutive ALERT Register Digital Filter Register Manufacturer ID Register SDA SCL Figure 8-1. Internal Register Structure

8.3 Temperature Registers

The TMP411/TMP411D has four 8-bit registers that hold temperature measurement results. The local and remote channels have a high byte register that contains the most significant bits (MSBs) of the temperature analog-to-digital converter (ADC) result and a low byte register that contains the least significant bits (LSBs) of the temperature ADC result. The local channel high byte address is 00h; the local channel low byte address is 15h. The remote channel high byte is at address 01h; the remote channel low byte address is 10h. These registers are read-only and are updated by the ADC each time a temperature measurement is completed. The TMP411/TMP411D contains circuitry to verify that a low byte register read command returns data from the same ADC conversion as the immediately preceding high byte read command. This verification remains valid only until another register is read. For proper operation, the high byte of a temperature register must be read first. The low byte register must be read in the next read command. The low byte register can be left unread if the LSBs are not needed. The temperature registers can be read as a 16-bit register using a single two-byte TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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read command from address 00h for the local channel result, or from address 01h for the remote channel result. The high byte is read first, followed by the low byte. Both bytes of this read operation are from the same ADC conversion. The power-on-reset value of both temperature registers is 00h.

8.4 Limit Registers

The TMP411/TMP411D has 11 registers for setting comparator limits for the local and remote measurement channels. These registers have read and write capability. The High and Low Limit Registers for both channels span two registers, as do the temperature registers. The local temperature high limit is set by writing the high byte to pointer address 0Bh, writing the low byte to pointer address 16h, or by using a single two-byte write command (high byte first) to pointer address 0Bh. The local temperature high limit is read by the high byte from pointer address 05h, the low byte from pointer address 16h, or by using a two-byte read command from pointer address 05h. The power-on-reset value of the local temperature high limit is 5500h. The power-on-reset value of the local temperature high limit is 5500h (85°C in standard temperature mode and 21°C in extended temperature mode). Similarly, the local temperature low limit is set by writing the high byte to pointer address 0Ch, writing the low byte to pointer address 17h, or by using a single two-byte write command to pointer address 0Ch. The local temperature low limit is read by the high byte from pointer address 06h, the low byte from pointer address 17h, or by using a two-byte read from pointer address 06h. The power-on-reset value of the local temperature low limit register is 00h (0°C in standard temperature mode, and −64°C in extended mode). The remote temperature high limit is set by writing the high byte to pointer address 0Dh, writing the low byte to pointer address 13h, or by using a two-byte write command to pointer address 0Dh. The remote temperature high limit is read by the high byte from pointer address 07h, the low byte from pointer address 13h, or by using a two-byte read command from pointer address 07h. The power-on-reset value of the Remote Temperature High Limit Register is 55h or 00h (85°C in standard temperature mode, and 21°C in extended temperature mode). The remote temperature low limit is set by writing the high byte to pointer address 0Eh, writing the low byte to pointer address 14h, or by using a two-byte write to pointer address 0Eh. The remote temperature low limit is read by the high byte from pointer address 08h, the low byte from pointer address 14h, or by using a two-byte read from pointer address 08h. The power-on-reset value of the Remote Temperature Low Limit Register is 00h (0°C in standard temperature mode, and −64°C in extended mode). The TMP411/TMP411D has a THERM limit register for the local and remote channels. These registers are eight bits and allow for THERM limits to be set to 1°C resolution. The local channel THERM limit is set by writing to pointer address 20h. The remote channel THERM limit is set by writing to pointer address 19h. The local channel THERM limit is read from pointer address 20h, and the remote channel THERM limit is read from pointer address 19h. The power-on-reset value of the THERM limit registers is 55h (85°C in standard temperature mode or 21°C in extended temperature mode). The THERM limit comparators have hysteresis. The hysteresis of the comparators is set by writing to pointer address 21h. The hysteresis value is obtained by reading from pointer address 21h. The Hysteresis Register value is an unsigned number that is always positive. The power-on-reset value of this register is 0Ah (10°C). When changing between standard and extended temperature ranges, note that the temperatures stored in the temperature limit registers do not automatically reformat to correspond to the new temperature range format. These values must be reprogrammed in the appropriate binary or extended binary format.

8.5 Status Register

The TMP411/TMP411D has a Status Register that reports the state of the temperature comparators. Table 8-2 lists the Status Register bits. The Status Register is read-only from pointer address 02h. The BUSY bit reads as 1 if the ADC is making a conversion, and 0 if the ADC is not converting. The OPEN bit reads as 1 if the remote transistor is detected as OPEN since the last read of the Status Register. The OPEN status is only detected when the ADC is attempting to convert a remote temperature. The RTHRM bit reads as 1 if the remote temperature exceeds the remote THERM limit, remains greater than the remote THERM limit, and less than the value in the shared Hysteresis Register, as shown in Figure 7-8. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TMP411 TMP411D

The LTHRM bit reads as 1 if the local temperature exceeds the local THERM limit, remains greater than the local THERM limit, and less than the value in the shared Hysteresis Register, as shown in Figure 7-8. The LHIGH and RHIGH bit values depend on the state of the AL or TH bit in the Configuration Register. If the AL or TH bit is 0, the LHIGH bit reads as 1 if the local high limit is exceeded since the last clearing of the Status Register. The RHIGH bit reads as 1 if the remote high limit is exceeded since the last clearing of the Status Register. If the AL or TH bit is 1, the remote high limit and the local high limit implement a THERM2 function. LHIGH reads as 1 if the local temperature has exceeded the local high limit and remains greater than the local high limit, and less than the value in the Hysteresis Register. The RHIGH bit reads as 1 if the remote temperature exceeds the remote high limit and remains greater than the remote high limit, and less than the value in the Hysteresis Register. The LLOW and RLOW bits are not effected by the AL or TH bit. The LLOW bit reads as 1 if the local low limit is exceeded since the last clearing of the Status Register. The RLOW bit reads as 1 if the remote low limit is exceeded since the last clearing of the Status Register. When there is no remote diode connected and the power supply ramp rate is less than 240V/s, RLOW flag is set as well and must be ignored. The values of the LLOW, RLOW, and OPEN (as well as LHIGH and RHIGH when AL or TH is 0) are latched and are read as 1 until the Status Register is read or a device reset occurs. These bits are cleared by reading the Status Register, provided that the condition causing the flag to be set no longer exists. The values of BUSY, LTHRM, and RTHRM (as well as LHIGH and RHIGH when ALERT/THERM2 is 1) are not latched and are not cleared by reading the Status Register. The values indicate the current state, and are updated appropriately at the end of the corresponding ADC conversion. Clearing the Status Register bits does not clear the state of the ALERT pin. An SMBus alert response address command must clear the ALERT pin. The TMP411/TMP411D NORs LHIGH, LLOW, RHIGH, RLOW, and OPEN, so a status change for any of these flags from 0 to 1 automatically causes the ALERT pin to go low. (This only applies when the ALERT/THERM2 pin is configured for ALERT mode). Table 8-2. Status Register Format STATUS REGISTER (READ = 02h, WRITE = NA) Bit Number D7 D6 D5 D4 D3 D2 D1 D0 Bit Name BUSY LHIGH LLOW RHIGH RLOW OPEN RTHRM LTHRM POR Value 0 (1) 0 0 0 0 0 0 0 (1) The BUSY bit changes to 1 almost immediately (<< 100µs) following power-up, as the TMP411/TMP411D device begins the first temperature conversion. The BUSY bit is high whenever the TMP411/TMP411D device is converting a temperature reading.

8.6 Configuration Register

The Configuration Register sets the temperature range, controls shutdown mode, and determines how the ALERT and THERM2 pins function. The Configuration Register is set by writing to pointer address 09h and by reading from pointer address 03h. The MASK bit (bit 7) enables or disables the ALERT pin output if AL or TH = 0. If AL or TH = 1, then the MASK bit has no effect. If MASK is set to 0, the ALERT pin goes low when one of the temperature measurement channels exceeds the high or low limits for the selected number of consecutive conversions. If the MASK bit is set to 1, the TMP411/TMP411D retains the ALERT pin status, but the ALERT pin does not go low. The shutdown (SD) bit (bit 6) enables or disables the temperature measurement circuitry. If SD = 0, the TMP411/ TMP411D converts continuously at the rate set in the conversion rate register. When SD is set to 1, the TMP411/ TMP411D immediately stops converting and enters shutdown mode. When SD is set to 0 again, the TMP411/ TMP411D resumes continuous conversions. A single conversion starts by writing to the One-Shot Register when SD = 1. The AL or TH bit (bit 5) controls if the ALERT pin functions in ALERT mode or THERM2 mode. If AL or TH = 0, the ALERT pin operates as an interrupt pin. In this mode, the ALERT pin goes low after the set number of consecutive out-of-limit temperature measurements occur. TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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If AL or TH = 1, the ALERT /THERM2 pin implements a THERM function ( THERM2). In this mode, THERM2 functions similarly to the THERM pin, except that the local high limit and remote high limit registers are used for the thresholds. THERM2 goes low when RHIGH or LHIGH is set. The temperature range is set by configuring bit 2 of the Configuration Register. Setting this bit low configures the TMP411/TMP411D device for the standard measurement range (0°C to 127°C). Temperature conversions are stored in the standard binary format. Setting bit 2 high configures the TMP411/TMP411D for the extended measurement range ( −55°C to +150°C). Temperature conversions are stored in the extended binary format, as listed in Table 7-1. The remaining bits of the Configuration Register are reserved and must be set to 0. The power-on-reset value for this register is 00h. Table 8-3 lists the Configuration Register bits. Table 8-3. Configuration Register Bit Descriptions CONFIGURATION REGISTER (READ = 03h, WRITE = 09h, POR = 00h) BIT NAME FUNCTION POWER-ON-RESET VALUE

7 MASK 0 = ALERT enabled

1 = ALERT masked 0

6 SD 0 = Run

1 = Shutdown 0

5 AL or TH 0 = ALERT mode

1 = THERM mode 0 4, 3 Reserved — 0

2 Temperature range 0 = 0°C to 127°C

1 = –55°C to 150°C 0 1, 0 Reserved — 0

8.7 Resolution Register

The RES1 and RES0 bits (resolution bits 1 and 0) of the Resolution Register set the resolution of the local temperature measurement channel. Remote temperature measurement channel resolution is not effected. Changing the local channel resolution affects the conversion time and rate of the TMP411 only. The Resolution Register is set by writing to pointer address 1Ah, and is read from pointer address 1Ah. Table 8-4 lists the resolution bits for the Resolution Register. Table 8-4. Resolution Register: Local Channel Programmable Resolution RESOLUTION REGISTER (READ = 1Ah, WRITE = 1Ah, POR = 1Ch) RES1 RES0 RESOLUTION CONVERSION TIME (TYPICAL) TMP411 (Legacy chip) CONVERSION TIME (TYPICAL) TMP411 (New chip) TMP411D 0 0 9 Bits (0.5°C) 12.5ms 17.7ms 0 1 10 Bits (0.25°C) 25ms 17.7ms 1 0 11 Bits (0.125°C) 50ms 17.7ms 1 1 12 Bits (0.0625°C) 100ms 17.7ms Bits 2 through 4 of the resolution register must be set to 1. Bits 5 through 7 of the resolution register must be set to 0. The power-on-reset value of this register is 1Ch.

8.8 Conversion Rate Register

The Conversion Rate Register controls the rate at which temperature conversions are performed. The register adjusts the idle time between conversions but not the conversion timing, which allows the TMP411/TMP411D www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TMP411 TMP411D

power dissipation to balance with the temperature register update rate. Table 8-5 lists the conversion rate options and corresponding current consumption. Table 8-5. Conversion Rate Register CONVERSION RATE REGISTER (READ = 04h, WRITE = 0Ah, POR = 08h R7 R6 R5 R4 R3 R2 R1 R0 CONVERSIONS PER SECOND AVERAGE IQ (TYPICAL) (µA) TMP411 (Legacy chip) AVERAGE IQ (TYPICAL)(µA) TMP411 (New chip) TMP411D V+ = 2.7V V+ = 5.5V V+ = 2.7V and 5.5V 0 0 0 0 0 0 0 0 0.0625 11 32 1.5 0 0 0 0 0 0 0 1 0.125 17 38 1.8 0 0 0 0 0 0 1 0 0.25 28 49 2.5 0 0 0 0 0 0 1 1 0.5 47 69 3.8 0 0 0 0 0 1 0 0 1 80 103 6.5 0 0 0 0 0 1 0 1 2 128 155 12 0 0 0 0 0 1 1 0 4 190 220 23 07h to 0Fh 8 373 413 45

8.9 N-Factor Correction Register

The TMP411/TMP411D allows for a different n-factor value to convert remote channel measurements to temperature. The remote channel uses sequential current excitation to extract a differential V BE voltage measurement to determine the temperature of the remote transistor. Equation 1 relates the voltage and temperature. BE2 BE1 InkTV V ln q I § · ¨ ¸ © ¹ (1) The value n is a characteristic of the particular transistor used for the remote channel. The default value for the TMP411/TMP411D is n = 1.008. The value in the Table 8-6 adjusts the effective n-factor according to Equation 2 and Equation 3: eff ADJUST 1.008 300n (300 N ) u (2) ADJUST eff 300 1.008N 300 n § · u ¨ ¸ © ¹ (3) The n-correction value must be stored in two’s-complement format, yielding an effective data range from −128 to 127, as listed in Table 8-6. The n-correction value is written to and read from pointer address 18h. The register power-on-reset value is 00h, which is not effected unless the value is written to. TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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Table 8-6. N-Factor Range NADJUST N BINARY HEX DECIMAL 01111111 7F 127 1.747977 00001010 0A 10 1.042759 00001000 08 8 1.035616 00000110 06 6 1.028571 00000100 04 4 1.021622 00000010 02 2 1.014765 00000001 01 1 1.011371 00000000 00 0 1.008 11111111 FF –1 1.004651 11111110 FE –2 1.001325 11111100 FC –4 0.994737 11111010 FA –6 0.988235 11111000 F8 –8 0.981818 11110110 F6 –10 0.975484 10000000 80 –128 0.706542

8.10 Minimum and Maximum Registers

The TMP411/TMP411D stores the measured minimum and maximum temperatures since power-on, chip-reset, or minimum and maximum register reset for the local and remote channels. The Local Temperature Minimum Register is read with the high byte from pointer address 30h, and the low byte is read from pointer address 31h. The Local Temperature Minimum Register is read with a two-byte read command from pointer address 30h. The Local Temperature Minimum Register resets at power-on by executing the chip-reset command, or by writing any value to any of the pointer addresses 30h through 37h. The reset value for these registers is FFh and F0h. The Local Temperature Maximum Register is read with the high byte from pointer address 32h, and the low byte is read from pointer address 33h. The Local Temperature Maximum Register is read with a two-byte read command from pointer address 32h. The Local Temperature Maximum Register resets at power-on by executing the chip reset command, or by writing any value to any of the pointer addresses 30h through 37h. The reset value for these registers is 00h and 00h. The Remote Temperature Minimum Register is read with the high byte from pointer address 34h, and the low byte is read from pointer address 35h. The Remote Temperature Minimum Register is read with a two-byte read command from pointer address 34h. The Remote Temperature Minimum Register resets at power-on by executing the chip reset command, or by writing any value to any of the pointer addresses 30h through 37h. The reset value for these registers is FFh and F0h. The Remote Temperature Maximum Register is read with the high byte from pointer address 36h and the low byte is read from pointer address 37h. The Remote Temperature Maximum Register is read with a two-byte read command from pointer address 36h. The Remote Temperature Maximum Register resets at power-on by executing the chip reset command, or by writing any value to any of the pointer addresses 30h through 37h. The reset value for these registers is 00h and 00h. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TMP411 TMP411D

8.11 Consecutive Alert Register

The value in the Consecutive Alert Register (address 22h) determines how many consecutive out-of-limit measurements must occur on a measurement channel before the ALERT signal is activated. The value in this register does not effect bits in the Status Register. Values of one, two, three, or four consecutive conversions can be selected; one conversion is the default. The function allows additional filtering for the ALERT pin. The consecutive alert bits are listed in Table 8-7: Table 8-7. Consecutive Alert Register CONSECUTIVE ALERT REGISTER (READ = 22h, WRITE = 22h, POR = 01h) C2 C1 C0 NUMBER OF CONSECUTIVE OUT OF LIMIT MEASUREMENTS 0 0 0 1 0 0 1 2 0 1 1 3 1 1 1 4 Note Bit 7 of the Consecutive Alert Register controls the enable/disable of the timeout function. See the Timeout Function section for a description of this feature.

8.12 THERM Hysteresis Register

The THERM Hysteresis Register, shown in Table 8-9, stores the hysteresis value for the THERM pin alarm function. This register must be programmed with a value that is less than the Local Temperature High Limit Register value, Remote Temperature High Limit Register value, Local THERM Limit Register value, or Remote THERM Limit Register value, otherwise the respective temperature comparator does not trip on the falling edges of the measured temperature. Permitted hysteresis values are listed in Table 8-8. The default hysteresis value is 10°C, whether the device is operating in the standard or extended mode setting. Table 8-8. Allowable THERM Hysteresis Values TEMPERATURE (°C) THERM HYSTERESIS VALUES TH [11:1] (STANDARD BINARY) (HEX) 0 0000 0000 00 1 0000 0001 01 5 0000 0101 05 10 0000 1010 0A 25 0001 1001 19 50 0011 0010 32 75 0100 1011 4B 100 0110 0100 64 125 0111 1101 7D 127 0111 1111 7F 150 1001 0110 96 175 1010 1111 AF 200 1100 1000 C8 225 1110 0001 E1 255 1111 1111 FF TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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Table 8-9. THERM Hysteresis Register Format THERM HYSTERESIS REGISTER (READ = 21h, WRITE = 21h, POR = 0Ah) BIT NUMBER D7 D6 D5 D4 D3 D2 D1 D0 BIT NAME TH11 TH10 TH9 TH8 TH7 TH6 TH5 TH4 POR VALUE 0 0 0 0 1 0 1 0

8.13 Remote Temperature Offset Register

The offset register allows the TMP411 E/TMP411DE to store any system offset compensation value that can result from precision calibration. The value in the register is stored in the same format as the temperature result, and is added to the remote temperature result after each conversion. Combined with the η-factor correction, the function allows for an accurate system calibration over the entire temperature range.

8.14 Identification Registers

The TMP411/TMP411D allows for the two-wire bus controller to query the device for manufacturer and device identification. This feature allows for software identification of the device at the particular two-wire bus address. The manufacturer identification is obtained by reading from pointer address FEh. The TMP411/TMP411D manufacturer code is 55h. The device identification depends on the specific model, as listed in Table 8-1. These registers are read-only. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TMP411 TMP411D

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TMP411/TMP411D only requires a transistor connected between the D+ and D– pins for remote temperature measurement. Tie the D+ pin to D- if the remote channel is not used and only the local temperature is measured. The SDA, ALERT and THERM pins (and SCL, if driven by an open-drain output) require pullup resistors as part of the communication bus. TI recommends using a 0.1µF power-supply decoupling capacitor for local bypassing. Figure 9-1 illustrates the typical configurations for the TMP411/TMP411D. For V+ ≥ 2.7V as shown in Figure 9-1, TMP411/TMP411D digital pins (4, 6, 7 and 8) can be connected to a separate I 2C pullup and supply voltage due to fixed logic input voltages. However, for V+ < 2.7V as shown in Figure 9-2, TMP411D digital pins (SCL, SDA) must be connected to an equal I 2C pullup and supply voltage due to ratiometric logic input voltages (30%/70% of V+ pin). TMP411 TMP411D SCL SDA GND Processor or ASIC SMBus Controller 4 5 2.7V to 5.5V 2.7V to 5.5V Fixed VIH/VIL Built-In Thermal Transistor, Diode Overtemperature Shutdown THERM THERM2ALERT / Figure 9-1. TMP411/TMP411D Simplified Block Diagram (Separate I2C Pullup and Supply Voltage Application while V+ ≥ 2.7V) TMP411D SCL SDA GND Processor or ASIC SMBus Controller 4 5 Built-In Thermal Transistor, Diode Overtemperature Shutdown THERM THERM2ALERT / 1.62V to 2.7V VIH/VIL: 0.7/0.3 V+ Figure 9-2. TMP411D Simplified Block Diagram (Equal I2C Pullup and Supply Voltage Application while V+ < 2.7V) TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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9.2 Typical Application

9.2.1 Design Requirements

The TMP411/TMP411D is designed to be used with discrete transistors or substrate transistors built into processor chips and ASICs. NPN or PNP transistors can be used, as long as the base-emitter junction is the remote temperature sensor. A transistor or diode connection can be used, as shown in Figure 7-1. The D+ pin waveform is shown in Figure 9-3 while a transistor is connected between the D+ and D– pins. Due to 3 different source currents shown in Functional Block Diagram , the D+ waveform has 3 levels of voltages during temperature conversion. Time (s) D+/DXP (V) -0.2 0.2 0.4 0.6 0.8 Time (s) D+/DXP (V) 0.5 0.55 0.6 0.65 0.7 Temperature Conversion No Conversion No Conversion Figure 9-3. D+ Waveform Errors in remote temperature sensor readings are the result of the ideality factor and current excitation from the TMP411/TMP411D versus the manufacturer-specified operating current for a given transistor. Some manufacturers specify a high-level and low-level current for the temperature-sensing substrate transistors. The TMP411/TMP411D has an I LOW value of 6 μA, and an I HIGH value of 120 μA. The TMP411/TMP411D allows for different n-factor values, as shown in Table 8-6. The ideality factor ( n) is a measured characteristic of a remote temperature sensor diode compared to an ideal diode. The ideality factor reduces to a value of 1.008. For transistors with an ideality factor that does not match the TMP411/TMP411D, Equation 4 calculates the temperature error. Note that the actual temperature (°C) must be converted to Kelvin (°K) for the equation to yield the correct results. ERR n 1.008T 273.15 T( C)1.008 § · u ¨ ¸ © ¹ or T ERR = n a ct u al − n ex pect ed n ex pect ed × 273.15 + T a ct u al ֯ C (4) where:

• n or nactual = the ideality factor of the remote temperature sensor
• T(°C) or Tactual(°C) = actual temperature
• TERR = Treported - Tactual= device reading error due to n or nactual ≠ 1.008
• Degree delta is the same for °C and °K
• nexpected = 1.008 www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TMP411 TMP411D

For n = 1.004 and T(°C) = 100°C, use Equation 5: ERR ERR 1.004 1.008T 273.15 100 C1.008 T 1.48 C § · u ¨ ¸ © ¹ (5) If a discrete transistor is used as the remote temperature sensor, please select the transistor according to the following criteria results in the best accuracy. 1. Base-emitter voltage > 0.25V at 6µA, at the highest sensed temperature. 2. Base-emitter voltage < 0.95V at 120µA, at the lowest sensed temperature. 3. Base resistance < 100Ω 4. Tight control of VBE characteristics indicated by small variations in hFE (that is, 50 to 150). Based on these criteria, TI recommends using two small-signal transistors, such as the 2N3904 (NPN) or 2N3906 (PNP).

9.2.2 Detailed Design Procedure

The temperature measurement accuracy of the TMP411/TMP411D depends on the remote or local temperature sensor being at the same temperature as the monitored system point. If the temperature sensor is not in good thermal contact with the part of the system being monitored, then there is a delay in the response of the sensor to a temperature change in the system. For remote temperature sensing applications using a substrate transistor (or a small, SOT-23 transistor) placed close to the device, this delay is typically not a concern. The local temperature sensor inside the TMP411/TMP411D monitors the ambient air around the device. The thermal time constant for the TMP411/TMP411D is approximately two seconds. This constant implies that if the ambient air changes quickly by 100°C, the TMP411/TMP411D takes approximately 10 seconds (that is, five thermal time constants) to settle within 1°C of the final value. In most applications, the TMP411/TMP411D package is in electrical (and thermal contact) with the printed circuit board (PCB), and subjected to forced airflow. The accuracy of the temperature measurement directly depends on how accurately the PCB and forced airflow temperatures represent the temperature measured by the device. Additionally, the internal power dissipation of the TMP411/TMP411D can cause the temperature to rise above the ambient or PCB temperature. The internal power dissipated as a result of exciting the remote temperature sensor is negligible because of the small currents used. TMP411 (Legacy Chip) : For a 3.3V supply and maximum conversion rate of eight conversions per second, the TMP411 dissipates 1.32mW (PD IQ = 3.3V × 400µA). If the ALERT/ THERM2 and THERM pins are each power dissipation equals 2.12mW (PD IQ + PD OUT) and (with a θJA value of 150°C/W) causes the junction temperature to rise approximately 0.318°C above the ambient. TMP411 (New Chip) : For a 3.3V supply and maximum conversion rate of eight conversions per second, the TMP411 dissipates 0.149mW (PD IQ = 3.3V × 45µA). If the ALERT/ THERM2 and THERM pins are each sinking power dissipation equals 0.949mW (PD IQ + PD OUT) and (with a θJA value of 162°C/W) causes the junction temperature to rise approximately 0.154°C above the ambient. TMP411D: For a 3.3V supply and maximum conversion rate of eight conversions per second, the TMP411D dissipates 0.149mW (PD IQ = 3.3V × 45µA). If the ALERT/ THERM2 and THERM pins are each sinking power dissipation equals 0.949mW (PD IQ + PD OUT) and (with a θJA value of 182°C/W) causes the junction temperature to rise approximately 0.173°C above the ambient. TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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9.2.3 Application Curves

í50 í25 1251007550250 Remote Temperature Error (°C) VS = 3.3V TDIODE = +25 °C (temperature at remote diode) = 1.008 Ambient Temperature, (°C) Figure 9-4. Remote Temperature Error vs TMP411 Ambient Temperature (Legacy chip) A m b i e n t T e m p e r a t u r e , T A ( C ) Remote Temperature Error ( - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 3 - 2 - 1 V S = 3 . 3 V T D I O D E = + 2 5 ° C ( t e m p e r a t u r e a t r e m o t e d i o d e ) 3 0 T y p i c a l U n i t s S h o w n  = 1 . 0 0 8 Figure 9-5. Remote Temperature Error vs TMP411 Ambient Temperature (New chip) Local T emperature Error ( °C) Ambient Temperature,TA ( °C) 3.0 2.0 1.0 í1.0 í2.0 í3.0 í50 125í25 0 25 50 75 100 50 Units ShownVS = 3.3V Figure 9-6. Local Temperature Error vs TMP411 Ambient Temperature (Legacy chip) A m b i e n t T e m p e r a t u r e , T A ( C ) Local Temperature Error ( - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 3 - 2 - 1 V S = 3 . 3 V ( 5 0 U n i t s S h o w n ) Figure 9-7. Local Temperature Error vs TMP411 Ambient Temperature (New chip) A m b i e n t T e m p e r a t u r e , T A ( C ) Remote Temperature Error ( - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 T M P 4 1 1 D M a x T M P 4 1 1 D m i n V + = 3 . 3 V ( 3 0 U n i t s S h o w n ) &  = 1 . 0 0 8 Figure 9-8. Remote Temperature Error vs TMP411D Ambient Temperature A m b i e n t T e m p e r a t u r e T A ( C ) Local Temperature Error ( - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 1 . 2 - 0 . 8 - 0 . 4 0 . 4 0 . 8 1 . 2 T M P 4 1 1 D ( M a x ) T M P 4 1 1 D ( m i n ) V + = 3 . 3 V ( 3 0 U n i t s S h o w n ) Figure 9-9. Local Temperature Error vs TMP411D Ambient Temperature www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TMP411 TMP411D

9.3 Power Supply Recommendations

The TMP411 operates with a power supply range of 2.7V to 5.5V while TMP411D power supply range is 1.62V to 5.5V. The device is optimized for operation at a 3.3V supply, but measures temperature accurately in the full supply range. TI recommends using a power supply bypass capacitor. Place the capacitor as close as possible to the supply and ground pins of the device. 0.1µF is a typical value for the supply bypass capacitor. Applications with noisy or high-impedance power supplies can require additional decoupling capacitors to reject power-supply noise.

9.4 Layout

9.4.1 Layout Guidelines

Remote temperature sensing on the TMP411/TMP411D measures small voltages using low currents, and therefore noise at the device inputs must be minimized. Most applications using the TMP411/TMP411D have high digital content with several clocks and logic-level transitions that create a noisy environment. The layout must adhere to the following guidelines:

• Place the TMP411/TMP411D as close to the remote junction sensor as possible.
• Route the D+ and D– traces next to each other and shield the traces from adjacent signals using ground guard traces, as shown in Figure 9-10. If a multilayer PCB is used, bury these traces between ground or VDD planes to shield the planes from extrinsic noise sources. TI recommends using 5mm (0.127mm) PCB traces.
• Minimize additional thermocouple junctions caused by copper-to-solder connections. If these junctions are used, make the same number and approximate location of copper-to-solder connections in the D+ and D– connections to cancel any thermocouple effects.
• Use a 0.1µF local bypass capacitor directly between the V+ and GND pins of the TMP411/TMP411D, as shown in Figure 9-11. Minimize filter capacitance between D+ and D– to 1000pF or less for optimum measurement performance. This capacitance includes any cable capacitance between the remote temperature sensor and the TMP411/TMP411D.
• If the connection between the remote temperature sensor and the TMP411/TMP411D is less than eight inches (20cm), use a twisted-wire pair connection. If the connection measures more than eight inches (20cm), use a twisted, shielded pair with the shield grounded as close to the TMP411/TMP411D as possible. Leave the remote sensor connection end of the shield wire open to avoid grounded loops and 60Hz pickup. GND Dí GND Ground or V+ layer on bottom and/or top, if possible. Figure 9-10. Example Signal Traces TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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0.1µF Ca pacit or P CB Via PCB Via V+ GND Figure 9-11. Suggested Bypass Capacitor Placement

9.4.2 Layout Example

VIA to Power or Ground Plane VIA to Internal Layer Figure 9-12. TMP411/TMP411D Device Layout (Equal I2C Pullup and Supply Voltage Application) Figure 9-13. TMP411/TMP411D Different Package Sizes www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TMP411 TMP411D

10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

• Texas Instruments, Optimizing Remote Temperature Sensor Design, application note
• Texas Instruments, TMP451 ±1°C Remote and Local Temperature Sensor With η-Factor and Offset Correction, Series-Resistance Cancellation, and Programmable Digital Filter, data sheet
• Texas Instruments, TMP4718 High-Accuracy Remote and Local Temperature Sensor with Pin Programmable Alert Thresholds, data sheet
• Texas Instruments, ±1°C Remote and Local Temperature Sensor, data sheet
• Texas Instruments, Remote Temperature Sensor Transistor Selection Guide, application note
• Texas Instruments, TMP411 Evaluation Module, EVM

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Changes from Revision D (August 2016) to Revision E (July 2025) Page TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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• Updated the Undervoltage Lockout section due to Undervoltage lockout voltage removal by POR in the
• Updated the Status Register section due to Undervoltage lockout voltage removal by POR in the New chip.33 Changes from Revision C (May 2008) to Revision D (August 2016) Page
• Added "Offset Registers for System Calibration" and "Pin and Registers Compatible With ADT7461 and

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: TMP411 TMP411D

12.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TMP411ADGKR VSSOP DGK 8 2500 330 12.4 5.3 3.3 1.3 8 12 Q1 TMP411ADGKR VSSOP DGK 8 2500 330 12.4 5.3 3.4 1.4 8 12 Q1 TMP411ADR SOIC D 8 2500 330 12.4 6.4 5.2 2.1 8 12 Q1 TMP411BDGKR VSSOP DGK 8 2500 330 12.4 5.3 3.4 1.4 8 12 Q1 TMP411BDGKR VSSOP DGK 8 2500 330 12.4 5.3 3.3 1.3 8 12 Q1 TMP411BDR SOIC D 8 2500 330 12.4 6.4 5.2 2.1 8 12 Q1 TMP411CDGKR VSSOP DGK 8 2500 330 12.4 5.3 3.4 1.4 8 12 Q1 TMP411CDR SOIC D 8 2500 330 12.4 6.4 5.2 2.1 8 12 Q1 TMP411EDGKR VSSOP DGK 8 2500 330 12.4 5.3 3.4 1.4 8 12 Q1 TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 www.ti.com

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP411ADGKR VSSOP DGK 8 2500 367 367 38 TMP411ADGKR VSSOP DGK 8 2500 366 364 50 TMP411ADR SOIC D 8 2500 356 356 35 TMP411BDGKR VSSOP DGK 8 2500 366 364 50 TMP411BDGKR VSSOP DGK 8 2500 367 367 38 TMP411BDR SOIC D 8 2500 356 356 35 TMP411CDGKR VSSOP DGK 8 2500 366 364 50 TMP411CDR SOIC D 8 2500 356 356 35 TMP411EDGKR VSSOP DGK 8 2500 366 364 50 www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: TMP411 TMP411D

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TMP411AD Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 125 T411A TMP411ADGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 411A TMP411ADGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 411A TMP411ADGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 411A TMP411ADR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T411A TMP411ADR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T411A TMP411BD Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 125 T411B TMP411BDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 411B TMP411BDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 411B TMP411BDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 411B TMP411BDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T411B TMP411BDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T411B TMP411CD Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 125 T411C TMP411CDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 411C TMP411CDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 411C TMP411CDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 411C TMP411CDGKT Obsolete Production VSSOP (DGK) | 8 - - Call TI Call TI -40 to 125 411C TMP411CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T411C TMP411CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T411C TMP411CDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T411C TMP411DADDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 3M7F TMP411DBDDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 3LJF TMP411DCDDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 3M8F TMP411DEDDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 3MAF TMP411EDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 411E TMP411EDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 411E TMP411EDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 411E TMP411EDGKT Obsolete Production VSSOP (DGK) | 8 - - Call TI Call TI -40 to 125 411E Addendum-Page 1

www.ti.com 7-Oct-2025 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMP411, TMP411D :

• Automotive : TMP411-Q1 , TMP411D-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX 6X 0.65 8X 0.38 0.22 1.95 0.20

0.08 TYP

0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 4X 0 -15 4X 4 -15 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6)

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

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