Sensor

TMP275AQDGKRQ1

Texas Instruments

Automotive Grade Temperature Sensor

Manufacturer: Texas Instruments

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0.01-µF Supply Bypass Capacitor 2.7-V to 5.5-V Supply Voltage Diode Senso r ΔΣ ADC OSC Control Logic Serial Interface Config. and T e mp. Reg ister T emperature ALERT SDA 1 5GND SCL 2 7 A0 T emp. Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMP275-Q1 SBOS760A –NOVEMBER 2015–REVISED JANUARY 2016 TMP275-Q1AutomotiveGrade±0.5°CTemperatureSensorwithI2CandSMBusInterface inIndustry-StandardLM75FormFactorandPinout

1 Features

1• AEC-Q100 Qualified with: – Temperature Grade 1: –40°C to +125°C Ambient Operation Temperature Range – HBM ESD Classification Level 2 – CDM ESD Classification Level C6

High Accuracy: – ±0.5°C (Maximum) from −20°C to +100°C – ±1°C (Maximum) from −40°C to +125°C
Low Quiescent Current: – 50 μA (Typical) – 0.1 μA (Standby)
Resolution: 9 to 12 Bits, User-Selectable
Digital Output: SMBus™ , Two-Wire, and I2C Interface Compatibility
8 I2C, SMBus Addresses
Wide Supply Range: 2.7 V to 5.5 V
Small 8-Pin VSSOP and SOIC Packages
No Specified Power-Up Sequence Required, Two- Wire Bus Pullups Can Be Enabled Before V+

2 Applications

Climate Controls
Infotainment Processor Management
Airflow Sensors
Battery Control Units
Engine Control Units
UREA Sensors
Water Pumps
HID Lamps
Airbag Control Units Simplified Schematic

3 Description

The TMP275-Q1 is a ±0.5°C, accurate integrated digital temperature sensor with a 12-bit, analog-to- digital converter (ADC) that can operate on a supply voltage as low as 2.7 V and is pin- and register- compatible with the Texas Instruments' LM75, TMP75, TMP75B, and TMP175 devices. The TMP275-Q1 device is available in 8-pin SOIC and VSSOP packages and requires no external components to sense temperature. The device is capable of reading temperatures with a maximum resolution of 0.0625°C (12 bits) and as low as 0.5°C (9 bits), thus allowing the user to maximize efficiency by programming for higher resolution or faster conversion time. The device is specified over the temperature range of –40°C to +125°C. The TMP275-Q1 device features SMBus and two- wire interface compatibility, and allows up to eight devices on the same bus with the SMBus overtemperature alert function. The factory-calibrated temperature accuracy and the noise-immune digital interface make the TMP275-Q1 the preferred solution for temperature compensation of other sensors and electronic components, without the need for additional system-level calibration or elaborate board layout for distributed temperature sensing. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMP275-Q1 SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Internal Block Diagram

12 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (November 2015) to Revision A Page

5 Pin Configuration and Functions

D, DGK Packages 8-Pin SOIC, VSSOP Top View Pin Functions PIN I/O DESCRIPTION NO. NAME 1 SDA I/O Serial data. Open-drain output; requires a pullup resistor. 2 SCL I Serial clock. Open-drain output; requires a pullup resistor. 3 ALERT O Overtemperature alert. Open-drain output; requires a pullup resistor.

4 GND — Ground

5 A2 I

Address select. Connect to GND or V+.6 A1 I

7 A0 I

8 V+ I Supply voltage, 2.7 V to 5.5 V

SBOS760A –NOVEMBER 2015–REVISED JANUARY 2016 www.ti.com Product Folder Links: TMP275-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Power supply, V+ 7 V Input voltage(2) –0.5 7 V Input current 10 mA Operating temperature –55 127 °C Junction temperature, TJ max 150 °C Storage temperature, Tstg –60 130 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage 2.7 5.5 V Operating free-air temperature, TA –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) TMP275-Q1 UNITD (SOIC) DGK (VSSOP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 121.6 185 °C/W RθJC(top) Junction-to-case (top) thermal resistance 70.5 76.1 °C/W RθJB Junction-to-board thermal resistance 62 106.4 °C/W ψJT Junction-to-top characterization parameter 23 14.1 °C/W ψJB Junction-to-board characterization parameter 61.5 104.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

www.ti.com SBOS760A –NOVEMBER 2015–REVISED JANUARY 2016 Product Folder Links: TMP275-Q1 Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated (1) Specified for 12-bit resolution.

6.5 Electrical Characteristics

at TA = –40°C to +125°C and V+ = 2.7 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE INPUT Range –40 125 °C Accuracy (temperature error) 0°C to 100°C, V+ = 3 V to 3.6 V ±0.125 ±0.75 –40°C to 125°C, V+ = 3 V to 3.6 V ±0.125 ±1 25°C to 100°C, V+ = 3.3 V to 5.5 V 0.2 ±1.5 Resolution(1) Selectable 0.0625 °C DIGITAL INPUT/OUTPUT Input capacitance 3 pF VIH High-level input logic 0.7 (V+) 6 V VIL Low-level input logic –0.5 0.3 (V+) V IIN Leakage input current 0 V ≤ VIN ≤ 6 V 1 µA Input voltage hysteresis SCL and SDA pins 500 mV VOL Low-level output logic SDA IOL = 3 mA 0 0.15 0.4 V ALERT IOL = 4 mA 0 0.15 0.4 Resolution Selectable 9 to 12 Bits Conversion time 9 bits 27.5 37.5 ms 10 bits 55 75 11 bits 110 150 12 bits 220 300 Time-out time 25 54 74 ms POWER SUPPLY Operating range 2.7 5.5 V IQ Quiescent current Serial bus inactive 50 85 µASerial bus active, SCL frequency = 400 kHz 100 Serial bus active, SCL frequency = 3.4 MHz 410 ISD Shutdown current Serial bus inactive 0.1 3 µASerial bus active, SCL frequency = 400 kHz 60 Serial bus active, SCL frequency = 3.4 MHz 380 TEMPERATURE RANGE Specified range –40 125 °C Operating range –55 127 °C

SBOS760A –NOVEMBER 2015–REVISED JANUARY 2016 www.ti.com Product Folder Links: TMP275-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) Values are based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and are not production tested.

6.6 Timing Requirements

see the Timing Diagrams section for timing diagrams(1) FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.38 MHz t(BUF) Bus-free time between STOP and START condition See the Timing Diagrams section 1300 160 ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns t(SUSTA) repeated start condition setup time 600 160 ns t(SUSTO) STOP Condition Setup Time 600 160 ns t(HDDAT) Data hold time 4 900 4 120 ns t(SUDAT) Data setup time 100 10 ns t(LOW) SCL-clock low period V+ , see the Timing Diagrams section 1300 280 ns t(HIGH) SCL-clock high period See the Timing Diagrams section 600 60 ns tFD Data fall time See the Timing Diagrams section 300 150 ns tRC Clock rise time See the Two-Wire Timing Diagrams section 300 40 ns SCLK ≤ 100 kHz, see the Timing Diagrams section 1000 ns tFC Clock fall time See the Two-Wire Timing Diagrams section 300 40 ns

6.7 Typical Characteristics

Figure 1. Quiescent Current vs Temperature Figure 2. Shutdown Current vs Temperature Figure 3. Conversion Time vs Temperature Figure 4. Temperature Error vs Temperature Figure 5. Quiescent Current with Bus Activity Figure 6. Temperature Error at 25°C

ΔΣ ADC OSC Control Logic Serial Interface Config. and T e mp. Reg ister T emperature ALERT SDA 1 5GND SCL 2 7 A0 T emp. TMP275-Q1 SBOS760A –NOVEMBER 2015–REVISED JANUARY 2016 www.ti.com Product Folder Links: TMP275-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TMP275-Q1 is a digital temperature sensor that is optimal for thermal management and thermal protection applications. The TMP275-Q1 is two-wire, SMBus, and I2C interface compatible, and is specified over the temperature range of –40°C to +125°C. The temperature sensor in the TMP275-Q1 is the device itself. Thermal paths run through the package leads as well as the plastic package. The package leads provide the primary thermal path because of the lower thermal resistance of the metal; see the Functional Block Diagram section for the internal block diagram of the TMP275-Q1 device.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Digital Temperature Output

least significant bits (LSBs) set to zero. Table 1. Temperature Data Format

7.3.2 Serial Interface

The TMP275-Q1 operates only as a slave device on the SMBus, two-wire, and I2C interface-compatible bus. integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. modes. All data bytes are transmitted most significant bit (MSB) first.

7.3.3 Bus Overview

generates the START and STOP conditions. responds to the master by generating an Acknowledge bit and pulling SDA low.

7.3.4 Serial Bus Address

To communicate with the TMP275-Q1, the master must first address slave devices through a slave address byte. address is latched to minimize power dissipation associated with detection. Table 2. Address Pins and Slave Addresses for the TMP275-Q1

7.3.4.1 Writing and Reading to the TMP275-Q1

bit low. Every write operation to the TMP275-Q1 requires a value for the Pointer register; see Figure 8. changed by the next write operation. Note that register bytes are sent most-significant byte first, followed by the least significant byte.

7.3.4.2 Slave Mode Operations

The TMP275-Q1 can operate as a slave receiver or slave transmitter.

7.3.4.2.1 Slave Receiver Mode

master can terminate data transfer by generating a START or STOP condition.

7.3.4.2.2 Slave Transmitter Mode

data byte, or by generating a START or STOP condition.

7.3.4.3 SMBus Alert Function

The TMP275-Q1 supports the SMBus alert function. When the TMP275-Q1 is operating in interrupt mode (TM = 1), the ALERT pin of the TMP275-Q1 can be connected as an SMBus alert signal. When a master senses that an Alert condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP275-Q1 is active, the device acknowledges the SMBus Alert command and responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below TLOW caused the Alert condition. This bit is high if the temperature is greater than or equal to THIGH. This bit is low if the temperature is less than TLOW; see Figure 10 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command determines which device clears its Alert status. If the TMP275-Q1 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP275-Q1 loses the arbitration, its ALERT pin remains active.

7.3.4.4 General Call

The TMP275-Q1 responds to a two-wire, general-call address (0000000) if the eighth bit is 0. The device acknowledges the general-call address and responds to commands in the second byte. If the second byte is 00000100, the TMP275-Q1 latches the status of its address pins but does not reset. If the second byte is 00000110, the TMP275-Q1 latches the status of its address pins and resets its internal registers to their power- up values.

7.3.4.5 High-Speed Mode

For the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP1275 device does not acknowledge this byte, but does switch its input filters on SDA and SCL and its output filters on SDA to operate in Hs-mode, thus allowing transfers at up to 2.38 MHz. After the Hs-mode master code is issued, the master transmits a two-wire slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP275-Q1 switches the input and output filter back to fast-mode operation.

7.3.4.6 Time-Out Function

The TMP275-Q1 resets the serial interface if either SCL or SDA is held low for 54 ms (typical) between a START and STOP condition. The TMP275-Q1 releases the bus if it is pulled low and waits for a START condition. To avoid activating the time-out function, a communication speed of at least 1 kHz must be maintained for the SCL operating frequency.

7.3.5 Timing Diagrams

The TMP275-Q1 is two-wire, SMBus, and I2C interface compatible. Figure 7 to Figure 10 describe the various operations on the TMP275-Q1. The following list provides bus definitions. Parameters for Figure 7 are defined in the Timing Requirements table. Bus Idle: Both the SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line, from high to low when the SCL line is high defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge bit on the last byte that is transmitted by the slave.

7.3.5.1 Two-Wire Timing Diagrams

Figure 7. Two-Wire Timing Diagram Figure 8. Two-Wire Timing Diagram for TMP275-Q1 Write Word Format

7.4 Device Functional Modes

7.4.1 Shutdown Mode (SD)

The shutdown mode of the TMP275-Q1 allows the user to save maximum power by shutting down all device circuitry other than the serial interface, thus reducing current consumption to typically less than 0.1 μA. Shutdown mode is enabled when the SD bit is 1; the device shuts down when the current conversion is completed. When SD is equal to 0, the device maintains a continuous conversion state.

7.4.2 Thermostat Mode (TM)

The thermostat mode bit of the TMP275-Q1 indicates to the device whether to operate in comparator mode (TM = 0) or interrupt mode (TM = 1). For more information on comparator and interrupt modes, see the High- and Low-Limit Registers section.

7.4.2.1 Comparator Mode (TM = 0)

In comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in the THIGH register and remains active until the temperature falls below the value in the TLOW register. For more information on the comparator mode, see the High- and Low-Limit Registers section.

7.4.2.2 Interrupt Mode (TM = 1)

In interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds THIGH or goes below the TLOW register. The ALERT pin is cleared when the host controller reads the temperature register. For more information on the interrupt mode, see the High- and Low-Limit Registers section.

7.4.3 One-Shot (OS)

The TMP275-Q1 features a one-shot temperature measurement mode. When the device is in shutdown mode, writing a 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the completion of the single conversion. This feature is useful for reducing power consumption in the TMP275-Q1 when continuous temperature monitoring is not required. When the configuration register is read, OS always reads zero.

7.5 Programming

7.5.1 Pointer Register

Figure 11. Internal Register Structure of the TMP275-Q1 Table 3. Pointer Register Byte (pointer = N/A) [reset = 00h] Table 4. Pointer Addresses of the TMP275-Q1

7.5.2 Temperature Register

reset, the Temperature register reads 0°C until the first conversion is complete. Table 5. Byte 1 of the Temperature Register Table 6. Byte 2 of the Temperature Register

7.5.3 Configuration Register

reset value of the Configuration register is all bits equal to 0. Table 7. Configuration Register Format

1 OS R1 R0 F1 F0 POL TM SD

7.5.4 Polarity (POL)

Figure 12. Output Transfer Function Diagrams

7.5.5 Fault Queue (F1/F0)

7.5.6 Converter Resolution (R1/R0)

identifies the resolution bits and the relationship between resolution and conversion time. Table 9. Resolution of the TMP275-Q1

7.5.7 High- and Low-Limit Registers

or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. device, returning the device to comparator mode (TM = 0). The format of the data for THIGH and TLOW is the same as for the Temperature register. Table 10. Byte 1 the THIGH Register

1 H11 H10 H9 H8 H7 H6 H5 H4

Table 11. Byte 2 of the THIGH Register

2 H3 H2 H1 H0 0 0 0 0

Table 12. Byte 1 the TLOW Register

1 L11 L10 L9 L8 L7 L6 L5 L4

Table 13. Byte 2 of the TLOW Register

2 L3 L2 L1 L0 0 0 0 0

configured for 9-bit resolution.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

of metal causes the leads to provide the primary thermal path.

8.2 Typical Applications

8.2.1 Typical Connections of the TMP275-Q1

Figure 13. Typical Connections of the TMP275-Q1 Schematic

8.2.1.1 Design Requirements

(nearly 0 V) and the I2C bus does not work. A 0.1-μF bypass capacitor is recommended, as shown in Figure 13.

A2) are connected to ground.

8.2.1.2 Detailed Design Procedure

helpful in achieving accurate surface temperature measurement.

8.2.1.3 Application Curve

TMP275-Q1 device was soldered to a two-layer PCB that measured 0.375 inches × 0.437 inches. Figure 14. Temperature Step Response

8.2.2 Connecting Multiple Devices on a Single Bus

low if the temperature is less than TLOW. completion of the SMBus Alert command. If the TMP275-Q1 loses the arbitration, its ALERT pin remains active. Figure 15. Connecting Multiple Devices on a Single Bus

3.0 Volts

8.2.3 Temperature Data Logger for Cold Chain Management Applications

from a CR2032 coin cell battery with a focus on low power to maximize the battery lifetime. application, see Ultralow Power Multi-sensor Data Logger with NFC Interface Reference Design, TIDU821. Figure 16. Temperature Data Logger

9 Power Supply Recommendations

power supplies can require additional decoupling capacitors to reject power-supply noise.

10 Layout

10.1 Layout Guidelines

Bypass the V+ pin to ground with a low-ESR ceramic bypass-capacitor. The typical recommended bypass capacitance is a 0.1-μF ceramic capacitor with a X5R or X7R dielectric. The optimum placement is closest to the V+ and GND pins of the device. Take care in minimizing the loop area formed by the bypass-capacitor connection, the V+ pin, and the GND pin of the device. Additional bypass capacitance can be added to compensate for noisy or high-impedance power supplies.
Pull up the open-drain output pins SDA, SCL, and ALERT through 5-kΩ pullup resistors.

10.2 Layout Example

Figure 17. TMP275-Q1 Layout Example

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

LM75 Data Sheet, SNOS808
TMP75, TMP175 Data Sheet, SBOS288
TMP75B Data Sheet, SBOS706
Ultralow Power Multi-sensor Data Logger with NFC Interface Reference Design, TIDU821

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. SMBus is a trademark of Intel Corporation. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 11-Jan-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMP275AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 275Q TMP275AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T275Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 11-Jan-2016 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMP275-Q1 :

Catalog: TMP275 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

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Product Information

TMP275AQDGKRQ1 specifications and overview.

Summary

Automotive Grade Temperature Sensor

Description

Automotive Grade Temperature Sensor

Source title TMP275AQDGKRQ1 Datasheet(PDF) - Texas Instruments

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