TMP275AIDGKR

TMP275 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 35

Technical content

T em p . Sen so r ΔΣ A/D Co nverter OSC Con tro l Logic Serial Interface Conf ig . and T emp. Register T emperature ALER T SDA 1 5GND SCL 2 7 A0 SCL ALERT GND 0.01 µF Two-Wire Host Controller TMP275 2.7V to 5.5V SDA Pullup Resistors Supply Bypass Capacitor Supply Voltage 5 k Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMP275 SBOS363F –JUNE 2006–REVISED MAY 2018 TMP275±0.5°CTemperatureSensorWithI2CandSMBusInterfaceinIndustryStandard LM75FormFactorandPinout

1 Features

1• High Accuracy: – ±0.5°C (Maximum) From −20°C to 100°C – ±1°C (Maximum) From −40°C to 125°C

• Low Quiescent Current: – 50 μA (Typical) – 0.1-μA Standby
• Resolution: 9 to 12 Bits, User-Selectable
• Digital Output: SMBus™ , Two-Wire, and I2C Interface Compatibility
• 8 I2C/SMBus Addresses
• Wide Supply Range: 2.7 V to 5.5 V
• Small VSSOP-8 and SOIC-8 Packages
• No Specified Power-up Sequence Required; Two- Wire Bus Pullups May Be Enabled Before V+

2 Applications

• Power-Supply Temperature Monitoring
• Computer Peripheral Thermal Protection
• Battery Management
• Office Machines
• Servers
• Thermostat Controls
• Environmental Monitoring and HVAC
• Electromechanical Device Temperature
• Data Logger

3 Description

The TMP275 is a ±0.5°C accurate integrated digital temperature sensor with a 12-bit analog-to-digital converter (ADC) that can operate as low as 2.7-V supply voltage and is pin- and register-compatible with the Texas Instruments LM75, TMP75, TMP75B, and TMP175 devices. This device is available in SOIC-8 and VSSOP-8 packages, and it requires no external components to sense the temperature. The TMP275 is capable of reading temperatures with a maximum resolution of 0.0625°C (12 bits) and as low as 0.5°C (9 bits), which allows the user to maximize efficiency by programming for higher resolution or faster conversion time. The device is specified over a temperature range of –40°C to 125°C. The TMP275 device features SMBus and two-wire interface compatibility, and allows up to eight devices on the same bus with the SMBus overtemperature alert function. The factory-calibrated temperature accuracy and the noise-immune digital interface make the TMP275 the preferred solution for temperature compensation of other sensors and electronic components, without the need for additional system-level calibration or elaborate board layout for distributed temperature sensing. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMP275 SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Simplified Schematic Internal Block Diagram

SBOS363F –JUNE 2006–REVISED MAY 2018 www.ti.com Product Folder Links: TMP275 Submit Documentation Feedback Copyright © 2006–2018, Texas Instruments Incorporated Table of Contents

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (November 2015) to Revision F Page Changes from Revision D (August 2007) to Revision E Page

• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

www.ti.com SBOS363F –JUNE 2006–REVISED MAY 2018 Product Folder Links: TMP275 Submit Documentation FeedbackCopyright © 2006–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

8-Pin SOIC and 8-Pin VSSOP Top View Pin Functions PIN I/O DESCRIPTION NO. NAME 1 SDA I/O Serail data. Open-drain output; requires a pullup resistor. 2 SCL I Serial clock. Open-drain output; requires a pullpup resistor. 3 ALERT O Overtemperature alert. Open-drain output; requires a pullup resistor.

4 GND — Ground

5 A2 I Address select. Connect to GND or V+. 6 A1 I Address select. Connect to GND or V+. 7 A0 I Address select. Connect to GND or V+. 8 V+ I Supply voltage, 2.7 to 5.5 V

SBOS363F –JUNE 2006–REVISED MAY 2018 www.ti.com Product Folder Links: TMP275 Submit Documentation Feedback Copyright © 2006–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Power supply, V+ 7 V Input voltage(2) –0.5 7 V Input current 10 mA Operating temperature –55 127 °C Junction temperature, TJ max, 150 °C Storage temperature, Tstg –60 130 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 Machine Model (MM) ±300

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage 2.7 5.5 V Operating free-air temperature, TA –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TMP275 UNITD (SOIC) AND DGK (VSSOP)

8 PINS

RθJA Junction-to-ambient thermal resistance 120 °C/W RθJC(top) Junction-to-case (top) thermal resistance 66.7 °C/W RθJB Junction-to-board thermal resistance 60.4 °C/W ψJT Junction-to-top characterization parameter 17.8 °C/W ψJB Junction-to-board characterization parameter 59.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

www.ti.com SBOS363F –JUNE 2006–REVISED MAY 2018 Product Folder Links: TMP275 Submit Documentation FeedbackCopyright © 2006–2018, Texas Instruments Incorporated (1) Specified for 12-bit resolution. (2) Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions. (3) One-shot mode setup, 1 sample per minute for 24 hours. (4) Long-term drift is determined using accelerated operational life testing at a junction temperature of 150°C.

6.5 Electrical Characteristics

at TA = −40°C to +125°C, and V+ = 2.7 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE INPUT Range –40 125 °C Accuracy (Temperature Error) 0°C to 100°C, V+ = 3 V to 3.6 V ±0.0625 ±0.75 °C –40°C to 125°C, V+ = 3 V to 3.6 V ±0.0625 ±1 °C 25°C to 100°C, V+ = 3.3 V to 5.5 V 0.2 ±1.5 °C Resolution(1) Selectable 0.0625 °C Repeatability(2) 25°C, V+= 3.3 V(3) ±0.0625 °C Long-term drift (4) 500 hours at 150°C ±0.0625 °C DIGITAL INPUT/OUTPUT Input Capacitance 3 pF Input logic level, HIGH, VIH 0.7(V+) 6 V Input logic level, LOW, VIL −0.5 0.3(V+) V Leakage Input Current, IIN 0 V ≤ VIN ≤ 6 V 1 µA Input Voltage Hysteresis SCL and SDA pins 500 mV SDA Output logic level, LOW, VOL IOL = 3 mA 0 0.15 0.4 V ALERT Output logic level, HIGH, VOL IOL = 4 mA 0 0.15 0.4 V Resolution Selectable 9 to 12 Bits Coversion Time 9-Bit 27.5 37.5 ms 10-Bit 55 75 ms 11-Bit 110 150 ms 12-Bit 220 300 ms Time-out time 25 54 74 ms POWER SUPPLY Operating range 2.7 5.5 V Quiescent Current, IQ Serial bus inactive 50 85 µA Serial bus active, SCL freq = 400 kHz 100 µA Serial bus active, SCL freq = 3.4 MHz 410 µA Shutdown Current, ISD Serial bus inactive 0.1 3 µA Serial bus active, SCL freq = 400 kHz 60 µA Serial bus active, SCL freq = 3.4 MHz 380 µA TEMPERATURE RANGE Specified Range –40 125 °C Operating Range –55 127 °C

SBOS363F –JUNE 2006–REVISED MAY 2018 www.ti.com Product Folder Links: TMP275 Submit Documentation Feedback Copyright © 2006–2018, Texas Instruments Incorporated (1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and not production tested.

6.6 Timing Requirements

See the Timing Diagrams section for timing diagrams.(1) FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.38 MHz t(BUF) Bus-free time between STOP and START condition See Timing Diagrams 1300 160 ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns t(SUSTA) Repeated start condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time 4 900 4 120 ns t(SUDAT) Data setup time 100 10 ns t(LOW) SCL-clock low period V+ , see Timing Diagrams 1300 280 ns t(HIGH) SCL-clock high period See Timing Diagrams 600 60 ns tFD Data fall time See Timing Diagrams 300 150 ns tRC Clock rise time See Timing Diagrams 300 40 ns SCLK ≤ 100 kHz, See Timing Diagrams 1000 ns tFC Clock fall time See Timing Diagrams 300 40 ns

6.7 Typical Characteristics

Figure 1. Quiescent Current vs Temperature Figure 2. Shutdown Current vs Temperature Figure 3. Conversion Time vs Temperature Figure 4. Temperature Error vs Temperature Figure 5. Quiescent Current with Bus Activity Figure 6. Temperature Error at 25°C

7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Digital Temperature Output

Table 1. Temperature Data Format

7.3.2 Serial Interface

The TMP275 operates only as slave devices on the SMBus, Two-Wire, and I2C interface-compatible bus. integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. modes. All data bytes are transmitted MSB first.

7.3.3 Bus Overview

generates the START and STOP conditions. responds to the master by generating an Acknowledge and pulling SDA LOW. interpreted as a control signal.

7.3.4 Serial Bus Address

To communicate with the TMP275, the master must first address slave devices through a slave address byte. to minimize power dissipation associated with detection. Table 2. Address Pins and Slave Addresses for the TMP275

7.3.4.1 Writing and Reading to the TMP275

bit LOW. Every write operation to the TMP275 requires a value for the Pointer Register (see Figure 8).

SBOS363F –JUNE 2006–REVISED MAY 2018 www.ti.com Product Folder Links: TMP275 Submit Documentation Feedback Copyright © 2006–2018, Texas Instruments Incorporated When reading from the TMP275, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer Register. This is accomplished by issuing a slave address byte with the R/W bit LOW, followed by the Pointer Register Byte. No additional data is required. The master can then generate a START condition and send the slave address byte with the R/W bit HIGH to initiate the read command. See Figure 9 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually send the Pointer Register bytes, as the TMP275 remembers the Pointer Register value until it is changed by the next write operation. Note that register bytes are sent most-significant byte first, followed by the least significant byte.

7.3.4.2 Slave Mode Operations

The TMP275 can operate as a slave receiver or slave transmitter.

7.3.4.2.1 Slave Receiver Mode

The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP275 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP275 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer Register. The TMP275 acknowledges reception of each data byte. The master may terminate data transfer by generating a START or STOP condition.

7.3.4.2.2 Slave Transmitter Mode

The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition.

7.3.4.3 SMBus Alert Function

The TMP275 supports the SMBus Alert function. When the TMP275 is operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP275 may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP275 is active, the device acknowledges the SMBus Alert command and responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below TLOW caused the ALERT condition. This bit will be HIGH if the temperature is greater than or equal to THIGH. This bit will be LOW if the temperature is less than TLOW. Refer to Figure 10 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command determines which device clears its ALERT status. If the TMP275 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP275 loses the arbitration, its ALERT pin remains active.

7.3.4.4 General Call

The TMP275 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device acknowledges the General Call address and responds to commands in the second byte. If the second byte is 00000100, the TMP275 latches the status of their address pins, but will not reset. If the second byte is 00000110, the TMP275 latches the status of their address pins and reset their internal registers to their power-up values.

7.3.4.5 High-Speed Mode

master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. code has been issued, the master will transmit a Two-Wire slave address to initiate a data transfer operation. condition, the TMP275 switches the input and output filter back to fast-mode operation.

7.3.4.6 Time-Out Function

7.3.5 Timing Diagrams

Bus Idle: Both SDA and SCL lines remain HIGH. defines a START condition. Each data transfer is initiated with a START condition. defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. is determined by the master device. The receiver acknowledges the transfer of data. a Not-Acknowledge on the last byte that has been transmitted by the slave.

7.3.6 Two-Wire Timing Diagrams

Figure 7. Two-Wire Timing Diagram

Figure 8. Two-Wire Timing Diagram for TMP275 Write Word Format

SBOS363F –JUNE 2006–REVISED MAY 2018 www.ti.com Product Folder Links: TMP275 Submit Documentation Feedback Copyright © 2006–2018, Texas Instruments Incorporated

7.4 Device Functional Modes

7.4.1 Shutdown Mode (SD)

The Shutdown Mode of the TMP275 allows the user to save maximum power by shutting down all device circuitry other than the serial interface, which reduces current consumption to typically less than 0.1 μA. Shutdown Mode is enabled when the SD bit is 1; the device will shut down once the current conversion is completed. When SD is equal to 0, the device maintains a continuous conversion state.

7.4.2 Thermostat Mode (TM)

The Thermostat Mode bit of the TMP275 indicates to the device whether to operate in Comparator Mode (TM = 0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the High and Low Limit Registers section.

7.4.2.1 Comparator Mode (TM = 0)

In Comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in the T(HIGH) register and it remains active until the temperature falls below the value in the T(LOW) register. For more information on the comparator mode, see the High and Low Limit Registers section.

7.4.2.2 Interrupt Mode (TM = 1)

In Interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds T(HIGH) or goes below T(LOW) registers. The ALERT pin is cleared when the host controller reads the temperature register. For more information on the interrupt mode, see the High and Low Limit Registers section.

7.4.3 One-Shot (OS)

The TMP275 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode, writing a ‘1’to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the completion of the single conversion. This mode is useful for reducing power consumption in the TMP275 when continuous temperature monitoring is not required. When the configuration register is read, the OS always reads zero.

7.5 Programming

7.5.1 Pointer Register

describes the pointer address of the registers available in the TMP275. Power-up reset value of P1/P0 is 00. Figure 11. Internal Register Structure of the TMP275

7.5.1.1 Pointer Register Byte (offset = N/A) [reset = 00h]

Figure 12. Pointer Register Byte

7.5.1.2 Pointer Addresses of the TMP275

Table 3. Pointer Addresses of the TMP275 Field Description

7.5.2 Temperature Register

the Temperature Register reads 0°C until the first conversion is complete.

Figure 13. Byte 1 of Temperature Register Figure 14. Byte 2 of Temperature Register

7.5.3 Configuration Register

the Configuration Register is all bits equal to 0. Table 4. Configuration Register Format

1 OS R1 R0 F1 F0 POL TM SD

7.5.4 Shutdown Mode (SD)

circuitry other than the serial interface, which reduces current consumption to typically less than 0.1 μA. completed. When SD is equal to 0, the device maintains a continuous conversion state.

7.5.5 Thermostat Mode (TM)

7.5.6 Polarity (POL)

Figure 15. Output Transfer Function Diagrams

7.5.7 Fault Queue (F1/F0)

environmental noise. The fault queue requires consecutive fault measurements to trigger the alert function. device. For THIGH and TLOW register format and byte order, see the section High and Low Limit Registers. Table 5. Fault Settings

7.5.8 Converter Resolution (R1/R0)

identifies the Resolution Bits and the relationship between resolution and conversion time. Table 6. Resolution of the TMP275

7.5.9 One-Shot (OS)

7.5.10 High and Low Limit Registers

device, returning the device to Comparator Mode (TM = 0). The format of the data for THIGH and TLOW is the same as for the Temperature Register. Table 7. Byte 1 THIGH Register

1 H11 H10 H9 H8 H7 H6 H5 H4

Table 8. Byte 2 of THIGH Register

2 H3 H2 H1 H0 0 0 0 0

Table 9. Byte 1 TLOW Register

1 L11 L10 L9 L8 L7 L6 L5 L4

Table 10. Byte 2 of TLOW Register

2 L3 L2 L1 L0 0 0 0 0

configured for 9-bit resolution.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.2 Typical Applications

8.2.1 Typical Connections of the TMP275

Figure 16. Typical Connections of the TMP275 Schematic

8.2.1.1 Design Requirements

ALERT lines can be pulled up to a supply that is equal to or higher than V+ through the pullup resistors. A1, A2) are connected to ground.

8.2.1.2 Detailed Design Procedure

adhesive is helpful in achieving accurate surface temperature measurement.

8.2.1.3 Application Curve

test, the TMP275 device was soldered to a two-layer PCB that measured 0.375 inches × 0.437 inches. Figure 17. Temperature Step Response

8.2.2 Connecting Multiple Devices on a Single Bus

SMBus Alert signal. Figure 18 shows eight TMP275 devices connected to a MCU (master) using one single bus. will be LOW if the temperature is less than TLOW. completion of the SMBus Alert command. If the TMP275 loses the arbitration, its ALERT pin remains active.

Figure 18. Connecting Multiple Devices on a Single Bus

3.0 Volts

8.2.3 Temperature Data Logger for Cold Chain Management Applications

battery with a focus on low power to maximize the battery lifetime. application, see Ultralow Power Multi-Sensor Data Logger with NFC Interface Reference Design (TIDU821). Figure 19. Temperature Data Logger

9 Power Supply Recommendations

supplies may require additional decoupling capacitors to reject power-supply noise.

10 Layout

10.1 Layout Guidelines

• Bypass the VS pin to ground with a low-ESR ceramic bypass-capacitor. The typical recommended bypass capacitance is a 0.1-μF ceramic capacitor with a X5R or X7R dielectric. The optimum placement is closest to the VS and GND pins of the device. Take care in minimizing the loop area formed by the bypass-capacitor connection, the VS pin, and the GND pin of the IC. Additional bypass capacitance can be added to compensate for noisy or high-impedance power supplies.
• Pull up the open-drain output pins SDA , SCL and ALERT through 5-kΩ pullup resistors.

10.2 Layout Example

Figure 20. TMP275 Layout Example

SBOS363F –JUNE 2006–REVISED MAY 2018 www.ti.com Product Folder Links: TMP275 Submit Documentation Feedback Copyright © 2006–2018, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• Ultralow Power Multi-sensor Data Logger with NFC Interface Reference Design (TIDU821)
• Understanding the I2C Bus (SLVA704)

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. SMBus is a trademark of Intel Corporation. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TMP275AID Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 125 TMP275 TMP275AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T275 TMP275AIDGKR.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T275 TMP275AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275 TMP275AIDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275 TMP275AIDR1G4.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 23-May-2025 OTHER QUALIFIED VERSIONS OF TMP275 :

• Automotive : TMP275-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP275AIDGKR VSSOP DGK 8 2500 367.0 367.0 38.0 TMP275AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 TMP275AIDR SOIC D 8 2500 356.0 356.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated