TMP105 TI | Alldatasheet
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YZC LEAD-□FREE 2□X□3□ARRA Y (TOP□VIEW) Note:□Pin□A1□is□marked□with□a for□Pb-free□(YZC)0 1,65□mm 1,50□mm 1,15□mm 1,00□mm (Bump□Side□Down) Diode T emp. Sensor /c68/c83 A/D Converter OSC Control Logic Serial Interface Config. and□T emp. Register TMP105 T emperature SDA A1 GND SCL B1 B2 ALERT TMP105 www.ti.com SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 DigitalTemperatureSensor withTwo-WireInterface Check forSamples: TMP105 1FEATURES
DESCRIPTION
23• SUPPORTS 1.8VI2C ™ BUS The TMP105 isa two-wire,serialoutputtemperature• TWO ADDRESSES sensoravailableina WCSP package.Requiringno
- DIGITAL OUTPUT: Two-Wire SerialInterface externalcomponents, the TMP105 is capable of readingtemperatureswitha resolutionof0.0625°C.• RESOLUTION: 9-to12-Bits,User-Selectable
- ACCURACY: The TMP105 featuresa Two-Wire interfacethatis SMBus-compatible,withthe TMP105 allowingup to– ±2.0°C (max) from –25°C to+85°C two deviceson one bus. The TMP105 featuresan– ±3.0°C (max) from –40°C to+125°C SMBus Alertfunction.
- LOW QUIESCENT CURRENT: The TMP105 is ideal for extended temperature50μA, 1.5μA Standby measurement in a variety of communication,• NO POWER-UP SEQUENCE REQUIRED, I2C computer,consumer, environmental,industrial,andPULLUPS CAN BE ENABLED PRIOR TO V+ instrumentationapplications. The TMP105 is specifiedfor operationover aAPPLICATIONS temperaturerangeof–40°C to+125°C.
- CELL PHONES
- COMPUTER PERIPHERAL THERMAL PROTECTION
- NOTEBOOK COMPUTERS
- BATTERY MANAGEMENT
- THERMOSTAT CONTROLS
- ENVIRONMENTAL MONITORING AND HVAC Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2I2C isa trademarkofNXP Semiconductors. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
WCSP-6□PACKAGE (TOP□VIEW) Note:□Pin□1□is□determined□by□orienting□the□package□marking□as□indicated□in□the□diagram. (Bump□Side□Down) TMP105 SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. ORDERING INFORMATION (1) PACKAGE PART NUMBER SYMBOL Wafer chip-scalepackage (YZC) TMP105YZC EY (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee the productfolderatwww.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Power Supply,V+ 7.0V InputVoltage(2) –0.5Vto7.0V InputCurrent 10mA OperatingTemperatureRange –55°C to+127°C StorageTemperatureRange –60°C to+130°C JunctionTemperature(TJ max) +150°C ESD Rating: Human Body Model (HBM) (3) 2000V Charged-DeviceModel (CDM) (4) 500V Machine Model (MM) (5) 200V (1) Stressesabove theseratingsmay cause permanentdamage. Exposuretoabsolutemaximum conditionsforextendedperiodsmay degradedevicereliability.These arestressratingsonly,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thosespecifiedisnotimplied. (2) InputvoltageratingappliestoallTMP105 inputvoltages. (3) HBM testinghas been testedtoTIspecificationsJEDEC JESD22-A114C.01. (4) CDM testinghas been testedtoTIspecificationsJEDEC EIA/JESD22-A115A. (5) MM testinghas been testedtoTIspecificationsJEDEC JESD22-C101C. PIN ASSIGNMENTS
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ELECTRICAL CHARACTERISTICS
AtTA = –40°C to+125°C, and V+ = 2.6Vto3.3V,unlessotherwisenoted. TMP105 PARAMETER CONDITION UNIT MIN TYP MAX TEMPERATURE INPUT Range –40 +125 °C Accuracy(TemperatureError) –25°C to+85°C ±0.5 ±2.0 °C vs Supply 0.2 ±0.5 °C/V Resolution(1) Selectable 0.0625 °C DIGITAL INPUT/OUTPUT (SCL,SDA, ALERT) InputCapacitance 3 pF InputLogicLevels: VIH 1.2 6.0 V VIL –0.5 0.6 V Leakage InputCurrent,IIN 0V ≤ VIN ≤ 6V 1 μA InputVoltageHysteresis SCL and SDA Pins 100 mV OutputLogicLevels: VOL SDA IOL = 3mA 0 0.15 0.4 V VOL ALERT IOL = 4mA 0 0.15 0.4 V Resolution Selectable 9 to12 Bits ConversionTime 9-Bit 27.5 37.5 ms 10-Bit 55 75 ms 11-Bit 110 150 ms 12-Bit 220 300 ms TimeoutTime 25 54 74 ms DIGITAL INPUT (A0) InputCapacitance 3 pF InputLogicLevels: VIH 0.7x (V+) (V+)+ 0.5 V VIL –0.5 0.3x (V+) V Leakage InputCurrent,IIN 0V ≤ VIN ≤ V+ 1 μA POWER SUPPLY OperatingRange 2.6 3.3 V QuiescentCurrent IQ SerialBus Inactive 50 85 μA SerialBus Active,SCL Freq= 400kHz 100 μA Shutdown Current ISD SerialBus Inactive 1.5 3 μA SerialBus Active,SCL Freq= 400kHz 60 μA TEMPERATURE RANGE SpecifiedRange –40 +125 °C OperatingRange –55 +127 °C ThermalResistance θJA 240 °C/W (1) Specifiedfor12-bitresolution. Copyright© 2005–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TMP105
T emperature□( C)/c176 I ( A) /c109 Q /c45 50 /c45 25 0 100 25 50 75 100 125 V+□=□2.6V T emperature□( C)/c176 Shutdown□Current□( A) /c109 /c45 50 /c45 25 0 3.0 2.5 2.0 1.5 1.0 0.5 25 50 75 100 125 V+□=□2.6V V+□=□3.3V T emperature□( C)/c176 Conversion□Time□(ms) /c45 50 /c45 25 0 225 220 215 210 205 200 25 50 75 100 125 12-Bit□Resolution V+□=□2.6V V+□=□3.3V Temperature Error (°C) 3 typical units 12-bit resolution Temperature (°C) /c4555 /c4535 /c4515 5 25 45 65 85 105 125 V+ = 3.0V V+ = 2.7V 2.0 1.5 1.0 0.5 0.5 1.0 1.5 2.0 /c45 /c45 /c45 /c45 500 450 400 350 300 250 200 150 100 Frequency□(Hz) 1k 10k 100k 1M 10M I ( A) /c109 Q +125 C/c176 +25 C/c176 /c45 55 C/c176 TMP105 SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS AtTA = +25°C and V+ = 2.8V,unlessotherwisenoted. QUIESCENT CURRENT SHUTDOWN CURRENT vs vs TEMPERATURE TEMPERATURE CONVERSION TIME TEMPERATURE ACCURACY vs vs TEMPERATURE TEMPERATURE QUIESCENT CURRENT WITH BUS ACTIVITY vs TEMPERATURE
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0.1 F/c109
(Output) C2 A0B1 SCL SDA T o T wo-Wire Controller I/O Control Interface SCL SDA T emperature Register Configuration Register TLOW Register THIGH Register Pointer Register TMP105 www.ti.com SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 APPLICATIONS INFORMATION The TMP105 isa digitaltemperaturesensor thatisoptimalforthermalmanagement and thermalprotection applications.The TMP105 isTwo-Wire and SMBus interface-compatible,and isspecifiedover a temperature rangeof–40°C to+125°C. The TMP105 requiresno externalcomponents foroperationexceptforpull-upresistorson SCL, SDA, and ALERT, althougha 0.1μF bypass capacitorisrecommended, as shown inFigure1.SCL, SDA and ALERT can be tiedtoa 1.8VsupplyorV+ throughpull-upresistors.A0 shouldbe tiedtoV+ orGND. Note: SCL, SDA, and ALERT pinsrequirepull-upresistors. Figure1. TypicalConnections oftheTMP105 The sensingdeviceoftheTMP105 isthechipitself.Thermal pathsrun throughthepackage leads.The lower thermalresistanceofmetalcausestheleadstoprovidetheprimarythermalpath. To maintainaccuracyinapplicationsrequiringairorsurfacetemperaturemeasurement,careshouldbe takento isolatethepackage and leadsfromambientairtemperature. POINTER REGISTER Figure2 shows theinternalregisterstructureoftheTMP105. The 8-bitPointerRegisterofthedevicesisused to addressa givendata register.The PointerRegisteruses the two LSBs to identifywhich of the data registers shouldrespond to a read or writecommand. Table 1 identifiesthe bitsof the PointerRegisterbyte.Table 2 describesthepointeraddressoftheregistersavailableintheTMP105. Power-upresetvalueofP1/P0 is00. Figure2. InternalRegisterStructureoftheTMP105 Copyright© 2005–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TMP105
SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 www.ti.com Table1.PointerRegisterByte P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 0 0 RegisterBits Table2.PointerAddresses oftheTMP105 P1 P0 REGISTER 0 0 TemperatureRegister(Read Only) 0 1 ConfigurationRegister(Read/Write) 1 0 TLOW Register(Read/Write) 1 1 THIGH Register(Read/Write) TEMPERATURE REGISTER The TemperatureRegisteroftheTMP105 isa 12-bit,read-onlyregisterthatstorestheoutputofthemost recent conversion.Two bytesmust be readtoobtaindata,and aredescribedinTable3 and Table4.Note thatbyte1 is the most significantbyte;byte2 isthe leastsignificantbyte(sentinthisorder).The first12 bitsare used to indicatetemperature,withallremainingbitsequaltozero.The leastsignificantbytedoes nothave tobe readif thatinformationisnot needed. Data formatfortemperatureissummarized inTable 5. Followingpower-up or reset,theTemperatureRegisterwillread0°C untilthefirstconversioniscomplete. Table3.Byte 1 ofTemperature Register D7 D6 D5 D4 D3 D2 D1 D0 T11 T10 T9 T8 T7 T6 T5 T4 Table4.Byte 2 ofTemperature Register D7 D6 D5 D4 D3 D2 D1 D0 T3 T2 T1 T0 0 0 0 0 Table5.Temperature Data Format TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX 128 0111 1111 1111 7FF 127.9375 0111 1111 1111 7FF 100 0110 0100 0000 640 80 0101 0000 0000 500 75 0100 1011 0000 4B0 50 0011 0010 0000 320 25 0001 1001 0000 190 0.25 0000 0000 0100 004 0 0000 0000 0000 000 –0.25 1111 1111 1100 FFC –25 1110 0111 0000 E70 –55 1100 1001 0000 C90 The usercan obtain9,10,11,or 12 bitsofresolutionby addressingtheConfigurationRegisterand settingthe resolutionbitsaccordingly.For 9-,10-,or11-bitresolution,themost significantbitsintheTemperatureRegister areused withtheunused LSBs settozero.
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TMP105 ALERT□PIN (Comparator□Mode) POL□=□0 TMP105 ALERT□PIN (Interrupt□Mode) POL□=□0 TMP105 ALERT□PIN (Comparator□Mode) POL□=□1 TMP105 ALERT□PIN (Interrupt□Mode) POL□=□1 Read Read Time Read TMP105 www.ti.com SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 CONFIGURATION REGISTER The ConfigurationRegisterisan 8-bitread/writeregisterused tostorebitsthatcontroltheoperationalmodes of thetemperaturesensor.Read/writeoperationsareperformedMSB first.The formatoftheConfigurationregister fortheTMP105 isshown inTable6,followedby a breakdown oftheregisterbits.The power-up/resetvalueof theConfigurationRegisterisallbitsequalto0. Table6.ConfigurationRegisterFormat BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 OS R1 R0 F1 F0 POL TM SD
SHUTDOWN MODE (SD) The Shutdown Mode of the TMP105 allowsthe user to save maximum power by shuttingdown alldevice circuitryotherthantheserialinterface,whichreducescurrentconsumptiontotypically1.5μA. Shutdown Mode is enabledwhen theSD bitis1;thedevicewillshutdown once thecurrentconversioniscompleted.When SD is equalto0,thedevicewillmaintaina continuousconversionstate. THERMOSTAT MODE (TM) The ThermostatMode bitoftheTMP105 indicatestothedevicewhethertooperateinComparatorMode (TM = 0)orInterruptMode (TM = 1).For more informationon comparatorand interruptmodes, see theHigh and Low LimitRegisterssection. POLARITY (POL) The PolarityBitoftheTMP105 allowstheusertoadjustthepolarityoftheALERT pinoutput.IfPOL = 0,the ALERT pinwillbe activeLOW, as shown inFigure3.For POL = 1,theALERT pinwillbe activeHIGH, and the stateoftheALERT pinisinverted. Figure3. Output TransferFunctionDiagrams Copyright© 2005–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TMP105
SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 www.ti.com FAULT QUEUE (F1/F0) A faultconditionisdefinedas when themeasured temperatureexceeds theuser-definedlimitssetintheTHIGH and TLOW Registers.Additionally,the number of faultconditionsrequiredto generate an alertmay be programmed using the faultqueue. The faultqueue is providedto preventa falsealertas a resultof environmentalnoise.The faultqueue requiresconsecutivefaultmeasurements in orderto triggerthe alert function.Table7 definesthenumber ofmeasured faultsthatmay be programmed totriggeran alertconditionin thedevice.ForTHIGH and TLOW registerformatand byteorder,see theHighand Low LimitRegisterssection. Table7.FaultSettingsoftheTMP105 F1 F0 CONSECUTIVE FAULTS 0 0 1 0 1 2 1 0 4 1 1 6 CONVERTER RESOLUTION (R1/R0) The ConverterResolutionbitscontroltheresolutionoftheinternalanalog-to-digital(A/D)converter.Thiscontrol allowstheusertomaximize efficiencyby programming forhigherresolutionor fasterconversiontime.Table8 identifiestheresolutionbitsand therelationshipbetween resolutionand conversiontime. Table8.ResolutionoftheTMP105 CONVERSION TIMER1 R0 RESOLUTION (typical) 0 0 9 Bits(0.5°C) 27.5ms 0 1 10 Bits(0.25°C) 55ms 1 0 11 Bits(0.125°C) 110ms 1 1 12 Bits(0.0625°C) 220ms ONE-SHOT (OS) The TMP105 featuresa One-Shot TemperatureMeasurement Mode. When the deviceisinShutdown Mode, writinga ‘1’ totheOS bitstartsa singletemperatureconversion.The devicewillreturntotheshutdown stateat thecompletionofthesingleconversion.Thisoptionisusefultoreducepower consumptionintheTMP105 when continuoustemperaturemonitoringisnot required.When the ConfigurationRegisterisread,the OS always readszero. HIGH AND LOW LIMITREGISTERS InComparatorMode (TM = 0),theALERT pinoftheTMP105 becomes activewhen thetemperatureequalsor exceeds thevalueinTHIGH and generatesa consecutivenumber offaultsaccordingtofaultbitsF1 and F0.The ALERT pinremainsactiveuntilthe temperaturefallsbelow the indicatedTLOW valueforthe same number of faults. InInterruptMode (TM = 1),theALERT pinbecomes activewhen thetemperatureequalsorexceeds THIGH fora consecutivenumber of faultconditions.The ALERT pinremainsactiveuntila read operationof any register occurs,oruntilthedevicesuccessfullyrespondstotheSMBus AlertResponse address.The ALERT pinclearsif thedeviceisplacedinShutdown Mode. Once theALERT piniscleared,itwillonlybecome activeagainby the temperaturefallingbelow TLOW . When the temperaturefallsbelow TLOW , the ALERT pinbecomes activeand remainsactiveuntilclearedby a read operationof any registeror a successfulresponseto the SMBus Alert Response address.When the ALERT pinclears,the above cyclewillrepeat,withthe ALERT pinbecoming activewhen the temperatureequalsor exceeds THIGH . The ALERT pincan alsobe clearedby resettingthe devicewiththe GeneralCallReset command. Thisresetalsoclearsthe stateof the internalregistersinthe devicereturningthedevicetoComparatorMode (TM = 0).
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www.ti.com SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 Both operationalmodes arerepresentedinFigure3.Table9 and Table10 describetheformatfortheTHIGH and TLOW Registers.Note thatthemost significantbyteissentfirst,followedby theleastsignificantbyte.Power-up resetvaluesforTHIGH and TLOW are: THIGH = 80°C and TLOW = 75°C The formatofthedataforTHIGH and TLOW isthesame as fortheTemperatureRegister. Table9.Bytes 1 and 2 ofTHIGH Register BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 H11 H10 H9 H8 H7 H6 H5 H4
BYTE D7 D6 D5 D4 D3 D2 D1 D0
2 H3 H2 H1 H0 0 0 0 0
Table10.Bytes 1 and 2 ofTLOW Register BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 L11 L10 L9 L8 L7 L6 L5 L4
BYTE D7 D6 D5 D4 D3 D2 D1 D0
2 L3 L2 L1 L0 0 0 0 0
All12 bitsfortheTemperature,THIGH ,and TLOW Registersareused inthecomparisonsfortheALERT function forallconverterresolutions.The threeLSBs inTHIGH and TLOW can affecttheALERT outputeven iftheconverter isconfiguredfor9-bitresolution. SERIAL INTERFACE The TMP105 operatesonlyas a slavedeviceon the Two-Wire bus and SMBus. Connectionsto the bus are made viatheopen-drainI/OlinesSDA and SCL. The SDA and SCL pinsfeatureintegratedspikesuppression filtersand Schmitttriggersto minimizethe effectsof inputspikesand bus noise.The TMP105 supportsthe transmissionprotocolforfast(1kHzto400kHz)mode. AlldatabytesaretransmittedMSB first. SERIAL BUS ADDRESS To communicate withtheTMP105, themastermust firstaddressslavedevicesviaa slaveaddressbyte.The slaveaddressbyteconsistsofseven addressbits,and a directionbitindicatingtheintentofexecutinga reador writeoperation. The TMP105 featuresone addresspinallowingup totwo devicestobe connectedperbus.Pinlogiclevelsare describedin Table 11. The address pin of the TMP105 isread afterreset,at startof communication,or in responsetoa Two-Wireaddressacquirerequest.Followingreadingofthestateofthepin,theaddressislatched tominimizepower dissipationassociatedwithdetection. Table11.Address Pin and SlaveAddresses forthe TMP105 A0 SLAVE ADDRESS 0 1001000 1 1001001 Copyright© 2005–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TMP105
SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 www.ti.com BUS OVERVIEW The devicethatinitiatesthetransferiscalleda master,and thedevicescontrolledby themasterareslaves.The bus must be controlledby a masterdevicethatgeneratestheserialclock(SCL),controlsthebus access,and generatestheSTART and STOP conditions. To addressa specificdevice,a START conditionisinitiated,indicatedby pullingthe data-line(SDA) from a HIGH toLOW logiclevelwhileSCL isHIGH. Allslaveson thebus shiftintheslaveaddressbyte,withthelastbit indicatingwhethera readorwriteoperationisintended.Duringtheninthclockpulse,theslavebeingaddressed respondstothemasterby generatingan Acknowledgeand pullingSDA LOW. Data transferisthen initiatedand sentover eightclockpulsesfollowedby an Acknowledge Bit.Duringdata transferSDA must remain stablewhileSCL is HIGH, as any change in SDA whileSCL is HIGH willbe interpretedas a controlsignal. Once alldatahas been transferred,themastergeneratesa STOP condition,indicatedby pullingSDA fromLOW toHIGH whileSCL isHIGH. WRITING/READING TO THE TMP105 Accessinga particularregisteron theTMP105 isaccomplishedby writingtheappropriatevaluetothePointer Register.The valueforthePointerRegisteristhefirstbytetransferredaftertheslaveaddressbytewiththeR/W bitLOW. EverywriteoperationtotheTMP105 requiresa valueforthePointerRegister.(RefertoFigure5.) When readingfrom the TMP105, the lastvaluestoredinthe PointerRegisterby a writeoperationisused to determinewhichregisterisreadby a readoperation.To change theregisterpointerfora readoperation,a new valuemust be writtentothePointerRegister.Thisisaccomplishedby issuinga slaveaddressbytewiththeR/W bitLOW, followedby thePointerRegisterbyte.No additionaldataarerequired.The mastercan thengeneratea START conditionand send the slaveaddressbytewiththe R/W bitHIGH to initiatethe read command. See Figure6 fordetailsofthissequence.Ifrepeatedreadsfromthesame registeraredesired,itisnotnecessaryto continuallysend the PointerRegisterbyte,as the TMP105 remembers the PointerRegistervalueuntilitis changed by thenextwriteoperation. Note thatregisterbytesaresentmost significantbytefirst,followedby theleastsignificantbyte. SLAVE MODE OPERATIONS The TMP105 can operateas a slavereceiverorslavetransmitter. SlaveReceiverMode: The firstbyte transmittedby the master is the slaveaddress,withthe R/W bitLOW. The TMP105 then acknowledgesreceptionofa validaddress.The nextbytetransmittedby themasteristhePointerRegister.The TMP105 then acknowledgesreceptionof the PointerRegisterbyte.The nextbyteor bytesare writtento the registeraddressedby thePointerRegister.The TMP105 acknowledgesreceptionofeach databyte.The master may terminatedatatransferby generatinga START orSTOP condition. SlaveTransmitterMode: The firstbyte is transmittedby the master and is the slaveaddress,withthe R/W bitHIGH. The slave acknowledgesreceptionof a validslaveaddress.The nextbyteistransmittedby the slaveand isthe most significantbyteoftheregisterindicatedby thePointerRegister.The masteracknowledgesreceptionofthedata byte.The nextbytetransmittedby theslaveistheleastsignificantbyte.The masteracknowledgesreceptionof the data byte.The master may terminatedata transferby generatinga Not-Acknowledgeon receptionof any databyte,orgeneratinga START orSTOP condition.
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www.ti.com SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 SMBus ALERT FUNCTION The TMP105 supportstheSMBus Alertfunction.When theTMP105 isoperatinginInterruptMode (TM = 1),the ALERT pinoftheTMP105 may be connectedas an SMBus Alertsignal.When a mastersenses thatan ALERT conditionispresenton theALERT line,themastersends an SMBus Alertcommand (00011001)on thebus.If theALERT pinoftheTMP105 isactive,thedeviceswillacknowledgetheSMBus Alertcommand and respondby returningitsslaveaddresson theSDA line.The eighthbit(LSB) oftheslaveaddressbytewillindicateifthe temperatureexceedingTHIGH or fallingbelow TLOW caused the ALERT condition.Thisbitwillbe HIGH ifthe temperatureisgreaterthanorequaltoTHIGH .Thisbitwillbe LOW ifthetemperatureislessthanTLOW .Referto Figure7 fordetailsofthissequence. Ifmultipledeviceson thebus respondtotheSMBus Alertcommand, arbitrationduringtheslaveaddressportion oftheSMBus Alertcommand willdeterminewhich devicewillclearitsALERT status.IftheTMP105 wins the arbitration,itsALERT pinwillbecome inactiveatthecompletionoftheSMBus Alertcommand. IftheTMP105 losesthearbitration,itsALERT pinwillremainactive. GENERAL CALL The TMP105 respondsto a Two-Wire GeneralCalladdress(0000000)ifthe eighthbitis0. The devicewill acknowledge the GeneralCalladdressand respond to commands inthe second byte.Ifthe second byteis 00000100,theTMP105 willlatchthestatusoftheaddresspin,butwillnotreset.Ifthesecond byteis00000110, theTMP105 willlatchthestatusoftheaddresspinand resettheinternalregisterstotheirpower-upvalues. TIMEOUT FUNCTION The TMP105 willresettheserialinterfaceifeitherSCL orSDA areheldLOW for54ms (typ)between a START and STOP condition.The TMP105 willreleasethebus ifitispulledLOW and willwaitfora START condition.To avoidactivatingthetimeoutfunction,itisnecessarytomaintaina communicationspeed ofatleast1kHz forSCL operatingfrequency. TIMING DIAGRAMS The TMP105 isTwo-Wire and SMBus-compatible.Figure4 toFigure7 describethevariousoperationson the TMP105. Bus definitionsaregivenbelow.ParametersforFigure4 aredefinedinTable12. Bus Idle: BothSDA and SCL linesremainHIGH. StartData Transfer: A change in the stateof the SDA line,from HIGH to LOW, whilethe SCL lineisHIGH, definesa START condition.Each datatransferisinitiatedwitha START condition. Stop Data Transfer: A change inthestateoftheSDA linefromLOW toHIGH whiletheSCL lineisHIGH definesa STOP condition. Each datatransferisterminatedwitha repeatedSTART orSTOP condition. Data Transfer: The number ofdatabytestransferredbetween a START and a STOP conditionisnotlimitedand isdetermined by themasterdevice.The receiveracknowledgesthetransferofdata. Acknowledge: Each receivingdevice,when addressed,isobligedtogeneratean Acknowledge bit.A devicethatacknowledges must pulldown theSDA lineduringtheAcknowledge clockpulseinsuch a way thattheSDA lineisstableLOW duringtheHIGH periodoftheAcknowledge clockpulse.Setup and holdtimesmust be takenintoaccount.On a masterreceive,theterminationofthedatatransfercan be signaledby themastergeneratinga Not-Acknowledge on thelastbytethathas been transmittedby theslave. Copyright© 2005–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TMP105
t(LOW) tR tF t(HDST A) t(HDST A) t(HDDA T) t(BUF) t(SUDA T) t(HIGH) t(SUST A) t(SUSTO) P S S P Frame□1□T wo-Wire□Slave□Address□Byte Frame□2□Pointer□Register□Byte Frame□4□Data□Byte□2 Start□By Master ACK□By TMP105 ACK□By TMP105 ACK□By TMP105 Stop□By Master 1 9 1 D7 D6 D5 D4 D3 D2 D1 D0 Frame□3□Data□Byte□1 ACK□By TMP105 D7SDA (Continued) SCL (Continued) D6 D5 D4 D3 D2 D1 D0 SDA SCL 0 0 1 0 0 A0 R/W 0 0 0 0 0 0 P1 P0 /c188 /c188 TMP105 SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 www.ti.com Table12.Timing Diagram DefinitionsfortheTMP105 FAST MODE PARAMETER UNITS MIN MAX SCL OperatingFrequency f(SCL) 1 400 kHz Bus FreeTime Between STOP and START Condition t(BUF) 600 ns HoldtimeafterrepeatedSTART condition. t(HDSTA) 100 nsAfterthisperiod,thefirstclockisgenerated. Repeated START ConditionSetupTime t(SUSTA) 100 ns STOP ConditionSetupTime t(SUSTO) 100 ns Data HoldTime t(HDDAT) 0 ns Data SetupTime t(SUDAT) 100 ns SCL ClockLOW Period t(LOW) 1300 ns SCL ClockHIGH Period t(HIGH) 600 ns Clock/DataFallTime tF 300 ns Clock/DataRiseTime 300 nstR 1000 nsforSCLK ≤ 100kHz TWO-WIRE TIMING DIAGRAMS Figure4. Two-Wire Timing Diagram Figure5. Two-Wire Timing Diagram forTMP105 WriteWord Format
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Frame□1□T wo-Wire□Slave□Address□Byte Frame□2□Pointer□Register□Byte Start□By Master ACK□By TMP105 ACK□By TMP105 Frame□3□T wo-Wire□Slave□Address□Byte Frame□4□Data□Byte□1□Read□Register Start□By Master ACK□By TMP105 ACK□By Master From TMP105 1 9 1 9 1 9 1 9 SDA SCL 0 0 R/W 0 0 0 0 0 0 P1 P0 /c188 /c188 /c188 /c188 SDA (Continued) SCL (Continued) SDA (Continued) SCL (Continued) 1 0 0 1 0 0 A0 0 0 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 Frame□5□Data□Byte□2□Read□Register Stop□By Master ACK□By Master From TMP105 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Frame□1□SMBus□ALERT□Response□Address□Byte Frame□2□Slave□Address□Byte Start□By Master ACK□By TMP105 From TMP105 NACK□By Master Stop□By Master 1 9 1 9 SDA SCL ALERT 0 0 0 1 1 0 0 R/W 1 0 0 1 0 0 A0 Status TMP105 www.ti.com SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011 Figure6. Two-Wire Timing Diagram forRead Word Format Figure7. Timing Diagram forSMBus ALERT Copyright© 2005–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TMP105
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REVISION HISTORY
NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionC (April,2008)toRevisionD Page
- IntheElectricalSpecificationstable,changed from:DIGITAL INPUT/OUTPUT to:DIGITAL INPUT/OUTPUT (SCL, Changes from RevisionB (January,2006)toRevisionC Page
14 SubmitDocumentationFeedback Copyright© 2005–2011,Texas InstrumentsIncorporated
ProductFolderLink(s):TMP105
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TMP105YZCR Active Production DSBGA (YZC) | 6 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 EY TMP105YZCR.B Active Production DSBGA (YZC) | 6 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 EY TMP105YZCT Obsolete Production DSBGA (YZC) | 6 - - Call TI Call TI -40 to 125 EY (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 28-Mar-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 28-Mar-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP105YZCR DSBGA YZC 6 3000 220.0 220.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C
0.625 MAX
0.35 0.15 TYP
0.25 TYP
6X 0.35 0.25 0.5 TYP
0.5 TYP
D 4219522/A 02/2015 DSBGA - 0.625 mm max heightYZC0006 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFree TM package configuration. NanoFree Is a trademark of Texas Instruments. BALL A1 CORNER SEATING PLANE BALL TYP 0.08 C A
0.015 C A B
C B SCALE 9.000 D: Max = E: Max = 1.61 mm, Min = 1.11 mm, Min = 1.55 mm 1.05 mm
www.ti.com EXAMPLE BOARD LAYOUT 6X ( ) 0.265 (0.5) TYP (0.5) TYP ( ) METAL 0.265 0.05 MAX SOLDER MASK OPENING METAL UNDER SOLDER MASK ( ) SOLDER MASK OPENING 0.265
0.05 MIN
DSBGA - 0.625 mm max heightYZC0006 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). SYMM SYMM LAND PATTERN EXAMPLE SCALE:30X 1 2 A B C NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP 6X ( 0.25) (R ) TYP 0.05 METAL TYP 4219522/A 02/2015 DSBGA - 0.625 mm max heightYZC0006 DIE SIZE BALL GRID ARRAY NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 1 2 A B C
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