TMP105YZC

TMP105 BURR-BROWN | Alldatasheet

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Technical content

FEATURES

/C0068SUPPORTS 1.8V I2C BUS /C0068TWO ADDRESSES /C0068DIGITAL OUTPUT: Two-Wire Serial Interface /C0068RESOLUTION: 9- to 12-Bits, User-Selectable /C0068ACCURACY: ±2.0°C (max) from −25°C to +85°C ±3.0°C (max) from −40°C to +125°C /C0068LOW QUIESCENT CURRENT: 50µA, 1.5µA Standby /C0068NO POWER-UP SEQUENCE REQUIRED, I 2C PULLUPS CAN BE ENABLED PRIOR TO V+

APPLICATIONS

/C0068CELL PHONES /C0068COMPUTER PERIPHERAL THERMAL PROTECTION /C0068NOTEBOOK COMPUTERS /C0068BATTERY MANAGEMENT /C0068THERMOSTAT CONTROLS /C0068ENVIRONMENTAL MONITORING AND HVAC SDA SCL GND ALERT YZC LEAD FREE

2 X 3 ARRAY

(TOP VIEW) Note: Pin A1 is marked with a ’0” for Pb−free (YZC) 1,65 mm 1,50 mm 1,15 mm 1,00 mm (Bump Side Down)

DESCRIPTION

The TMP105 is a two-wire, serial output temperature sensor available in a WCSP package. Requiring no external components, the TMP105 is capable of reading temperatures with a resolution of 0.0625°C. The TMP105 features a Two-Wire interface that is SMBus-compatible, with the TMP105 allowing up to two devices on one bus. The TMP105 features an SMBus Alert function. The TMP105 is ideal for extended temperature measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. The TMP105 is specified for operation over a temperature range of −40°C to +125°C. Diode Te mp . Sensor A/D Converter OSC Control Logic Serial Interface Config. and T emp. Register TMP105 T emperature SDA A1 GND SCL B1 B2 ALERT TMP105 SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 Digital Temperature Sensor with Two-Wire Interface Chip-Scale Package /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 www.ti.com Copyright  2005−2006, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

/C0084/C0077/C0080/C0049/C0048/C0053 SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) ESD Rating: (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2)Input voltage rating applies to all TMP105 input voltages. (3)HBM testing has been tested to TI specifications JEDEC JESD22-A114C.01. (4)CDM testing has been tested to TI specifications JEDEC EIA/JESD22-A1 15A. (5)MM testing has been tested to TI specifications JEDEC JESD22-C101C. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE PART NUMBER SYMBOL Wafer chip-scale package (YZC) TMP105YZC EY (1)For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN ASSIGNMENTS NOTE: Pin 1 is determined by orienting the package marking as indicated in the diagram. SDA SCL GND ALERT (Bump Side Down) WCSP-6 P ACKAGE (TOP VIEW)

/C0084/C0077/C0080/C0049/C0048/C0053 SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 www.ti.com

ELECTRICAL CHARACTERISTICS

At TA = −40°C to +125°C, and V+ = 2.6V to 3.3V, unless otherwise noted. PARAMETER CONDITION TMP105 UNITSPARAMETER CONDITION MIN TYP MAX UNITS TEMPERATURE INPUT Range −40 +125 °C Accuracy (Temperature Error) −25°C to +85°C ±0.5 ±2.0 °C vs Supply 0.2 ±0.5 °C/V Resolution(1) Selectable 0.0625 °C DIGITAL INPUT/OUTPUT Input Capacitance 3 pF Input Logic Levels: VIH 1.2 6.0 V VIL −0.5 0.6 V Leakage Input Current, IIN 0V ≤ VIN ≤ 6V 1 µA Input Voltage Hysteresis SCL and SDA Pins 100 mV Output Logic Levels: VOL SDA IOL = 3mA 0 0.15 0.4 V VOL ALERT IOL = 4mA 0 0.15 0.4 V Resolution Selectable 9 to 12 Bits Conversion Time 9-Bit 27.5 37.5 ms 10-Bit 55 75 ms 11-Bit 110 150 ms 12-Bit 220 300 ms Timeout Time 25 54 74 ms POWER SUPPLY Operating Range 2.6 3.3 V Quiescent Current IQ Serial Bus Inactive 50 85 µA Serial Bus Active, SCL Freq = 400kHz 100 µA Shutdown Current ISD Serial Bus Inactive 1.5 3 µA Serial Bus Active, SCL Freq = 400kHz 60 µA TEMPERATURE RANGE Specified Range −40 +125 °C Operating Range −55 +127 °C Thermal Resistance /C0113JA 240 °C/W (1)Specified for 12-bit resolution.

/C0084/C0077/C0080/C0049/C0048/C0053 SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C and V+ = 2.8V, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE T emperature (/C0095C) IQ (µA) −50 −25 0 100 25 50 75 100 125 V +=2 . 6 V CONVERSION TIME vs TEMPERATURE Temperature (/C0095C) Conversion Time (ms) −50 −25 0 225 220 215 210 205 200 25 50 75 100 125 12−Bit Resolution V+ = 2.6V V +=3 . 3 V SHUTDOWN CURRENT vs TEMPERATURE Temperature (/C0095C) Shutdown Current (µA) −50 −25 0 3.0 2.5 2.0 1.5 1.0 0.5 25 50 75 100 125 V +=2 . 6 V V +=3 . 3 V 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 TEMPERATURE ACCURACY vs TEMPERATURE Temperature Error (/C0095C) 3 typical units 12−bit resolution. Temperature (/C0095C) −55 −35 −1 55 2 54 56 58 5 1 0 5 1 2 5 1 3 0 500 450 400 350 300 250 200 150 100 QUIESCENT CURRENT WITH BUS ACTIVITY vs TEMPERATURE Frequency (Hz) 1k 10k 100k 1M 10M IQ (µA) +125/C0095C +25/C0095C −55/C0095C

Table 5. Temperature Data Format used with the unused LSBs set to zero. Configuration Register is all bits equal to 0.

1 OS R1 R0 F1 F0 POL TM SD

Table 6. Configuration Register Format Figure 3. Output Transfer Function Diagrams order, see the High and Low Limit Registers section. Table 7. Fault Settings of the TMP105

resolution and conversion time. Table 8. Resolution of the TMP105 the indicated TLOW value for the same number of faults. returning the device to Comparator Mode (TM = 0). Both operational modes are represented in Figure 3. for the Temperature Register.

1 H11 H10 H9 H8 H7 H6 H5 H4

2 H3 H2 H1 H0 0 0 0 0

Table 9. Bytes 1 and 2 of THIGH Register

1 L11 L10 L9 L8 L7 L6 L5 L4

2 L3 L2 L1 L0 0 0 0 0

Table 10. Bytes 1 and 2 of TLOW Register configured for 9-bit resolution.

power dissipation associated with detection. Table 11. Address Pin and Slave Addresses for the START and STOP conditions. indicating whether a read or write operation is intended. bit HIGH to initiate the read command. by the next write operation. followed by the least significant byte.

/C0084/C0077/C0080/C0049/C0048/C0053 SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 www.ti.com SLAVE MODE OPERATIONS The TMP105 can operate as a slave receiver or slave transmitter. Slave Receiver Mode: The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP105 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP105 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer Register. The TMP105 acknowledges reception of each data byte. The master may terminate data transfer by generating a START or STOP condition. Slave Transmitter Mode: The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition. SMBus ALERT FUNCTION The TMP105 supports the SMBus Alert function. When the TMP105 is operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP105 may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP105 is active, the devices will acknowledge the SMBus Alert command and respond by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte will indicate if the temperature exceeding T HIGH or falling below TLOW caused the ALERT condition. This bit will be HIGH if the temperature is greater than or equal to THIGH . This bit will be LOW if the temperature is less than TLOW . Refer to Figure 7 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command will determine which device will clear its ALERT status. If the TMP105 wins the arbitration, its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP105 loses the arbitration, its ALERT pin will remain active. GENERAL CALL The TMP105 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device will acknowledge the General Call address and respond to commands in the second byte. If the second byte is 00000100, the TMP105 will latch the status of the address pin, but will not reset. If the second byte is 00000110, the TMP105 will latch the status of the address pin and reset the internal registers to their power-up values. TIMEOUT FUNCTION The TMP105 will reset the serial interface if either SCL or SDA are held LOW for 54ms (typ) between a START and STOP condition. The TMP105 will release the bus if it is pulled LOW and will wait for a START condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1kHz for SCL operating frequency.

Figure 5. Two-Wire Timing Diagram for TMP105 Write Word Format

00 R / W 0 0000 0 P 1 P 0 …

00 A 0

00 A 0 R/W D7 D6 D5 D4 D3 D2 D1 D0

Figure 6. Two-Wire Timing Diagram for Read Word Format

Figure 7. Timing Diagram for SMBus ALERT

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TMP105YZCR ACTIVE DSBGA YZC 6 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TMP105YZCRG4 ACTIVE DSBGA YZC 6 TBD Call TI Call TI TMP105YZCT ACTIVE DSBGA YZC 6 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TMP105YZCTG4 ACTIVE DSBGA YZC 6 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 31-Jul-2006 Addendum-Page 1

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