TMP102AIDRLR

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T emp. Sensor /c68/c83 A/D Converter OSC Control Logic Serial Interface Config. and□T emp. Register TMP102 T emperature SCL 1 4ALERT SDA GND 2 5 V+ ADD0 TMP102 www.ti.com SBOS397B AUGUST 2007 REVISED OCTOBER 2008 Low Power Digital Temperature Sensor With SMBus /Two-Wire Serial Interface in SOT563 TINY SOT563 PACKAGE The TMP102 is a two-wire, serial output temperature sensor available in a tiny SOT563 package. Requiring ACCURACY: 0.5 C C to +85 no external components, the TMP102 is capable of LOW QUIESCENT CURRENT: reading temperatures to a resolution of 0.0625 µ A Active (max) The TMP102 µ A Shutdown (max) compatibility, and allows up to four devices on one SUPPLY RANGE: 1.4V to 3.6V bus. It also function. RESOLUTION: Bits The TMP102 is ideal for extended temperature DIGITAL OUTPUT: Two-Wire Serial Interface measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. The device is specified PORTABLE AND BATTERY-POWERED for operation over a temperature range of C to +125 POWER-SUPPLY TEMPERATURE MONITORING COMPUTER PERIPHERAL THERMAL PROTECTION NOTEBOOK COMPUTERS BATTERY MANAGEMENT OFFICE MACHINES THERMOSTAT CONTROLS ELECTROMECHANICAL DEVICE TEMPERATURES GENERAL TEMPERATURE MEASUREMENTS: Industrial Controls Test Equipment Medical Instrumentations Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. SMBus is a trademark of Intel, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2007 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1) PIN CONFIGURATION SDA ADD0 SCL GND ALERT CBZ TMP102 SBOS397B AUGUST 2007 REVISED OCTOBER 2008 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING TMP102 SOT563 DRL CBZ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com PARAMETER TMP102 UNIT Supply Voltage 3.6 V Input Voltage (2) 0.5 to +3.6 V Operating Temperature to +150 C Storage Temperature to +150 C Junction Temperature +150 C Human Body Model (HBM) 2000 V ESD Rating Charged Device Model (CDM) 1000 V Machine Model (MM) 200 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input voltage rating applies to all TMP102 input voltages. DRL Package SOT563 Top View Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TMP102

www.ti.com SBOS397B AUGUST 2007 REVISED OCTOBER 2008 At T A +25 C and V S +1.4V to +3.6V, unless otherwise noted. TMP102 PARAMETER CONDITIONS MIN TYP MAX UNIT TEMPERATURE INPUT Range +125 C Accuracy (Temperature Error) C to +85 C 0.5 C C to +125 C C vs Supply 0.2 0.5 C/V Resolution 0.0625 C DIGITAL INPUT/OUTPUT Input Logic Levels: V IH 0.7 (V+) 3.6 V V IL 0.5 0.3 (V+) V Input Current I IN V IN 3.6V µ A Output Logic Levels: V OL SDA 2V, I OL 3mA 0.4 V 2V, I OL 3mA 0.2 (V+) V V OL ALERT 2V, I OL 3mA 0.4 V 2V, I OL 3mA 0.2 (V+) V Resolution Bit Conversion Time ms Conversion Modes CR1 CR0 0.25 Conv/s CR1 CR0 Conv/s CR1 CR0 (default) Conv/s CR1 CR0 Conv/s Timeout Time ms POWER SUPPLY Operating Supply Range +1.4 +3.6 V Quiescent Current I Q Serial Bus Inactive, CR1 CR0 (default) µ A Serial Bus Active, SCL Frequency 400kHz µ A Serial Bus Active, SCL Frequency 3.4MHz µ A Shutdown Current I SD Serial Bus Inactive 0.5 µ A Serial Bus Active, SCL Frequency 400kHz µ A Serial Bus Active, SCL Frequency 3.4MHz µ A TEMPERATURE RANGE Specified Range +125 C Operating Range +150 C Thermal Resistance, SOT563 θ JA 260 C/W Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMP102

T emperature□( C)/c176 /c45 60 /c45 20 40 60 140 160 I ( /c109A) Q 3.6V□Supply /c45 40 0 20 80 100 120 1.4V□Supply T emperature□( C)/c176 /c45 60 /c45 40 0 40 140 160 I ( /c109A) SD 3.6V□Supply 1.4V□Supply /c45 20 20 60 80 100 120 T emperature□( C)/c176 /c45 60 /c45 20 40 60 140 160 Conversion□Time□(ms) 3.6V□Supply 1.4V□Supply /c45 40 20 0 80 100 120 100 Bus□Frequency□(Hz) 1k 10k 100k 1M 10M I ( A) /c109 Q /c45 /c176 55 C+25 C/c176 +125 C/c176 2.0 1.5 1.0 0.5 /c45 0.5 /c45 1.0 /c45 1.5 /c45 2.0 T emperature□( C)/c176 /c45 60 /c45 40 40 60 140 160 T emperature□Error□( C) /c176 /c45 20 200 80 100 120 T emperature□Error□( C)/c176 Population TMP102 SBOS397B AUGUST 2007 REVISED OCTOBER 2008 www.ti.com At T A +25 C and 3.3V, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE Conversions per Second) SHUTDOWN CURRENT vs TEMPERATURE Figure Figure QUIESCENT CURRENT vs BUS FREQUENCY CONVERSION TIME vs TEMPERATURE (Temperature at 3.3V Supply) Figure Figure TEMPERATURE ERROR vs TEMPERATURE TEMPERATURE ERROR AT +25 C Figure Figure Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TMP102

0.01/c109F GND

3 ALERT

(Output)

4 ADD01SCL

NOTE:□SCL,□SDA,□and□ALERT pins□require□pull-up□resistors. I/O Control Interface SCL SDA T emperature Register Configuration Register TLOW Register THIGH Register Pointer Register TMP102 www.ti.com SBOS397B AUGUST 2007 REVISED OCTOBER 2008 The TMP102 is a digital temperature sensor that is optimal for thermal-management and thermal- Figure shows the internal register structure of the protection applications. The TMP102 is two-wire- and TMP102. The 8-bit Pointer Register of the device is SMBus interface-compatible, and is specified over a used to address a given data register. The Pointer temperature range of C to +125 Register uses the two LSBs (see Table to identify which of the data registers should respond to a read Pull-up resistors are required on SCL, SDA, and or write command. Table identifies the bits of the ALERT. A 0.01 µ F bypass capacitor is recommended, Pointer Register byte. During a write command, as shown in Figure through must always be '0'. Table describes the pointer address of the registers available in the TMP102. Power-up reset value of P1/P0 is '00'. By default, the TMP102 reads the temperature on power-up. Figure Typical Connections The temperature sensor in the TMP102 is the chip itself. Thermal paths run through the package leads, as well as the plastic package. The lower thermal resistance of metal causes the leads to provide the primary thermal path. To maintain accuracy in measurement, care should be taken to isolate the package and leads from ambient air temperature. A thermally-conductive adhesive is Table Pointer Register Byte helpful in achieving accurate surface temperature measurement. Register Bits Table Pointer Addresses REGISTER Temperature Register (Read Only) Configuration Register (Read/Write) T LOW Register (Read/Write) T HIGH Register (Read/Write) Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMP102

www.ti.com indicates Normal mode (EM bit '0') or Extended mode (EM bit '1') and can be used to distinguish The Temperature Register of the TMP102 is between the two temperature register data formats. configured as a 12-bit, read-only register The unused bits in the Temperature Register always (Configuration Register EM bit '0', see the Extended read '0'. Mode section), or as a 13-bit, read-only register (Configuration Register EM bit '1') that stores the Table Byte of Temperature Register (1) output of the most recent conversion. Two bytes must be read to obtain data, and are described in Table and Table Note that byte is the most significant T11 T10 byte, followed by byte the least significant byte. (T12) (T11) (T10) (T9) (T8) (T7) (T6) (T5) The first bits (13 bits in Extended mode) are used (1) Extended mode 13-bit configuration shown in parenthesis. to indicate temperature. The least significant byte does not have to be read if that information is not Table Byte of Temperature Register (1) needed. The data format for temperature is summarized in Table and Table One LSB equals 0.0625 Negative numbers are represented in binary twos complement format. Following power-up (T4) (T3) (T2) (T1) (T0) (0) (0) (1) or reset, the Temperature Register will read C until (1) Extended mode 13-bit configuration shown in parenthesis. the first conversion is complete. Bit of byte Table 12-Bit Temperature Data Format (1) TEMPERATURE DIGITAL OUTPUT (BINARY) HEX 128 0111 1111 1111 7FF 127.9375 0111 1111 1111 7FF 100 0110 0100 0000 640 0101 0000 0000 500 0100 1011 0000 4B0 0011 0010 0000 320 0001 1001 0000 190 0.25 0000 0000 0100 004 0000 0000 0000 000 0.25 1111 1111 1100 FFC 1110 0111 0000 E70 1100 1001 0000 C90 (1) The resolution for the Temp ADC in Internal Temperature mode is 0.0625 C/count. For positive temperatures (for example, +50 C): Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary code with the 12-bit, left-justified format, and MSB to denote a positive sign. Example: (+50 C)/(0.0625 C/count) 800 320h 0011 0010 0000 For negative temperatures (for example, C): Generate the twos complement of a negative number by complementing the absolute value binary number and adding Denote a negative number with MSB Example: C|)/(0.0625 C/count) 400 190h 0001 1001 0000 Twos complement format: 1110 0110 1111 1110 0111 0000 Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TMP102

(AL Bit) CONVERSION RATE EXTENDED MODE (EM) TMP102 www.ti.com SBOS397B AUGUST 2007 REVISED OCTOBER 2008 Table 13-Bit Temperature Data Format TEMPERATURE DIGITAL OUTPUT (BINARY) HEX 150 1001 0110 0000 0960 128 1000 0000 0000 0800 127.9375 0111 1111 1111 07FF 100 0110 0100 0000 0640 0101 0000 0000 0500 0100 1011 0000 04B0 0011 0010 0000 0320 0001 1001 0000 0190 0.25 0000 0000 0100 0004 0000 0000 0000 0000 0.25 1111 1111 1100 1FFC 1110 0111 0000 1E70 1100 1001 0000 1C90 The Configuration Register is a 16-bit read/write The AL bit is a read-only function. Reading the AL bit register used to store bits that control the operational will provide information about the comparator mode modes of the temperature sensor. Read/write status. The state of the POL bit inverts the polarity of operations are performed MSB first. The format and data returned from the AL bit. For POL the AL bit power-up/reset value of the Configuration Register is will read as '1' until the temperature equals or shown in Table For compatibility, the first byte exceeds T HIGH for the programmed number of corresponds to the Configuration Register in the consecutive faults, causing the AL bit to read as '0'. TMP75 and TMP275 All registers are updated byte The AL bit will continue to read as '0' until the by byte. temperature falls below T LOW for the programmed number of consecutive faults, when it will again read Table Configuration and Power-Up/Reset as '1'. The status of the TM bit does not affect the Format status of the AL bit. BYTE OS POL TM SD The conversion rate bits, CR1 and CR0, configure the TMP102 for conversion rates of 8Hz, 4Hz, 1Hz, or CR1 CR0 AL EM 0.25Hz. The default rate is 4Hz. The TMP102 has a typical conversion time of 26ms. To achieve different conversion rates, the TMP102 makes a conversion and after that powers down and waits for the appropriate delay set by CR1 and CR0. Table The Extended mode bit configures the device for shows the settings for CR1 and CR0. Normal mode operation (EM or Extended mode operation (EM 1). In Normal mode, the Table Conversion Rate Settings Temperature Register and high- and low-limit CR1 CR0 CONVERSION RATE registers use a 12-bit data format. Normal mode is used to make the TMP102 compatible with the 0.25Hz TMP75 1Hz Extended mode (EM allows measurement of 4Hz (default) temperatures above +128 C by configuring the 8Hz Temperature Register, and high- and low-limit registers, for 13-bit data format. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMP102

Startup Start□of Conversion Delay(1) 26ms 26ms Measured T emperature THIGH TLOW TMP102 ALERT□PIN (Comparator□Mode) POL□=□0 TMP102 ALERT□PIN (Interrupt□Mode) POL□=□0 TMP102 ALERT□PIN (Comparator□Mode) POL□=□1 TMP102 ALERT□PIN (Interrupt□Mode) POL□=□1 Read Read Time Read SHUTDOWN MODE (SD) FAULT QUEUE (F1/F0) THERMOSTAT MODE (TM) POLARITY (POL) TMP102 SBOS397B AUGUST 2007 REVISED OCTOBER 2008 www.ti.com After power-up or general-call reset, the TMP102 immediately starts a conversion, as shown in Figure The first result is available after 26ms (typical). The active quiescent current during conversion is µ A (typical at +27 C). The quiescent current during delay is 2.2 µ A (typical at +27 C). Figure Conversion Start The Shutdown mode bit saves maximum power by Figure 10. Output Transfer Function Diagrams shutting down all device circuitry other than the serial interface, reducing current consumption to typically less than 0.5 µ Shutdown mode is enabled when the SD bit is '1'; the device shuts down when current A fault condition exists when the measured conversion is completed. When SD is equal to '0', the temperature exceeds the user-defined limits set in the device maintains a continuous conversion state. T HIGH and T LOW registers. Additionally, the number of fault conditions required to generate an alert may be programmed using the fault queue. The fault queue is The Thermostat mode bit indicates to the device provided to prevent a false alert as a result of whether to operate in Comparator mode (TM or environmental noise. The fault queue requires Interrupt mode (TM 1). For more information on consecutive fault measurements in order to trigger comparator and interrupt modes, see the High- and the alert function. Table defines the number of Low-Limit Registers section. measured faults that may be programmed to trigger an alert condition in the device. For T HIGH and T LOW register format and byte order, see the High- and Low-Limit Registers section. The Polarity bit allows the user to adjust the polarity of the ALERT pin output. If POL the ALERT pin Table TMP102 Fault Settings will be active low, as shown in Figure For POL CONSECUTIVE FAULTS the ALERT pin will be active high, and the state of the ALERT pin is inverted. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TMP102

(R1/R0) ONE-SHOT/CONVERSION READY (OS) HIGH- AND LOW-LIMIT REGISTERS BUS OVERVIEW TMP102 www.ti.com SBOS397B AUGUST 2007 REVISED OCTOBER 2008 Both operational modes are represented in Figure Table and Table describe the format for the R1/R0 are read-only bits. The TMP102 converter T HIGH and T LOW registers. Note that the most resolution is set on start up to '11'. This sets the significant byte is sent first, followed by the least temperature register to a bit-resolution. significant byte. Power-up reset values for T HIGH and T LOW are: T HIGH +80 C and T LOW +75 The format of the data for T HIGH and T LOW is the same as for the Temperature Register. The TMP102 a One-Shot Temperature Measurement mode. When the device is in Shutdown Table 10. Bytes and of T HIGH Register (1) mode, writing a to the OS bit starts a single temperature conversion. During the conversion, the BYTE OS bit reads '0'. The device returns to the shutdown H11 H10 state at the completion of the single conversion. After (H12) (H11) (H10) (H9) (H8) (H7) (H6) (H5) the conversion, the OS bit reads '1'. This feature is BYTE useful for reducing power consumption in the TMP102 when continuous temperature monitoring is not required. (H4) (H3) (H2) (H1) (H0) (0) (0) (0) (1) Extended mode 13-bit configuration shown in parenthesis. As a result of the short conversion time, the TMP102 can achieve a higher conversion rate. A single Table 11. Bytes and of T LOW Register (1) conversion typically takes 26ms and a read can take place in less than µ When using One-Shot mode, BYTE or more conversions per second are possible. L11 L10 (L12) (L11) (L10) (L9) (L8) (L7) (L6) (L5) BYTE In Comparator mode (TM 0), the ALERT pin becomes active when the temperature equals or (L4) (L3) (L2) (L1) (L0) (0) (0) (0) exceeds the value in T HIGH and generates a (1) Extended mode 13-bit configuration shown in parenthesis. consecutive number of faults according to fault bits and F0. The ALERT pin remains active until the temperature falls below the indicated T LOW value for the same number of faults. The device that initiates the transfer is called a In Interrupt mode (TM 1), the ALERT pin becomes master and the devices controlled by the master are active when the temperature equals or exceeds the slaves The bus must be controlled by a master value in T HIGH for a consecutive number of fault device that generates the serial clock (SCL), controls conditions (as shown in Table The ALERT pin the bus access, and generates the START and STOP remains active until a read operation of any register conditions. occurs, or the device successfully responds to the To address a specific device, a START condition is SMBus Alert Response address. The ALERT pin will initiated, indicated by pulling the data-line (SDA) from also be cleared if the device is placed in Shutdown a high to low logic level while SCL is high. All slaves mode. Once the ALERT pin is cleared, it becomes on the bus shift in the slave address byte on the active again only when temperature falls below T LOW rising edge of the clock, with the last bit indicating and remains active until cleared by a read operation whether a read or write operation is intended. During of any register or a successful response to the the ninth clock pulse, the slave being addressed SMBus Alert Response address. Once the ALERT responds to the master by generating an pin is cleared, the above cycle repeats, with the Acknowledge and pulling SDA low. ALERT pin becoming active when the temperature equals or exceeds T HIGH The ALERT pin can also be Data transfer is then initiated and sent over eight cleared by resetting the device with the General Call clock pulses followed by an Acknowledge Bit. During Reset command. This action also clears the state of data transfer SDA must remain stable while SCL is the internal registers in the device, returning the high, because any change in SDA while SCL is high device to Comparator mode (TM 0). will be interpreted as a START or STOP signal. Once all data have been transferred, the master generates a STOP condition indicated by pulling SDA from low to high, while SCL is high. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMP102

Mode: WRITING/READING OPERATION Slave Transmitter Mode: TMP102 SBOS397B AUGUST 2007 REVISED OCTOBER 2008 www.ti.com This action is accomplished by issuing a slave address byte with the W bit low, followed by the The TMP102 operates as a slave device only on the Pointer Register byte. No additional data are two-wire bus and SMBus. Connections to the bus are required. The master can then generate a START made via the open-drain I/O lines SDA and SCL. The condition and send the slave address byte with the SDA and SCL pins feature integrated spike W bit high to initiate the read command. See suppression filters and Schmitt triggers to minimize Figure for details of this sequence. If repeated the effects of input spikes and bus noise. The reads from the same register are desired, it is not TMP102 supports the transmission protocol for both necessary to continually send the Pointer Register fast (1kHz to 400kHz) and high-speed (1kHz to bytes, because the TMP102 remembers the Pointer 3.4MHz) modes. All data bytes are transmitted MSB Register value until it is changed by the next write first. operation. Note that register bytes are sent with the most significant byte first, followed by the least significant To communicate with the TMP102, the master must byte. first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP102 can operate as a slave receiver or slave transmitter. As a slave device, the TMP102 never The TMP102 line. four devices to be addressed on a single bus. Table describes the pin logic levels used to properly connect up to four devices. The first byte transmitted by the master is the slave Table 12. Address Pin and Slave Addresses address, with the W bit low. The TMP102 then acknowledges reception of a valid address. The next DEVICE TWO-WIRE PIN CONNECTION byte transmitted by the master is the Pointer ADDRESS Register. The TMP102 then acknowledges reception 1001000 Ground of the Pointer Register byte. The next byte or bytes 1001001 are written to the register addressed by the Pointer 1001010 SDA Register. The TMP102 acknowledges reception of each data byte. The master can terminate data 1001011 SCL transfer by generating a START or STOP condition. Accessing a particular register on the TMP102 is The first byte transmitted by the master is the slave accomplished by writing the appropriate value to the address, with the W bit high. The slave Pointer Register. The value for the Pointer Register is acknowledges reception of a valid slave address. The the first byte transferred after the slave address byte next byte is transmitted by the slave and is the most with the W bit low. Every write operation to the significant byte of the register indicated by the Pointer TMP102 requires a value for the Pointer Register Register. The master acknowledges reception of the (see Figure data byte. The next byte transmitted by the slave is When reading from the TMP102, the last value stored the least significant byte. The master acknowledges in the Pointer Register by a write operation is used to reception of the data byte. The master can terminate determine which register is read by a read operation. data transfer by generating a Not-Acknowledge on To change the register pointer for a read operation, a reception of any data byte, or generating a START or new value must be written to the Pointer Register. STOP condition. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TMP102

(Hs) MODE TIMEOUT FUNCTION NOISE GENERAL CALL TMP102 SCL SDA GND V+ ALERT ADD0 CF 10nF/c179 RF 5k/c163 /c87 Supply□Voltage TMP102 www.ti.com SBOS397B AUGUST 2007 REVISED OCTOBER 2008 The TMP102 supports the SMBus Alert function. In order for the two-wire bus to operate at frequencies When the TMP102 operates in Interrupt mode (TM above 400kHz, the master device must issue an '1'), the ALERT pin may be connected as an SMBus Hs-mode master code (00001xxx) as the first byte Alert signal. When a master senses that an ALERT after a START condition to switch the bus to condition is present on the ALERT line, the master high-speed operation. The TMP102 does not sends an SMBus Alert command (00011001) to the acknowledge this byte, but switches its input filters on bus. If the ALERT pin is active, the device SDA and SCL and its output filters on SDA to operate acknowledges the SMBus Alert command and in Hs-mode, allowing transfers at up to 3.4MHz. After responds by returning its slave address on the SDA the Hs-mode master code has been issued, the line. The eighth bit (LSB) of the slave address byte master transmits a two-wire slave address to initiate a indicates if the ALERT condition was caused by the data transfer operation. The bus continues to operate temperature exceeding T HIGH or falling below T LOW in Hs-mode until a STOP condition occurs on the bus. For POL '0', this bit is low if the temperature is Upon receiving the STOP condition, the TMP102 greater than or equal to T HIGH this bit is high if the switches the input and output filters back to temperature is less than T LOW The polarity of this bit fast-mode operation. is inverted if POL '1'. Refer to Figure for details of this sequence. If multiple devices on the bus respond to the SMBus The TMP102 resets the serial interface if SCL is held Alert command, arbitration during the slave address low for 30ms (typ). The TMP102 releases the bus if it portion of the SMBus Alert command determines is pulled low and waits for a START condition. To which device will clear its ALERT status. The device avoid activating the timeout function, it is necessary with the lowest two-wire address wins the arbitration. to maintain a communication speed of at least 1kHz If the TMP102 wins the arbitration, its ALERT pin for SCL operating frequency. becomes inactive at the completion of the SMBus Alert command. If the TMP102 loses the arbitration, its ALERT pin remains active. The TMP102 is a very low-power device and generates very low noise on the supply bus. Applying an RC filter to the pin of the TMP102 can further The TMP102 responds to a two-wire General Call reduce any noise the TMP102 might propagate to address (0000000) if the eighth bit is '0'. The device other components. R F in Figure should be less acknowledges the General Call address and than Ω and C F should be greater than 10nF. responds to commands in the second byte. If the second byte is 00000110, the TMP102 internal registers are reset to power-up values. The TMP102 does not support the General Address acquire command. Figure 11. Noise Reduction Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMP102

www.ti.com Data Transfer: The number of data bytes transferred between a START and a STOP condition is not The TMP102 is two-wire and SMBus compatible. limited and is determined by the master device. It is Figure to Figure describe the various also possible to use the TMP102 for single byte operations on the TMP102. Parameters for Figure updates. To update only the MS byte, terminate the are defined in Table Bus definitions are: communication by issuing a START or STOP communication on the bus. Bus Idle: Both SDA and SCL lines remain high. Acknowledge: Each receiving device, when Start Data Transfer: A change in the state of the addressed, is obliged to generate an Acknowledge SDA line, from high to low, while the SCL line is high, bit. A device that acknowledges must pull down the defines a START condition. Each data transfer is SDA line during the Acknowledge clock pulse in such initiated with a START condition. a way that the SDA line is stable low during the high Stop Data Transfer: A change in the state of the period of the Acknowledge clock pulse. Setup and SDA line from low to high while the SCL line is high hold times must be taken into account. On a master defines a STOP condition. Each data transfer is receive, the termination of the data transfer can be terminated with a repeated START or STOP signaled by the master generating a condition. Not-Acknowledge ('1') on the last byte that has been transmitted by the slave. Table 13. Timing Diagram Definitions FAST MODE HIGH-SPEED MODE PARAMETER TEST CONDITIONS MIN MAX MIN MAX UNIT f (SCL) SCL Operating Frequency, V S 1.7V 0.001 0.4 0.001 3.4 MHz f (SCL) SCL Operating Frequency, V S 1.7V 0.001 0.4 0.001 2.75 MHz Bus Free Time Between STOP and START t (BUF) 600 160 ns Condition Hold time after repeated START condition. t (HDSTA) 100 100 ns After this period, the first clock is generated. t (SUSTA) Repeated START Condition Setup Time 100 100 ns t (SUSTO) STOP Condition Setup Time 100 100 ns t (HDDAT) Data Hold Time ns t (SUDAT) Data Setup Time 100 ns t (LOW) SCL Clock Low Period, V S 1.7V 1300 160 ns t (LOW) SCL Clock Low Period, V S 1.7V 1300 200 ns t (HIGH) SCL Clock High Period 600 ns t F Clock/Data Fall Time 300 ns t R Clock/Data Rise Time 300 160 ns t R Clock/Data Rise Time for SCLK 100kHz 1000 ns Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TMP102

t(LOW) tR tF t(HDST A) t(HDST A) t(HDDA T) t(BUF) t(SUDA T) t(HIGH) t(SUST A) t(SUSTO) P S S P Frame□1□T wo-Wire□Slave□Address□Byte Frame□2□Pointer□Register□Byte Frame□4□Data□Byte□2 Start□By Master ACK□By TMP102 ACK□By TMP102 ACK□By TMP102 Stop□By Master 1 9 1 D7 D6 D5 D4 D3 D2 D1 D0 Frame□3□Data□Byte□1 ACK□By TMP102 D7SDA (Continued) SCL (Continued) D6 D5 D4 D3 D2 D1 D0 SDA SCL 0 0 1 0 A1(1) A0(1) R/W 0 0 0 0 0 0 P1 P0 /c188 /c188 TMP102 www.ti.com SBOS397B AUGUST 2007 REVISED OCTOBER 2008 Figure 12. Two-Wire Timing Diagram Figure 13. Two-Wire Timing Diagram for Write Word Format Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMP102

Frame□1□T wo-Wire□Slave□Address□Byte Frame□2□Pointer□Register□Byte Start□By Master ACK□By TMP102 ACK□By TMP102 Frame□3□T wo-Wire□Slave□Address□Byte Frame□4□Data□Byte□1□Read□Register Start□By Master ACK□By TMP102 ACK□By Master(2) From TMP102 1 9 1 9 1 9 1 9 SDA SCL 0 0 1 R/W 0 0 0 0 0 0 P1 P0 /c188 /c188 /c188 SDA (Continued) SCL (Continued) SDA (Continued) SCL (Continued) 1 0 0 1 0 A1 (1) (1) 0 A1 (1) (1) R/W D7 D6 D5 D4 D3 D2 D1 D0 Frame□5□Data□Byte□2□Read□Register Stop□By Master ACK□By Master(3) From TMP102 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Stop□By Master NOTE: (1)□The□value□of□A0□and□A1□are□determined□by□the□ADD0□pin. (2)□Master□should□leave□SDA□high□to□terminate□a□single-byte□read□operation. (3)□Master□should□leave□SDA□high□to□terminate□a□two-byte□read□operation. Frame□1□SMBus□ALERT□Response□Address□Byte Frame□2□Slave□Address□From□TMP102 Start□By Master ACK□By TMP102 From TMP102 NACK□By Master Stop□By Master 1 9 1 9 SDA SCL ALERT 0 0 0 1 1 0 0 R/W 1 0 0 1 A1 A0 Status TMP102 SBOS397B AUGUST 2007 REVISED OCTOBER 2008 www.ti.com Figure 14. Two-Wire Timing Diagram for Read Word Format Figure 15. Timing Diagram for SMBus ALERT Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TMP102

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TMP102AIDRLR ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TMP102AIDRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TMP102AIDRLT ACTIVE SOT DRL 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TMP102AIDRLTG4 ACTIVE SOT DRL 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 22-Oct-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 22-Oct-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP102AIDRLR SOT DRL 6 4000 202.0 201.0 28.0 TMP102AIDRLT SOT DRL 6 250 202.0 201.0 28.0 PACKAGE MATERIALS INFORMATION www.ti.com 22-Oct-2008 Pack Materials-Page 2

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