TMP100NA/250

TMP100 TI | Alldatasheet

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SBOS231C – JANUARY 2002 – REVISED JULY 2003 www.ti.com

DESCRIPTION

The TMP100 and TMP101 are 2-wire, serial output tempera- ture sensors available in SOT23-6 packages. Requiring no external components, the TMP100 and TMP101 are capable of reading temperatures with a resolution of 0.0625°C. The TMP100 and TMP101 feature SMBus and I 2C™ inter- face compatibility, with the TMP100 allowing up to eight devices on one bus. The TMP101 offers SMBus alert func- tion with up to three devices per bus. The TMP100 and TMP101 are ideal for extended tempera- ture measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. The TMP100 and TMP101 are specified for operation over a temperature range of –55°C to +125°C.

FEATURES

G DIGITAL OUTPUT: I2C Serial 2-Wire G RESOLUTION: 9- to 12-Bits, User-Selectable G ACCURACY: ±2.0°C from –25°C to +85°C (max) ±3.0°C from –55°C to +125°C (max) G LOW QUIESCENT CURRENT: 45 µA, 0.1µA Standby G WIDE SUPPLY RANGE: 2.7V to 5.5V G TINY SOT23-6 PACKAGE PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002-2003, Texas Instruments Incorporated Digital Temperature Sensor with I2C Interface

APPLICATIONS

G POWER-SUPPLY TEMPERATURE MONITORING G COMPUTER PERIPHERAL THERMAL PROTECTION G NOTEBOOK COMPUTERS G CELL PHONES G BATTERY MANAGEMENT G OFFICE MACHINES G THERMOSTAT CONTROLS G ENVIRONMENTAL MONITORING and HVAC G ELECTROMECHANICAL DEVICE TEMPERATURE I2C is a registered trademark of Philips Incorporated. Diode Temp. Sensor A/D Converter OSC Control Logic Serial Interface Config and Temp Register TMP100 Temperature GND SCL 1 4ADD1 SDA ADD0 Diode Temp. Sensor A/D Converter OSC Control Logic Serial Interface Config and Temp Register TMP101 Temperature GND SCL ALERT SDA ADD0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

TMP100, 1012 SBOS231Cwww.ti.com ABSOLUTE MAXIMUM RATINGS (1) NOTES: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. (2) Input voltage rating applies to all TMP100 and TMP101 input voltages. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR (1) RANGE MARKING NUMBER MEDIA, QUANTITY TMP100 SOT23-6 DBV –55 °C to +125°C T100 TMP100NA/250 Tape and Reel, 250 "" "" " TMP100NA/3K Tape and Reel, 3000 TMP101 SOT23-6 DBV –55 °C to +125°C T101 TMP101NA/250 Tape and Reel, 250 "" "" " TMP101NA/3K Tape and Reel, 3000 PACKAGE/ORDERING INFORMATION NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATIONS Top View SOT23 Top View SOT23 SCL GND ADD1 SDA ADD0 T100 SCL GND ALERT SDA ADD0 T101 TMP100 TMP101

TMP100, 101 3 SBOS231C www.ti.com

ELECTRICAL CHARACTERISTICS

At TA = –55°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted. PARAMETER CONDITION MIN TYP MAX UNITS TEMPERATURE INPUT Range –55 +125 °C Accuracy (Temperature Error) –25°C to +85°C ±0.5 ±2.0 °C Resolution Selectable ±0.0625 °C DIGITAL INPUT/OUTPUT Input Logic Levels: VIH 0.7(V+) 6.0 V VIL –0.5 0.3(V+) V Input Current, IIN 0V ≤ VIN ≤ 6V 1 µA Output Logic Levels: VOL SDA I OL = 3mA 0 0.15 0.4 V VOL ALERT I OL = 4mA 0 0.15 0.4 V Resolution Selectable 9 to 12 Bits Conversion Time 9-Bit 40 75 ms 10-Bit 80 150 ms 11-Bit 160 300 ms 12-Bit 320 600 ms Conversion Rate 9-Bit 25 s/s 10-Bit 12 s/s 11-Bit 6 s/s 12-Bit 3 s/s POWER SUPPLY Operating Range 2.7 5.5 V Quiescent Current I Q Serial Bus Inactive 45 75 µA Serial Bus Active, SCL Freq = 400kHz 70 µA Serial Bus Active, SCL Freq = 3.4MHz 150 µA Shutdown Current I SD Serial Bus Inactive 0.1 1 µA Serial Bus Active, SCL Freq = 400kHz 20 µA Serial Bus Active, SCL Freq = 3.4MHz 100 µA TEMPERATURE RANGE Specified Range –55 +125 °C Storage Range –60 +150 °C Thermal Resistance, θJA SOT23-6 Surface-Mount 150 °C/W TMP100, TMP101

TMP100, 1014 SBOS231Cwww.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, V+ = 5.0V, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE Temperature (°C) –60 –40 –20 0 20 40 60 80 100 120 140 IQ (µA) Serial Bus Inactive V+ = 5V V+ = 2.7V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 SHUTDOWN CURRENT vs TEMPERATURE Temperature (°C) –60 –40 –20 0 20 40 60 80 100 120 140 ISD (µA) 400 350 300 250 CONVERSION TIME vs TEMPERATURE Temperature (°C) –60 –40 –20 0 20 40 60 80 100 120 140 Conversion Time (ms) V+ = 5V V+ = 2.7V NOTE: 12-bit resolution. 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 TEMPERATURE ACCURACY vs TEMPERATURE Temperature (°C) –60 –40 –20 0 20 40 60 80 100 120 140 Temperature Error (°C) 3 Typical Units NOTE: 12-bit resolution. 180 160 140 120 100 QUIESCENT CURRENT WITH BUS ACTIVITY vs TEMPERATURE SCL Frequency (Hz) 10k 100k 1M 10M IQ (µA) 125°C FAST MODE Hs MODE –55°C –55°C 125°C 25°C 25°C

as shown in Figure 1 and Figure 2. TMP100 and TMP101. Power-up Reset value of P1/P0 is 00. FIGURE 1. Typical Connections of the TMP101. FIGURE 2. Typical Connections of the TMP100. sensing device of the TMP100 and TMP101 is the chip itself. lead frame, and is the best choice for thermal input. isolate the package and leads from ambient air temperature. accurate surface temperature measurement. TABLE I. Pointer Register Byte.

11 T HIGH Register (READ/WRITE)

TABLE III. Byte 1 of Temperature Register. TABLE IV. Byte 2 of Temperature Register. to indicate temperature with all remaining bits equal to zero. Data format for temperature is summarized in Table V. read 0°C until the first conversion is complete. FIGURE 3. Internal Register Structure of TMP100 and TMP101.

ALERT bit will read as 1 after power-up/reset. programmed to trigger an alert condition. TABLE V. Temperature Data Format. TABLE VII. Fault Settings of the TMP100 and TMP101. TABLE VIII. Resolution of the TMP100 and TMP101.

1 OS/ALERT R1 R0 F1 F0 POL TM SD

TABLE VI. Configuration Register Format. equal to 0, the device will maintain continuous conversion. FIGURE 4. Output Transfer Function Diagrams.

TMP100, 101 7 SBOS231C www.ti.com OS/ALERT (OS) The TMP100 and TMP101 feature a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode, writing a 1 to the OS/ALERT bit will start a single temperature conversion. The device will return to the shutdown state at the completion of the single conversion. This is useful to reduce power consumption in the TMP100 and TMP101 when continuous monitoring of temperature is not required. Reading the OS/ALERT bit will provide information about the Comparator Mode status. The state of the POL bit will invert the polarity of data returned from the OS/ALERT bit. For POL = 0, the OS/ALERT will read as 0 until the temperature equals or exceeds T HIGH for the programmed number of consecutive faults, causing the OS/ALERT bit to read as 1. The OS/ALERT bit will continue to read as 1 until the temperature falls below T LOW for the programmed number of consecutive faults when it will again read as 0. The status of the TM bit does not affect the status of the OS/ALERT bit. HIGH AND LOW LIMIT REGISTERS In Comparator Mode (TM = 0), the ALERT Pin of the TMP101 becomes active when the temperature equals or exceeds the value in T HIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin will remain active until the temperature falls below the indicated T LOW value for the same number of faults. In Interrupt Mode (TM = 1) the ALERT Pin becomes active when the temperature equals or exceeds THIGH for a con- secutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs or the device successfully responds to the SMBus Alert Response Address. The ALERT pin will also be cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active again by the temperature falling below T LOW . When the temperature falls below TLOW , the ALERT pin will become active and remain active until cleared by a read operation of any register or a successful response to the SMBus Alert Response Address. Once the ALERT pin is cleared, the above cycle will repeat with the ALERT pin becoming active when the temperature equals or exceeds T HIGH . The ALERT pin can also be cleared by resetting the device with the General Call Reset command. This will also clear the state of the internal registers in the device returning the device to Comparator Mode (TM = 0). Both operational modes are represented in the Figure 4. Tables IX and X describe the format for the T HIGH and TLOW registers. Power-up Reset values for THIGH and TLOW are: THIGH = 80°C and TLOW = 75°C. The format of the data for THIGH and TLOW is the same as for the Temperature Register. All 12 bits for the Temperature, THIGH , and TLOW registers are used in the comparisons for the ALERT function for all con- verter resolutions. The three LSBs in T HIGH and TLOW can affect the ALERT output even if the converter is configured for 9-bit resolution. SERIAL INTERFACE The TMP100 and TMP101 operate only as slave devices on the I 2C bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The TMP100 and TMP101 support the transmission protocol for fast (up to 400kHz) and high-speed (up to 3.4MHz) modes. All data bytes are transmitted most significant bit first. SERIAL BUS ADDRESS To program the TMP100 and TMP101, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP100 features two address pins to allow up to eight devices to be addressed on a single I 2C interface. Table XI describes the pin logic levels used to properly connect up to eight devices. ‘Float’ indicates the pin is left unconnected. The state of pins ADD0 and ADD1 is sampled on the first I 2C bus communi- cation and should be set prior to any activity on the interface. B y t e D 7D 6D 5 D 4 D 3D 2 D 1D 0

1 H11 H10 H9 H8 H7 H6 H5 H4

B y t e D 7D 6D 5 D 4 D 3D 2 D 1D 0

2 H 3H 2H 1 H 0 0 0 0 0

TABLE IX. Bytes 1 and 2 of THIGH Register. B y t e D 7D 6D 5 D 4 D 3D 2 D 1D 0

1 L11 L10 L9 L8 L7 L6 L5 L4

B y t e D 7D 6D 5 D 4 D 3D 2 D 1D 0 2L 3L 2L 1 L 00 0 0 0 TABLE X. Bytes 1 and 2 of TLOW Register. ADD0 SLAVE ADDRESS 0 1001000 Float 1001001 1 1001010 TABLE XII. Address Pins and Slave Address for TMP101. ADD1 ADD0 SLAVE ADDRESS 0 0 1001000

0 Float 1001001

1 Float 1001101

TABLE XI. Address Pins and Slave Addresses for TMP100. The TMP101 features one address pin and an ALERT pin, allowing up to three devices to be connected per bus. Pin logic levels are described in Table XII. The address pins of the TMP100 and TMP101 are read after reset or in response to an I 2C address acquire request. Following reading, the state of the address pins is latched to minimize power dissipation associated with detection.

TMP100, 1018 SBOS231Cwww.ti.com BUS OVERVIEW The device that initiates the transfer is called a “master,” and the devices controlled by the master are “slaves.” The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by gener- ating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be interpreted as a control signal. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH, while SCL is HIGH. WRITING/READING TO THE TMP100 AND TMP101 Accessing a particular register on the TMP100 and TMP101 is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the I 2C slave address byte with the R/W bit LOW. Every write operation to the TMP100 and TMP101 requires a value for the Pointer Register. (Refer to Figure 6.) When reading from the TMP100 and TMP101, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer Register. This is accomplished by issuing an I 2C slave address byte with the R/W bit LOW, followed by the Pointer Register Byte. No additional data is required. The master can then generate a START condition and send the I 2C slave address byte with the R/W bit HIGH to initiatnlthe read command. See Figure 7 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually send the Pointer Register bytes as the TMP100 and TMP101 will remember the Pointer Register value until it is changed by the next write operation. SLAVE MODE OPERATIONS The TMP100 and TMP101 can operate as slave receivers or slave transmitters. Slave Receiver Mode: The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP100 or TMP101 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP100 or TMP101 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer register. The TMP100 and TMP101 will acknowledge recep- tion of each data byte. The master may terminate data transfer by generating a START or STOP condition. Slave Transmitter Mode: The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave acknowledges reception of a valid slave address. The next byte is transmit- ted by the slave and is the most significant byte of the register indicated by the Pointer Register. The master ac- knowledges reception of the data byte. The next byte trans- mitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition. SMBus ALERT FUNCTION The TMP101 supports the SMBus Alert function. When the TMP101 is operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP101 may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP101 is active, the TMP101 will acknowledge the SMBus Alert command and respond by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte will indicate if the temperature exceeding T HIGH or falling below TLOW caused the ALERT condition. This bit will be HIGH if the temperature is greater than or equal to THIGH . This bit will be LOW if the temperature is less than TLOW . Refer to Figure 8 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus alert command will determine which device will clear its ALERT status. If the TMP101 wins the arbitration, its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP101 loses the arbitration, its ALERT pin will remain active. The TMP100 will also respond to the SMBus ALERT com- mand if its TM bit is set to 1. Since it does not have an ALERT pin, the master needs to periodically poll the device by issuing an SMBus Alert command. If the TMP100 has gen- erated an ALERT, it will acknowledge the SMBus Alert command and return its slave address in the next byte. GENERAL CALL The TMP100 and TMP101 respond to the I2C General Call address (0000000) if the eighth bit is 0. The device will acknowledge the General Call address and respond to com- mands in the second byte. If the second byte is 00000100, the TMP100 and TMP101 will latch the status of their address pins, but will not reset. If the second byte is 00000110, the TMP100 and TMP101 will latch the status of their address pins and reset their internal registers.

TMP100, 101 9 SBOS231C www.ti.com HIGH-SPEED MODE In order for the I2C bus to operate at frequencies above 400kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP100 and TMP101 will not acknowledge this byte as required by the I specification, but will switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4MHz. After the Hs-mode master code has been issued, the master will transmit an I 2C slave address to initiate a data transfer operation. The bus will continue to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP100 and TMP101 will switch their input and output filters back to fast-mode operation. TIMING DIAGRAMS The TMP100 and TMP101 are I2C and SMBus compatible. Figures 5 to 8 describe the various operations on the TMP100 and TMP101. Bus definitions are given below. Parameters for Figure 5 are defined in Table XIII. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred be- tween a START and a STOP condition is not limited and is determined by the master device. The receiver acknowl- edges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into ac- count. On a master receive, the termination of the data transfer can be signaled by the master generating a Not- Acknowledge on the last byte that has been transmitted by the slave. FAST MODE HIGH-SPEED MODE PARAMETER MIN MAX MIN MAX UNITS SCLK Operating Frequency f (SCLK) 0.4 3.4 MHz Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns Hold Time After Repeated START Condition. t (HDSTA) 600 160 ns After this period, the first clock is generated. Repeated START Condition Setup Time t (SUSTA) 600 160 ns STOP Condition Setup Time t (SUSTO) 600 160 ns Data Hold Time t (HDDAT) 00 n s Data Setup Time t (SUDAT) 100 10 ns SCLK Clock LOW Period t (LOW) 1300 160 ns SCLK Clock HIGH Period t (HIGH) 600 60 ns Clock/Data Fall Time t F 300 160 ns Clock/Data Rise Time t R 300 160 ns TABLE XIII. Timing Diagram Definitions.

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY TMP100NA/250 ACTIVE SOP DBV 6 250 TMP100NA/3K ACTIVE SOP DBV 6 3000 TMP101NA/250 ACTIVE SOP DBV 6 250 TMP101NA/3K ACTIVE SOP DBV 6 3000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003

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